Chip, display method and display device

Abstract

The present disclosure relates to a chip, a display method, and a display device. The chip includes: a flash memory, two caches, an adjustment interface generation module, and a control core. The first cache is configured to: upon receiving a first standby interface update instruction, obtain and save multiple first standby sub-interfaces corresponding to the first standby interface update instruction in the flash memory; upon receiving a transmission end instruction, send a display request to the adjustment interface generation module; the adjustment interface generation module is configured to: obtain and generate a current adjustment interface based on the standby sub-interfaces saved in the second cache; upon receiving a first current interface update instruction and a display request, determine a first current sub-interface identifier; obtain the first current sub-interface corresponding to the first current sub-interface identifier saved in the first cache; and load the first current sub-interface into the current adjustment interface of the chip. Embodiments of the present disclosure can reduce the duration of an OSD black screen.

Description

Technical Field

[0001] The present disclosure relates to the field of information processing, and in particular to a chip, a display method, and a display device. Background Art

[0002] With the development of display devices, an increasing number of display device chips support On Screen Display (OSD). By pressing the main menu button on the display device, an adjustment interface with various display adjustment items can be called up. Various operating parameters of the display device, such as color, mode, and geometry, can be adjusted accordingly to achieve the user's desired display effect. Therefore, how to better implement the display of this adjustment interface is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0003] In view of this, the present disclosure proposes a display technology solution.

[0004] According to one aspect of the present disclosure, a chip is provided, which includes: a flash memory, two caches connected to the flash memory, an adjustment interface generation module connected to the two caches, and a control core connected to the two caches and the adjustment interface generation module; the first cache of the two caches is configured to: upon receiving a first standby interface update instruction sent by the control core, obtain and save a plurality of first standby sub-interfaces corresponding to the first standby interface update instruction in the flash memory; upon receiving a transmission end instruction corresponding to the plurality of first standby sub-interfaces sent by the flash memory, send a display request to the adjustment interface generation module; wherein the plurality of first standby sub-interfaces are used to constitute an adjustment parameter in the current adjustment interface of the chip The present invention relates to a chip that has a plurality of adjustment interfaces of different types; the adjustment parameters are used to adjust the display effect of the display unit connected to the chip; the adjustment interface generation module is configured to: obtain and generate a current adjustment interface based on the spare sub-interface saved in the second cache of the two caches; wherein the storage address of the first cache is different from that of the second cache; upon receiving the first current interface update instruction sent by the control core and receiving the display request sent by the first cache, determine the first current sub-interface identifier in the first current interface update instruction; obtain the first current sub-interface corresponding to the first current sub-interface identifier among the multiple first spare sub-interfaces saved in the first cache; and load the first current sub-interface in the current adjustment interface of the chip.

[0005] In one possible embodiment, the control core is configured to: upon receiving an update request for an adjustment interface, determine the multiple standby sub-interfaces corresponding to the update request; when the multiple standby sub-interfaces corresponding to the update request are different from the multiple standby sub-interfaces stored in the two caches, and the data size of the multiple standby sub-interfaces corresponding to the update request is less than or equal to the storage space size of any one of the two caches, use the cache of the two caches that is not currently communicating and interacting with the adjustment interface generation module as the first cache; generate and send a first standby interface update instruction to the first cache; generate and send a first current interface update instruction to the adjustment interface generation module.

[0006] In one possible embodiment, the first cache is configured to: upon receiving a second standby interface update instruction, obtain and save a plurality of second standby sub-interfaces corresponding to the second standby interface update instruction in the flash memory; upon a situation where the available storage space in the first cache is less than a preset threshold, generate and send a transmission start instruction to the second cache, and stop communicating with the flash memory; the flash memory is configured to: upon determining that communication with the first cache has been stopped, determine a plurality of third standby sub-interfaces among the plurality of second standby sub-interfaces; wherein the third standby sub-interface is used to represent a second standby sub-interface that has not been obtained by the first cache; the second cache is further configured to: upon receiving a transmission sent by the first cache In the case of a start instruction, the multiple third spare sub-interfaces in the flash memory are obtained and saved; in the case of receiving a transmission end instruction corresponding to the multiple third spare sub-interfaces sent by the flash memory, a display request is sent to the adjustment interface generation module; the adjustment interface generation module is further configured to: in the case of receiving a second current interface update instruction sent by the control core and a display request sent by the second cache, determine the second current sub-interface identifier in the second current interface update instruction; obtain the second current sub-interface corresponding to the second current sub-interface identifier from the multiple second spare sub-interfaces saved in the first cache and the second cache; and load the second current sub-interface in the current adjustment interface of the chip.

[0007] In one possible embodiment, the control core is configured to: upon receiving an update request for an adjustment interface, determine the multiple standby sub-interfaces corresponding to the update request; if the multiple standby sub-interfaces corresponding to the update request are different from the multiple standby sub-interfaces stored in the two caches, and the data size of the multiple standby sub-interfaces corresponding to the update request is greater than the storage space size of any one of the two caches, use any one of the two caches as the first cache; generate and send a second standby interface update instruction to the first cache; generate and send a second current interface update instruction to the adjustment interface generation module.

[0008] In one possible embodiment, the chip is connected to multiple display units; the display unit is used to display the current adjustment interface; the display unit includes a display panel, and the display panel includes at least one of a liquid crystal display panel, a micro-light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel and a small-pitch display panel.

[0009] According to another aspect of the present disclosure, a display method is provided, which is applied to a chip, wherein the chip includes: a flash memory, two caches connected to the flash memory, an adjustment interface generation module connected to the two caches, and a control core connected to the two caches and the adjustment interface generation module; the display method includes: upon receiving a first standby interface update instruction sent by the control core, obtaining and saving a plurality of first standby sub-interfaces corresponding to the first standby interface update instruction in the flash memory through the first cache of the two caches; upon receiving a transmission end instruction corresponding to the plurality of first standby sub-interfaces sent by the flash memory, sending a display request to the adjustment interface generation module through the first cache of the two caches; wherein the plurality of first standby sub-interfaces are used to constitute a seed of adjustment parameters in the current adjustment interface of the chip. Different types of adjustment interfaces; the adjustment parameters are used to adjust the display effect of the display unit connected to the chip; through the adjustment interface generation module, obtain and generate the current adjustment interface based on the spare sub-interface saved in the second cache of the two caches; wherein the storage address of the first cache is different from that of the second cache; upon receiving the first current interface update instruction sent by the control core and receiving the display request sent by the first cache, determine the first current sub-interface identifier in the first current interface update instruction through the adjustment interface generation module; obtain the first current sub-interface corresponding to the first current sub-interface identifier among the multiple first spare sub-interfaces saved in the first cache through the adjustment interface generation module; load the first current sub-interface in the current adjustment interface of the chip through the adjustment interface generation module.

[0010] In a possible embodiment, the display method also includes: upon receiving an update request for the adjustment interface, determining, through the control core, a plurality of standby sub-interfaces corresponding to the update request; when the plurality of standby sub-interfaces corresponding to the update request are different from the plurality of standby sub-interfaces stored in the two caches, and the data size of the plurality of standby sub-interfaces corresponding to the update request is less than or equal to the storage space size of any one of the two caches, using, through the control core, the cache of the two caches that is not currently communicating and interacting with the adjustment interface generation module as the first cache; generating and sending, through the control core, a first standby interface update instruction to the first cache, and generating and sending a first current interface update instruction to the adjustment interface generation module.

[0011] In a possible embodiment, the display method further includes: when a second standby interface update instruction is received, obtaining and saving multiple second standby sub-interfaces corresponding to the second standby interface update instruction in the flash memory through the first cache; when the available storage space in the first cache is less than a preset threshold, generating and sending a transmission start instruction to the second cache through the first cache, and stopping communication interaction with the flash memory; when it is determined that communication interaction with the first cache has been stopped, determining multiple third standby sub-interfaces among the multiple second standby sub-interfaces through the flash memory; wherein the third standby sub-interface is used to represent the second standby sub-interface that has not been obtained by the first cache; upon receiving the transmission sent by the first cache In the case of receiving a transmission start instruction, the multiple third spare sub-interfaces in the flash memory are obtained and saved through the second cache; in the case of receiving a transmission end instruction corresponding to the multiple third spare sub-interfaces sent by the flash memory, a display request is sent to the adjustment interface generation module through the second cache; in the case of receiving a second current interface update instruction sent by the control core and a display request sent by the second cache, the second current sub-interface identifier in the second current interface update instruction is determined; the second current sub-interface corresponding to the second current sub-interface identifier in the multiple second spare sub-interfaces saved in the first cache and the second cache is obtained; and the second current sub-interface is loaded in the current adjustment interface of the chip.

[0012] In a possible embodiment, the display method also includes: when an update request for an adjustment interface is received, determining, through the control core, a plurality of standby sub-interfaces corresponding to the update request; when the plurality of standby sub-interfaces corresponding to the update request are different from the plurality of standby sub-interfaces stored in the two caches, and the data size of the plurality of standby sub-interfaces corresponding to the update request is greater than the storage space size of any one of the two caches, using, through the control core, any one of the two caches as the first cache; generating and sending, through the control core, a second standby interface update instruction to the first cache, and generating and sending a second current interface update instruction to the adjustment interface generation module.

[0013] In a possible implementation, the chip to which the display method is applied is the aforementioned chip.

[0014] According to another aspect of the present disclosure, a display device is provided, comprising a plurality of display units and the above chip.

[0015] An embodiment of the present disclosure provides a chip comprising: a flash memory, two caches connected to the flash memory, an adjustment interface generation module connected to the two caches, and a control core connected to the two caches and the adjustment interface generation module. A first cache of the two caches is configured to, upon receiving a first backup interface update instruction from the control core, retrieve and save multiple first backup sub-interfaces corresponding to the first backup interface update instruction in the flash memory. Upon receiving a transfer end instruction corresponding to the multiple first backup sub-interfaces from the flash memory, send a display request to the adjustment interface generation module. The adjustment interface generation module is configured to retrieve and generate a current adjustment interface based on the backup sub-interfaces saved in the second cache of the two caches. Upon receiving both the first current interface update instruction from the control core and a display request from the first cache, the module determines a first current sub-interface identifier in the first current interface update instruction. Retrieve a first current sub-interface corresponding to the first current sub-interface identifier from the multiple first backup sub-interfaces saved in the first cache. Load the first current sub-interface into the current adjustment interface of the chip. The disclosed embodiment can support the first cache to obtain the spare sub-interface in the flash memory and adjust the interface generation module to obtain the spare sub-interface in the second cache at the same time, thereby reducing the duration of the black screen phenomenon of the OSD in related technologies, which is beneficial to the adaptability of the OSD to display devices with higher refresh rates.

[0016] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0018] Figure 1 A block diagram of a chip provided according to an embodiment of the present disclosure is shown.

[0019] Figure 2 A reference schematic diagram of a chip provided according to an embodiment of the present disclosure is shown.

[0020] Figure 3 A flow chart of a display method provided according to an embodiment of the present disclosure is shown.

[0021] Figure 4 A block diagram of an electronic device provided according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0022] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0023] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0024] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0025] In this disclosure, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on specific circumstances.

[0026] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of three situations: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0027] In the related art, the OSD function can be implemented through character-type display. In the character-type display, the display content of the OSD will be cut into blocks according to the format and stored in the flash memory. When the OSD needs to switch the adjustment interface, the backup adjustment interface to be called needs to be dynamically moved from the flash memory to the SRAM (Static Random Access Memory), and then the corresponding data is extracted from the SRAM through the character index number. When the table item switches in the OSD adjustment interface (for example: calling out another interface in the adjustment interface), in order to ensure that the table item update operation does not affect the OSD display effect, the related art only allows the above-mentioned transfer process to be performed during the period when the OSD is not displayed. This is likely to cause the following problems: when the menu items are very complex or the refresh rate of the display device is very high, the time during which the OSD is not displayed is not long enough to transfer data from the flash memory to the SRAM, which can easily lead to disordered OSD display.

[0028] In view of this, an embodiment of the present disclosure provides a chip comprising: a flash memory, two cache memories connected to the flash memory, an adjustment interface generation module connected to the two cache memories, and a control core connected to the two cache memories and the adjustment interface generation module. A first cache memory of the two cache memories is configured to, upon receiving a first backup interface update instruction from the control core, retrieve and save multiple first backup sub-interfaces corresponding to the first backup interface update instruction in the flash memory. Upon receiving a transfer end instruction corresponding to the multiple first backup sub-interfaces from the flash memory, send a display request to the adjustment interface generation module. The adjustment interface generation module is configured to retrieve and generate a current adjustment interface based on the backup sub-interfaces saved in the second cache memory of the two cache memories. Upon receiving both the first current interface update instruction from the control core and a display request from the first cache memory, the chip determines a first current sub-interface identifier in the first current interface update instruction. Retrieve a first current sub-interface corresponding to the first current sub-interface identifier from the multiple first backup sub-interfaces saved in the first cache memory. Load the first current sub-interface into the current adjustment interface of the chip. The disclosed embodiment can support the first cache to obtain the spare sub-interface in the flash memory and adjust the interface generation module to obtain the spare sub-interface in the second cache at the same time, thereby reducing the duration of the black screen phenomenon of the OSD in related technologies, which is beneficial to the adaptability of the OSD and chips with higher refresh rates.

[0029] See Figure 1 As shown, Figure 1 A block diagram of a chip according to an embodiment of the present disclosure is shown, Figure 1As shown, the chip 100 may include: a flash memory 110, two caches connected to the flash memory 110 (wherein the two caches include a first cache 120 and a second cache 130), an adjustment interface generation module 140 connected to the two caches, and a control core 150 connected to the two caches and the adjustment interface generation module 140. For example, the developer can select the corresponding storage medium for the above-mentioned flash memory and cache according to needs, and the embodiments of the present disclosure are not limited here. For example, the above-mentioned chip can be built into a display device.

[0030] The first cache of the two caches is configured to: upon receiving the first standby interface update instruction sent by the control core, obtain and save the multiple first standby sub-interfaces corresponding to the first standby interface update instruction in the flash memory. Upon receiving the transmission end instruction corresponding to the multiple first standby sub-interfaces sent by the flash memory, send a display request to the adjustment interface generation module. The multiple first standby sub-interfaces are used to constitute an adjustment interface that is different from the type of adjustment parameters in the current adjustment interface of the chip. Exemplarily, the type of adjustment parameters of the current adjustment interface may be "overview of adjustable parameters", and the type of adjustment parameters corresponding to the multiple first standby sub-interfaces may be "adjustment of specific brightness values". The adjustment parameters are used to adjust the display effect of the display unit connected to the chip. For example, the above-mentioned adjustment parameters may include: contrast, resolution, brightness, etc. Exemplarily, the above-mentioned first standby interface update instruction can be triggered in response to the user pressing a physical button or a virtual button on the display device (for example: the menu call-out button on the display device), and the multiple first standby sub-interfaces include all sub-interfaces that the user may use in the current adjustment interface. For example: the standby sub-interface can be expressed as a specific value of brightness, and each value can correspond to a sub-interface. When the user adjusts, the corresponding sub-interface data is retrieved and loaded into the current adjustment interface to achieve visual adjustment of the brightness value. Here, only the numerical adjustment of brightness is taken as an example, and it can also be a table item switch of the adjustment interface (for example, calling out a numerical adjustment interface of an adjustment parameter in the current adjustment interface). Exemplarily, the above-mentioned transmission end instruction is used to indicate that the first standby sub-interfaces in the flash memory have been transferred, so as to ensure the data integrity of the first standby sub-interface. The above-mentioned transmission end instruction can also be expressed as a data identifier, etc., and the embodiment of the present disclosure is not limited here, and it can be expressed as the end of the transmission.

[0031] The adjustment interface generation module is configured to retrieve and generate a current adjustment interface based on the backup sub-interface stored in the second of the two caches. The first and second caches have different storage addresses. Exemplarily, the adjustment interface generation module can interact with only one cache at a time. The cache not currently interacting with the adjustment interface generation module can access the memory upon receiving a current interface update instruction. In the disclosed embodiment, the first and second caches have independent data transmission paths. At the same time, one of the two caches can communicate with the adjustment interface generation module, while the other can communicate with the flash memory. Therefore, the disclosed embodiment does not close the OSD currently displayed on the display device, thereby reducing the duration of the OSD black screen. Upon receiving a first current interface update instruction from the control core and a display request from the first cache, a first current sub-interface identifier in the first current interface update instruction is determined. Exemplarily, the first current interface update instruction and the first backup interface update instruction described above can be triggered simultaneously in response to a user pressing a physical or virtual button on the display device. The first current sub-interface identifier in the first current interface update instruction indicates the data content currently to be displayed. For example: if the user presses a physical button or a virtual button to call the brightness adjustment interface to adjust the specific value of the brightness (if the range is 0-100), then the brightness 0-100 is the sub-interface that the user may need to use later, and the first standby interface update instruction can be used to call out the standby sub-interface corresponding to 0-100. If the user wants to adjust it to 50 this time, the first current interface update instruction is used to call out the sub-interface corresponding to 50. The adjustment interface generation module then obtains the first current sub-interface corresponding to the first current sub-interface identifier among the multiple first standby sub-interfaces saved in the first cache. The first current sub-interface is loaded in the current adjustment interface of the chip. Exemplarily, the first current sub-interface can be loaded on top of the current adjustment interface. In one example, the transparency of the current adjustment interface can also be processed to improve the display effect, which is not limited in the embodiments of the present disclosure.

[0032] In one possible embodiment, the control core is configured to: upon receiving an update request for an adjustment interface, determine the multiple standby sub-interfaces corresponding to the update request. When the multiple standby sub-interfaces corresponding to the update request are different from the multiple standby sub-interfaces stored in the two caches, and the data size of the multiple standby sub-interfaces corresponding to the update request is less than or equal to the storage space size of any one of the two caches, the cache in the two caches that is not currently communicating and interacting with the adjustment interface generation module is used as the first cache. Generate and send a first standby interface update instruction to the first cache. Generate and send a first current interface update instruction to the adjustment interface generation module. Exemplarily, the above-mentioned update request can be expressed as a user pressing a physical button or a virtual button on a display device. For example: the above-mentioned update request can correspond to a first identifier (or each callable table entry can correspond to a first identifier), and the multiple standby sub-interfaces stored in the cache can correspond to a second identifier. When the first identifier and the second identifier are different, it can be regarded that the multiple standby sub-interfaces corresponding to the update request are different from the multiple standby sub-interfaces stored in the cache. In one example, the storage space sizes of the above-mentioned two caches can be set to be the same or different, and the embodiments of the present disclosure do not impose any restrictions on this. For example, the two caches can also directly set the storage mode, that is, the control core does not compare the data size of the multiple standby sub-interfaces corresponding to the update request with the storage space size of any one of the two caches. In other words, when the cache is in the preset first mode and the multiple standby sub-interfaces corresponding to the update request are different from the multiple standby sub-interfaces stored in the two caches, the cache in the two caches that is not currently communicating and interacting with the adjustment interface generation module is directly used as the first cache. Developers can also adjust the selection rules of the first cache according to the actual application scenario, and the embodiments of the present disclosure do not impose any restrictions on this. The preset mode of the above-mentioned cache can be saved in the above-mentioned control core.

[0033] In one possible embodiment, the first cache is configured to, upon receiving a second standby interface update instruction, retrieve and save multiple second standby sub-interfaces corresponding to the second standby interface update instruction in the flash memory. If the available storage space in the first cache is less than a preset threshold, a transfer start instruction is generated and sent to the second cache, and communication with the flash memory is stopped. For example, the preset threshold can be set based on the developer's actual needs and is not limited in this embodiment of the present disclosure. The flash memory is configured to, upon determining that communication with the first cache has ceased, identify multiple third standby sub-interfaces from the multiple second standby sub-interfaces. The third standby sub-interfaces represent second standby sub-interfaces that have not been retrieved by the first cache. For example, a pause flag can be set during the transmission of the second standby sub-interfaces. If the first cache ceases communication with the flash memory, the pause flag can be used to identify the third standby sub-interfaces in the first cache that have not been saved by the first cache. In one example, determining that communication with the first cache has ceased can include any of the following: the first cache sending a stop interaction instruction to the flash memory, or the flash memory not exchanging data with the first cache for a certain period of time (the specific value of which can be set by the developer based on actual conditions). The second cache is further configured to, upon receiving a transfer start instruction from the first cache, retrieve and save the multiple third standby sub-interfaces in the flash memory. Upon receiving a transfer end instruction from the flash memory corresponding to the multiple third standby sub-interfaces, send a display request to the adjustment interface generation module. Exemplarily, the transfer start instruction indicates that the first cache has completed storage and that the second cache begins storing the third standby sub-interfaces in the flash memory. The adjustment interface generation module is further configured to, upon receiving a second current interface update instruction from the control core and a display request from the second cache, determine the second current sub-interface identifier in the second current interface update instruction. Retrieve the second current sub-interface corresponding to the second current sub-interface identifier from the multiple second standby sub-interfaces stored in the first and second caches. Load the second current sub-interface into the current adjustment interface of the chip. In this disclosed embodiment, two caches can be combined to form a larger cache to load an OSD adjustment interface with a larger data volume for display on the display device screen. For example, if the size of each cache is 4KB, the two caches can store an OSD adjustment interface of up to 8KB in size, thereby improving the display quality of the OSD adjustment interface. For example, here, the storage space of each cache is 4KB. The physical address of one of the two caches can be 0x00 to 0xFFF, and the physical address of the other cache can be 0x1000 to 0x1FFF. The physical addresses of the two caches can be continuous.

[0034] In one possible embodiment, the control core is configured to: upon receiving an update request for an adjustment interface, determine the multiple backup sub-interfaces corresponding to the update request. If the multiple backup sub-interfaces corresponding to the update request differ from the multiple backup sub-interfaces stored in the two caches, and the data size of the multiple backup sub-interfaces corresponding to the update request is greater than the storage space size of either of the two caches, select either of the two caches as the first cache. Generate and send a second backup interface update instruction to the first cache. Generate and send a second current interface update instruction to the adjustment interface generation module. For example, the two caches may also be directly set to a storage mode, i.e., the control core does not compare the data size of the multiple backup sub-interfaces corresponding to the update request with the storage space size of either of the two caches. In other words, if the cache is in a preset second mode and the multiple backup sub-interfaces corresponding to the update request differ from the multiple backup sub-interfaces stored in the two caches, select either of the two caches as the first cache. Developers may also adjust the selection rules for the first cache based on actual application scenarios, and this disclosure is not limiting. The preset mode of the cache and the selection rule of the first cache can be saved in the control core.

[0035] In one possible embodiment, the chip may be connected to multiple display units. The display units are used to display the current adjustment interface. The display units include display panels, which include at least one of a liquid crystal display panel, a micro-LED display panel, a light-emitting diode display panel, a mini-LED display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a fine-pitch display panel.

[0036] See Figure 2 As shown, Figure 2 FIG2 shows a reference schematic diagram of a chip provided according to an embodiment of the present disclosure. Figure 2, the first standby interface update instruction and the second standby interface update instruction can be expressed as two instructions with different flags of a specific flag bit in an instruction. For example, a specific flag bit of "0" can represent a first standby interface update instruction, and a specific flag bit of "1" can represent a second standby interface update instruction, etc. For example, when the first cache and the second cache receive the second standby interface update instruction, they will act as a larger cache to obtain the standby sub-interface stored in the flash memory. When the first cache receives the first standby interface update instruction, it obtains the standby sub-interface stored in the flash memory. The second cache interacted with the adjustment interface generation module in the previous time period. In the embodiment of the present disclosure, the adjustment interface generation module may temporarily not disconnect the interaction with the second cache until the standby sub-interface in the first cache is stored, and then start communicating and interacting with the first cache. For example, the control core can send an instruction message to any one of the two caches (or according to a preset rule, such as one of the caches always acts as the first cache) to make it the first cache in this transmission process. The embodiment of the present disclosure does not limit the specific information composition here, and the developer can set it according to the actual situation.

[0037] See Figure 3 As shown, Figure 3 A flow chart of a display method according to an embodiment of the present disclosure is shown. Figure 3 As shown, the display method is applied to a chip, the chip comprising: a flash memory, two caches connected to the flash memory, an adjustment interface generation module connected to the two caches, and a control core connected to the two caches and the adjustment interface generation module. The display method comprises:

[0038] Step S100 , upon receiving a first standby interface update instruction sent by the control core, obtaining and saving a plurality of first standby sub-interfaces corresponding to the first standby interface update instruction in the flash memory through a first cache of the two caches.

[0039] Step S200: Upon receiving a transmission end instruction corresponding to the plurality of first standby sub-interfaces sent by the flash memory, a display request is sent to the adjustment interface generation module via the first cache of the two caches. The plurality of first standby sub-interfaces are used to form adjustment interfaces of a different type than the adjustment parameters in the current adjustment interface of the chip. The adjustment parameters are used to adjust the display effect of a display unit connected to the chip.

[0040] Step S300: The adjustment interface generation module obtains and generates a current adjustment interface based on a standby sub-interface stored in a second cache of the two caches, wherein the first cache and the second cache have different storage addresses.

[0041] Step S400: upon receiving the first current interface update instruction sent by the control core and the display request sent by the first cache, the adjustment interface generation module determines the first current sub-interface identifier in the first current interface update instruction.

[0042] Step S500: Acquire, through the adjustment interface generation module, a first current sub-interface corresponding to the first current sub-interface identifier among the multiple first standby sub-interfaces stored in the first cache.

[0043] Step S600: Loading the first current sub-interface into the current adjustment interface of the chip through the adjustment interface generation module.

[0044] In a possible embodiment, the display method also includes: upon receiving an update request for the adjustment interface, determining, through the control core, a plurality of standby sub-interfaces corresponding to the update request; when the plurality of standby sub-interfaces corresponding to the update request are different from the plurality of standby sub-interfaces stored in the two caches, and the data size of the plurality of standby sub-interfaces corresponding to the update request is less than or equal to the storage space size of any one of the two caches, using, through the control core, the cache of the two caches that is not currently communicating and interacting with the adjustment interface generation module as the first cache; generating and sending, through the control core, a first standby interface update instruction to the first cache, and generating and sending a first current interface update instruction to the adjustment interface generation module.

[0045] In a possible embodiment, the display method further includes: when a second standby interface update instruction is received, obtaining and saving multiple second standby sub-interfaces corresponding to the second standby interface update instruction in the flash memory through the first cache; when the available storage space in the first cache is less than a preset threshold, generating and sending a transmission start instruction to the second cache through the first cache, and stopping communication interaction with the flash memory; when it is determined that communication interaction with the first cache has been stopped, determining multiple third standby sub-interfaces among the multiple second standby sub-interfaces through the flash memory; wherein the third standby sub-interface is used to represent the second standby sub-interface that has not been obtained by the first cache; upon receiving the transmission sent by the first cache In the case of receiving a transmission start instruction, the multiple third spare sub-interfaces in the flash memory are obtained and saved through the second cache; in the case of receiving a transmission end instruction corresponding to the multiple third spare sub-interfaces sent by the flash memory, a display request is sent to the adjustment interface generation module through the second cache; in the case of receiving a second current interface update instruction sent by the control core and a display request sent by the second cache, the second current sub-interface identifier in the second current interface update instruction is determined; the second current sub-interface corresponding to the second current sub-interface identifier in the multiple second spare sub-interfaces saved in the first cache and the second cache is obtained; and the second current sub-interface is loaded in the current adjustment interface of the chip.

[0046] In a possible embodiment, the display method also includes: when an update request for an adjustment interface is received, determining, through the control core, a plurality of standby sub-interfaces corresponding to the update request; when the plurality of standby sub-interfaces corresponding to the update request are different from the plurality of standby sub-interfaces stored in the two caches, and the data size of the plurality of standby sub-interfaces corresponding to the update request is greater than the storage space size of any one of the two caches, using, through the control core, any one of the two caches as the first cache; generating and sending, through the control core, a second standby interface update instruction to the first cache, and generating and sending a second current interface update instruction to the adjustment interface generation module.

[0047] In a possible implementation, the chip to which the display method is applied is the chip described above.

[0048] According to another aspect of the present disclosure, a display device is provided, comprising a plurality of display units and the above chip.

[0049] For example, the display device, or electronic device, in this embodiment includes, but is not limited to, desktop computers, televisions, mobile devices with large screens such as mobile phones and tablet computers, and other common electronic devices that require multiple chips to be cascaded to achieve driving. For example, the above-mentioned electronic devices may include the chips described above.

[0050] Exemplarily, the electronic device may also be user equipment (UE), mobile device, user terminal, terminal, handheld device, computing device or vehicle-mounted device, etc. Exemplarily, some examples of terminals include: display, smart phone or portable device, mobile phone, tablet computer, laptop computer, PDA, mobile Internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control (Industrial Control), wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid (Smart Grid), wireless terminal in transportation safety (Transportation Safety), wireless terminal in smart city (Smart City), wireless terminal in smart home (Smart Home), wireless terminal in Internet of Vehicles, etc. For example, the server may be a local server or a cloud server.

[0051] Figure 4 FIG1 shows a block diagram of an electronic device 1900 provided according to an embodiment of the present disclosure. For example, the electronic device 1900 can be provided as a server or a terminal device. Figure 4 The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above-described method.

[0052] The electronic device 1900 may further include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, or the like.

[0053] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0054] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the scope of protection of the present invention. The scope of protection of the present invention is determined by the appended claims.

[0055] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0056] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0057] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0058] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A chip, characterized in that: The chip includes: a flash memory, two caches connected to the flash memory, an adjustment interface generation module connected to the two caches, and a control core connected to the two caches and the adjustment interface generation module; The first cache of the two caches is configured to: upon receiving a first standby interface update instruction sent by the control core, obtain and save a plurality of first standby sub-interfaces corresponding to the first standby interface update instruction in the flash memory; upon receiving a transmission end instruction corresponding to the plurality of first standby sub-interfaces sent by the flash memory, send a display request to the adjustment interface generation module; wherein the plurality of first standby sub-interfaces are used to constitute an adjustment interface of a type different from that of adjustment parameters in the current adjustment interface of the chip; and the adjustment parameters are used to adjust a display effect of a display unit connected to the chip; The adjustment interface generation module is configured to: obtain and generate a current adjustment interface based on the backup sub-interface saved in the second cache of the two caches; wherein the storage addresses of the first cache and the second cache are different; upon receiving the first current interface update instruction sent by the control core and the display request sent by the first cache, determine the first current sub-interface identifier in the first current interface update instruction; obtain the first current sub-interface corresponding to the first current sub-interface identifier among the multiple first backup sub-interfaces saved in the first cache; and load the first current sub-interface in the current adjustment interface of the chip.

2. The chip according to claim 1, wherein: The control core is configured to: upon receiving an update request for an adjustment interface, determine a plurality of standby sub-interfaces corresponding to the update request; and if the plurality of standby sub-interfaces corresponding to the update request are different from the plurality of standby sub-interfaces stored in the two caches, and if the data size of the plurality of standby sub-interfaces corresponding to the update request is less than or equal to the storage space size of any one of the two caches, use the cache of the two caches that is not currently communicating and interacting with the adjustment interface generation module as the first cache; generating and sending a first standby interface update instruction to the first cache; Generate and send a first current interface update instruction to the adjustment interface generation module.

3. The chip according to claim 1, wherein: The first cache is configured to: upon receiving a second standby interface update instruction, obtain and save a plurality of second standby sub-interfaces corresponding to the second standby interface update instruction in the flash memory; When the available storage space in the first cache is less than a preset threshold, generating and sending a transmission start instruction to the second cache, and stopping communication interaction with the flash memory; The flash memory is configured to: determine a plurality of third standby sub-interfaces among the plurality of second standby sub-interfaces when it is determined that the communication interaction with the first cache has stopped; wherein the third standby sub-interfaces are used to represent second standby sub-interfaces that have not been acquired by the first cache; The second cache is further configured to: upon receiving a transmission start instruction sent by the first cache, obtain and save the multiple third standby sub-interfaces in the flash memory; upon receiving a transmission end instruction corresponding to the multiple third standby sub-interfaces sent by the flash memory, send a display request to the adjustment interface generation module; The adjustment interface generation module is further configured to: determine the second current sub-interface identifier in the second current interface update instruction when receiving the second current interface update instruction sent by the control core and the display request sent by the second cache; obtain the second current sub-interface corresponding to the second current sub-interface identifier from the multiple second standby sub-interfaces saved in the first cache and the second cache; and load the second current sub-interface in the current adjustment interface of the chip.

4. The chip according to claim 3, wherein: The control core is configured to: upon receiving an update request for adjusting an interface, determine a plurality of standby sub-interfaces corresponding to the update request; and if the plurality of standby sub-interfaces corresponding to the update request are different from the plurality of standby sub-interfaces stored in the two caches, and if the data size of the plurality of standby sub-interfaces corresponding to the update request is larger than the storage space size of any one of the two caches, use any one of the two caches as the first cache; generating and sending a second standby interface update instruction to the first cache; Generate and send a second current interface update instruction to the adjustment interface generation module.

5. The chip according to any one of claims 1 to 4, characterized in that: The chip is connected to multiple display units; the display units are used to display the current adjustment interface; the display units include display panels, and the display panels include at least one of a liquid crystal display panel, a micro-light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small-pitch display panel.

6. A display method, applied to a chip, characterized in that: The chip includes: a flash memory, two caches connected to the flash memory, an adjustment interface generation module connected to the two caches, and a control core connected to the two caches and the adjustment interface generation module; the display method includes: Upon receiving a first standby interface update instruction sent by the control core, acquiring and saving, through a first cache of the two caches, a plurality of first standby sub-interfaces corresponding to the first standby interface update instruction in the flash memory; Upon receiving a transmission end instruction corresponding to the plurality of first standby sub-interfaces sent by the flash memory, sending a display request to the adjustment interface generation module through the first cache of the two caches; wherein the plurality of first standby sub-interfaces are used to constitute an adjustment interface of a type different from that of adjustment parameters in the current adjustment interface of the chip; and the adjustment parameters are used to adjust a display effect of a display unit connected to the chip; The adjustment interface generation module acquires and generates a current adjustment interface based on a standby sub-interface stored in a second cache of the two caches; wherein the storage addresses of the first cache and the second cache are different; Upon receiving the first current interface update instruction sent by the control core and the display request sent by the first buffer, determining, by the adjustment interface generation module, the first current sub-interface identifier in the first current interface update instruction; Obtaining, by the adjustment interface generation module, a first current sub-interface corresponding to the first current sub-interface identifier among the multiple first standby sub-interfaces stored in the first cache; The first current sub-interface is loaded into the current adjustment interface of the chip through the adjustment interface generation module.

7. The display method according to claim 6, wherein: The display method further includes: In the case of receiving an update request for adjusting the interface, determining, by the control core, a plurality of standby sub-interfaces corresponding to the update request; In a case where the multiple standby sub-interfaces corresponding to the update request are different from the multiple standby sub-interfaces stored in the two caches, and the data size of the multiple standby sub-interfaces corresponding to the update request is less than or equal to the storage space size of any one of the two caches, the control core uses the cache of the two caches that is not currently communicating and interacting with the adjustment interface generation module as the first cache; The control core generates and sends a first standby interface update instruction to the first cache, and generates and sends a first current interface update instruction to the adjustment interface generation module.

8. The display method according to claim 6, wherein: The display method further includes: When a second standby interface update instruction is received, obtaining and saving, through the first cache, a plurality of second standby sub-interfaces corresponding to the second standby interface update instruction in the flash memory; When the available storage space in the first cache is less than a preset threshold, generating and sending a transmission start instruction to the second cache through the first cache, and stopping communication interaction with the flash memory; In the case where it is determined that the communication interaction with the first cache has stopped, determining, through the flash memory, a plurality of third spare sub-interfaces among the plurality of second spare sub-interfaces; wherein the third spare sub-interfaces are used to represent second spare sub-interfaces that have not been acquired by the first cache; Upon receiving the transmission start instruction sent by the first cache, acquiring and saving the plurality of third standby sub-interfaces in the flash memory through the second cache; When receiving the transmission end instruction corresponding to the plurality of third standby sub-interfaces sent by the flash memory, sending a display request to the adjustment interface generation module through the second cache; Upon receiving a second current interface update instruction sent by the control core and a display request sent by the second cache, determine the second current sub-interface identifier in the second current interface update instruction; obtain the second current sub-interface corresponding to the second current sub-interface identifier from the multiple second standby sub-interfaces saved in the first cache and the second cache; and load the second current sub-interface in the current adjustment interface of the chip.

9. The display method according to claim 8, wherein: The display method further includes: In the case of receiving an update request for adjusting the interface, determining, by the control core, a plurality of standby sub-interfaces corresponding to the update request; In a case where the multiple standby sub-interfaces corresponding to the update request are different from the multiple standby sub-interfaces stored in the two caches, and the data size of the multiple standby sub-interfaces corresponding to the update request is larger than the storage space size of any one of the two caches, using, by the control core, any one of the two caches as the first cache; The control core generates and sends a second standby interface update instruction to the first cache, and generates and sends a second current interface update instruction to the adjustment interface generation module.

10. The display method according to any one of claims 6 to 9, characterized in that: The chip is the chip according to any one of claims 1 to 5.

11. A display device, characterized in that: The display device includes a plurality of display units and the chip according to any one of claims 1 to 5.

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