A circuit simulation model and modeling method of ferroelectric negative capacitance transistor
By establishing the cross-sectional structure of ferroelectric devices and calculating the bias voltage, and combining the Poisson equation and the Landau-Khalatnikov equation, an analytical channel current model is constructed, which solves the problems of low modeling accuracy and slow simulation speed of MFMIS negative capacitance transistor devices, and realizes efficient circuit simulation and design guidance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGXI NORMAL UNIV
- Filing Date
- 2022-11-07
- Publication Date
- 2026-05-29
AI Technical Summary
Existing MFMIS negative capacitance transistor device modeling methods have low accuracy and slow simulation speed, and cannot effectively perform multi-device circuit simulation. The physical mechanism of commercial BSIM models is unclear and cannot be adjusted.
A cross-sectional structure of the ferroelectric device was established, the bias voltage of the MOSFET device was set, the surface charge density was calculated using the Poisson equation and Gaussian boundary conditions, and an analytical channel current model was constructed by combining the current continuity equation and the Landau-Khalatnikov equation. The circuit simulation of the ferroelectric device was achieved by compiling the model using Verilog-A language.
It improves simulation accuracy and speed, achieves compatibility with mainstream commercial circuit simulators, is suitable for logic computing, storage and neuromorphic computing, and has clear physical meaning and high versatility.
Smart Images
Figure CN116205192B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a circuit simulation model and modeling method for a ferroelectric negative capacitance transistor. Background Technology
[0002] Currently, there are two main methods for modeling the electrical characteristics of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) negative capacitance transistor (NC-FET) devices both domestically and internationally: (1) Based on commercial numerical simulators such as Sentaurus and Silvaco, this method is actually a finite element method based on solving a series of semiconductor physical equations. It has a slow calculation speed, consumes a lot of computational and storage resources, and has poor convergence. It cannot simulate circuits containing multiple devices. (2) Based on the coupled solution method of commercial BSIM models of benchmark MOSFET devices and Landau-Khalatnikov equations.
[0003] However, commercial BSIM models suffer from unclear physical mechanism images due to the large number of fitting parameters and the limitation of allowing users to modify only a few model parameters such as gate length and gate width. Furthermore, the device structure and physical mechanism modeled by commercial BSIM models are fixed, preventing users from adjusting them according to actual conditions. Summary of the Invention
[0004] The purpose of this invention is to provide a circuit simulation model and modeling method for ferroelectric negative capacitance transistors, aiming to solve the problems of low accuracy and slow simulation speed of existing modeling methods.
[0005] To achieve the above objectives, in a first aspect, the present invention provides a modeling method for a circuit simulation model of a ferroelectric negative capacitance transistor, comprising the following steps:
[0006] Establish the cross-sectional structure of the ferroelectric device and set the bias voltages of the gate, drain and source of the reference MOSFET device;
[0007] The source surface charge density and drain surface charge density are calculated based on the bias voltage of the drain and the source.
[0008] The channel current of the reference MOSFET device is obtained based on the source surface charge density and the drain surface charge density;
[0009] Calculate the gate surface charge density of a reference MOSFET device;
[0010] The total gate voltage of the entire ferroelectric device is obtained by the gate surface charge density.
[0011] A circuit simulation model of the entire ferroelectric device is constructed based on the channel current and the total gate voltage.
[0012] The specific method for calculating the source surface charge density and drain surface charge density based on the bias voltages of the drain and the source is as follows:
[0013] The source surface charge density and drain surface charge density are obtained by calculating based on the bias voltages of the drain and the source using the Poisson equation and the Gaussian boundary condition equation.
[0014] The specific method for obtaining the channel current of the reference MOSFET device through the source surface charge density and the drain surface charge density is as follows:
[0015] The channel current of the reference MOSFET device is calculated using explicit equations based on the source surface charge density and the drain surface charge density.
[0016] The specific method for calculating the gate surface charge density of the reference MOSFET device is as follows:
[0017] The gate surface charge density of the reference MOSFET device was calculated using the current continuity equation and the charge division method.
[0018] The specific method for obtaining the total gate voltage of the entire ferroelectric device through the gate surface charge density is as follows:
[0019] The total gate voltage of the entire ferroelectric device is calculated using the Landau-Kharatnikov phase transition equation based on the gate surface charge density.
[0020] Secondly, a ferroelectric negative capacitance transistor simulation circuit simulator model is constructed using the modeling method for the ferroelectric negative capacitance transistor circuit simulation model described in the first aspect.
[0021] The simulation model of the ferroelectric negative capacitance transistor circuit includes a series combination of a reference MOSFEF device and a ferroelectric capacitor electrical characteristic model.
[0022] This invention proposes a circuit simulation model and modeling method for a ferroelectric negative capacitance transistor. It establishes a cross-sectional structure of the ferroelectric device and sets the bias voltages for the gate, drain, and source of a reference MOSFET device. Based on the bias voltages of the drain and source, the source and drain surface charge densities are calculated. The channel current of the reference MOSFET device is obtained based on the source and drain surface charge densities. The gate surface charge density of the MOSFET device is calculated, and the total gate voltage of the entire ferroelectric device is obtained from the gate surface charge density. A complete circuit simulation model of the ferroelectric device is constructed based on the channel current and the total gate voltage. Starting from the Poisson equation, the current continuity equation, and the Landau-Khalatnikov equation, this invention obtains fully analytical expressions for the channel current and terminal charge density. Compiled using Verilog-A, it achieves compatibility with mainstream commercial circuit simulators, thus solving the problems of low accuracy and slow simulation speed of existing modeling methods. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a flowchart of a circuit simulation modeling method for a ferroelectric negative capacitance transistor provided by the present invention.
[0025] Figure 2 This is a diagram showing the steps involved in modeling an MFMIS NC-FET device.
[0026] Figure 3 This is a cross-sectional view of the dual-gate MFMIS NC-FET device structure.
[0027] Figure 4 This is a transfer characteristic curve of a dual-gate MFMIS NC-FET device.
[0028] Figure 5 This is a graph showing the output characteristics of a dual-gate MFMIS NC-FET device.
[0029] Figure 6 This is the channel current-source bias curve of a dual-gate MFMIS NC-FET device.
[0030] Figure 7 This is a schematic diagram of the circuit simulation model of a ferroelectric NC-FET device. Detailed Implementation
[0031] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.
[0032] Please see Figures 1 to 7 In a first aspect, the present invention provides a modeling method for a circuit simulation model of a ferroelectric negative capacitance transistor, comprising the following steps:
[0033] S1 establishes the cross-sectional structure of the ferroelectric device and sets the bias voltages of the gate, drain, and source of the reference MOSFET device;
[0034] Specifically, a cross-sectional structure of the ferroelectric device is established, and the bias voltages of the gate (gi), drain (d), and source (s) of the reference MOSFET device are set to Vi, ... gi V d and V s .
[0035] S2 calculates the source surface charge density and drain surface charge density based on the bias voltage of the drain and the source.
[0036] The source surface charge density and drain surface charge density are obtained by calculating based on the bias voltages of the drain and the source using the Poisson equation and the Gaussian boundary condition equation.
[0037] Specifically, the Q s and the Q d The calculation formula is:
[0038]
[0039]
[0040] In formulas (1) and (2), C in =ε in / t in ε is the capacitance per unit area of the insulating oxide layer. in and t in These represent the dielectric constant and thickness of the insulating oxide layer, respectively. th =k B T / q is the thermal voltage, where k B Here, q is Boltzmann's constant, T is the absolute temperature, and q is the elementary electron charge, Q0 = 4v. th C in V0 is a parameter dependent on temperature and device geometry, and it is the threshold voltage of a long-channel dual-gate reference MOSFET device, expressed as:
[0041]
[0042] In formula (3), This represents the work function difference between the gate metal and channel material of the reference MOSFET device. i This represents the intrinsic carrier concentration of the channel material. The source / drain surface charge density Q is calculated using the Poisson equation and the Gaussian boundary condition equation. s and Q d .
[0043] S3 obtains the channel current of the reference MOSFET device based on the source surface charge density and the drain surface charge density;
[0044] The channel current of the reference MOSFET device is calculated using the Pao-Sah double integral equation based on the source surface charge density and the drain surface charge density.
[0045] Specifically, the formula for calculating the channel current is as follows:
[0046]
[0047] Q s and Q d The values are calculated using formulas (1) and (2), respectively. μ is the constant carrier mobility, and W and L are the gate width and gate length of the device, respectively. C si The capacitance per unit area of the channel is calculated using the following formula: ε si / t si ε si t is the dielectric constant of the channel material. si This refers to the channel thickness.
[0048] S4 calculates the gate surface charge density of a reference MOSFET device;
[0049] The gate surface charge density of the reference MOSFET device was calculated using the current continuity equation and the charge division method.
[0050] Specifically, the formula for calculating the gate surface charge density of the reference MOSFET device is as follows:
[0051]
[0052] In formula (5), F(Q) s Q d ) and G(Q s Q d () is an intermediate variable, and the expression is as follows:
[0053]
[0054]
[0055] In formulas (6) and (7), where Q s and Q d The results are obtained by formulas (1) and (2) respectively.
[0056] The gate surface charge density, Q, of the reference MOSFET device is calculated using the current continuity equation and the Ward-Dutton charge partitioning method. av .
[0057] S5 obtains the total gate voltage of the entire ferroelectric device through the gate surface charge density;
[0058] The total gate voltage of the entire ferroelectric device is calculated using the Landau-Khalatnikov phase transition equation based on the gate surface charge density.
[0059] Specifically, the formula for calculating the total gate voltage of the ferroelectric NC-FET device is as follows:
[0060]
[0061] In formula (8), Q av The values are calculated from equation (5). α, β, and γ are Landau parameters of the ferroelectric material, which are related to the specific type of ferroelectric material and temperature. ρ is the constant damping coefficient that depends on the specific ferroelectric material.
[0062] S6 constructs a complete circuit simulation model of the ferroelectric device based on the channel current and the total gate voltage.
[0063] The specific equations (1)-(8) establish I ds With port bias V g V s V d The direct mathematical relationship between them was used to construct a complete analytical channel current model for the MFMIS NC-FET device.
[0064] The circuit simulation model of a ferroelectric negative capacitance transistor is also known as the Spice model.
[0065] The technical advantages of this invention are as follows: Unlike traditional numerical modeling methods, this invention starts from the Poisson equation, the current continuum equation, and the Landau-Khalatnikov physical equation to obtain fully analytical expressions for channel current and terminal charge density. These expressions can be implemented using Verilog-A, thus achieving compatibility with mainstream commercial circuit simulators. The fully analytical expressions improve the simulation speed and convergence of the circuit. Unlike most ferroelectric transistor models based on multi-domain Preisach theory, this invention employs the Landau-Khalatnikov ferroelectric phase transition equation, capturing the unique negative capacitance effect of nanoscale ferroelectric materials. This allows for simulation design of circuits for logic computing, storage, and neuromorphic computing, making the model highly versatile. In summary, the ferroelectric negative capacitance transistor circuit simulation model proposed in this invention has advantages such as clear physical meaning, fully analytical expressions, strong versatility, high simulation efficiency, and good convergence. It is of great significance for studying the working mechanism of ferroelectric NC-FET devices and guiding the optimization design and circuit simulation design of ferroelectric NC-FET devices.
[0066] like Figure 4 As shown, the prediction results of the circuit simulation (i.e., Spice) model proposed in this invention for the transfer characteristic curve of the dual-gate MFMIS NC-FET device are in high agreement with the calculation results of the Sentaurus TCAD numerical simulator. From Figure 4 It can be observed that when the thickness of the ferroelectric thin film (t) f When the t is less than 55nm, there is no hysteresis loop on the transfer characteristic curve of the device. At this time, the ferroelectric NC-FET device can be used as a logic computing switch. f When the wavelength is greater than 55nm, there is a significant hysteresis loop on the transfer characteristic curve of the device, so the ferroelectric NC-FET device at this time can be used as a memory.
[0067] like Figure 5 As shown, the Spice model proposed in this invention provides a good match between the prediction results of the output characteristic curve of the dual-gate MFMIS NC-FET device and the calculation results of the Sentaurus TCAD numerical simulator. This demonstrates that the Spice model proposed in this invention can accurately simulate the numerical simulation results.
[0068] like Figure 6 As shown, the Spice model proposed in this invention provides good agreement with the channel current-source bias curve prediction results of the dual-gate MFMIS NC-FET device, and the calculation results from the Sentaurus TCAD numerical simulator. Furthermore, it successfully predicts the negative differential resistance (NDR) effect of the MFMIS NC-FET device, indicating that this device can be used to construct artificial neuron circuits and has significant application potential in neuromorphic computing.
[0069] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.
[0070] Please see Figure 7 Secondly, a simulation circuit model for a ferroelectric negative capacitance transistor is constructed using the modeling method for the simulation circuit model of a ferroelectric negative capacitance transistor described in the first aspect.
[0071] The simulation model of the ferroelectric negative capacitance transistor circuit includes a reference MOSFET electrical model and a ferroelectric capacitor electrical model.
[0072] Specifically, the gate (gi) of the MOSFET device is connected to the cathode of the ferroelectric capacitor, and the anode of the ferroelectric capacitor serves as the gate (g) of the entire ferroelectric NC-FET device. s is the source of the ferroelectric NC-FET device, and d is the drain of the ferroelectric NC-FET device.
[0073] The above-disclosed embodiments are merely preferred embodiments of the circuit simulation model and modeling method for a ferroelectric negative capacitance transistor of the present invention. Of course, they should not be construed as limiting the scope of the present invention. Those skilled in the art can understand that all or part of the processes of the above embodiments can be implemented, and equivalent changes made in accordance with the claims of the present invention are still within the scope of the invention.
Claims
1. A modeling method for circuit simulation of a ferroelectric negative capacitance transistor, characterized in that, Includes the following steps: Establish the cross-sectional structure of the ferroelectric device and set the bias voltages of the gate, drain and source of the reference MOSFET device; The source surface charge density and drain surface charge density are calculated based on the bias voltages of the drain and the source, specifically as follows: Based on the bias voltages of the drain and source electrodes, the source surface charge density and drain surface charge density are calculated using the Poisson equation and the Gaussian boundary condition equation. The calculation formula is as follows: (1) (2) In formulas (1) and (2), , is the capacitance per unit area of the insulating oxide layer. and These are the dielectric constant and thickness of the insulating oxide layer, respectively. , where is the thermal voltage, and . It is Boltzmann's constant. It is absolute temperature. It is the fundamental electron charge. It is a parameter that depends on temperature and device geometry. It is the threshold voltage of a long-channel dual-gate reference MOSFET device, expressed as: (3) In formula (3), The work function difference between the gate metal and channel material of the reference MOSFET device; This represents the intrinsic carrier concentration of the channel material; the source / drain surface charge density Q is calculated based on the Poisson equation and the Gaussian boundary condition equation. s and Q d ; The channel current of the reference MOSFET device is obtained based on the source surface charge density and the drain surface charge density, specifically in the following manner: The channel current of the MOSFET device is calculated using explicit equations based on the source surface charge density and the drain surface charge density. The formula for calculating the channel current is as follows: (4) Q s and Q d The results are obtained by formulas (1) and (2) respectively; Let W be the constant carrier mobility, and W and L be the gate width and gate length of the device, respectively. The capacitance per unit area of the channel. The calculation formula is: ; Where is the dielectric constant of the channel material. For the channel thickness; The gate surface charge density of a reference MOSFET device is calculated using the current continuity equation and the charge segmentation method. The formula for calculating the gate surface charge density of the reference MOSFET device is as follows: (5) In formula (5), and As an intermediate variable, the expression is as follows: (6) (7) In formulas (6) and (7), where Q s and Q d The results are obtained by formulas (1) and (2) respectively; The gate surface charge density, Q, of the reference MOSFET device is calculated using the current continuity equation and the Ward-Dutton charge partitioning method. av ; The total gate voltage of the ferroelectric device is obtained by using the gate surface charge density. Specifically, the total gate voltage of the ferroelectric device is calculated using the Landau-Kharatnikov phase transition equation based on the gate surface charge density. The formula for calculating the total gate voltage of the ferroelectric device is as follows: (8) In formula (8), It is calculated from equation (5); , The Landau parameters for ferroelectric materials are related to the specific type of ferroelectric material and the temperature. The constant damping coefficient depends on the specific ferroelectric material; A circuit simulation model of the entire ferroelectric negative capacitance transistor is constructed based on the channel current and the total gate voltage.
2. A circuit simulation model of a ferroelectric negative capacitance transistor, employing the modeling method for the circuit simulation model of a ferroelectric negative capacitance transistor as described in claim 1, characterized in that, It is composed of a reference MOSFEF device and a ferroelectric capacitor electrical characteristic model connected in series.