Pixel Circuit and Display Panel

Abstract

The present invention discloses a pixel circuit and a display panel. The pixel circuit includes a timing control module and a current optimization module. The timing control module includes a first data writing terminal, a first control terminal, and a timing output terminal; the timing control module is configured to write a timing data signal into the first control terminal, and control whether the timing output terminal outputs a first driving current in response to a signal of the first control terminal; the current optimization module includes a second data writing terminal, a second control terminal, and a voltage maintaining terminal; the second data writing terminal is connected to a maintaining voltage signal, and the current optimization module is configured to write the maintaining voltage signal into the voltage maintaining terminal; the second control terminal is electrically connected to the first control terminal; the current optimization module is connected in series to a generation path of the first driving current, and is configured to delay a generation time of the first driving current and reduce an edge change time of the first driving current. Embodiments of the present invention can reduce a conversion time between a light emitting state and a non-light emitting state of a light emitting device, and improve a display effect.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technologies, and in particular, to a pixel circuit and a display panel. Background Art

[0002] With the continuous development of display technologies, the application scope of display panels has become increasingly wide, and people's requirements for display panels have also become higher and higher. In particular, the display image quality of display panels has always been one of the important indicators for consumers and panel manufacturers to measure the quality of display panels. A display panel includes a light-emitting device and a pixel circuit for driving the light-emitting device. The performance of the pixel circuit determines the light-emitting effect of the light-emitting device, and thus determines the display effect of the display panel. Among them, a pixel circuit driven by an analog pulse width modulation (PWM) method has been widely studied because it can control the light-emitting time. However, the conversion time of this pixel circuit between the light-emitting state and the non-light-emitting state of the light-emitting device is relatively long, which will cause serious color deviation in the display image and affect the display effect. Summary of the Invention

[0003] Embodiments of the present invention provide a pixel circuit and a display panel to reduce the conversion time between the light-emitting state and the non-light-emitting state of the light-emitting device and improve the display effect.

[0004] To achieve the above technical objectives, embodiments of the present invention provide the following technical solutions:

[0005] A pixel circuit includes:

[0006] A time control module, including a first data writing terminal, a first control terminal, and a time output terminal; the first data writing terminal is connected to a time data signal; the time control module is configured to write the time data signal into the first control terminal and control whether the time output terminal outputs a first driving current in response to a signal of the first control terminal;

[0007] A current optimization module, including a second data writing terminal, a second control terminal, and a voltage maintaining terminal; the second data writing terminal is connected to a maintaining voltage signal, and the current optimization module is configured to write the maintaining voltage signal into the voltage maintaining terminal; the second control terminal is electrically connected to the first control terminal; the current optimization module is connected in series to a generation path of the first driving current and is configured to delay the generation time of the first driving current and reduce the edge change time of the first driving current.

[0008] Optionally, the current optimization module includes:

[0009] A delay unit; a control terminal of the delay unit is electrically connected to the second control terminal, and a first terminal of the delay unit is electrically connected to the voltage maintaining terminal; the delay unit is connected in series to the generation path of the first driving current;

[0010] A write maintenance unit; an input end of the write maintenance unit is electrically connected to the second data write end, and an output end of the write maintenance unit is electrically connected to the voltage maintenance end.

[0011] Optionally, the delay unit includes: a first transistor; a gate of the first transistor serves as a control end of the delay unit, a first pole of the first transistor serves as a first end of the delay unit, and a second pole of the first transistor serves as a second end of the delay unit.

[0012] Optionally, the write maintenance unit includes: a second transistor and a first capacitor; a gate of the second transistor receives a first scan signal, a first pole of the second transistor serves as an input end of the write maintenance unit, and a second pole of the second transistor serves as an output end of the write maintenance unit; a first end of the first capacitor receives a reference voltage signal, and a second end of the first capacitor is electrically connected to the voltage maintenance end.

[0013] Optionally, the time control module includes:

[0014] A first driving unit; a control end of the first driving unit serves as the first control end; a first end of the first driving unit is electrically connected to a first power supply end; a second end of the first driving unit is electrically connected to the time output end;

[0015] The current optimization module is connected in series between the first power supply end and the first end of the first driving unit, and the voltage maintenance end is electrically connected to the first end of the first driving unit; or, the current optimization module is connected in series between the second end of the first driving unit and the time output end, and the voltage maintenance end is electrically connected to the second end of the first driving unit.

[0016] Optionally, the time control module includes:

[0017] A first driving unit; a control end of the first driving unit serves as the first control end;

[0018] A first light emission control unit; a control end of the first light emission control unit receives a light emission control signal, a first end of the first light emission control unit is electrically connected to a first power supply end; a second end of the first light emission control unit is electrically connected to the first end of the first driving unit;

[0019] A second light emission control unit; a control end of the second light emission control unit receives the light emission control signal, a first end of the second light emission control unit is electrically connected to the second end of the first driving unit, and a second end of the second light emission control unit is electrically connected to the time output end;

[0020] The current optimization module is connected in series between the first power supply terminal and the first end of the first light-emitting control unit, and the voltage maintaining terminal is connected to the first end of the first light-emitting control unit;

[0021] Alternatively, the current optimization module is connected in series between the second end of the first light-emitting control unit and the first end of the first driving unit, and the voltage maintaining terminal is connected to the first end of the first driving unit;

[0022] Alternatively, the current optimization module is connected in series between the second end of the first driving unit and the first end of the second light-emitting control unit, and the voltage maintaining terminal is connected to the second end of the first driving unit;

[0023] Alternatively, the current optimization module is connected in series between the second end of the second light-emitting control unit and the time output terminal, and the voltage maintaining terminal is connected to the second end of the second light-emitting control unit.

[0024] Optionally, the pixel circuit further includes: a current control module, including a third data writing terminal, a third control terminal, and a driving current output terminal; the third data writing terminal accesses an amplitude data signal; the current control module is configured to write the amplitude data signal into the third control terminal; the third control terminal is electrically connected to the time output terminal, and the driving current output terminal is electrically connected to the light-emitting device; the current control module is configured to control whether the driving current output terminal outputs a second driving current;

[0025] Preferably, the amplitude data signal is multiplexed as the sustaining voltage signal.

[0026] Optionally, the current control module includes:

[0027] A second driving unit; the control terminal of the second driving unit serves as the third control terminal, the first end of the second driving unit is electrically connected to a second power supply terminal, and the second end of the second driving unit is electrically connected to the first pole of the light-emitting device; the second pole of the light-emitting device is electrically connected to a third power supply terminal;

[0028] A first data writing unit; the control terminal of the first data writing unit accesses a second scanning signal, the first end of the first data writing unit accesses an amplitude data signal, and the second end of the first data writing unit is electrically connected to the control terminal of the second driving unit;

[0029] A first storage unit; the first end of the first storage unit is electrically connected to the second power supply terminal, and the second end of the first storage unit is electrically connected to the control terminal of the second driving unit.

[0030] Optionally, the current control module includes:

[0031] a second driving unit; a control end of the second driving unit serving as the third control end, a first end of the second driving unit being electrically connected to the second power supply end, a second end of the second driving unit being electrically connected to the first electrode of the light-emitting device; and a second electrode of the light-emitting device being electrically connected to the third power supply end;

[0032] a first initialization unit; a control end of the first initialization unit receiving a third scanning signal, a first end of the first initialization unit receiving an initialization voltage signal, and a second end of the first initialization unit being electrically connected to the control end of the second driving unit;

[0033] a second data writing unit; wherein a control end of the second data writing unit is connected to the fourth scanning signal, a first end of the second data writing unit is connected to the amplitude data signal, and a second end of the second data writing unit is electrically connected to the first end of the second driving unit;

[0034] a first compensation unit; a control end of the first compensation unit receiving the fourth scanning signal, a first end of the first compensation unit being electrically connected to the second end of the second driving unit, and a second end of the first compensation unit being electrically connected to the control end of the second driving unit;

[0035] a third light-emitting control unit; a control terminal of the third light-emitting control unit receiving a light-emitting control signal, and the third light-emitting control unit being connected in series between the second power supply terminal and the first terminal of the second driving unit;

[0036] a fourth light-emitting control unit; a control terminal of the fourth light-emitting control unit receiving the light-emitting control signal, and the fourth light-emitting control unit being connected in series between the second terminal of the second driving unit and the first terminal of the light-emitting device;

[0037] Preferably, the amplitude data signal and the time data signal are transmitted in time-sharing manner via the same data line. Accordingly, an embodiment of the present invention further provides a display panel, comprising: a pixel circuit as provided in any embodiment of the present invention.

[0038] In an embodiment of the present invention, a current optimization module is added to the pixel circuit and connected in series with the path for generating the first drive current. Specifically, the second data write terminal of the current optimization module is connected to the maintenance voltage signal, and the second control terminal is electrically connected to the first control terminal of the time control module. During the light-emitting phase, the current optimization module and the time control module cooperate to delay the generation of the first drive current, effectively reducing the edge change time of the first drive current, thereby achieving precise control of the light-emitting device's light-emitting time. Therefore, the embodiment of the present invention can reduce the transition time between the light-emitting state and the non-light-emitting state of the light-emitting device, thereby improving the display effect. Brief Description of the Drawings

[0039] Figure 1 It is a schematic structural diagram of an existing pixel circuit;

[0040] Figure 2 It is a schematic diagram of the driving timing of an existing pixel circuit;

[0041] Figure 3 It is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0042] Figure 4 It is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0043] Figure 5 It is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present invention;

[0044] Figure 6 It is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present invention;

[0045] Figure 7 It is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present invention;

[0046] Figure 8 It is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present invention;

[0047] Figure 9 It is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present invention;

[0048] Figure 10 It is a schematic comparison diagram of the second driving current waveform between the present solution and the prior art provided by an embodiment of the present invention;

[0049] Figure 11 It is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present invention;

[0050] Figure 12 It is a schematic diagram of the driving timing of a pixel circuit provided by an embodiment of the present invention;

[0051] Figure 13 It is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present invention;

[0052] Figure 14 It is a schematic diagram of the driving timing of another pixel circuit provided by an embodiment of the present invention;

[0053] Figure 15 It is a schematic comparison diagram of the second driving current waveform between another present solution and the prior art provided by an embodiment of the present invention;

[0054] Figure 16 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0055] Figure 17 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0056] Figure 18 A schematic diagram of the driving timing of another pixel circuit provided by an embodiment of the present invention;

[0057] Figure 19 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Detailed implementation manners

[0058] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that for the sake of description, only parts related to the present invention are shown in the accompanying drawings rather than all the structures.

[0059] As described in the background art, in the existing pixel circuit, the conversion time between the light-emitting state and the non-light-emitting state of the light-emitting device is relatively long, resulting in color deviation in the display screen. After research by the inventor, the reasons for this problem are as follows:

[0060] For display devices such as OLED or Micro LED, there are problems such as large fluctuations in luminous efficiency under low current conditions and steep brightness-voltage curves, making it difficult to control the display gray scale. The prior art provides a pixel circuit that uses the combined action of a PWM signal and a ramp signal to control the light-emitting time of the light-emitting device, such as a digital drive pixel circuit or a digital-analog hybrid drive pixel circuit. Figure 1 A schematic structural diagram of an existing pixel circuit. Refer to Figure 1 , taking the digital-analog hybrid drive pixel circuit as an example, this pixel circuit includes a current control module 010, a time control module 020, and a light-emitting device 030. Among them, the current control module 010 is used to generate a second drive current Id2' in response to the potential of its control terminal (node C) to drive the light-emitting device 030 to emit light. The time control module 020 generates a first drive current Id1' by responding to the potential of its control terminal (node A), thereby controlling the potential of the control terminal of the current control module 010 to control the conduction time of the current control module 010, and thus controlling the light-emitting time of the light-emitting device 030.

[0061] The time control module 020 requires a variety of control signals, such as the time control signal SPWM', the ramp signal Vsweep', the data signal Sig', the light emission control signal Em', etc. Exemplarily, the time control module 020 includes transistors M1', M2', M3', M4', M5' and a capacitor C1'. Figure 2 It is a schematic diagram of the driving timing of an existing pixel circuit. Combining Figure 1 and Figure 2 , exemplarily, the driving process of the pixel circuit includes:

[0062] Before the light emission stage t3', under the control of the time control signal SPWM' and the data signal Sig', a set voltage signal containing a time data signal is written to the gate (node A) of the transistor M1'.

[0063] In the light emission stage t3', the ramp signal Vsweep' changes with time, and its voltage gradually decreases. Through the coupling effect of the capacitor C1', the potential VA of node A also presents a ramp signal with a gradually decreasing voltage. Ideally, when the potential VA of node A drops to the theoretical turn-on voltage V0' of the transistor M1', the transistor M1' immediately turns on, and the generated driving current should quickly control the potential VC of node C to increase, thereby controlling the current control module 010 to disconnect, dividing the light emission stage t3' into a light emission sub-stage t31' and a non-light emission sub-stage t32'. However, the ramp signal Vsweep' changes slowly, so the potential VA of node A also changes slowly; at the same time, due to the existence of the subthreshold swing, there is a critical state of semi-conduction between the switching states of the transistor M1', and the first driving current Id1' generated in the critical state changes slowly (the edge change time is long), making the potential VC of node C change slowly, resulting in a gradually decreasing stage of the second driving current Id2' of the current control module 010, and this stage is the critical light emission sub-stage t30', which is between the light emission sub-stage t31' and the non-light emission sub-stage t32'.

[0064] In the critical light-emitting sub-phase t30', the following process exists: the potential VA of node A gradually decreases → transistor M1' gradually turns on → the potential VC of node C gradually changes to VDD1' → current control module 010 gradually turns off → the second driving current Id2' gradually decreases. Among them, for transistor M1', the potential of its gate (node A) is VA, the potential of its first pole (node B) is VB, and the gate-source voltage difference Vgs = VA - VB. Since the potential VB of node B is a fixed value, the change in Vgs is actually controlled by the potential VA of node A. For P-type transistor M1', when the potential VA of node A reaches V1', its gate-source voltage difference Vgs reaches the critical turn-on voltage. Until the potential VA of node A drops to V2', transistor M1' is fully turned on. Therefore, when the potential VA of node A is between V1' and V2', it is defined that transistor M1' is in the critical voltage range, and the critical voltage range corresponds to the critical light-emitting sub-phase t30'.

[0065] In summary, whether it is a digital driving pixel circuit (only including the time control module 020) or an analog-digital hybrid driving pixel circuit (the time control module 020 and the current control module 010 act together), it is the time control module 020 that controls the light-emitting time of the light-emitting device 030, and the edge change of the first driving current Id1' determines the adjustment effect of the display gray level. The longer the time of the critical light-emitting sub-phase t30', the longer the uncontrollable time of the driving current Id1', the worse the adjustment effect of the display gray level, and the more serious the color shift, thus affecting the display effect of the display panel.

[0066] In view of this, an embodiment of the present invention provides a pixel circuit. Figure 3 It is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention. Refer to Figure 3 , this pixel circuit includes: a time control module 120 and a current optimization module 130.

[0067] Among them, the current optimization module 130 is used to adjust the edge change condition of the time control module 120. Specifically, the time control module 120 includes a first data writing end 21, a first control end 22, and a time output end 23; the first data writing end 21 accesses a time data signal Sig2; the time control module 120 is used to write the time data signal Sig2 into the first control end 22, and control whether the time output end 23 outputs a first driving current Id1 in response to the signal of the first control end 22. The current optimization module 130 includes a second data writing end 31, a second control end 32, and a voltage maintaining end 33; the second data writing end 31 accesses a maintaining voltage signal VE, and the current optimization module 130 is used to write the maintaining voltage signal VE into the voltage maintaining end 33; the second control end 32 is electrically connected to the first control end 22; the current optimization module 130 is connected in series to the generation path of the first driving current Id1, and is used to delay the generation time of the first driving current Id1 and reduce the edge change time of the first driving current Id1.

[0068] Exemplarily, the current optimization module 130 is arranged between the first power supply end and the time control module 120. The current optimization module 130 further includes a first connection end 34, which is electrically connected to the first power supply end and accesses a first power supply signal VDD1; the time control module 120 further includes a second connection end 24, which is electrically connected to the voltage maintaining end 33. The potential of the second control end 32 controls whether the current optimization module 130 is turned on. When the current optimization module 130 is turned on, the first power supply signal VDD1 is transmitted to the voltage maintaining end 33 (the second connection end 24). The potentials of the second connection end 24 and the first control end 22 jointly control whether the time control module 120 is turned on. When the time control module 120 is turned on, a first driving current Id1 is output, and the potential of the time output end 23 is changed.

[0069] Exemplarily, the time control module 120 also accepts the control of a time control signal, and this time control signal can be a ramp signal or other forms of signals. The ramp signal can be accessed externally or generated inside the time control module 120. The working process of the pixel circuit is described below by taking the time control module 120 accessing a ramp signal as an example. Exemplarily, the working process of the pixel circuit includes:

[0070] During the time data writing stage, the time data signal Sig2 is written into the first control end 22.

[0071] During the maintaining voltage writing stage, the maintaining voltage signal VE is written into the voltage maintaining end 33.

[0072] During the light-emitting stage, the first control terminal 22 and the second control terminal 32 are controlled by a ramp signal. This ramp signal can be externally connected or internally generated by the time control module 120. In the first light-emitting sub-stage, as the potential of the ramp signal decreases, the voltage difference between the first connection terminal 34 and the second control terminal 32 gradually increases and first reaches the critical turn-on voltage of the current optimization module 130. The current optimization module 130 gradually turns on, and the potential of the voltage maintenance terminal 33 gradually increases until it reaches the potential of the first power supply signal VDD1. During the process of the potential of the voltage maintenance terminal 33 gradually increasing, the voltage difference between the second connection terminal 24 and the first control terminal 22 gradually increases, but does not reach the critical turn-on voltage of the time control module 120, and the time control module 120 remains off and does not generate the first drive current Id1. After that, in the critical light-emitting sub-stage, due to the continuous decrease of the ramp signal and the continuous increase of the potential of the voltage maintenance terminal 33, the time control module 120 can reach the fully-on state faster and quickly output the first drive current Id1. In the second light-emitting sub-stage, the time control module 120 remains in the fully-on state, and the first drive current Id1 is continuously and stably output. Among them, if the time output terminal 23 is directly connected to the light-emitting device, in the first light-emitting sub-stage, the light-emitting device does not emit light; in the second light-emitting sub-stage, the light-emitting device emits light.

[0073] As can be seen from the above analysis, the embodiment of the present invention reduces the edge change time of the first drive current Id1, which is beneficial to realizing precise control of the light-emitting time of the light-emitting device and improving the display effect.

[0074] It can be seen that the embodiment of the present invention adds a current optimization module 130 to the pixel circuit and connects the current optimization module 130 in series in the generation path of the first drive current Id1. Specifically, the second data writing terminal 31 of the current optimization module 130 accesses the amplitude data signal Sig1, and the second control terminal 32 is electrically connected to the first control terminal 22 of the time control module 120. During the light-emitting stage, the current optimization module 130 and the time control module 120 cooperate to delay the generation time of the first drive current Id1 and effectively reduce the edge change time of the first drive current Id1, thereby realizing precise control of the light-emitting time of the light-emitting device. Therefore, the embodiment of the present invention can reduce the conversion time between the light-emitting state and the non-light-emitting state of the light-emitting device and improve the display effect.

[0075] Figure 4 It is a schematic structural diagram of another pixel circuit provided by the embodiment of the present invention. Refer to Figure 4, based on the above embodiments, optionally, the current optimization module 130 includes: a delay unit 131 and a write maintenance unit 132. Among them, the control terminal of the delay unit 131 is electrically connected to the second control terminal 32, the first terminal is electrically connected to the voltage maintenance terminal 33, and the second terminal is connected to the first power signal VDD1; the delay unit 131 is connected in series in the generation path of the first drive current Id1. The input terminal of the write maintenance unit 132 is electrically connected to the second data write terminal 31 and receives the maintenance voltage signal VE; the output terminal of the write maintenance unit 132 is electrically connected to the voltage maintenance terminal 33.

[0076] Specifically, taking the current optimization module 130 connected between the time control module 120 and the first power supply terminal as an example, the driving process of the pixel circuit includes:

[0077] During the time data writing stage, the time data signal Sig2 is written into the first control terminal 22.

[0078] During the maintenance voltage writing stage, the maintenance voltage signal VE is written into the voltage maintenance terminal 33 through the write maintenance unit 132; and the write maintenance unit 132 maintains the potential of the voltage maintenance terminal 33.

[0079] During the light emitting stage, the first control terminal 22 and the second control terminal 32 are controlled by a ramp signal. As the potential of the ramp signal decreases, the voltage difference between the second terminal and the control terminal of the delay unit 131 gradually increases, reaching the critical turn-on voltage of the delay unit 131. The delay unit 131 gradually turns on, and the potential of the voltage maintenance terminal 33 gradually increases. During the process of the potential of the voltage maintenance terminal 33 gradually increasing, the voltage difference between the voltage maintenance terminal 33 and the first control terminal 22 gradually increases, but does not reach the critical turn-on voltage of the time control module 120, and the time control module 120 remains off, so the potential of the time output terminal 23 remains unchanged. After that, due to the continuous decrease of the ramp signal and the continuous increase of the potential of the voltage maintenance terminal 33, the time control module 120 can quickly reach the fully turned-on state and quickly output the first drive current Id1.

[0080] In summary, the embodiment of the present invention sets the current optimization module 130 to include a delay unit 131 and a write maintenance unit 132, achieving the effect of effectively reducing the edge change time of the first drive current Id1 by using the current optimization module 130.

[0081] Figure 5 It is a schematic structural diagram of another pixel circuit provided by the embodiment of the present invention. See Figure 5, the implementation principle of the embodiment of the present invention is described with the least number of components. On the basis of the above embodiments, optionally, the delay unit 131 includes: a first transistor M1; the gate of the first transistor M1 serves as the control end of the delay unit 131 and is electrically connected to the second control end 32; the first pole of the first transistor M1 serves as the first end of the delay unit 131 and is electrically connected to the voltage maintenance end 33; the second pole of the first transistor M1 serves as the second end of the delay unit 131 and is connected to the first power supply signal VDD1. In this embodiment, it is set that the delay unit 131 only includes one transistor, making the circuit structure simple and easy to implement. It should be noted that the specific connection mode of the first transistor M1 is determined according to the position of the current optimization module in the pixel circuit.

[0082] Continue to refer to Figure 5 , in an embodiment, optionally, the time control module includes: a first driving unit 121, including a first driving transistor DTFT1. The gate of the first driving transistor DTFT1 serves as the control end of the first driving unit 121 and is electrically connected to the first control end 22; the first pole of the first driving transistor DTFT1 is electrically connected to the voltage maintenance end 33, and the second pole is used to output a first driving current. In practical applications, in addition to the first driving transistor DTFT1, the time control module can also be provided with other components, which will be described in subsequent embodiments.

[0083] Continue to refer to Figure 5 , exemplarily, the driving process of the pixel circuit includes:

[0084] Before the light-emitting stage, a maintenance voltage signal is pre-written to the voltage maintenance end 33; wherein, the maintenance voltage signal needs to ensure that the first driving transistor DTFT1 is in the off state, for example, the same as or close to the potential of the time output end 23.

[0085] In the light-emitting stage, when the first control end 22 and the second control end 32 are controlled by a ramp signal and the potential gradually decreases, the potential difference between the second control end 32 and the first power supply end first reaches the critical turn-on voltage of the first transistor M1, and the first transistor M1 gradually turns on, and the potential of the voltage maintenance end 33 gradually increases. However, since the potential difference between the voltage maintenance end 33 and the first control end 22 does not reach the critical turn-on voltage of the first driving transistor DTFT1, the first driving transistor DTFT1 is cut off, and the potential of the time output end 23 remains unchanged. As the ramp signal continues to decrease, the potential difference between the voltage maintenance end 33 and the first control end 22 reaches the critical turn-on voltage of the first driving transistor DTFT1, and due to the dual effects of the continuously decreasing ramp signal and the continuously increasing potential of the voltage maintenance end 33, the first driving transistor DTFT1 quickly reaches the fully turned-on state, that is, the potential of the time output end 23 quickly reaches the potential of the first power supply signal VDD1, and the first driving current quickly rises to the peak value.

[0086] It can be seen that by adding a first transistor M1 between the connection path of the first driving transistor DFTT1 and the first power supply terminal, and pre-writing a sustain voltage signal to the voltage sustain terminal 33 before the light-emitting stage, the edge change time of the potential of the time output terminal 23 can be effectively reduced.

[0087] Figure 5 Exemplarily, the first transistor M1 is provided between the first power supply terminal and the first pole of the first driving transistor DTFT1, but it is not a limitation to the present invention. Figure 6 It is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Refer to Figure 6 and Figure 5 is different in that the first transistor M1 is provided between the second pole of the first driving transistor DTFT1 and the time output terminal 23. Then, in the light-emitting stage, the potential value between the first control terminal 22 and the first power signal VDD1 first reaches the critical turn-on voltage of the first driving transistor DTFT1, and the first driving transistor DTFT1 is first turned on; as the ramp signal gradually decreases, the voltage of the voltage sustain terminal 33 gradually increases, and the first transistor M1 quickly reaches the fully turned-on state.

[0088] Figure 7 It is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Refer to Figure 7 Based on the above embodiments, optionally, the write-sustain unit 132 includes: a second transistor M2 and a first capacitor C1. The gate of the second transistor M2 is connected to the first scan signal S1; the first pole of the second transistor M2 serves as the input terminal of the write-sustain unit 132 and is connected to the sustain voltage signal VE; the second pole of the second transistor M2 serves as the output terminal of the write-sustain unit 132 and is electrically connected to the voltage sustain terminal 33. The first end of the first capacitor C1 is connected to the reference voltage signal Vref1, and the second end is electrically connected to the voltage sustain terminal 33. In this embodiment, the write-sustain unit 132 is provided to include only one transistor and one capacitor, making the circuit structure simple and easy to implement.

[0089] Continue to refer to Figure 7 Based on the above embodiments, optionally, the time control module 120 further includes: a transistor M01 and a capacitor C4. The transistor M01 is used to respond to the time scan signal SPWM and write the time data signal Sig2 to the first control terminal 22; the capacitor C4 is used to couple the time control signal Vsweep in the form of a ramp to the first control terminal 22 and the second control terminal 32.

[0090] Figure 8 It is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Refer to Figure 8, in one embodiment, optionally, the structure of the pixel circuit is different from that in Figure 7 in that: the current optimization module 130 is connected between the second pole of the first driving transistor DTFT and the time output terminal 23.

[0091] In the above embodiments, the pixel circuit is exemplarily shown to include a current optimization module and a time control module, but this is not a limitation to the present invention. The pixel circuits with other structures will be described below.

[0092] Figure 9 It is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Refer to Figure 9 , on the basis of the above embodiments, optionally, in the pixel circuit, in addition to the time control module 120 and the current optimization module 130, it further includes: a current control module 110. The current control module 110 includes a third data writing terminal 11, a third control terminal 12, and a driving current output terminal 13; the third data writing terminal 11 accesses an amplitude data signal Sig1; the current control module 110 is configured to write the amplitude data signal Sig1 into the third control terminal 12; the driving current output terminal 13 is electrically connected to the first pole 141 of the light emitting device 140; the second pole 142 of the light emitting device 140 is electrically connected to the third power supply terminal, accessing a third power supply signal VSS; the current control module 110 is configured to control whether the driving current output terminal 13 outputs a second driving current Id2. Exemplarily, the third power supply signal VSS may be a ground signal, for example.

[0093] Among them, the potential level of the third control terminal 12 controls whether the current control module 110 conducts during the light emitting stage. When the current control module 110 conducts, the second driving current Id2 is output, and the potential level of the third control terminal 12 can also control the magnitude of the second driving current Id2.

[0094] Exemplarily, the working process of the pixel circuit includes:

[0095] During the time data writing stage, the time data signal Sig2 is written into the first control terminal 22.

[0096] During the amplitude data writing stage, the amplitude data signal Sig1 is written into the third control terminal 12, and at the same time, the amplitude data signal Sig1 is written into the voltage holding terminal 33. In this way, the potentials of the third control terminal 12 and the voltage holding terminal 33 are equal. The voltage difference between the second connection terminal 24 and the time output terminal 23 of the time control module 120 is 0, and the voltage difference between the second connection terminal 24 and the first control terminal 22 is small, so as to avoid the mis-conduction of the time control module 120 and at the same time avoid the leakage of the current control module 110 through the time control module 120 during the light emitting stage.

[0097] During the light emitting stage, in combination with Figure 9 andFigure 10 The current control module 110 generates a second driving current Id2 in response to the amplitude data signal Sig1 to drive the light-emitting device 140 to emit light.

[0098] After entering the light-emitting stage T3, the first control terminal 22 and the second control terminal 32 are controlled by a ramp signal. In the light-emitting sub-stage T31, as the potential of the ramp signal decreases, the voltage difference between the first connection terminal 34 and the second control terminal 32 gradually increases and first reaches the critical turn-on voltage of the current optimization module 130. The current optimization module 130 gradually turns on, and the potential of the voltage maintenance terminal 33 gradually increases until it reaches the potential of the first power signal VDD1. During the process of the potential of the voltage maintenance terminal 33 gradually increasing, the voltage difference between the second connection terminal 24 and the first control terminal 22 gradually increases, but does not reach the critical turn-on voltage of the time control module 120, and the time control module 120 remains off. Therefore, the potential of the third control terminal 12 remains unchanged, and the second driving current Id2 is stably output to the light-emitting device 140. After that, in the critical light-emitting sub-stage T30, due to the continuous decrease of the ramp signal and the continuous increase of the potential of the voltage maintenance terminal 33, the time control module 120 can reach the fully turned-on state faster and quickly output the first driving current Id1, so that the potential of the third control terminal 12 rapidly increases, and quickly controls the current control module 110 to turn off. In the non-light-emitting sub-stage T32, the time control module 120 remains in the fully turned-on state, the current control module 110 remains off, and the light-emitting device 140 does not emit light. Figure 10 The change of the second driving current Id2' in the prior art is drawn with a dotted line. It can be clearly seen that compared with the prior art, the embodiment of the present invention reduces the fall time of the second driving current Id2, which is beneficial to realizing the precise control of the light-emitting time of the light-emitting device 140 and improving the display effect.

[0099] It can be seen that the embodiment of the present invention adds a current optimization module 130 to the pixel circuit and connects the current optimization module 130 in series in the generation path of the first driving current Id1. In the light-emitting stage, the current optimization module 130 and the time control module 120 cooperate to delay the generation time of the first driving current Id1, maintain the voltage of the third control terminal 12, effectively reduce the rise time of the potential of the third control terminal 12, and reduce the fall edge time of the second driving current Id2. Therefore, the embodiment of the present invention can reduce the conversion time between the light-emitting state and the non-light-emitting state of the light-emitting device and improve the display effect.

[0100] It should be noted that Figure 9Exemplarily, the current optimization module 130 is provided between the first power supply terminal and the time control module 120, but this is not a limitation on the present invention. In other embodiments, the current optimization module 130 may also be provided between the time control module 120 and the current control module 110; or the current optimization module 130 may be interspersed inside the time control module 120. As long as it is ensured that the current optimization module 130 is located in the generation path of the first driving current Id1, and the voltage maintaining terminal 33 is located between the time control module 120 and the current optimization module 130.

[0101] Exemplarily, when the current optimization module 130 is located between the time control module 120 and the current control module 110, the potential difference between the potential of the first control terminal 22 and the first power supply signal VDD1 first reaches the critical turn-on voltage of the time control module 120, and the time control module 120 is first turned on; as the ramp signal gradually decreases, the voltage of the voltage maintaining terminal 33 gradually increases, and the current optimization module 130 quickly reaches the fully turned-on state and outputs the first driving current Id1.

[0102] Continue to refer to Figure 9 , on the basis of the above embodiments, optionally, the amplitude data signal Sig1 is multiplexed as the voltage maintaining signal, which can reduce the number of signal lines and is beneficial to simplifying the wiring of the display panel.

[0103] Continue to refer to Figure 9 , on the basis of the above embodiments, optionally, the power supply terminal 14 of the current control module 110 is electrically connected to the second power supply terminal, and the second power supply signal VDD2 is accessed. Optionally, the first power supply terminal and the second power supply terminal access the same power supply signal, that is, the first power supply signal VDD1 is multiplexed as the second power supply signal VDD2, so as to simplify the wiring of the display panel and the structure of the scan driving circuit.

[0104] Figure 11 This is a schematic structural diagram of another pixel circuit provided by the embodiment of the present invention. Refer to Figure 11 , in one embodiment, optionally, the structure of the current optimization module 130 is the same as that in Figure 7 or Figure 8 , and details are not described herein again. It should be noted that the voltage of the reference voltage signal accessed by the first end of the first capacitor C1 is constant, and the voltage of the voltage maintaining terminal 33 can be stabilized through the first capacitor C1. Therefore, any signal with a constant voltage can be used as the reference voltage signal Vref1. Exemplarily, the first power supply signal VDD1 is multiplexed as the reference voltage signal Vref1; or, the second power supply signal VDD2 is multiplexed as the reference voltage signal Vref1; or, the third power supply signal VSS is multiplexed as the reference voltage signal Vref1. Such a setting can simplify the pixel circuit structure and the wiring of the display panel.

[0105] Continue to refer to Figure 11 In one embodiment, optionally, the time control module includes: a first driving unit 121 and a first coupling unit 201. Exemplarily, the first driving unit 121 includes a first driving transistor DTFT1. The first coupling unit 201 includes a capacitor C4; a first end of the capacitor C4 is connected to a time control signal Vsweep, and a second end is electrically connected to the first control end 22. Wherein, the time control signal Vsweep is a ramp signal in the light emitting stage, and through the coupling action of the first coupling unit 201, the potential of the first control end 22 is a ramp signal in the light emitting stage.

[0106] Continue to refer to Figure 11 In one embodiment, optionally, the current control module 110 includes: a second driving unit 111, including a second driving transistor DTFT2. A gate of the second driving transistor DTFT2 serves as a control end of the second driving unit 111 and is electrically connected to the third control end 12; a first pole of the second driving transistor DTFT2 is connected to a first power supply signal VDD1, and a second pole is used to output a first driving current. In this embodiment, it is set that the second driving unit 111 only includes one transistor, and the circuit structure is simple and easy to implement.

[0107] It should be noted that there are various ways to set the time control module 120 and the current control module 110. In order to simply show the working principle of the pixel circuit, Figure 11 only some devices in the pixel circuit are shown, and there may be other devices connected between these devices, which are represented by ellipsis in Figure 11 and will be specifically described in the following embodiments.

[0108] Next, the driving process of the pixel circuit shown in Figure 11 will be described in conjunction with a specific driving timing diagram. Figure 12 This is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention. Combining Figure 11 and Figure 12 taking the current optimization module 130 connected between the first power supply terminal and the first driving unit 121 and each transistor being a P-type transistor as an example, the driving process of the pixel circuit includes:

[0109] During the amplitude data writing stage T2, the first scan signal S1 is at a low level, and the potential V22 of the first control end 22 and the potential V32 of the second control end are time data signals Sig2 written before the amplitude data writing stage T2. The second transistor M2 is turned on in response to the control of the first scan signal S1, and the amplitude data signal Sig1 is written into the voltage holding terminal 33 and the second end of the first capacitor C1.

[0110] In the light-emitting stage T3, the current control module 110 generates a second driving current Id2 in response to the amplitude data signal Sig1 to drive the light-emitting device 140 to emit light. Meanwhile, the potential V22 of the first control terminal 22 and the potential V32 of the second control terminal 32 are controlled by the time control signal Vsweep and present a gradually decreasing voltage signal. According to the change of the second driving current Id2, the light-emitting stage T3 is divided into a light-emitting sub-stage T31, a critical light-emitting sub-stage T30, and a non-light-emitting sub-stage T32. According to the conduction state of the first transistor M1, the light-emitting sub-stage T31 is divided into a first light-emitting sub-stage T311 and a second light-emitting sub-stage T312.

[0111] In the first light-emitting sub-stage T311, as the potential of the time control signal Vsweep decreases, the difference between the potential of the first power supply signal VDD1 and the potential V32 of the second control terminal 32 gradually increases, but does not reach the critical turn-on voltage of the first transistor M1, and the first transistor M1 is turned off; the voltage holding terminal 33 maintains the potential of the previous stage; the difference between the potential V33 of the voltage holding terminal 33 and the potential V22 of the first control terminal 22 does not reach the critical turn-on voltage of the first driving transistor DTFT1, and the first driving transistor DTFT1 is turned off; the time control module 120 does not generate the first driving current Id1, the potential V12 of the third control terminal 12 remains unchanged, and the second driving current Id2 remains unchanged.

[0112] In the second light-emitting sub-stage T312, as the potential of the time control signal Vsweep decreases, the difference between the potential of the first power supply signal VDD1 and the potential V32 of the second control terminal 32 gradually increases and reaches the critical turn-on voltage of the first transistor M1, and the first transistor M1 gradually turns on, and the potential of the voltage holding terminal 33 gradually rises. During the process of the potential of the voltage holding terminal 33 gradually increasing, the difference between the potential V33 of the voltage holding terminal 33 and the potential V22 of the first control terminal 22 gradually increases, but does not reach the critical turn-on voltage of the first driving transistor DTFT1, and the first driving transistor DTFT1 remains turned off. The first driving current Id1 is still not generated, the potential V12 of the third control terminal 12 remains unchanged, and the second driving current Id2 remains unchanged.

[0113] In the critical light-emitting sub-stage T30, due to the continuous decrease of the potential of the time control signal Vsweep and the continuous increase of the potential of the voltage holding terminal 33, the first driving transistor DTFT1 quickly reaches the fully turned-on state. Therefore, the potential V12 of the third control terminal 12 quickly increases to the first power supply signal VDD1, the second driving transistor DTFT2 quickly turns off, and the second driving current Id2 quickly decreases.

[0114] During the non-light-emitting photon stage T32, the potential V33 of the voltage holding terminal 33 and the potential V12 of the third control terminal 12 are both maintained at the first power supply signal VDD1, the second driving transistor DTFT2 remains cut off, and the light-emitting device 140 does not emit light.

[0115] Furthermore, Figure 12 The variation of the potential V12' of the third control terminal 12' and the second driving current Id2' in the prior art without setting the current optimization module 130 is exemplarily shown in dashed lines. Refer to Figure 12 , in the prior art, the falling edge of the second driving current Id2' starts from the second light-emitting photon stage T312 and continues until the critical light-emitting photon stage T30. By comparing the second driving current Id2' with the second driving current Id2, it can be seen that in this embodiment, the potential of the third control terminal 12 is effectively maintained, and the time of the falling edge of the second driving current Id2 is reduced.

[0116] It should be noted that in the above embodiments, when the potential of the third control terminal 12 reaches the first power supply signal VDD1, the second driving transistor DTFT2 is cut off and no longer generates the second driving current Id2, which is given by way of example and is not a limitation to the present invention. In other embodiments, it is also possible that the second driving transistor DTFT2 has been cut off before the potential of the third control terminal 12 reaches the first power supply signal VDD1.

[0117] In the above embodiments, the setting method of the current optimization module 130 is described. The current optimization module 130 provided by the embodiments of the present invention can be applied to any combination of the current control module 110 and the time control module 120 in any form. The basic constituent unit of the time control module 120 includes a time driving unit for generating a first driving current in response to a ramp signal. The basic constituent units of the current control module 110 include a current driving unit, a current data writing unit, and a storage unit; the current driving unit includes a control terminal, which serves as the third control terminal; the current driving unit is used to generate a second driving current in response to the potential of its control terminal; the current data writing unit is used to write an amplitude data signal into the first control terminal; the storage unit is used to store the potential of the first control terminal. Both the current control module 110 and the time control module 120 have various setting methods. Several specific structures of the pixel circuit will be described below, which are not limitations to the present invention.

[0118] Figure 13 It is a schematic structural diagram of another pixel circuit provided by the embodiments of the present invention. Refer to Figure 13, in one embodiment, optionally, the time control module 120 includes: a first driving unit 121, a first light emitting control unit 125, a second light emitting control unit 126, a first coupling unit 201, a third data writing unit 127, a second compensation unit 128, and a second initialization unit 129.

[0119] Among them, the first driving unit 121 includes a first driving transistor DTFT1. The gate of the first driving transistor DTFT1 serves as the control end of the first driving unit 121 and is electrically connected to the first control end 22. The first pole of the first driving transistor DTFT1 serves as the first end of the first driving unit 121, and the second pole serves as the second end of the first driving unit 121. The first light emitting control unit 125 includes a transistor M12. The gate of the transistor M12 serves as the control end of the first light emitting control unit 125 and receives the light emitting control signal EM. The first pole of the transistor M12 serves as the first end of the first light emitting control unit 125 and is electrically connected to the first power supply end. The second pole of the transistor M12 serves as the second end of the first light emitting control unit 125 and is electrically connected to the first end of the first driving unit 121. The second light emitting control unit 126 includes a transistor M13. The gate of the transistor M13 serves as the control end of the second light emitting control unit 126 and receives the light emitting control signal EM. The first pole of the transistor M13 serves as the first end of the second light emitting control unit 126 and is electrically connected to the second end of the first driving unit 121. The second pole of the transistor M13 serves as the second end of the second light emitting control unit 126 and is electrically connected to the time output end.

[0120] The first coupling unit 201 includes a capacitor C4; the first end of the capacitor C4 serves as the first end of the first coupling unit 201 and is connected to the time control signal Vsweep, and the second end of the capacitor C4 serves as the second end of the first coupling unit 201 and is electrically connected to the first control end 22. The second initialization unit 129 includes a transistor M16; the gate of the transistor M16 serves as the control end of the second initialization unit 129 and is connected to the third scan signal S3; the first pole of the transistor M16 serves as the first pole of the second initialization unit 129 and is connected to the initialization voltage signal Vini; the second pole of the transistor M16 serves as the second end of the first initialization unit and is electrically connected to the first control end 22. The third data writing unit 127 includes a transistor M14; the control end of the transistor M14 serves as the control end of the third data writing unit 127 and is connected to the time scan signal SPWM; the first pole of the transistor M14 serves as the first end of the third data writing unit 127 and is connected to the time data signal Sig2; the second pole of the transistor M14 serves as the second end of the third data writing unit 127 and is electrically connected to the first end of the first driving unit 121. The second compensation unit 128 includes a transistor M15; the gate of the transistor M15 serves as the control end of the second compensation unit 128 and is connected to the time scan signal SPWM; the first pole of the transistor M15 serves as the first end of the second compensation unit 128 and is connected to the second end of the first driving unit 121; the second pole of the transistor M15 serves as the second end of the second compensation unit 128 and is electrically connected to the first control end 22.

[0121] Continue to refer to Figure 13 , in an embodiment, optionally, the current control module 110 includes: a second driving unit 111, a first initialization unit 118, a second data writing unit 114, a first compensation unit 115, a third light emission control unit 116, a fourth light emission control unit 117, and a first storage unit 113.

[0122] The second driving unit 111 includes a second driving transistor DTFT2; the gate of the second driving transistor DTFT2 serves as the control end of the second driving unit 111 and is connected to the third control end 12; the first pole of the second driving transistor DTFT2 serves as the first end of the second driving unit 111, and the second pole serves as the second end of the second driving unit 111. The third light emission control unit 116 includes a transistor M8; the gate of the transistor M8 serves as the control end of the third light emission control unit 116 and is connected to the light emission control signal EM; the third light emission control unit 116 is connected in series between the second power supply end and the first end of the second driving unit 111. The fourth light emission control unit 117 includes a transistor M9; the gate of the transistor M9 serves as the control end of the fourth light emission control unit 117 and is connected to the light emission control signal EM; the fourth light emission control unit 117 is connected in series between the second end of the second driving unit 111 and the first pole of the light emitting device 140.

[0123] The first initialization unit 118 includes a transistor M10; the gate of the transistor M10 serves as the control terminal of the first initialization unit 118 and is connected to the third scan signal S3; the first end of the transistor M10 serves as the first end of the first initialization unit 118 and is connected to the initialization voltage signal Vini; the second pole of the transistor M10 serves as the second end of the first initialization unit 118 and is electrically connected to the third control terminal 12. The second data writing unit 114 includes a transistor M6; the gate of the transistor M6 serves as the control terminal of the second data writing unit 114 and is connected to the fourth scan signal S4; the first pole of the transistor M6 serves as the first end of the second data writing unit 114 and is connected to the amplitude data signal Sig1; the second pole of the transistor M6 serves as the second end of the second data writing unit 114 and is electrically connected to the first end of the second driving unit 111. The first compensation unit 115 includes a transistor M7; the gate of the transistor M7 serves as the control terminal of the first compensation unit 115 and is connected to the fourth scan signal S4; the first pole of the transistor M7 serves as the first end of the first compensation unit 115 and is electrically connected to the second end of the second driving unit 111; the second end of the transistor M7 serves as the second end of the first compensation unit 115 and is electrically connected to the third control terminal 12. The first storage unit 113 includes a capacitor C2; the first end of the capacitor C2 serves as the first end of the first storage unit 113 and is connected to the first power supply terminal; the second end of the capacitor C2 serves as the second end of the first storage unit 113 and is electrically connected to the third control terminal 12.

[0124] Regarding Figure 13 For the setting manners of the time control module 120 and the current control module 110 shown, there are various setting positions for the current optimization module 130, which will be specifically described below.

[0125] Continue to refer to Figure 13 , in one embodiment, optionally, the current optimization module 130 is serially connected between the second end of the first light emitting control unit 125 and the first end of the first driving unit 121, and the voltage holding terminal 33 is connected to the first end of the first driving unit 121. That is, the second pole of the first transistor M1 in the delay unit 131 is electrically connected to the second pole of the transistor M12.

[0126] In another embodiment, optionally, the current optimization module 130 is serially connected between the first power supply terminal and the first end of the first light emitting control unit 125, and the voltage holding terminal 33 is connected to the first end of the first light emitting control unit 125. That is, the second pole of the first transistor M1 in the delay unit 131 is electrically connected to the first power supply terminal.

[0127] Under the above two setting manners of the current optimization module 130, in the light emitting stage, the delay unit 131 in the current optimization module 130 is turned on first.

[0128] In another embodiment, optionally, the current optimization module 130 is connected in series between the second end of the first driving unit 121 and the first end of the second light-emitting control unit 126, and the voltage holding terminal 33 is connected to the second end of the first driving unit 121. That is, the second pole of the first transistor M1 in the delay unit 131 is electrically connected to the first end of the second light-emitting control unit 126.

[0129] In another embodiment, optionally, the current optimization module 130 is connected in series between the second end of the second light-emitting control unit 126 and the third control terminal 12, and the voltage holding terminal 33 is connected to the second end of the second light-emitting control unit 126. That is, the second pole of the first transistor M1 in the delay unit 131 is electrically connected to the third control terminal 12.

[0130] In the above two setting manners of the current optimization module 130, during the light-emitting stage, the first driving unit 121 in the time control module 120 is turned on first.

[0131] In summary, the setting manner of the current optimization module 130 can be flexibly selected according to requirements and is not limited herein.

[0132] Continue to refer to Figure 13 , in one embodiment, optionally, the light-emitting device 140 includes a light-emitting diode L; the anode of the light-emitting diode L serves as the first pole of the light-emitting device 140 and is electrically connected to the second end of the fourth light-emitting control unit 117; the cathode of the light-emitting diode L serves as the second pole of the light-emitting device 140 and is electrically connected to the third power supply terminal.

[0133] Continue to refer to Figure 13 , on the basis of the above embodiments, optionally, the pixel circuit further includes: a test module 150, including a transistor M17; the gate of the transistor M17 serves as the control terminal of the test module 150 and receives a test signal TEST; the test module 150 is connected in parallel across the light-emitting device 140.

[0134] Figure 14 This is a schematic diagram of the driving timing of another pixel circuit provided by an embodiment of the present invention. Combining Figure 13 and Figure 14 , taking all transistors as P-type transistors as an example, the driving process of this pixel circuit includes:

[0135] During the initialization stage T0, the third scan signal S3 is at a low level, and the transistors M10 and M16 are turned on; the initialization voltage signal Vini is written into the third control terminal 12 through the transistor M10 and written into the first control terminal 22 through the transistor M16.

[0136] During the time data writing stage T1, the time scanning signal SPWM is at a low level, and the transistors M14 and M15 are turned on; the sum of the time data signal Sig2 and the threshold voltage Vth1 of the first driving transistor DTFT1 is written to the first control terminal 22 and the second control terminal 32.

[0137] During the amplitude data writing stage T2, the fourth scanning signal S4 is at a low level, and the transistors M6 and M7 are turned on. The sum of the amplitude data signal Sig1 and the threshold voltage Vth2 of the second driving transistor DTFT2 is written to the third control terminal 12; meanwhile, the first scanning signal S1 is at a low level, and the second transistor M2 is turned on, and the amplitude data signal Sig1 is written to the voltage holding terminal 33 through the second transistor M2.

[0138] During the light emitting stage T3, the time control signal Vsweep continuously decreases. Through the coupling effect of the capacitor C4, the potential V22 of the first control terminal 22 and the potential V32 of the second control terminal 32 continuously decrease. The changes in the potential V33 of the voltage holding terminal 33 and the potential V12 of the third control terminal 12, as well as the change in the second driving current Id2, are similar to those in the above embodiments and will not be elaborated here.

[0139] It should be noted that during the normal light emitting driving process, the test signal TEST remains at a high level to keep the transistor M17 cut off and not affect the normal light emission of the light emitting transistor L.

[0140] Figure 15 This is a comparison schematic diagram of the second driving current waveform between another solution provided by the embodiment of the present invention and the prior art. To verify the beneficial effects of the embodiment of the present invention, the inventor uses Figure 13 the pixel circuit shown as the circuit of this solution, and Figure 13 removes the current optimization module 130 from the pixel circuit shown as the prior art circuit, and conducts simulation verification on the two structures. Figure 15 Exemplarily, the abscissa represents time, and the ordinate represents the current value of the second driving current. From Figure 15 it can be seen that the falling edge duration t91 of the second driving current in the prior art is 2.1 ms, and the falling edge duration t92 of the second driving current in this solution is 0.9 ms, indicating that this solution can effectively reduce the falling edge duration of the second driving current.

[0141] Based on the above embodiments, optionally, the fourth scanning signal S4 is multiplexed as the first scanning signal S1; the second power supply signal VDD2 is multiplexed as the reference voltage signal, or the initialization voltage signal Vini is multiplexed as the reference voltage signal. Such a setting can effectively reduce the number of signal lines and is beneficial to simplifying the wiring of the display panel.

[0142] Figure 16This is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention. Figure 16 In one embodiment, the current optimization module 130 is connected in series between the second terminal of the second light emitting control unit 126 and the third control terminal 12. Figure 13 The pixel circuit structure is similar to Figure 13 The differences are as follows: First, in this embodiment, the amplitude data signal Sig1 and the timing data signal Sig2 are transmitted in time-sharing mode over the same data line Sig, reducing the number of data lines. The first terminal of the third light-emitting control unit 116 is electrically connected to the second terminal of the first light-emitting control unit 125, which is equivalent to connecting the first power supply signal VDD1 to the current control module 110 during the light-emitting phase, thus reducing the number of power lines. In summary, this configuration effectively reduces the number of signal lines and helps save wiring space.

[0143] For example, Figure 16 The driving timing of the pixel circuit shown is similar to Figure 14 The driving timing shown is similar and will not be repeated here. The difference is that the data line Sig provides the time data signal Sig2 to the pixel circuit in the time data writing phase T1, and provides the amplitude data signal Sig1 to the pixel circuit in the amplitude data writing phase T2 to ensure the normal operation of the pixel circuit.

[0144] Figure 17 This is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention. Figure 17 In one embodiment, the time control module 120 optionally forms a ramp signal within itself, and does not require an external driver chip to provide a ramp signal (eg Figure 14 Therefore, it is possible to realize simultaneous writing and emitting of pixel circuits in different rows, which is beneficial to reducing the writing time of the control signal and is beneficial to high refresh rate, high brightness display and high pixel density of the pixel circuit.

[0145] Specifically, see Figure 17 In one embodiment, optionally, the time control module 120 includes: a first driving unit 121 , a time initialization unit 122 , a time data writing unit 123 and a second coupling unit 124 .

[0146] Among them, the first driving unit 121 includes a first driving transistor DTFT1; the gate of the first driving transistor DTFT1 serves as the control end of the first driving unit 121 and is electrically connected to the first control end 22; the first pole of the first driving transistor DTFT1 serves as the first end of the first driving unit 121; the second pole of the first driving transistor DTFT1 serves as the second end of the first driving unit 121. The time initialization unit 122 includes a transistor M4; the gate of the transistor M4 serves as the control end of the time initialization unit 122 and receives the first switching signal SW1; the first pole of the transistor M4 serves as the first end of the time initialization unit 122 and receives the second reference voltage signal Vref2; the second pole of the transistor M4 serves as the second end of the time initialization unit 122 and is electrically connected to the first control end 22. The time data writing unit 123 includes a transistor M5; the gate of the transistor M5 serves as the control end of the time data writing unit 123 and receives the second switching signal SW2; the first pole of the transistor M5 serves as the first end of the time data writing unit 123 and receives the time data signal Sig2; the second pole of the transistor M5 serves as the second end of the time data writing unit 123. The second coupling unit 124 includes a capacitor C3; the first end of the capacitor C3 serves as the first end of the second coupling unit 124 and is electrically connected to the second end of the time data writing unit 123; the second end of the capacitor C3 serves as the second end of the second coupling unit 124 and is electrically connected to the first control end 22. Exemplarily, the transistor M4 is an N-type transistor and the transistor M5 is a P-type transistor.

[0147] Continue to refer to Figure 17 , in an embodiment, optionally, the current optimization module 130 is connected in series between the second end of the first driving unit 121 and the third control end 12, and the voltage maintaining end 33 is electrically connected to the second end of the first driving unit 121.

[0148] Continue to refer to Figure 17 , in an embodiment, optionally, the structure of the current control module 110 is similar to that of the Figure 13 or Figure 16 The current control module 110 in, the difference is that: the current control module 110 in this embodiment further includes an anode initialization unit 119, including a transistor M11; the gate of the transistor M11 receives the third scan signal S3, the first pole receives the initialization voltage signal Vini, and the second pole is electrically connected to the first pole of the light-emitting device 140. The current control module 110 constitutes a 7T1C structure.

[0149] Figure 18 This is a schematic diagram of the driving timing of another pixel circuit provided by the embodiment of the present invention. Combining Figure 17 and Figure 18, in one embodiment, optionally, the waveform of the time data signal Sig2 changes in a square wave shape, and the waveform of the second reference voltage signal Vref2 changes in a square wave shape; the driving process of the pixel circuit includes:

[0150] In the initialization stage T0, the third control signal S3 is at a low level, transistors M10 and M11 are turned on, and the initialization voltage signal Vini initializes the third control terminal 12 and the first pole of the light-emitting device 140. At the same time, the first switch signal SW1 is at a high level, the second switch signal SW2 is at a low level, the second initialization voltage signal Vref2 is at a high level, and the time data signal Sig2 is at a low level. Transistor M4 is turned on in response to the first switch signal SW1, and the high level of the second initialization voltage signal Vref2 is written into the first control terminal 22; transistor M5 is turned on in response to the second switch signal SW2, and the low level of the time data signal Sig2 is written into the capacitor C3 as the reference value before the voltage jump.

[0151] The time data writing stage T1 and the amplitude data writing stage T2 are carried out simultaneously. The first switch signal SW1 is at a low level, the second switch signal SW2 is at a low level, the second initialization voltage signal Vref2 is at a high level, and the time data signal Sig2 jumps upward by ΔS. Transistor M5 is turned on in response to the second switch signal SW2. The potential of the left plate of the capacitor C3 jumps upward by ΔS, so the potential of its right plate also jumps upward by ΔS. At the same time, the fourth scan signal S4 is at a low level, and the sum of the amplitude data signal Sig1 and the threshold voltage Vth2 of the second driving transistor DTFT2 is transmitted to the third control terminal 12 and the voltage holding terminal 33.

[0152] In the light-emitting stage T3, the first switch signal SW1 is at a high level, the second switch signal SW2 is at a high level, and the second initialization voltage signal Vref2 jumps downward. Transistor M4 is turned on in response to the first switch signal SW1, and the first control terminal 22 starts to gradually discharge through transistor M4 to form a ramp signal. The changes in the potential V33 of the voltage holding terminal 33 and the potential V12 of the third control terminal 12, as well as the change in the second driving current Id2 in this stage are similar to those in the above embodiments and will not be elaborated here.

[0153] Figure 19 This is a schematic structural diagram of another pixel circuit provided by the embodiment of the present invention. Refer to Figure 19 , in one embodiment, optionally, the structure of the time control module 120 is the same as Figure 17Similar to those in the above, details are not described herein again. The differences are as follows: First, the current optimization module 130 is connected in series between the first power supply terminal and the first end of the first driving unit 121, and the voltage maintaining terminal 33 is electrically connected to the first end of the first driving unit 121. Second, the current control module 110 only includes a second driving unit 111, a first data writing unit 112, and a first storage unit 113. The structures of the second driving unit 111 and the first storage unit 113 are similar to those in the above embodiments, and details are not described herein again. The first data writing unit 112 includes a transistor M3; the gate of the transistor M3 serves as the control terminal of the first data writing unit 112 and is connected to the second scanning signal S2; the first pole of the transistor M3 serves as the first end of the first data writing unit 112 and is connected to the amplitude data signal Sig1, and the second pole of the transistor M3 serves as the second end of the first data writing unit 112 and is connected to the third control terminal 12. The current control module 110 constitutes a 2T1C structure.

[0154] Figure 19 The driving timing of the pixel circuit shown is similar to that of Figure 18 The driving timing shown, with the difference being that the amplitude data writing stage is divided into a first writing sub-stage and a second writing sub-stage.

[0155] Exemplarily, the first writing sub-stage is set between the initialization stage and the time data writing stage. In the first writing sub-stage, the first scanning signal S1 is at a low level, and the second transistor M2 is turned on in response to the first scanning signal S1, and the amplitude data signal Sig1 is written into the voltage maintaining terminal 33.

[0156] Exemplarily, the second writing sub-stage overlaps with the light emitting stage. In the second writing sub-stage, the second scanning signal S2 is at a low level, and the transistor M3 is turned on in response to the second scanning signal S2, and the amplitude data signal Sig1 is written into the third control terminal 12. Before the first power signal VDD1 is transmitted to the third control terminal 12, the amplitude data signal Sig1 controls the second driving unit 111 to generate a first driving current to drive the light emitting device 140 to emit light.

[0157] It should be noted that the polarities of the respective transistors in the above embodiments are only examples for explaining the working process of the pixel circuit and do not limit the present invention. In other ways, the polarities of the respective transistors can be selected according to requirements, and the effective levels of the respective gate control signals can be set accordingly.

[0158] The embodiment of the present invention also provides a display panel, including the pixel circuit provided in any embodiment of the present invention, and having corresponding effects. Exemplarily, the display panel can be a display panel of types such as OLED or Micro LED; the pixel circuits can be arranged in an array in the display panel.

[0159] Note that the above is only a preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that, Comprising: A time control module, including a first data writing terminal, a first control terminal, and a time output terminal; the first data writing terminal is connected to a time data signal; The time control module is configured to write the time data signal into the first control terminal, and control whether the time output terminal outputs a first driving current in response to a signal of the first control terminal; A current optimization module, including a second data writing terminal, a second control terminal, and a voltage maintaining terminal; the second data writing terminal is connected to a maintaining voltage signal, and the current optimization module is configured to write the maintaining voltage signal into the voltage maintaining terminal; The second control terminal is electrically connected to the first control terminal; the current optimization module is serially connected in a generation path of the first driving current, and is configured to delay a generation time of the first driving current and reduce an edge change time of the first driving current; The current optimization module includes: A delay unit; a control terminal of the delay unit is electrically connected to the second control terminal, a first terminal of the delay unit is electrically connected to the voltage maintaining terminal; the delay unit is serially connected in the generation path of the first driving current; A writing and maintaining unit; an input terminal of the writing and maintaining unit is electrically connected to the second data writing terminal, an output terminal of the writing and maintaining unit is electrically connected to the voltage maintaining terminal; Further comprising: a current control module, including a third data writing terminal, a third control terminal, and a driving current output terminal; the third data writing terminal is connected to an amplitude data signal; the current control module is configured to write the amplitude data signal into the third control terminal; the third control terminal is electrically connected to the time output terminal, and the driving current output terminal is electrically connected to a light-emitting device; the current control module is configured to control whether the driving current output terminal outputs a second driving current.

2. The pixel circuit according to claim 1, wherein The delay unit includes: a first transistor; a gate of the first transistor serves as the control terminal of the delay unit, a first pole of the first transistor serves as the first terminal of the delay unit, and a second pole of the first transistor serves as the second terminal of the delay unit.

3. The pixel circuit according to claim 1, wherein The writing and maintaining unit includes: a second transistor and a first capacitor; a gate of the second transistor is connected to a first scanning signal, a first pole of the second transistor serves as the input terminal of the writing and maintaining unit, and a second pole of the second transistor serves as the output terminal of the writing and maintaining unit; a first terminal of the first capacitor is connected to a reference voltage signal, and a second terminal of the first capacitor is electrically connected to the voltage maintaining terminal.

4. The pixel circuit according to claim 1, wherein The time control module includes: A first driving unit; a control terminal of the first driving unit serves as the first control terminal; a first terminal of the first driving unit is electrically connected to a first power supply terminal; a second terminal of the first driving unit is electrically connected to the time output terminal; The current optimization module is serially connected between the first power supply terminal and the first terminal of the first driving unit, and the voltage maintaining terminal is electrically connected to the first terminal of the first driving unit; or, the current optimization module is serially connected between the second terminal of the first driving unit and the time output terminal, and the voltage maintaining terminal is electrically connected to the second terminal of the first driving unit.

5. The pixel circuit according to claim 1, wherein The time control module includes: A first driving unit; the control end of the first driving unit serves as the first control end; A first light-emitting control unit; the control end of the first light-emitting control unit is connected to a light-emitting control signal, the first end of the first light-emitting control unit is electrically connected to a first power supply end; the second end of the first light-emitting control unit is electrically connected to the first end of the first driving unit; A second light-emitting control unit; the control end of the second light-emitting control unit is connected to the light-emitting control signal, the first end of the second light-emitting control unit is electrically connected to the second end of the first driving unit, and the second end of the second light-emitting control unit is electrically connected to the time output end; The current optimization module is connected in series between the first power supply end and the first end of the first light-emitting control unit, and the voltage maintaining end is connected to the first end of the first light-emitting control unit; Alternatively, the current optimization module is connected in series between the second end of the first light-emitting control unit and the first end of the first driving unit, and the voltage maintaining end is connected to the first end of the first driving unit; Alternatively, the current optimization module is connected in series between the second end of the first driving unit and the first end of the second light-emitting control unit, and the voltage maintaining end is connected to the second end of the first driving unit; Alternatively, the current optimization module is connected in series between the second end of the second light-emitting control unit and the time output end, and the voltage maintaining end is connected to the second end of the second light-emitting control unit.

6. The pixel circuit according to claim 1, wherein The amplitude data signal is multiplexed as the maintaining voltage signal.

7. The pixel circuit according to claim 1, wherein The current control module includes: A second driving unit; the control end of the second driving unit serves as the third control end, the first end of the second driving unit is electrically connected to a second power supply end, and the second end of the second driving unit is electrically connected to the first pole of the light-emitting device; the second pole of the light-emitting device is electrically connected to a third power supply end; A first data writing unit; the control end of the first data writing unit is connected to a second scanning signal, the first end of the first data writing unit is connected to an amplitude data signal, and the second end of the first data writing unit is electrically connected to the control end of the second driving unit; A first storage unit; the first end of the first storage unit is electrically connected to the second power supply end, and the second end of the first storage unit is electrically connected to the control end of the second driving unit.

8. The pixel circuit according to claim 1, wherein The current control module includes: A second driving unit; the control end of the second driving unit serves as the third control end, the first end of the second driving unit is electrically connected to a second power supply end, and the second end of the second driving unit is electrically connected to the first pole of the light-emitting device; the second pole of the light-emitting device is electrically connected to a third power supply end; A first initialization unit; the control end of the first initialization unit is connected to a third scanning signal, the first end of the first initialization unit is connected to an initialization voltage signal, and the second end of the first initialization unit is electrically connected to the control end of the second driving unit; A second data writing unit; a control terminal of the second data writing unit is connected to a fourth scanning signal, a first terminal of the second data writing unit is connected to the amplitude data signal, and a second terminal of the second data writing unit is electrically connected to a first terminal of the second driving unit; A first compensation unit; a control terminal of the first compensation unit is connected to the fourth scanning signal, a first terminal of the first compensation unit is connected to a second terminal of the second driving unit, and a second terminal of the first compensation unit is connected to a control terminal of the second driving unit; A third light emission control unit; a control terminal of the third light emission control unit is connected to a light emission control signal, and the third light emission control unit is connected in series between the second power supply terminal and the first terminal of the second driving unit; A fourth light emission control unit; a control terminal of the fourth light emission control unit is connected to the light emission control signal, and the fourth light emission control unit is connected in series between the second terminal of the second driving unit and the first electrode of the light emitting device.

9. The pixel circuit according to claim 8, wherein The amplitude data signal and the time data signal are time-division transmitted by the same data line.

10. A display panel, characterized in that, Comprising: The pixel circuit according to any one of claims 1-9.

Images