Semiconductor device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductor. The manufacturing method of the semiconductor device comprises: providing a wafer, the wafer comprising a substrate and a plurality of dies, the substrate having a first surface and a second surface opposite in a first direction, each die comprising a portion of the substrate and a first electrode, the first electrode being located on the first surface; forming at least one set of metal parts corresponding to at least one die, each set of metal parts comprising at least one metal part, the at least one metal part comprising a first metal part in contact with the first electrode of the corresponding die; forming an insulating layer covering the at least one set of metal parts; supporting the insulating layer, and performing grinding from the second surface in the first direction to reduce the thickness of the substrate; and after the grinding, cutting the substrate and the insulating layer in the first direction to separate the plurality of dies. In this way, the on-resistance of the semiconductor device can be effectively reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] The higher the on-resistance (Rdson) of a semiconductor device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), the greater the conduction loss of the semiconductor device. Summary of the Invention

[0003] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a wafer including a substrate and a plurality of dies, the substrate having a first surface and a second surface opposite to each other in a first direction, each die including a portion of the substrate and a first electrode located on the first surface; forming at least one set of metal portions corresponding to at least one die, each set of metal portions including at least one metal portion, the at least one metal portion including a first metal portion in contact with the first electrode of a corresponding die; forming an insulating layer covering the at least one set of metal portions; using the insulating layer as a support, performing grinding along the first direction from the second surface to reduce the thickness of the substrate; and after the grinding, cutting the substrate and the insulating layer along the first direction to separate the plurality of dies.

[0004] In some embodiments, after the grinding, the thickness of the substrate is greater than or equal to 1 micrometer and less than 10 micrometers.

[0005] In some embodiments, after the grinding, the thickness of each die is greater than or equal to 2 micrometers and less than or equal to 50 micrometers.

[0006] In some embodiments, the thickness of each of the at least one metal part is greater than or equal to 10 micrometers and less than or equal to 500 micrometers.

[0007] In some embodiments, the method further includes: forming a first metal layer electrically coupled to the second surface on the second surface between the grinding and the cutting; wherein the cutting separates the first metal layer into a plurality of portions, each portion serving as a second electrode of one of the plurality of dies.

[0008] In some embodiments, the at least one metal portion further includes a second metal portion located on a first surface and spaced apart from the first metal portion of a corresponding die along a second direction, the second direction being perpendicular to the first direction; the method further includes: after the grinding, forming at least one opening through the substrate to expose the second metal portion in the at least one set of metal portions; forming at least one connector located in the at least one opening; forming a first metal layer covering the second surface and the at least one connector; wherein the cutting separates the first metal layer into a plurality of portions, each portion serving as a second electrode of one die in the plurality of dies; each connector is electrically coupled to the second metal portion in the set of metal portions and electrically coupled to the second electrode of a die corresponding to the set of metal portions.

[0009] In some embodiments, each die further includes a gate located on the first surface; the at least one metal portion further includes a third metal portion in contact with the gate G of a corresponding die.

[0010] In some embodiments, the method further includes performing a planarization process on the insulating layer prior to the grinding.

[0011] In some embodiments, the planarization process exposes the at least one set of metal portions.

[0012] In some embodiments, the grinding is supported by the insulating layer and the at least one set of metal portions.

[0013] In some embodiments, the at least one set of metal portions includes multiple sets of metal portions that correspond one-to-one with the plurality of dies.

[0014] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: a die, the die including a substrate and a first electrode, the substrate having a first surface and a second surface opposite to each other in a first direction, the first electrode being located on the first surface; a set of metal portions including a first metal portion in contact with the first electrode and a second metal portion spaced apart from the first metal portion; a first metal layer located on the second surface and electrically coupled to the second surface, the first metal layer serving as a second electrode of the die; and a connector penetrating the substrate and electrically coupled to the first metal layer and the second metal portions.

[0015] In some embodiments, the thickness of the substrate is greater than or equal to 1 micrometer and less than 10 micrometers.

[0016] In some embodiments, the thickness of the die is greater than or equal to 2 micrometers and less than or equal to 50 micrometers.

[0017] In some embodiments, the thickness of each metal part in the group of metal parts is greater than or equal to 10 micrometers and less than or equal to 500 micrometers.

[0018] In some embodiments, the device further includes an insulating layer, wherein the first metal portion and the second metal portion are spaced apart by the insulating layer.

[0019] In some embodiments, the die further includes a gate located on the first surface; the set of metal portions further includes a third metal portion in contact with the gate.

[0020] In the semiconductor device manufacturing method provided in this disclosure, by forming at least one set of metal portions and forming an insulating layer covering at least one set of metal portions, it is possible to perform grinding with the insulating layer as a support to reduce the thickness of the substrate. Thus, since the insulating layer has a certain thickness, it can support the substrate during the grinding process to prevent substrate deformation or breakage. Therefore, this method can effectively reduce the thickness of the ground substrate while saving process steps, thereby effectively reducing the on-resistance of the semiconductor device.

[0021] Other features, aspects, and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0022] The accompanying drawings form part of this specification, illustrating exemplary embodiments of the present disclosure, and together with the specification serve to explain the principles of the present disclosure.

[0023] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, in which:

[0024] Figure 1 This is a schematic flowchart of a semiconductor manufacturing method according to some embodiments of the present disclosure;

[0025] Figures 2A-2F These are cross-sectional views of different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0026] Figures 3A-3C These are cross-sectional views of different stages of a method for manufacturing a semiconductor device according to other embodiments of this disclosure;

[0027] Figure 4 This is a schematic flowchart of a semiconductor manufacturing method according to other embodiments of the present disclosure;

[0028] Figures 5A-5I These are cross-sectional views of different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0029] Figure 6This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0030] It should be understood that the dimensions of the various parts shown in the accompanying drawings are not necessarily drawn to actual scale. Furthermore, the same or similar reference numerals denote the same or similar components. Detailed Implementation

[0031] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless specifically stated otherwise, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values ​​set forth in these embodiments should be interpreted as exemplary only and not as limiting.

[0032] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "containing" mean that the element preceding the word encompasses the element listed after the word, and do not exclude the possibility of encompassing other elements as well. Terms such as "above" and "below" are used only to indicate relative positional relationships, and these relative positional relationships may also change accordingly when the absolute position of the described object changes.

[0033] In this disclosure, when a specific component is described as being located between a first component and a second component, an intermediary component may or may not be present between the specific component and the first or second component. When a specific component is described as connecting to other components, the specific component may be directly connected to the other components without having an intermediary component, or it may not be directly connected to the other components but may have an intermediary component.

[0034] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0035] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0036] The on-resistance of a semiconductor device is positively correlated with the thickness of the substrate in the semiconductor device. That is, the smaller the substrate thickness, the smaller the on-resistance of the semiconductor device. Therefore, in order to obtain a semiconductor device with a smaller on-resistance, the substrate thickness needs to be reduced as much as possible during the manufacturing process of the semiconductor device.

[0037] In related technologies, during the manufacturing process of semiconductor devices, a substrate is first polished using a grinding wheel to reduce its thickness before forming other components of the semiconductor device. However, since the thinner the substrate is polished, the more easily it deforms, this method cannot effectively reduce the thickness of the polished substrate, resulting in a higher on-resistance of the semiconductor device.

[0038] In view of this, the present disclosure proposes the following solution, which can effectively reduce the thickness of the substrate, thereby reducing the on-resistance of the semiconductor device.

[0039] Figure 1 This is a schematic flowchart of a semiconductor manufacturing method according to some embodiments of the present disclosure.

[0040] like Figure 1 As shown, the method for manufacturing a semiconductor device includes steps 102 to 110.

[0041] To facilitate understanding, the following will be combined with Figures 2A-2F right Figure 1 The manufacturing method of the semiconductor device shown will be described. Figures 2A-2F These are cross-sectional views of different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0042] In step 102, wafer 1100 is provided.

[0043] Here, as Figure 2A As shown, wafer 1100 includes a substrate 1111 and a plurality of dies 1110. Figure 2 schematically shows two dies 1110.

[0044] In some embodiments, die 1110 may be a field effect transistor (FET), such as a MOSFET or a junction field effect transistor (JFET).

[0045] The substrate 1111 has a first surface 1112 and a second surface 1113 opposite each other in a first direction Y. Each die 1110 includes a portion of the substrate 1111 and a first electrode E1, wherein the first electrode E1 is located on the first surface 1112.

[0046] In some embodiments, the substrate 1111 may be made of silicon or silicon carbide. In some embodiments, the first electrode E1 may be a source or a drain.

[0047] In step 104, at least one set of metal portions corresponding to at least one die 1110 is formed.

[0048] Here, as Figure 2B As shown, Figure 2B Two sets of metal portions corresponding to two dies 1110 are schematically shown. Each set of metal portions includes at least one metal portion, and the at least one metal portion includes a first metal portion 1121 that contacts the first electrode E1 of the corresponding die 1110. In other embodiments, the at least one metal portion may also include other metal portions besides the first metal portion 1121, for example... Figure 2B The third metal part 1123 shown will be explained further later.

[0049] In step 106, an insulating layer 1130 is formed covering at least one set of metal parts.

[0050] In some embodiments, see Figure 2C The insulating layer 1130 can be made of a flexible insulating material. For example, the insulating layer 1130 can be made of one of epoxy resin adhesive, molding compound, and underfill.

[0051] As one implementation of step 106, a fluid material covering at least one set of metal parts can be formed and cured to form an insulating layer 1130. For example, the fluid material can be an epoxy resin adhesive.

[0052] In step 108, with the insulating layer 1130 as a support, grinding is performed along the first direction Y from the second surface 1113 to reduce the thickness of the substrate 1111.

[0053] In some embodiments, see Figure 2D After polishing with the insulating layer 1130 as a support, a portion of the substrate 1111 is removed. For example, the thickness of the substrate 1111 after polishing can be 5 micrometers.

[0054] In step 110, after grinding, the substrate 1111 and the insulating layer 1130 are cut along the first direction Y to separate the multiple dies 1110.

[0055] For example, according to Figure 2D The wire-cut substrate 1111 and insulating layer 1130 shown can separate multiple dies 1110, thereby fabricating a semiconductor device with low on-resistance.

[0056] In the above embodiments, by forming at least one set of metal portions and forming an insulating layer 1130 covering at least one set of metal portions, it is possible to perform grinding with the insulating layer 1130 as a support to reduce the thickness of the substrate 1111. Thus, since the insulating layer 1130 has a certain thickness, it can support the substrate 1111 during the grinding process to prevent deformation or breakage of the substrate 1111. Therefore, this method can effectively reduce the thickness of the ground substrate while saving process steps, thereby effectively reducing the on-resistance of the semiconductor device.

[0057] Furthermore, when the thickness of the substrate 1111 is small, the distance between the first electrode E1 and the other electrode (e.g., the first electrode E1 is the source and the other electrode is the drain) is also small, thereby reducing the parasitic inductance between the first electrode E1 and the other electrode.

[0058] In some embodiments, during the formation Figure 2C After the insulating layer 1130 is shown, and before polishing, a planarization process, such as chemical mechanical polishing (CMP), can be performed on the insulating layer 1130. For example, a portion of the insulating layer 1130 can be removed before polishing to make the side of the insulating layer 1130 away from the substrate 1111 flat. In this way, a stable support can be provided for subsequent polishing to further prevent deformation or breakage of the substrate 1111, thereby further effectively reducing the on-resistance of the semiconductor device.

[0059] In some embodiments, see Figure 2E In formation Figure 2C Following the insulating layer 1130 and prior to polishing, a planarization process performed on the insulating layer 1130 can expose at least one set of metal portions. For example, the planarization process can remove a portion of the insulating layer 1130 and a portion of at least one set of metal portions to expose at least one set of metal portions. Alternatively, the planarization process can use at least one set of metal portions as a stop layer, removing only a portion of the insulating layer 1130 to expose at least one set of metal portions. This not only provides more stable support for subsequent polishing but also facilitates subsequent processes, thereby further saving steps and effectively reducing the on-resistance of the semiconductor device.

[0060] In some embodiments, see Figure 2F When the planarization process performed on the insulating layer 1130 exposes at least one set of metal portions, grinding can be performed with the insulating layer 1130 and at least one set of metal portions as supports to reduce the thickness of the substrate 1111.

[0061] In some embodiments, the thickness of each metal part in at least one metal part may be greater than or equal to 10 micrometers and less than or equal to 500 micrometers. For example, the thickness of each metal part may be 20 micrometers, 50 micrometers, 100 micrometers, 200 micrometers, or 400 micrometers.

[0062] In some embodiments, the thickness of each metal portion in at least one metal portion can be greater than or equal to 30 micrometers and less than or equal to 300 micrometers. For example, the thickness of each metal portion can be 40 micrometers, 150 micrometers, or 250 micrometers. In this way, on the one hand, the substrate can be effectively supported to prevent deformation or breakage during the polishing process, further effectively reducing the thickness of the polished substrate, thereby more effectively reducing the on-resistance of the die; on the other hand, it helps to reduce the size of the semiconductor device.

[0063] In some embodiments, at least one set of metal portions may include multiple sets of metal portions corresponding one-to-one with the plurality of dies 1110. That is, in step 104, multiple sets of metal portions corresponding one-to-one with the plurality of dies 1110 can be formed. In this way, the substrate can be further supported to prevent deformation or breakage during the polishing process, and the thickness of the polished substrate can be further reduced more effectively, thereby further reducing the on-resistance of the die more effectively.

[0064] In some embodiments, after polishing, the thickness of the substrate 1111 can be greater than or equal to 1 micrometer and less than 10 micrometers. For example, after polishing, the thickness of the substrate 1111 can be 3 micrometers, 6 micrometers, or 9 micrometers.

[0065] In some embodiments, after polishing, the thickness of the substrate 1111 can be greater than or equal to 5 micrometers and less than 10 micrometers. For example, after polishing, the thickness of the substrate 1111 can be 5 micrometers, 8 micrometers, or 10 micrometers. Thus, the semiconductor device manufacturing method provided by the embodiments of this disclosure can achieve a minimum substrate thickness of 1 micrometer without affecting the function of the die, thereby further and more effectively reducing the on-resistance of the semiconductor device.

[0066] In some embodiments, after polishing, the thickness of each die 1110 can be greater than or equal to 2 micrometers and less than or equal to 50 micrometers. For example, after polishing, the thickness of each die 1110 can be 5 micrometers, 20 micrometers, 35 micrometers, or 40 micrometers.

[0067] In some embodiments, after grinding, the thickness of each die 1110 can be greater than or equal to 10 micrometers and less than or equal to 30 micrometers. For example, after grinding, the thickness of each die 1110 can be 10 micrometers, 15 micrometers, 25 micrometers, or 30 micrometers. Thus, the semiconductor device manufacturing method provided by the embodiments of this disclosure can effectively reduce the on-resistance of the semiconductor device while also making the die size smaller, thereby reducing the size of the semiconductor device.

[0068] In some embodiments, the electrode located on the first surface 1112 of the substrate 1111 of each die 1110 may consist only of the first electrode E1.

[0069] In other embodiments, please continue to refer to Figure 2A Each die 1110 may further include a gate G located on the first surface 1112. That is, the electrode located on the first surface 1112 of the substrate 1111 of each die 1110 may include a first electrode E1 and a gate G. In these embodiments, see [link to relevant documentation]. Figure 2B At least one metal portion may include a first metal portion 1121 that contacts the first electrode E1 of a corresponding die 1110 and a third metal portion 1123 that contacts the gate G of a corresponding die 1110. The first metal portion 1121 and the third metal portion 1123 are spaced apart.

[0070] In some embodiments, the first metal portion 1121 and the third metal portion 1123 may be formed in the same patterning process, i.e., by patterning the same material layer.

[0071] Figures 3A-3C These are cross-sectional views of different stages of a method for manufacturing a semiconductor device according to other embodiments of this disclosure.

[0072] In some embodiments, see Figure 3A Between grinding and cutting, a first metal layer 1140 electrically coupled to the second surface 1113 can be formed on the second surface 1113 of the substrate 1111.

[0073] In some embodiments, see Figure 3B A second metal layer 1150, a third metal layer 1151, and a fourth metal layer 1152 may also be formed. The second metal layer 1150 may be located on the side of the first metal layer 1140 away from the insulating layer 1130; the third metal layer 1151 may be located on the side of the first metal portion 1121 away from the first electrode E1 of the corresponding die 1110; and the fourth metal layer 1152 may be located on the side of the third metal portion 1123 away from the gate G of the corresponding die 1110.

[0074] As some implementations, the second metal layer 1150, the third metal layer 1151, and the fourth metal layer 1152 can be made of the same material, for example, nickel-gold.

[0075] In some embodiments, see Figure 3C The second metal layer 1150 can be separated into multiple parts 1150a by cutting. Each die 1110 can dissipate heat through a part 1150a of the second metal layer 1150, the third metal layer 1151, and the fourth metal layer 1152. In this way, the fabricated semiconductor device can dissipate heat from both sides through two surfaces opposite each other along the first direction Y, resulting in better heat dissipation.

[0076] In some embodiments, please continue to see Figure 3C The first metal layer 1140 can be separated into multiple parts 1140a by cutting, and each part 1140a can serve as the second electrode of one of the multiple dies 1110. For example, the first electrode E1 can be the source and the second electrode can be the drain; or, for another example, the first electrode E1 can be the drain and the second electrode can be the source.

[0077] Figure 4 This is a schematic flowchart of a semiconductor manufacturing method according to other embodiments of the present disclosure.

[0078] like Figure 4 As shown, the method for manufacturing a semiconductor device includes steps 402 to 416.

[0079] To facilitate understanding, the following will be combined with Figures 5A-5I right Figure 4 The manufacturing method of the semiconductor device shown will be explained. Figures 5A-5I These are cross-sectional views of different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0080] In step 402, wafer 1100 is provided.

[0081] Please continue reading here. Figure 2A The wafer 1100 includes a substrate 1111 and a plurality of dies 1110. The substrate 1111 has a first surface 1112 and a second surface 1113 opposite to each other in a first direction Y, and each die 1110 includes a portion of the substrate 1111 and a first electrode E1 located on the first surface 1112.

[0082] In step 404, at least one set of metal portions corresponding to at least one die 1110 is formed.

[0083] Please see here. Figure 5A , Figure 5ATwo sets of metal portions are schematically shown. Each set of metal portions includes a first metal portion 1121 that contacts the first electrode E1 of a corresponding die 1110, and a second metal portion 1122 located on the first surface 1112 and spaced apart from the first metal portion 1121 of the corresponding die 1110 along the second direction X, wherein the second direction X is perpendicular to the first direction Y.

[0084] In some embodiments, such as Figure 5A As shown, the electrodes on the first surface 1112 of the substrate 1111 of each die 1110 include a first electrode E1 and a gate G. Each group of metal portions may include a first metal portion 1121, a second metal portion 1122 spaced apart from each other, and a third metal portion 1123 in contact with the gate G of the corresponding die 1110.

[0085] In some embodiments, the first metal portion 1121, the second metal portion 1122, and the third metal portion 1123 can be formed in the same patterning process, i.e., by patterning the same material layer.

[0086] In step 406, an insulating layer 1130 is formed covering at least one set of metal parts.

[0087] For example, such as Figure 5B As shown, the insulating layer 1130 can cover the first metal part 1121, the second metal part 1122 and the third metal part 1123 in each group of metal parts.

[0088] In some embodiments, a planarization process may be performed on the insulating layer 1130 prior to polishing. For example, see... Figure 5C Prior to grinding, the planarization process performed on the insulating layer 1130 can make Figure 5C Both sets of metal parts shown are exposed.

[0089] In step 408, with the insulating layer 1130 as a support, grinding is performed along the first direction Y from the second surface 1113 to reduce the thickness of the substrate 1111.

[0090] For example, see Figure 5D When the planarization process performed on the insulating layer 1130 exposes the two sets of metal parts, the thickness of the substrate 1111 can be reduced by using the insulating layer 1130 and the two sets of metal parts as supports.

[0091] The implementation methods of steps 402 to 408 are similar to those of steps 102 and 108 described above. For other specific descriptions, please refer to the relevant embodiments of steps 102 and 108 described above, which will not be repeated here.

[0092] In step 410, after grinding, at least one opening V1 is formed through the substrate 1111 to expose a second metal portion 1122 in at least one group of metal portions.

[0093] For example, see Figure 5E , Figure 5E Two openings V1 penetrating the substrate 1111 are schematically shown. A second metal portion 1122 in each group of metal portions is located on the first surface 1112 of the substrate 1111 and spaced apart from the first metal portion 1121 of the corresponding die 1110. In cases where each group of metal portions also includes a third metal portion 1123 corresponding to the die 1110, the second metal portion 1122 in each group is spaced apart from both the first metal portion 1121 and the third metal portion 1123 of the corresponding die 1110. The second metal portion 1122 of the corresponding die 1110 near the substrate 1111 is exposed through an opening V1. This ensures that the formed opening V1 does not disrupt the structure of the corresponding die 1110, thereby ensuring that the formed opening V1 does not alter the electrical characteristics of the corresponding die 1110.

[0094] In some embodiments, after polishing, a plurality of openings V1 through the substrate 1111 can be formed to expose the second metal portion 1122 of a plurality of metal portions in a one-to-one correspondence.

[0095] In step 412, at least one connector 1124 is formed in at least one opening V1.

[0096] Here, each connector 1124 is electrically coupled to the second metal part 1122 in a set of metal parts.

[0097] In some embodiments, a plurality of connectors 1124 may be formed after grinding. The plurality of connectors 1124 may be located one-to-one in a plurality of openings V1. For example, Figure 5F Two connectors 1124 are schematically shown in two openings V1 in the substrate 1111. The two connectors 1124 are electrically coupled to two second metal portions 1122 in two sets of metal portions.

[0098] In step 414, a first metal layer 1140 is formed covering the second surface 1113 and at least one connector 1124.

[0099] Here, the first metal layer 1140 is electrically coupled to the second surface 1113 and to at least one connector 1124. See, for example, [link to documentation]. Figure 5G The first metal layer 1140 is electrically coupled to the second surface 1113 and to two connectors 1124 located in the two openings V1 of the substrate 1111.

[0100] In some embodiments, see Figure 5H Similarly, a fifth metal layer 1160, a sixth metal layer 1161, a seventh metal layer 1162, and an eighth metal layer 1163 can be formed. The fifth metal layer 1160 can be located on the side of the first metal layer 1140 away from the insulating layer 1130; the sixth metal layer 1161 can be located on the side of the first metal portion 1121 away from the first electrode E1 of the corresponding die 1110; the seventh metal layer 1162 can be located on the side of the second metal portion 1122 of the corresponding die 1110 away from the first metal layer 1140; and the eighth metal layer 1163 can be located on the side of the third metal portion 1123 away from the gate G of the corresponding die 1110.

[0101] As some implementations, the fifth metal layer 1160, the sixth metal layer 1161, the seventh metal layer 1162, and the eighth metal layer 1163 can be made of the same material, for example, nickel-gold.

[0102] In step 416, the substrate 1111 and the insulating layer 1130 are cut along the first direction Y to separate the plurality of dies 1110.

[0103] See here. Figure 5I The first metal layer 1140 can be separated into multiple parts 1140a by cutting, and each part 1140a can serve as the second electrode of one of the multiple dies 1110.

[0104] Each connector 1124 is electrically coupled not only to the second metal part 1122 in a group of metal parts, but also to the second electrode of a die 1110 corresponding to that group of metal parts. That is, the second metal part 1122 in a group of metal parts can be electrically coupled to the second electrode of a die 1110 corresponding to that group of metal parts through the connector 1124.

[0105] Thus, for each die 1110, the first metal portion 1121 that contacts the first electrode E1, the second metal portion 1122 that is electrically coupled to the second electrode, and the third metal portion 1123 that contacts the gate G can all be located on the same side, eliminating the need for repackaging and benefiting the user.

[0106] In some embodiments, please continue to see Figure 5I With the fifth metal layer 1160 formed, it can be separated into multiple portions 1160a by cutting. Each die 1110 can dissipate heat through a portion 1160a of the fifth metal layer 1160, the sixth metal layer 1161, the seventh metal layer 1162, and the eighth metal layer 1163. In this way, the fabricated semiconductor device can dissipate heat from both sides through two surfaces opposite each other along the first direction Y, resulting in better heat dissipation.

[0107] According to another aspect of the embodiments of this disclosure, a semiconductor device is provided. Figure 6 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0108] like Figure 6 As shown, the semiconductor device 1000 includes a die 1110, a set of metal parts, a first metal layer 1140, and a connector 1124.

[0109] The die 1110 includes a substrate 1111 and a first electrode E1. The substrate 1111 has a first surface 1112 and a second surface 1113 opposite to each other in a first direction Y, and the first electrode E1 is located on the first surface 1112. In some embodiments, the substrate 1111 may be made of silicon or silicon carbide.

[0110] A set of metal portions includes a first metal portion 1121 that is in contact with the first electrode E1 and a second metal portion 1122 that is spaced apart from the first metal portion 1121.

[0111] The first metal layer 1140 is located on the second surface 1113 and is electrically coupled to the second surface 1113.

[0112] Here, the first metal layer 1140 can serve as the second electrode of the die 1110. For example, the first electrode E1 can be the source and the second electrode can be the drain; or, for another example, the first electrode E1 can be the drain and the second electrode can be the source.

[0113] Connector 1124 penetrates substrate 1111 and is electrically coupled to first metal layer 1140 and second metal portion 1122. For example, as Figure 6 As shown, connector 1124 is located between the first surface 1112 and the second surface 1113 of substrate 1111. Connector 1124 has a third surface 1124a and a fourth surface 1124b opposite to each other in a first direction Y. The third surface 1124a is flush with the first surface 1112 of substrate 1111 and is electrically coupled to the second metal portion 1122. The fourth surface 1124b is flush with the second surface 1113 of substrate 1111 and is electrically coupled to the first metal layer 1140.

[0114] In some embodiments, the thickness of substrate 1111 can be greater than or equal to 1 micrometer and less than 10 micrometers. For example, the thickness of substrate 1111 can be greater than or equal to 5 micrometers and less than 10 micrometers. In this way, the on-resistance of the semiconductor device can be further reduced more effectively.

[0115] In some embodiments, the thickness of die 1110 can be greater than or equal to 2 micrometers and less than or equal to 50 micrometers. For example, the thickness of die 1110 can be greater than or equal to 10 micrometers and less than or equal to 30 micrometers. In this way, the size of the semiconductor device can be reduced while effectively reducing the on-resistance of the semiconductor device.

[0116] In some embodiments, the thickness of each metal portion in a group of metal portions is greater than or equal to 10 micrometers and less than or equal to 500 micrometers. For example, the thickness of each metal portion in a group of metal portions can be greater than or equal to 30 micrometers and less than or equal to 300 micrometers. This allows for a more effective reduction in the on-resistance of the semiconductor device.

[0117] In some embodiments, please continue to see Figure 6 The die 1110 may further include a gate G located on the first surface 1112. A set of metal portions may further include a third metal portion 1123 in contact with the gate G. The first metal portion 1121, the second metal portion 1122, and the third metal portion 1123 are spaced apart from each other. Thus, the first metal portion 1121 in contact with the first electrode E1, the second metal portion 1122 electrically coupled to the metal layer portion 1140a, and the third metal portion 1123 in contact with the gate G can all be located on the same surface. This means that the first electrode E1, the second electrode, and the gate G of the die 1110 can all be located on the same surface, eliminating the need for repackaging and improving usability for users.

[0118] In some embodiments, the semiconductor device 1000 may further include an insulating layer 1130, wherein the first metal portion 1121 and the second metal portion 1122 are spaced apart by the insulating layer 1130. For example, as Figure 6 As shown, when a group of metal portions also includes a third metal portion 1123 that contacts the gate G, the first metal portion 1121, the second metal portion 1122 and the third metal portion 1123 are separated by an insulating layer 1130 in the second direction X, wherein the second direction X is perpendicular to the first direction Y.

[0119] In some embodiments, the semiconductor device 1000 may further include a fifth metal layer 1160, a sixth metal layer 1161, a seventh metal layer 1162, and an eighth metal layer 1163. The fifth metal layer 1160 may be located on the side of the first metal layer 1140 away from the insulating layer 1130; the sixth metal layer 1161 may be located on the side of the first metal portion 1121 away from the first electrode E1; the seventh metal layer 1162 may be located on the side of the second metal portion 1122 away from the first metal layer 1140; and the eighth metal layer 1163 may be located on the side of the third metal portion 1123 away from the gate G. Thus, the fabricated semiconductor device can achieve double-sided heat dissipation through two surfaces opposite each other along the first direction Y, resulting in better heat dissipation.

[0120] It should be understood that the semiconductor devices provided in this disclosure can be manufactured, but are not limited to, using the manufacturing methods of any of the above embodiments. The beneficial effects and further embodiments of the semiconductor devices provided in this disclosure can be found in the above description of the manufacturing methods for semiconductor devices, and will not be repeated here.

[0121] This disclosure also provides a battery management system (BMS) including a semiconductor device (e.g., semiconductor device 1000) from any of the above embodiments. For example, the BMS may include one or more semiconductor devices 1000 (e.g., two semiconductor devices 1000).

[0122] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0123] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: A wafer is provided, the wafer including a substrate and a plurality of dies, the substrate having a first surface and a second surface opposite each other in a first direction, each die including a portion of the substrate and a first electrode located on the first surface; At least one set of metal portions is formed corresponding to at least one die, each set of metal portions includes at least one metal portion, the at least one metal portion including a first metal portion that contacts the first electrode of the corresponding die; An insulating layer is formed covering the at least one group of metal portions; Using the insulating layer as a support, grinding is performed along the first direction from the second surface to reduce the thickness of the substrate; After the grinding, the substrate and the insulating layer are cut along the first direction to separate the plurality of dies.

2. The method according to claim 1, wherein, After the grinding, the thickness of the substrate is greater than or equal to 1 micrometer and less than 10 micrometers.

3. The method according to claim 2, wherein, After the grinding process, the thickness of each die is greater than or equal to 2 micrometers and less than or equal to 50 micrometers.

4. The method according to any one of claims 1-3, wherein, The thickness of each of the at least one metal part is greater than or equal to 10 micrometers and less than or equal to 500 micrometers.

5. The method according to claim 1, further comprising: Between the grinding and the cutting, a first metal layer electrically coupled to the second surface is formed on the second surface; The cutting process separates the first metal layer into multiple parts, each of which serves as the second electrode of one of the multiple dies.

6. The method according to claim 1, wherein: The at least one metal portion further includes a second metal portion located on the first surface and spaced apart from the first metal portion of a corresponding die along a second direction, wherein the second direction is perpendicular to the first direction; The method further includes: After the grinding, at least one opening is formed through the substrate to expose the second metal portion of the at least one set of metal portions; Form at least one connector located in the at least one opening; A first metal layer is formed covering the second surface and the at least one connector; The cutting process separates the first metal layer into multiple parts, each part serving as the second electrode of one of the multiple dies. Each connector is electrically coupled to the second metal part in a set of metal parts and electrically coupled to the second electrode of a die corresponding to the set of metal parts.

7. The method according to claim 5 or 6, wherein: Each die also includes a gate located on the first surface; The at least one metal portion further includes a third metal portion that contacts the gate G of a corresponding die.

8. The method according to any one of claims 1-3, further comprising: Prior to the grinding, a planarization process is performed on the insulating layer.

9. The method according to claim 8, wherein, The planarization process exposes the at least one set of metal parts.

10. The method according to claim 9, wherein, The grinding is supported by the insulating layer and the at least one set of metal parts.

11. The method according to any one of claims 1-3, wherein, The at least one set of metal parts includes multiple sets of metal parts that correspond one-to-one with the plurality of tube cores.

12. A semiconductor device, comprising: A die, the die comprising a substrate and a first electrode, the substrate having a first surface and a second surface opposite each other in a first direction, the first electrode being located on the first surface; A set of metal portions, including a first metal portion in contact with the first electrode, and a second metal portion spaced apart from the first metal portion; A first metal layer is located on the second surface and electrically coupled to the second surface, and the first metal layer serves as the second electrode of the die; A connector extends through the substrate and is electrically coupled to the first metal layer and the second metal portion.

13. The device according to claim 12, wherein, The thickness of the substrate is greater than or equal to 1 micrometer and less than 10 micrometers.

14. The device according to claim 13, wherein, The thickness of the die is greater than or equal to 2 micrometers and less than or equal to 50 micrometers.

15. The device according to any one of claims 12-14, wherein, The thickness of each metal part in the group is greater than or equal to 10 micrometers and less than or equal to 500 micrometers.

16. The device according to any one of claims 12-14, further comprising: An insulating layer, wherein the first metal portion and the second metal portion are separated by the insulating layer.

17. The device according to any one of claims 12-14, wherein: The die also includes a gate located on the first surface; The set of metal portions also includes a third metal portion that contacts the gate.

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