Transient voltage suppression device

Abstract

A transient voltage suppression device includes a first strip of semiconductor regions and a second strip of semiconductor regions, a first portion of the semiconductor regions in the first strip and the second strip forming a thyristor, a second portion of the semiconductor regions in the first strip and the second strip forming a P-N junction diode, the first strip and the second strip defining a current conduction region between the strips; the first strip including a first doped region of a first conductivity type, and a second doped region of a second conductivity type; and the second strip including a first doped region of the second conductivity type, and a second doped region of the first conductivity type. The transient voltage suppression device of the present invention achieves low capacitance at the protected node. The transient voltage suppression device is suitable for protecting data pins of an integrated circuit, particularly when the data pins are used in high speed device applications.

Description

[0001] This application is a divisional application

[0002] Original application title: Low capacitance transient voltage suppressor

[0003] Original application number: 201811092680.9

[0004] Original application date: September 14, 2018 TECHNICAL FIELD

[0005] The present invention relates to integrated circuits, and more particularly to a transient voltage suppressor (TVS) device. BACKGROUND

[0006] Voltage and current transients are the primary cause of integrated circuit failure in electronic systems. Transients are generated from a variety of sources both internal and external to the system. For example, common sources of transients include normal switching operation of power supplies, AC line surges, lightning transients, and electrostatic discharge (ESD).

[0007] A transient voltage suppressor (TVS) is a standalone device commonly used to protect integrated circuits from damage due to transients or overvoltage that occur when the integrated circuit is in operation. Overvoltage protection is important for consumer or internet of things (IoT) devices because these devices are often subjected to frequent human handling and are therefore very susceptible to damage from ESD or transient voltage events.

[0008] Specifically, both the power pins and data pins of an electronic device need to be protected from overvoltage due to ESD or switching and lightning transients. Typically, the power pins require high surge protection, but the protection device can tolerate a higher capacitance. Meanwhile, the data pins, which can operate at very high data speeds, require a protection device that can provide surge protection with low capacitance so as not to affect the data speed of the protected data pins.

[0009] In both vertical and horizontal types of semiconductor circuit structures, existing TVS protection solutions use input / output (I / O) terminals. In a conventional vertical TVS structure, I / O current during ESD is diverted from the high and low terminals to a vertical diode flow to ground. In a conventional horizontal TVS structure, the high and low terminals are diverted to a horizontal diode integrated on a semiconductor substrate. Regardless of the TVS circuit structure, a TVS protection device for high speed I / O applications should have very low capacitance so as to not impede signal activity on the high speed data lines. SUMMARY

[0010] The present invention aims to provide a transient voltage suppression device to improve one or more problems in the prior art.

[0011] One aspect of the present application is to provide a transient voltage suppression device comprising:

[0012] The semiconductor regions of the first and second strip structures are laterally adjacent along a first direction on a major surface of the semiconductor layer, the first and second strip structures extending in a second direction on the major surface of the semiconductor layer orthogonal to the first direction, a first portion of the semiconductor regions in the first and second strip structures forming a silicon controlled rectifier, a second portion of the semiconductor regions in the first and second strip structures forming a P-N junction diode, the first and second strip structures defining a current conduction region between the strip structures;

[0013] The first strip structure includes a first doped region of a first conductivity type contained in a well region of a second conductivity type opposite the first conductivity type, and a second doped region of the second conductivity type disposed along a length of the first strip structure in the second direction; and

[0014] The second strip structure includes a first doped region of the second conductivity type contained in a well region of the first conductivity type, and a second doped region of the first conductivity type disposed along a length of the second strip structure in the second direction.

[0015] Preferably, the current conduction region between the first and second strip structures includes a first current path of the silicon controlled rectifier and a second current path of the P-N junction diode, the first current path of the silicon controlled rectifier and the second current path of the P-N junction diode being isolated in the current conduction region in the second direction on the major surface of the semiconductor layer orthogonal to the first direction.

[0016] Preferably, the first doped regions and the well regions of the first and second strip structures form the silicon controlled rectifier, and the second doped regions of the first and second strip structures form the P-N junction diode.

[0017] Preferably, the semiconductor regions of the first strip structure of the first type are electrically connected to a reference node, and the semiconductor regions of the second strip structure are electrically connected to a protected node.

[0018] Preferably, the second doped regions of the first strip structure cover first ends of the well regions of the first strip structure, and the second doped regions of the second strip structure cover first ends of the well regions of the second strip structure.

[0019] Preferably, the first bar structure further comprises a third doped region of the second conductivity type overlapping a second end of the first bar structure well region, the second end being opposite the first end along a length of the first bar structure; and wherein the second bar structure comprises a fourth doped region of the first conductivity type overlapping a second end of the second bar structure well region, the second end being opposite the first end along a length of the second bar structure.

[0020] Preferably, the first doped region of the second bar structure comprises a pair of spaced apart doped regions arranged laterally along the first direction and extending longitudinally along the second direction within the well region of the second bar structure.

[0021] Preferably, the second doped region of the first bar structure overlaps the first end of the well region of the first bar structure; and

[0022] The second doped region of the second bar structure further comprises an extension portion extending through the well region between the pair of spaced apart doped regions of the second bar structure; the extension portion of the second doped region extending from the first end of the well region of the second bar structure to a second end of the well region, the second end being opposite the first end along a length of the second bar structure.

[0023] Preferably, further comprising:

[0024] In the second bar structure, a plurality of junction contacts are formed and connected to a pair of spaced apart doped regions between which the extension portion of the second doped region is formed.

[0025] Preferably, the first bar structure further comprises a third doped region of the second conductivity type overlapping a second end of the first bar structure well region, the second end being opposite the first end along a length of the first bar structure; and wherein the second bar structure comprises a fourth doped region of the first conductivity type overlapping a second end of the second bar structure well region, the second end being opposite the first end along a length of the second bar structure.

[0026] wherein the second bar structure further comprises a fourth doped region of the first conductivity type formed outside a second end of the well region of the second bar structure and connected to the extension portion of the second doped region of the second bar structure, the second end being opposite the first end along a length of the second bar structure.

[0027] Preferably, further comprising:

[0028] a fifth doped region of the first conductivity type formed in the current conduction region between the first bar structure and the second bar structure, the fifth doped region having a first portion overlapping the well region of the first bar structure and a second portion overlapping the well region of the second bar structure.

[0029] Preferably, further comprising a plurality of said fifth doped regions formed in the current conduction region between said first and second bar structures.

[0030] Preferably, said semiconductor layer comprises a semiconductor substrate and a lightly doped second conductivity type epitaxial layer formed on the semiconductor substrate.

[0031] Preferably, each of said first and second bar structures has a well region extending to accommodate the second doped region in each bar structure.

[0032] Preferably, further comprising:

[0033] a sixth doped region of a first conductivity type formed in the current conduction region between the first and second bar structures, said sixth doped region having a first portion overlapping the well region of said first bar structure and a second portion overlapping the well region of said second bar structure.

[0034] Preferably, further comprising:

[0035] a plurality of said sixth doped regions formed in the current conduction region between said first and second bar structures.

[0036] Preferably, the first doped region of said first bar structure comprises an extended portion, the well region of said first bar structure comprises an extended portion around the extended portion of said first doped region, the extended portion of said well region extends into the current conduction region between said first and second bar structures, the current conduction region between said first and second bar structures has a first spacing outside the extended portion, and the conductive region between the extended portions has a second spacing narrower than said first spacing.

[0037] Preferably, further comprising:

[0038] a polysilicon gate formed on a gate dielectric layer and around the first doped region of said first bar structure, said polysilicon gate formed in the well region of said first bar structure; and

[0039] a seventh doped region of a first conductivity type formed on the outer edge of the polysilicon gate, said seventh doped region covering the well region of said first bar structure and extending through the current conduction region to cover the well region of said second bar structure,

[0040] wherein said polysilicon gate, said first doped region and said seventh doped region form a MOS transistor.

[0041] Preferably, further comprising:

[0042] a polysilicon gate formed on the gate dielectric layer and adjacent to the first doped region of the first strip structure, the polysilicon gate overlapping the well region of the first strip structure; and

[0043] an eighth doped region of the first conductivity type formed on an outer edge of the polysilicon gate and in the current conducting region between the first strip structure and the adjacent second strip structure, wherein the polysilicon gate, the first doped region, and the eighth doped region form a MOS transistor.

[0044] Preferably, further comprising:

[0045] a ninth doped region of the first conductivity type formed in the current conducting region between the first strip structure and the adjacent second strip structure and overlapping the well region of the first strip structure; and

[0046] a trench formed adjacent to the ninth doped region and on the direct current path between the first strip structure and the second strip structure, the trench filled with a dielectric layer.

[0047] These and other features and advantages of the present application will become apparent to those skilled in the art from the following detailed description, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 shows a circuit diagram of a unidirectional TVS protection device in an embodiment of the present application;

[0049] Figure 2 shows Figure 1 shows an equivalent circuit diagram of a TVS protection device;

[0050] Figure 3 shows a set of TVS devices in parallel forming a multi-channel protection circuit 20 for providing transient voltage protection for a set of I / O 1 terminals to I / O N terminals;

[0051] Figure 4 shows in certain embodiments of the present application, the use of Figure 1 shows a unidirectional multi-channel TVS protection device of a TVS protection device;

[0052] Figure 5 shows a perspective view of an example device structure of a TVS protection device in certain examples;

[0053] Figure 6 shows a perspective view of an example device structure of a TVS protection device in another example;

[0054] Figure 7 includes Figure 7(a) shows a top view of a low capacitance TVS protection device in an example of the present application;

[0055] Figure 8 shows a top view of a low capacitance multi-channel TVS protection device in an example of the present application;

[0056] Figure 9 shows in some examples, Figure 7 shows a detail top view of a pair of strip structures in a TVS protection device;

[0057] Figure 10 shows in some examples, a cross-sectional view of a portion of a TVS device along the A-A' axis;

[0058] Figure 11 shows in some examples, a cross-sectional view of a portion of a TVS device along the B-B' axis;

[0059] Figure 12 shows a detail top view of a pair of strip structures in a TVS protection device in an alternative example;

[0060] Figure 13 shows in some examples, a cross-sectional view of a portion of a TVS device along the A-A' axis Figure 12 shows a cross-sectional view of a portion of a TVS device;

[0061] Figure 14 shows in some examples, a cross-sectional view of a portion of a TVS device along the B-B' axis Figure 12 shows a cross-sectional view of a portion of a TVS device;

[0062] Figure 15(a) shows current-voltage properties of a TVS protection device in an example of the present application;

[0063] Figure 15(b) shows current-voltage properties of a TVS protection device in an alternative example of the present application;

[0064] Figure 16 comprises Figure 16 (a) shows a top view of a TVS device in some examples of the present application incorporating a trigger voltage adjustment structure;

[0065] Figure 17 shows a top view of a TVS device incorporating a trigger voltage adjustment structure in an alternative example of the present application;

[0066] Figure 18 shows a top view of a TVS device incorporating a trigger voltage adjustment structure in an alternative example of the present application;

[0067] Figure 19 shows a top view of a TVS device incorporating a trigger voltage adjustment structure in an alternative example of the present application;

[0068] Figure 20 Figure (a) shows a top view of a TVS device incorporating a trigger voltage adjustment structure in accordance with alternative embodiments of the present application;

[0069] Figure 21 Figure (a) shows a top view of a TVS device incorporating a trigger voltage adjustment structure in accordance with alternative embodiments of the present application;

[0070] Figure 22 Figure (a) shows a top view of a TVS device incorporating a trigger voltage adjustment structure in accordance with alternative embodiments of the present application; Figure 22 (a), shows a top view of a TVS device incorporating a MOS trigger voltage adjustment structure in accordance with certain embodiments of the present application;

[0071] Figure 23 Figure (a) shows a top view of a TVS device incorporating a MOS trigger voltage adjustment structure in accordance with alternative embodiments of the present application;

[0072] Figure 24 Figure (a) shows a top view of a TVS device incorporating a trigger voltage adjustment structure in accordance with alternative embodiments of the present application; Figure 24 (a), shows a top view of a TVS device incorporating a MOS trigger voltage adjustment structure in accordance with certain embodiments of the present application;

[0073] Figure 25 Figure (a) shows a top view of a TVS device incorporating a MOS trigger voltage adjustment structure in accordance with alternative embodiments of the present application;

[0074] Figure 26 Figure (a) shows a top view of a TVS device incorporating a MOS trigger voltage adjustment structure in accordance with alternative embodiments of the present application;

[0075] Figure 27 Figure (a) shows a top view of a TVS device incorporating a MOS trigger voltage adjustment structure in accordance with alternative embodiments of the present application. DETAILED DESCRIPTION

[0076] The present application can be implemented in numerous ways, including as a process; an apparatus; a system; and / or a composition of matter. Generally, the

[0077] The principles of the application are explained and illustrated in detail in one or more embodiments of the application together with the attached drawings. Although the application is illustrated together with these embodiments, the scope of the application is not limited to any embodiment. The scope of the application is only defined by the claims, and the application encompasses various alternatives, modifications and equivalents. In the following description, various specific details are set forth in order to provide a thorough understanding of the application. These details are provided for the purpose of explanation only and are not intended to limit the application, according to the claims. For the purpose of simplicity and clarity, technical material that is well known in the art has not been described in detail so as not to obscure the application.

[0078] In embodiments of the application, a transient voltage suppressor (TVS) device includes a P-N junction diode and a silicon controlled rectifier (SCR) integrated in a lateral device structure of a semiconductor layer. The lateral device structure includes a plurality of strip structures of semiconductor regions horizontally arranged in a first direction on a main plane of the semiconductor layer, defining current conduction regions between the strip structures. A current path of the SCR and a current path of the P-N junction diode are formed in each current conduction region, but the current path of the SCR is primarily separated from the current path of the P-N junction diode in each current conduction region, a second direction being orthogonal to the first direction on the main plane of the semiconductor layer. The TVS device described in the present application is made using an integrated SCR and P-N diode device structure, which allows for low capacitance at the protected node by reducing the capacitance represented by the P-N junction diode. In this case, the TVS device with very low parasitic capacitance can be effectively used to protect data pins of an integrated circuit, especially when the data pins are used for high speed applications.

[0079] In the present application, a transient voltage suppressor device refers to a device that is coupled to a protected node of an integrated circuit ("protected node") to protect the protected node from overvoltage transients, such as voltage surges or voltage spikes. When a surge voltage at the protected node exceeds a breakdown voltage of the TVS device, the TVS device clamps the excess current on the protected node. The TVS device typically includes a clamping device for clamping the voltage at the protected node to a clamping voltage that is lower than the voltage surge voltage value while safely diverting the surge current.

[0080] TVS devices can be either unidirectional or bidirectional. Unidirectional TVS devices have asymmetric current-voltage properties and are typically used to protect a circuit node for unidirectional signals - that is, signals that are always above or below a particular reference voltage (e.g., ground). For example, a unidirectional TVS device can be used to protect a circuit node for which the normal signal is a positive voltage from 0V to 5V. Bidirectional TVS devices, on the other hand, have symmetric current-voltage properties and are typically used to protect a circuit node for bidirectional signals, or signals that have voltage levels above and below a reference voltage (low voltage). For example, a bidirectional TVS device can be used to protect a circuit node for which the normal signal varies symmetrically above and below ground, e.g., from -12V to 12V. In this case, the bidirectional TVS protects the circuit node from surges that are not below -12V or above 12V.

[0081] In operation, the TVS device is in the latched mode and non-conductive except for a leakage current that can occur when the voltage at the protected node is below the breakdown voltage (sometimes also referred to as the reverse breakdown voltage) of the TVS device. That is, the TVS device is non-conductive and in the latched mode when the voltage at the protected node is within the operating voltage range of the protected node. However, in the latched mode, the TVS device has capacitance to the protected node. When the protected node is connected to a high-speed data pin, the capacitance of the TVS device in the latched or non-conductive mode should be low so as not to impede the high-speed operation of the data pin.

[0082] In certain embodiments, the TVS devices described herein achieve very low capacitance values, below 0.2 pf, in the latched mode. The low capacitance TVS devices described herein can be effectively used to protect high-speed data pins or input-output (I / O) terminals in high-speed electronic devices, such as data pins in a USB 3.1 data bus, HDMI-2.0 data lines, or a cable V.

[0083] The TVS devices described herein have several advantages over conventional TVS protection devices. For example, the TVS devices described herein utilize an integrated diode / SCR structure to achieve very low junction capacitance at the protected node. Thus, the TVS devices described herein are suitable for high-speed data pin applications. In addition, the trigger voltage of the TVS device can be adjusted to a desired value by adjusting the breakdown voltage of the SCR device without changing the device area. In certain examples, an NPN transistor or MOS device is incorporated into the TVS device to adjust the trigger voltage to a desired value.

[0084] Figure 1 A circuit diagram of a unidirectional TVS protection device is shown in an embodiment of the present application. Referring to FIG. 1, a unidirectional TVS protection device 100 includes a diode 102 and a silicon controlled rectifier (SCR) 104. The diode 102 is connected in series with the SCR 104. The diode 102 is connected between a first node 106 and a second node 108. The SCR 104 is connected between the first node 106 and a third node 110. The first node 106 is connected to a protected node 112. The second node 108 is connected to a reference voltage 114, such as ground. The third node 110 is connected to a trigger node 116. The trigger node 116 is connected to a trigger voltage 118, such as a positive voltage. Figure 1The TVS protection device 10 (or "TVS device 10") includes a PN junction diode DL1 and a silicon controlled rectifier (SCR) connected in parallel between the I / O ports as the protected ("protected node") and ground potential. TVS device 10 integrates the high-side switching diode and clamping device onto a single SCR device. Additionally, TVS device 10 integrates the low-side switching diode DL1 and the SCR into a lateral device structure formed in a semiconductor layer. The purpose of TVS device 10 is to generate a parasitic capacitance on the protected node, thereby enabling its effective application in high-speed data line applications. In this embodiment, circuit symbol 15 is used to represent TVS protection device 10, which includes a PN junction diode and an SCR connected in parallel.

[0085] Figure 2 express Figure 1 The equivalent circuit diagram of the TVS protection device is shown. See also... Figure 2 The TVS device 10 includes a PN junction diode DL1, forward-biased between the protected node (I / O terminal) and ground potential. That is, the anode of diode DL1 is connected to the ground node, and the cathode of diode DL1 is connected to the protected node. Diode DL1 serves as the low-side switching diode of the TVS protection device. The TVS device 10 includes an SCR device connected in parallel with the PN junction diode DL1. Specifically, the SCR device can be represented as two back-to-back PNP and NPN bipolar transistors. The anode of the SCR device is the P-type emitter of the PNP bipolar transistor, which is also connected to the base resistor R. NW The cathode of the SCR device is the N-type emitter of the NPN bipolar transistor, connected to ground potential and through the base resistor R. PW It is connected to the N-type base of the NPN bipolar transistor. Therefore, at the protected node (I / O port), the main contributors to the parasitic capacitance of the TVS device are the N-type region of the PN junction diode DL1 and the anode of the SCR device.

[0086] Figure 1 The unidirectional TVS device 10 shown can be used to prepare a multi-channel TVS protection circuit for multiple protected nodes. Figure 3 A group of TVS devices 10, denoted by symbol 15, are connected in parallel to form a multichannel protection circuit 20, which provides transient voltage protection for a group of I / O ports I / O 1 to I / O 0. In some examples, the multichannel protection circuit 20 may include four or five TVS protection devices 10 to protect four or five protection nodes.

[0087] existFigure 1 and Figure 3 TVS protection device 10 is connected between a protected node (I / O port) and ground potential for protection of the ground from positive or negative voltage spikes. In other embodiments, TVS protection device 10 can also be connected between a protected node (I / O port) and a power supply potential (e.g., Vcc and Vdd) for protection of the power supply potential from positive or negative voltage spikes. In other embodiments, TVS protection device 10 can also be connected between two circuit nodes for protection of the two nodes from transient voltages.

[0088] In addition, Figure 1 and 3 TVS protection device is configured as a unidirectional TVS device with asymmetric current-voltage properties. In other embodiments, TVS protection device 10 can be configured as a bidirectional TVS protection device with symmetric current-voltage properties. Figure 4 TVS protection device 10 is configured as a bidirectional multi-channel TVS protection device 30. Referring to Figure 1 , bidirectional multi-channel TVS protection device 30 includes one TVS protection device 10 coupled to a first I / O port I / O 1 and another TVS protection device 10 coupled to a second I / O port I / O 2. The common node N1 between the two TVS protection devices is left floating, or not electrically connected to or biased to any potential. A sudden current from a positive or negative spike to one I / O port is shunted through the TVS protection device to the other I / O port. Figure 4

[0089] Figure 5 TVS protection device 50 is configured as a TVS protection device with a lateral device structure in a semiconductor substrate 52. Referring to Figure 5 , TVS protection device 50 is configured as a TVS protection device with a lateral device structure in a semiconductor substrate 52. Referring to Figure 1 Figure 5 ​​In the illustrated example device structure, the TVS device 50 includes alternating P-well regions 54 and N-well regions 56, horizontally arranged in a first direction on the main surface of a P-type semiconductor substrate 52. In this description, the first direction on the surface of the semiconductor substrate 52 is taken along the X-axis. Each P-well region 54 has a P+ doped region 58 and an N+ doped region 60. Each N-well region 56 has an N+ doped region 60 formed between two P+ doped regions 58. The well regions and doped regions extend as elongated strip structures in the P-type substrate 52 along the Z-axis. The doped regions in the N-well 56 are connected to protected nodes (I / O ports), while the doped regions in the P-well 54 are connected to ground potential. Thus, the TVS device 50 includes a current path formed between adjacent pairs of P-well and N-well regions. The well regions and doped regions are arranged in an alternating manner, forming an SCR device that serves as both a PN junction diode and a TVS protection device. Specifically, the PN junction diode and the SCR device share each current path along the entire length of the well and doped regions. The TVS protection circuit 50 is unsuitable for use with high-speed I / O ports because the TVS device introduces a large parasitic capacitance to the protected node. Additionally, the formed PN junction diode has high resistance due to its central location between the N-well and P-well. The TVS protection device 50 occupies a significant amount of space for its very low clamping capability.

[0090] Figure 6 This is a perspective view of an example device structure for a TVS protection device, shown in another example. See also... Figure 6 TVS protection device 70 and Figure 5 The TVS device 50 shown is similar, using a lateral device structure in a semiconductor substrate 72. However, in Figure 6 In the TVS device 70 shown, each well region (P-well 74 and N-well 76) includes a P+ doped region 78 and an N+ doped region 80 to form a current path for the PN junction diode and SCR device in an optional current path. That is, the PN junction diode and SCR device do not share the same current path. The PN junction diode conducts in the current path between two adjacent P and N well regions, while the SCR device conducts in the next current path between the next pair of adjacent P and N well regions. In each current path, the PN junction diode or SCR device conducts current along the entire length of the well and doped region in the Z-axis direction. While the TVS protection device 70 applies a low capacitance to the protected node, it has several drawbacks. For example, the device parameters of the TVS protection device 70 (such as the carrying voltage and trigger voltage) cannot be easily modulated, and modulation of the device parameters may result in an unnecessarily maximized device area, thus increasing the capacitance. Furthermore, the triggering of the TVS protection device 70 is non-uniform.

[0091] Figure 7 comprising Figure 7 (a) represents a top view of a low capacitance TVS protection device in an embodiment of the present invention. In the present description, a top view refers to the Z-axis plane of the TVS protection device. See Figure 7 The TVS protection device 100 described herein is formed in a semiconductor layer. In the present embodiment, the semiconductor layer comprises an epitaxial layer 102 formed on a semiconductor substrate. In one example, the epitaxial layer 102 is a P-type epitaxial layer and the substrate is a P-type substrate. Additionally, in some embodiments, the P-type substrate is a lightly doped substrate and the P-type epitaxial layer 102 can be a lightly doped P-type epitaxial layer or an intrinsic epitaxial layer. For example, the P-type substrate can have a resistivity of 20 ohm-cm and the P-type epitaxial layer can have a resistivity of approximately 100 ohms-cm or more. The P-type epitaxial layer 102 can have a thickness of approximately 20 microns.

[0092] The TVS protection device ("TVS device") 100 comprises a plurality of strip structures of semiconductor regions arranged laterally along a first direction on a major surface of the semiconductor layer. In the present description, the first direction on the major surface is taken along the X-axis, as shown in Figure 7 Each strip structure is formed of a first doped region having an opposite conductivity type and a second doped region arranged longitudinally along a second direction orthogonal to the first direction on the major surface of the semiconductor layer. In the present description, the orthogonal axis is taken along the Z-axis, as shown in Figure 7 In the present embodiment, the first doped region is located in a well region having a conductivity type opposite to that of the first doped region. Additionally, in the present embodiment, the second doped region is formed in the epitaxial layer and has a small portion of overlap with the well region at one end. The plurality of strip structures are arranged such that adjacent strip structures are formed of doped regions having opposite conductivity types. That is, a first strip structure can be formed of a first doped region of a first conductivity type located in a well region of a second conductivity type opposite to the first conductivity type. The first strip structure also has a second doped region of the second conductivity type overlapping the well region. Then, a second strip structure adjacent to the first strip structure will be formed of a first doped region of the second conductivity type located in a well region of the first conductivity type and a second doped region of the first conductivity type.

[0093] In this description, the multiple strip structures constituting the TVS device 10 are identified according to the conductivity type of the well region of the strip structure, where the well region of the strip structure carries a first doped region. Therefore, strip structure 15 is also referred to as a P-well strip structure, and strip structure 118 is also referred to as an N-well strip structure. In the P-well strip structure 115, the first doped region is an N+ doped region 110 located in the P-well 104, and the second doped region is a P+ doped region 108 extending longitudinally along the Z-axis of the strip structure. The P+ doped region 108 is formed in the P-type epitaxial layer 102, but only overlaps a small portion of the P-well 104. In the N-well strip structure 118, the first doped region is a P+ doped region 108 located in the N-well 106, and the second doped region is an N+ doped region 110 arranged longitudinally along the Z-axis of the strip structure. The N+ doped region 110 is formed in the P-type epitaxial layer 102, but only overlaps a small portion of the N-well 106.

[0094] TVS device 100 is made of alternating P-well strip structures 115 and N-well strip structures 118, such as Figure 7 As shown. The P-well strip structure 115 is electrically connected to the ground terminal 126 via conductive lines 122, such as metal wires. The N-well strip structure 118 is electrically connected to the protected node 124 via conductive lines 120, such as metal wires. In this example, the protected node 124 can be an I / O port of an integrated circuit. Conductive lines 120 and 122 are connected to the adjacent doped region via connectors. Figure 7 The connector is not shown in the image. Additionally, Figure 7 The description of conductive lines 120 and 122 shown is for illustrative purposes only, to provide a clearer depiction of the semiconductor regions. Those skilled in the art will understand that in the actual physical layout of the TVS device 100, conductive lines or metal lines 120, 122 will most likely be formed over the vast majority of the semiconductor regions. Figure 7 Used for indication only, not for limitation.

[0095] The P-well 104 of the P-well stripe structure of the base region of the NPN transistor of the SCR device 100 is electrically connected to the ground potential through the overlapping P+ doped region 108. In this embodiment, to enhance the good electrical connection and to improve the symmetrical current flow during the transient, each P-well 104 includes an additional P+ doped region 108a formed on the opposite side of the P-well from the overlapping P+ doped region. The P+ doped region 108a is also electrically connected to the ground node (126). The N-well is similar, each N-well 106 includes an additional N+ doped region 110a formed on the opposite end of the N-well from the overlapping N+ doped region. The N+ doped region 110a is electrically connected to the protected node 124 (I / O port). In this case, each P-well 104 is electrically connected to the ground node 126 through the P+ region 108 at one end and the P+ doped region 108a at the opposite end. At the same time, each N-well 104 is electrically connected to the protected node 124 through the N+ region 110 at one end and the N+ doped region 110a at the opposite end.

[0096] The TVS device 100 is formed of alternating P-well stripe structures 115 and N-well stripe structures 118 as the high-side protection structure of the SCR device and P-N junction diode as the low-side protection structure. The N-well stripe structures 118 are electrically connected to the protected node, such as the I / O port 124. The P-well stripe structures 115 are electrically connected to the ground node 126. In this case, the unidirectional single-channel TVS device 100 has the SCR device and the P-N junction diode, the SCR device is formed of the first doped regions and well regions in the alternating N-well stripe structures and P-well stripe structures, and the P-N junction diode is formed of the second doped regions in the alternating N-well stripe structures and P-well stripe structures. Specifically, the SCR device is formed of the P+ regions 108 and the N-well 106, the P-well 104, and the N+ regions 110 between a pair of adjacent N-well stripe structure and P-well stripe structure 118, 115. The P-N junction diode is formed of the N+ regions 110 and the P+ regions 108 between a pair of adjacent N-well stripe structure and P-well stripe structure 118, 115. Figure 7 (a) represents Figure 7 The equivalent circuit of the TVS device 100 is shown. The SCR device is formed of the P+ regions, the N-well, the P-well, and the N+ regions between a pair of adjacent N-well stripe structure and P-well stripe structure.

[0097] A distinguishing feature of the TVS device 100 is that the current paths of both the SCR device and the P-N junction diode are formed between each pair of stripe structures, but are separated in orthogonal directions. More specifically, alternating P-well stripe structures and N-well stripe structures define current conduction regions between the stripe structures. The current paths of both the SCR device and the P-N junction diode are formed between a pair of stripe structures in each current conduction region, but the current path of the SCR device is separated from the current path of the P-N junction diode in each current conduction region in a direction orthogonal to the first direction on the major surface of the semiconductor substrate. That is, the SCR current path is separated from the P-N junction diode current path in the Z-axis, which is orthogonal to the X-axis of the first direction on the major surface of the semiconductor substrate.

[0098] As such, the TVS device 100 results in very low capacitance to the protected node 124 (I / O port). More specifically, the P-N junction diode is the primary source of parasitic capacitance to the protected node. In embodiments of the present application, the P-N junction diode is formed from a doped region formed in the epitaxial layer 102 without any well region. Elimination of the well region for the P-N junction diode doped region has the effect of reducing parasitic capacitance on the protected node. In this case, the TVS device 100 achieves low capacitance at the protected node.

[0099] In Figure 7 The TVS device 100 is shown in the embodiment as a one-directional, single channel TVS device. In other embodiments, Figure 7 The TVS device structure shown in Figure 8 represents a top view of a low capacitance, multi-channel TVS protection device in embodiments of the present application. Referring to Figure 8 , a multi-channel TVS protection device 150 for a pair of I / O ports, I / O 1 and I / O 2, is made using Figure 7 the single channel TVS device structure shown in . More specifically, the TVS device 150 is made using a core device unit, and a mirror image of the core device unit connected at the ground node 126. In some cases, the TVS device 150 can be made as a bi-directional, multi-channel TVS device using a floating node instead of the ground node. That is, the node 126 can be grounded or floating (not connected to any potential). In a bi-directional TVS device, a transient current from one I / O can be diverted to another I / O.

[0100] Figure 9 represents a detail top view of a pair of stripe structures in the TVS protection device shown in Figure 7 . Referring to Figure 9TVS device 100 is fabricated with alternating P-well bar structures 115 and N-well bar structures 118 formed in P-type epitaxial layer 102. In P-well bar structure 115, the first doped region is an N+ doped region 110 in P-well 104, and the second doped region is a P+ doped region 108 arranged longitudinally along the bar structure in the Z-axis. P+ doped region 108 is formed in P-type epitaxial layer 102, but overlaps a small portion of P-well 104. P+ doped regions 108a are formed on opposite sides of P-well 104 to provide a symmetric junction to P-well. Junctions 128 are formed on P+ regions 108a, N+ region 110, and P+ region 108. Metal lines 122 are formed over junctions 128, connected together to form electrical junctions to P+ regions 108a, N+ region 110, and P+ region 108 to connect these semiconductor regions to a ground node.

[0101] In N-well bar structure 118, the first doped region is a P+ doped region 108 in N-well 106, and the second doped region is an N+ doped region 110 arranged longitudinally along the bar structure in the Z-axis. N+ doped region 110 is formed in P-type epitaxial layer 102, but overlaps a small portion of N-well 106. N+ doped regions 110a are formed on opposite ends of N-well 106 to provide a symmetric junction to N+ region 110. Junctions 128 are formed on N+ regions 110a, P+ region 108, and N+ region 110. Metal lines 120 are formed over junctions 128, connected together to form electrical junctions to N+ regions 110a, P+ region 108, and N+ region 110 to connect these semiconductor regions to a protected node (I / O port).

[0102] In this way, the first doped regions of two adjacent bar structures, along with the well regions, form an SCR device. The P-N junction diode is formed by the second doped regions of two adjacent bar structures. Figure 10 shows a portion of TVS device 100 along the A-A' axis Figure 9 shows a cross-sectional view of a portion of TVS device 100. Figure 10 shows a cross-sectional view of the SCR device of TVS device 100. Figure 11 shows a portion of TVS device 100 along the B-B' axis Figure 9 shows a cross-sectional view of a portion of TVS device 100. Figure 11 shows a cross-sectional view of the P-N junction diode of TVS device 100.

[0103] Referring to Figure 10 and Figure 11 TVS device 100 is formed on a semiconductor substrate, such as P-type substrate 101 with P-type epitaxial layer 102 formed on top of P-type substrate 101. P-type substrate 101 and P-type epitaxial layer 102 can be very lightly doped. As shown inFigure 10 As shown, the SCR device is formed in the first doped region and the respective well region of two adjacent strip structures. Specifically, the SCR device consists of the P+ doped region 108 and N-well 106 of the N-well strip structure 118, and the P-well 104 and N+ region 110 of the P-well strip structure 115. The P+ doped region 108 is connected to the protected node (I / O port) via a connector 128 and a metal line 120. The N+ doped region 110 is connected to the ground node via a connector 128 and a metal line 122. Meanwhile, along the orthogonal axis (Z-axis) strip structure, the PN junction diode is formed by the second doped region. Specifically, the PN junction diode is formed by the P+ doped region 108 and N+ doped region 110 formed in the P-type epitaxial layer 102, without any well region. The P+ doped region 108 is connected to the ground node via a connector 128 and a metal line 122. The N+ doped region 110 is connected to the protected node (I / O port) via connector 128 and metal line 120.

[0104] Figure 12 This is a detailed top view of a pair of strip structures in an alternative embodiment of the TVS protection device. See also Figure 12 Except for the well region, the configuration of the TVS device 160 is the same as that of other devices. Figure 7 The TVS device 100 shown is identical. In the TVS device 100, the well region is primarily fabricated to accommodate the first doped region. Figure 12 In the embodiment of the TVS device 160 shown, both the N-well 106 and the P-well 104 are extended to accommodate the second doped region. Specifically, the P-well 104 is extended to accommodate the N+ doped region 110 and the P+ doped region 108. Simultaneously, the N-well 106 is extended to accommodate the P+ doped region 108 and the N+ doped region 110. The remaining structure of the TVS device 160 is the same as... Figure 7 The TVS device 100 shown is the same.

[0105] Figure 13 In some embodiments, this indicates a portion along the A-A' axis. Figure 12 The diagram shows a cross-sectional view of the TVS device. Figure 13 This is a cross-sectional view of the SCR device, which is a TVS device 160. Figure 14 In some embodiments, this means along the B-B' axis Figure 12 The image shows a cross-sectional view of a portion of a TVS device. Figure 14A cross-sectional view of a P-N junction diode device representing the TVS device 160. In this way, the SCR device in the TVS device 160 is identical in device structure to the TVS device 100. However, the P-N junction diode in the TVS device 160 is formed by the P+ doped region 108 formed in the P-well 104 and the N+ doped region 110 formed in the N-well 106. The TVS device 160 represents an alternative embodiment of the TVS device 100 such that the N-well and P-well of the bar structure can be extended so that the first and second doped regions can be accommodated in each bar structure.

[0106] Figure 15(a) illustrates the current-voltage behavior of a TVS protection device in certain embodiments of the present application. Referring to Figure 15(a), the curve 180 depicts the relationship between the reverse current conducted by the TVS device and the voltage applied at the protected node. During normal operation, the voltage at the protected node should be within the operating voltage range and the TVS device is in the latched mode and does not conduct any current except for the leakage current. If the voltage at the protected node reaches the trigger voltage (V Tri ) of the TVS device, the TVS device turns on and conducts the excess current. Specifically, the SCR of the TVS device snaps back quickly and clamps the voltage at the protected node at the holding voltage while the TVS device safely conducts the current away from the protected node.

[0107] In certain situations, it is necessary to adjust the trigger voltage of the TVS device so that the TVS device is more sensitive to voltage surges. In embodiments of the present application, the TVS device is introduced with a structure so that the trigger voltage of the TVS device is adjusted to the desired voltage level while preserving the very low parasitic capacitance property of the TVS device. In certain embodiments, the TVS device described in the present application has a very low trigger voltage. Alternatively, the TVS device described in the present application has a very low holding voltage close to the operating voltage. Further, in certain embodiments, the TVS device described in the present application is designed to directly enter the holding voltage of the SCR when a transient condition occurs at the protected node where the voltage exceeds the trigger voltage without snapping back quickly or with a very low snap back.

[0108] Figure 15(b) illustrates the current-voltage behavior of a TVS protection device in an alternative embodiment of the present application. Referring to Figure 15(b), the curve 185 depicts the relationship between the reverse current conducted by the TVS device and the voltage applied at the protected node. In this illustration, the protected node has a very low operating voltage range, for example, 1 V or less. The TVS device is in the latched mode and does not conduct any current except for the leakage current for voltages within the operating voltage range (1 V or less). The TVS device has a relatively large trigger voltage (V Tri), above but close to the operating voltage range. When a transient causes the voltage at the protected node to exceed the trigger voltage, the TVS device turns on, directly entering the holding voltage of the SCR, conducting the excess current. That is, the TVS device enters the holding voltage without going through a rapid snapback. Alternatively, the TVS device enters the holding voltage through a small rapid snapback, as shown by curve 187 in the figure. In this case, the TVS device clamps the voltage at the protected node at the holding voltage while the TVS device safely conducts current away from the protected node.

[0109] In some embodiments, the TVS device shown in Fig. 15(a) has a trigger voltage in the range of 12V for an operating voltage of 5V or less. Meanwhile, the TVS device shown in Fig. 15(b) has a trigger voltage of 5V or less for a trigger voltage of 1V or less.

[0110] The TVS device directly enters the holding voltage without going through a large rapid snapback has many benefits, especially when used to protect low voltage nodes. Referring still to Fig. 15(b), some protected nodes can have a fault voltage (V Fail ) that is very close to the operating voltage range. In this case, a TVS device with a high trigger voltage or a large rapid snapback performance can expose the protected node to a voltage above the fault voltage, causing permanent damage to the protected node. In accordance with embodiments of the present application, a TVS device with the current-voltage performance shown in Fig. 15(b) directly enters the holding voltage without a rapid snapback or with only a small rapid snapback to clamp the voltage at the protected node, ensuring that the voltage at the protected node never exceeds the fault voltage. In one example, the operating voltage range is 1V or less and the fault voltage is 3V. When a transient occurs, the configuration voltage of the TVS device is directly between 1V and 3V, the TVS device enters the holding voltage clamping the voltage at the protected node at the holding voltage between 1V and 3V. The TVS device does not snapback or only experiences a small snapback, so that the voltage at the protected node never exceeds the fault voltage of 3V V Fail The TVS devices shown in accordance with the present application can be effectively used to protect protected nodes with a low operating voltage range (e.g., 1V) or protected nodes with a fault voltage close to the operating voltage range (e.g., 3V).

[0111] Figure 16 includes Figure 16 (a) shows a top view of a TVS device incorporating a trigger voltage adjustment structure in accordance with some embodiments of the present application. Referring to Fig. 16(a), the TVS device 200 is configured in a similar manner as the TVS device 100 shown in Fig. 16(a). Figure 16 The TVS device 200 is configured in a similar manner as the TVS device 100 shown in Fig. 16(a). Figure 7 The TVS device 200 is configured in a similar manner as the TVS device 100 shown in Fig. 16(a). Figure 7and 16 Similar elements in FIGS. 2A and 2B are given similar reference numbers, and will not be described again. To enable tuning or adjustment of the trigger voltage, TVS device 200 incorporates an N+ and P- well structure for trigger voltage adjustment. TVS device 200 includes an N+ doped region 110b formed in the current conduction region between the adjacent P- and N- well stripe structures as a trigger voltage adjustment structure. In this embodiment, N+ doped region 110b occupies only a small fraction of the P- well length, so as not to introduce parasitic capacitance to the protected node. N+ doped region 110b includes a first portion superimposed on P- well 104, and a second portion extending through the current conduction region and superimposed on N- well 106. Thus, N+ doped region 110b is biased to the N- well voltage, bridging the N- well voltage to P- well 104. Figure 16 (a) indicates that in some embodiments, a small portion of the length of the P- well along the C-C' axis is occupied by the N+ doped region Figure 16 A cross-sectional view of the TVS device is shown. Referring to Figure 16 (a), the additional N+ doped region 110b connects the N- well voltage to P- well 104, which has the effect of lowering the trigger voltage.

[0112] In TVS device 200, the width of P- well 104 can be extended, increasing the distance between N+ doped region 110b and N+ region 110, which is located in P- well 104. The increased distance prevents punchthrough between the two N+ doped regions.

[0113] In this embodiment, N+ doped region 110b is configured in a T-shape, with the horizontal portion of the N+ doped region overlapping P- well 104, and the very narrow extended portion of the N+ doped region extending over the current conduction region and overlapping N- well 106. In an alternative embodiment, N+ doped region 110b includes only the long overlap region over the P- well, and N+ doped region 110b can be electrically connected to N- well 106 by other means, such as a junction and a metal line.

[0114] In an alternative embodiment, a TVS device can incorporate a P+ doped region overlapping the N- well as a trigger voltage adjustment structure. The P+ doped region is biased to the P- well potential.

[0115] Figure 17 A top view of a TVS device incorporating a trigger voltage adjustment structure is shown. Referring to Figure 17 , TVS device 250 is configured in a similar manner as TVS device 200 shown in Figure 16 , and incorporates N+ doped region 110b as a trigger voltage adjustment structure. In Figure 17In the illustrated embodiment, the N-well bar structure is fabricated using a split P+ doped region. More specifically, a P+ doped region is formed in the N-well 106 and split into a first P+ doped region 108b and a second P+ doped region 108c. In addition, an N+ doped region 110 generally overlaps the N-well 106, including an elongated portion 110c that extends through the N-well and connects to an N+ doped region 110a at the other end of the N-well. In particular, the N+ doped region 110c can be placed directly between the first and second P+ doped regions 108b and 108c. The split P+ doped region achieves an increase in the holding voltage of the TVS device by reducing the base resistance of the N-well. In other embodiments, a TVS device can be fabricated by splitting the N+ doped region into two and elongating the P+ doped region between the split N+ doped regions, as shown in Figure 25 .

[0116] Figure 25 A top view of a TVS device incorporating a trigger voltage adjustment structure in an alternative embodiment of the present application is shown. Referring to Figure 25 , the TVS device 500 is configured in a similar manner as the TVS device 250 shown in Figure 17 , and incorporates an N+ doped region 110b as a trigger voltage adjustment structure. In Figure 25 , the P-well bar structure is fabricated using a split N+ doped region. More specifically, the N+ doped region formed in the P-well 104 is split into a first N+ doped region 110b and a second N+ doped region 110c. In addition, a P+ doped region 108 generally overlaps the P-well 104, including an elongated portion 108c that extends through the P-well and connects to a P+ doped region 108a at the other end of the P-well. In particular, the P+ doped region 108c can be placed directly between the first and second N+ doped regions 110b and 110c. The split N+ doped region achieves an increase in the holding voltage of the TVS device by reducing the base resistance of the P-well.

[0117] In Figure 17 and 25 , a split P+ doped region or a split N+ doped region is used to increase the holding voltage. In both cases, a heavily doped region of opposite polarity extends between the split doped regions. In other embodiments, a TVS device can be fabricated using islands of oppositely doped regions, as shown in Figure 26 and 27 .

[0118] Figure 26 A top view of a TVS device incorporating a trigger voltage adjustment structure in an alternative embodiment of the present application is shown. Referring to Figure 26 , the TVS device 550 is configured in a similar manner as the TVS device 250 shown in Figure 17The configuration of the TVS device 250 is similar to that shown in Figure 26 In the embodiment shown, the N-well bar structure is made using islands of P+ doped regions formed in the N+ doped region 110. The islands of P+ doped regions can be shorted to the N+ doped region by a butt joint. Alternatively, the P+ doped regions can be connected to the N+ doped region and surrounding P+ doped regions using separate joints. In Figure 26 In the embodiment shown, the N-well 106 overlaps the P+ doped region 108 at one end. The P+ doped region is omitted at the other end.

[0119] Figure 27 A top view of a TVS device incorporating a trigger voltage adjustment structure in an alternative embodiment of the present application is shown. Referring to Fig. 28, a TVS device 280 is shown. The configuration of the TVS device 280 is similar to that shown in Figure 27 , the configuration of the TVS device 580 is similar to that shown in Figure 25 The configuration of the TVS device 500 is similar to that shown in Figure 27 In the embodiment shown, the P-well bar structure is made using islands of P+ doped regions formed in the N+ doped region 110. The islands of P+ doped regions can be shorted to the N+ doped region by a butt joint. Alternatively, the P+ doped regions can be connected to the N+ doped region and surrounding P+ doped regions using separate joints. In Figure 27 In the embodiment shown, the P-well 104 overlaps the N+ doped region 110 at one end. The N+ doped region is omitted at the other end.

[0120] Figure 18 A top view of a TVS device incorporating a trigger voltage adjustment structure in an alternative embodiment of the present application is shown. Referring to Fig. 28, a TVS device 280 is shown. The configuration of the TVS device 280 is similar to that shown in Figure 18 , the configuration of the TVS device 580 is similar to that shown in Figure 17 The configuration of the TVS device 250 is similar to that shown in

[0121] Figure 19This is a top view of a TVS device in an optional embodiment of the invention, incorporating a trigger voltage regulation structure. See also... Figure 19 The configuration method of TVS device 300 and Figure 7 The TVS device 100 shown is configured similarly. (Given...) Figure 7 and 19 Similar components are assigned similar reference quantities, and will not be repeated here. To tune or adjust the trigger voltage, the TVS device 300 introduces a P-well in the N-well spacing structure for trigger voltage regulation. Specifically, the TVS device 300 includes a P-well 104 with an extension 104a and an N+ doped region 110 with an extension 110d, serving as the trigger voltage regulation structure. The extensions 104a and 110d extend a portion of the N+ doped region and the P-well, extending into the current conduction region between the P-well stripe and the N-well stripe. Therefore, the region containing the narrow spacing (distance "Y") between two adjacent stripes is formed by the normal spacing between two adjacent stripes, denoted by distance "X".

[0122] As the N+ doped region 110d extends towards the N-well 106, the NPN transistor formed in this region will turn on first, and the NPN transistor has the effect of reducing the trigger voltage. Specifically, the N-well 106 forms the NPN transistor as the collector, the P-well 104 as the base, and the extended N+ doped region 110d as the emitter. Simultaneously, the TVS device 300 maintains a very low parasitic capacitance.

[0123] In this embodiment, the N+ doped region and P-well are extended only locally, that is, for a small portion of the P-well's length. For example, the extension could be 15-30% of the P-well length. In other embodiments, the overall length of the P-well and N+ doped region can extend towards the adjacent N-well. In other words, the distance between the P-well strip and the N-well strip can be reduced to improve the trigger voltage.

[0124] In this embodiment, the N+ doped region and P-well are extended locally only to reduce the distance to the N-well. In other embodiments, the extended portion may be made using the N-well and P+ region located therein. That is, the P+ region and N-well may include extended portions to reduce the distance between the well regions of two adjacent strip structures.

[0125] Figure 20 This is a top view of a TVS device in an optional embodiment of the invention, incorporating a trigger voltage regulation structure. See also... Figure 20 The configuration method of TVS device 320 and Figure 19The TVS device 300 is configured similarly to the TVS device 200 shown in FIG. 14(a), and incorporates an N+ doped region extension 110d and a P-well extension 104a as a trigger voltage adjustment structure. The TVS device 320 also shows the use of split P+ doped regions 108b, 108c in the adjacent N-well strip structure. In the N-well strip structure, the N+ doped region 110 extends through the N-well to be adjacent to the N+ doped region 110a. The TVS device 320 also shows the use of a butt joint 130 to electrically connect the P+ doped regions 108b and 108c to the N+ region 110 in the N-well 106.

[0126] Figure 21 A top view of a TVS device incorporating a trigger voltage adjustment structure in an alternative embodiment of the present application is shown. Referring to FIG. 16(a), the TVS device 340 is configured similarly to the TVS device 300 shown in FIG. 15(a), and incorporates an N+ doped region extension 110d and a P-well extension 104a as a trigger voltage adjustment structure. In this embodiment, the TVS device 340 does not have an N+ doped region 110a and a P+ doped region 108a for better connection of the well region away from the second doped region at one end. In this case, the N-well 106 is connected to the N+ region 110 at the overlapping region. Thus, the N-well is only biased to the N+ region 110 at one end of the well region, thereby increasing the well resistance. The increase in well resistance increases the base resistance of the NPN bipolar transistor of the SCR device, and decreases the trigger voltage of the SCR. At the same time, in the P-well strip structure, the P+ region 108 is not overlapped by the P-well 104. The P-well 104 is connected to the P+ region 108 through the resistance of the underlying P-type epitaxial layer 102. Thus, the P-well resistance is increased, and the trigger voltage of the SCR is decreased. Figure 21 Figure 19 The TVS device 340 shown can be effectively used to achieve the current-voltage property as shown in FIG. 15(b). In particular, by increasing the base resistance of the NPN bipolar transistor of the SCR device, the trigger voltage can be decreased, and the TVS device can directly enter the holding voltage when a transient occurs, without jumping back quickly.

[0127] The TVS device 340 shown represents one method of increasing the base resistance of the NPN bipolar transistor of the SCR device. Other methods of increasing the base resistance can also be used, such as omitting the use of the butt joint shown in FIG. 16(a). Figure 21 Figure 21 Figure 20 In an alternative embodiment of the present application, a TVS device incorporates a MOS trigger condition structure.

[0128] In an alternative embodiment of the present application, a TVS device incorporates a MOS trigger condition structure. Figure 22 Figure 22 ​​​(a) shows a top view of a TVS device incorporating a MOS trigger voltage regulation structure in some embodiments of the invention. See also Figure 22 The configuration method of TVS device 360 ​​and Figure 7 The TVS device 100 shown is configured similarly. Figure 7 and 22 Similar reference quantities are given for similar components and will not be repeated here. To tune or adjust the trigger voltage, the TVS device 360 ​​incorporates a MOS transistor for trigger voltage regulation. The TVS device 360 ​​includes a polysilicon gate 140 formed in a raceway structure surrounding an N+ doped region 110e, with all the aforementioned components formed in a P-well 104. The polysilicon gate 140 is formed above a gate oxide layer (not shown) on the surface of the epitaxial layer 102. The N+ doped region 110e formed inside the polysilicon gate 140 constitutes the source of the MOS transistor. The N+ doped region 110f formed outside the polysilicon gate 140 and the covering P-well 104 constitute the drain of the MOS transistor. The N+ doped region 110f includes a first portion covering the P-well 104 and a second portion extending through the current-conducting region and covering an adjacent N-well 106. In this way, the MOS transistor is formed directly on the polysilicon gate 140 by N+ doped regions 110e and 110f. The drain of the MOS transistor, the N+ doped region 110f, is biased to the N-well voltage by covering the N-well 106.

[0129] Figure 22 (a) indicates that in some embodiments, along the D-D' axis Figure 22 A cross-sectional view of a portion of a TVS device is shown. See also... Figure 22 (a) The MOS transistor trigger structure is formed by a polysilicon gate 140 and provides a gate oxide layer 142, which is insulated from the P-type epitaxial layer 102. The polysilicon gate 140 is formed above the P-well 104 and serves as the body region of the MOS transistor. The N+ doped region 110e serves as the source of the MOS transistor. The N+ doped region 110f covers the P-well 104, extends through the current conduction region, and overlaps with the N-well 106. The N+ doped region 110f serves as the drain of the MOS transistor and is electrically connected to the N-well potential.

[0130] The polysilicon gate 140 is electrically connected to the N-well potential (as shown by line 144 in the figure). The physical connection between the polysilicon gate 140 and the N-well can be achieved in various ways. For example, conductive lines such as polysilicon or metal can be used to connect the polysilicon gate 140 to the N-well. Because the polysilicon gate is electrically connected to the N-well potential, and the drain is not connected to the N-well potential, the gate of the MOS transistor is shorted to the drain. This causes current to flow from the N+ source 110e to the N+ drain 110f below the control terminal of the polysilicon gate 140. In this case, the trigger voltage of the SCR can be modulated or adjusted.

[0131] Figure 23 This is a top view of a TVS device in an optional embodiment of the invention, incorporating a MOS trigger voltage regulation structure. See also... Figure 23 The configuration method of TVS device 380 and Figure 22 The TVS device 360 ​​shown is configured similarly, and a MOS transistor is introduced as a trigger voltage regulation structure. Figure 23 In the illustrated embodiment, the polysilicon gate of the MOS transistor serves as a dwell structure rather than a raceway. In this embodiment, the polysilicon gate 146 has a T-shaped structure, including a horizontal portion formed in the P-well 104, constituting the body of the MOS transistor, and an extension extending through the current conduction region between the P-well stripe and the N-well stripe. An N+ region 110 located in the P-well 104 includes an extension 110e touching the inner edge of the polysilicon gate 146. The N+ doped region 110e constitutes the source of the MOS transistor. Another N+ doped region 110f is formed on the opposite side of the polysilicon gate 146, constituting the drain of the MOS transistor. A junction may be formed on the drain region 110f, electrically connecting the drain to the gate of the MOS transistor.

[0132] exist Figure 23 In the illustrated embodiment, the N+ doped region 110f does not touch the N-well 106 of the adjacent strip structure. However, during operation, the depletion region of the N-well 106 will touch the N+ doped region 110f in order to bias the N+ doped region 110f to the N-well potential.

[0133] Figure 24 include Figure 24 (a) shows a top view of a TVS device incorporating a trigger voltage regulation structure in some embodiments of the invention. See also Figure 24 The configuration method of TVS device 400 and Figure 7 The TVS device 100 shown is configured similarly. Figure 7 and 24Similar elements in the figures are designated with similar reference numbers and similar elements will not be discussed further below. To tune or adjust the trigger voltage, the TVS device 400 incorporates an N+ to P-well structure for trigger voltage adjustment. More specifically, the TVS device 400 includes an N+ doped region 110g formed in the current conduction region overlying the P-well 104 as a trigger voltage adjustment structure. In the present embodiment, the trigger voltage adjustment structure includes one or more dielectric-filled trenches 170 disposed adjacent the N+ doped region 110g in the DC path between the N+ doped region 110g and the adjacent N-well 106. In some embodiments, the trenches 170 are filled with silicon oxide or silicon nitride. Figure 24 (a) indicates that in some embodiments, along the E-e' axis Figure 24 (b) shows a cross-sectional view of a portion of a TVS device. Figure 24 (a), the N+ doped region 110g is formed overlying the P-well 104 but is not connected to the N-well 106. Conversely, the trenches 170 are formed to isolate the N+ doped region 110g from the N-well in the DC path between the N+ doped region 110g and the N-well 106.

[0134] The trenches 170 in the DC path between the N+ doped region 110g and the N-well 106 serve to reduce the parasitic capacitance at the protected node. Although the N+ doped region 110g is not directly connected to the N-well 106, during operation the N-well 106 will reach around the outer edge of the N+ doped region 110g to indirectly connect the N+ doped region 110g to the N-well potential to bias the N+ doped region 110g to the N-well potential.

[0135] In the above embodiments, the split P+ doped region and the use of the butt joint are presented in combination with the trigger voltage adjustment structure. In other embodiments, either the split P+ doped region or the split N+ doped region or the use of the butt joint can be used alone in a TVS device without the use of the trigger voltage adjustment structure.

[0136] While the foregoing is directed to embodiments of the application, the application is not limited to such details. Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing. The embodiments discussed herein are presented for purposes of illustration and not limitation.​​​​​​

Claims

1. A transient voltage suppression device, characterized by, The semiconductor regions of the first and second strip structures are arranged in a first direction on a main surface of the semiconductor layer, the first and second strip structures extending in a second direction on the main surface of the semiconductor layer that is orthogonal to the first direction, a first portion of the semiconductor regions of the first strip structure and a first portion of the semiconductor regions of the second strip structure forming a thyristor, a second portion of the semiconductor regions of the first strip structure and a second portion of the semiconductor regions of the second strip structure forming a P-N junction diode, the first and second strip structures defining a current conduction region between the strip structures; in each of the strip structures, the first portion of the semiconductor regions, the second portion of the semiconductor regions are arranged in a sequence in the second direction; the first strip structure includes a first doped region of a first conductivity type contained in a well region of a second conductivity type opposite the first conductivity type, and a second doped region of the second conductivity type arranged along a length of the first strip structure in the second direction; and the second strip structure includes a first doped region of the second conductivity type contained in a well region of the first conductivity type, and a second doped region of the first conductivity type arranged along a length of the second strip structure in the second direction. the current conduction region between the first and second strip structures includes a first current path of the thyristor and a second current path of the P-N junction diode, the first current path of the thyristor and the second current path of the P-N junction diode being isolated in the current conduction region in the second direction that is orthogonal to the first direction on the main surface of the semiconductor layer.

2. The transient voltage suppression device of claim 1, wherein, the first doped region and the well region of the first strip structure, the first doped region and the well region of the second strip structure form the thyristor, the second doped region of the first strip structure, the second doped region of the second strip structure form the P-N junction diode.

3. The transient voltage suppression device of Claim 1, wherein, the semiconductor regions of the first strip structure are electrically connected to a reference node, the semiconductor regions of the second strip structure are electrically connected to a protected node.

4. The transient voltage suppression device of Claim 1, wherein, the second doped region of the first strip structure covers a first end of the well region of the first strip structure, the second doped region of the second strip structure covers a first end of the well region of the second strip structure.

5. The transient voltage suppression device of Claim 1, wherein, the first strip structure further includes a third doped region of the second conductivity type covering a second end of the well region of the first strip structure, the second end being opposite the first end along the length of the first strip structure, and wherein the second strip structure includes a fourth doped region of the first conductivity type covering a second end of the well region of the second strip structure, the second end being opposite the first end along the length of the second strip structure.

6. The transient voltage suppression device of Claim 5, wherein, the first doped region of the second strip structure includes a pair of spaced apart doped regions arranged in the first direction and extending in the second direction in the well region of the second strip structure.

7. The transient voltage suppression device of Claim 1, wherein, ​ 8. The transient voltage suppression device of claim 7, wherein: the second doped region of the first bar-shaped structure overlaps a first end of a well region of the first bar-shaped structure; and the second doped region of the second bar-shaped structure further comprises an extension portion extending through a well region between a pair of spaced apart doped regions of the second bar-shaped structure; the extension portion of the second doped region of the second bar-shaped structure extending from a first end of the well region of the second bar-shaped structure to a second end of the well region of the second bar-shaped structure, the second end opposite the first end along a length of the second bar-shaped structure.

9. The transient voltage suppression device of Claim 8, wherein, Further comprising: a plurality of contact pads formed in the second bar-shaped structure and connected to the pair of spaced apart doped regions, the extension portion of the second doped region of the second bar-shaped structure being formed therebetween.

10. The transient voltage suppression device of Claim 8, wherein, the first bar-shaped structure further comprises a third doped region of the second conductivity type overlapping a second end of the well region of the first bar-shaped structure, the second end opposite the first end along a length of the first bar-shaped structure; and wherein the second bar-shaped structure further comprises a fourth doped region of the first conductivity type formed outside the second end of the well region of the second bar-shaped structure and connected to the extension portion of the second doped region of the second bar-shaped structure, the second end opposite the first end along a length of the second bar-shaped structure.

11. The transient voltage suppression device of Claim 7, wherein, Further comprising: a fifth doped region of the first conductivity type formed in a current conduction region between the first bar-shaped structure and the second bar-shaped structure, the fifth doped region having a first portion overlapping the well region of the first bar-shaped structure and a second portion overlapping the well region of the second bar-shaped structure.

12. The transient voltage suppression device of Claim 11, wherein, Further comprising: a plurality of the fifth doped regions formed in the current conduction region between the first bar-shaped structure and the second bar-shaped structure.

13. The transient voltage suppression device of Claim 1, wherein, the semiconductor layer comprises a semiconductor substrate and a lightly doped epitaxial layer of the second conductivity type formed on the semiconductor substrate.

14. The transient voltage suppression device of Claim 1, wherein, each of the well regions of the first and second bar-shaped structures extends to accommodate the second doped region in each bar-shaped structure.

15. The transient voltage suppression device of Claim 1, wherein, Further comprising: a sixth doped region of the first conductivity type formed in a current conduction region between the first bar-shaped structure and the second bar-shaped structure, the sixth doped region having a first portion overlapping the well region of the first bar-shaped structure and a second portion overlapping the well region of the second bar-shaped structure.

16. The transient voltage suppression device of Claim 15, wherein, Further comprising: a plurality of the sixth doped regions formed in the current conduction region between the first bar-shaped structure and the second bar-shaped structure.

17. The transient voltage suppression device of Claim 1, wherein, the first doped region of the first bar-shaped structure comprises an extension portion, the well region of the first bar-shaped structure comprises an extension portion surrounding the extension portion of the first doped region, the extension portion of the well region of the first bar-shaped structure extending into a current conduction region between the first bar-shaped structure and the second bar-shaped structure, the current conduction region between the first bar-shaped structure and the second bar-shaped structure having a first spacing outside the extension portion and a conductive region between the extension portions having a second spacing narrower than the first spacing.

18. The transient voltage suppression device of Claim 1, wherein, Further comprising: a polysilicon gate formed on a gate dielectric layer and surrounding a first doped region of the first strip structure, the polysilicon gate formed in a well region of the first strip structure; and a seventh doped region of a first conductivity type formed on an outer edge of the polysilicon gate, the seventh doped region covering the well region of the first strip structure and extending through the current conduction region to cover a well region of the second strip structure, wherein the polysilicon gate, the first doped region of the first strip structure, and the seventh doped region form a MOS transistor.

19. The transient voltage suppression device of Claim 1, wherein, Further comprising: a polysilicon gate formed on a gate dielectric layer and adjacent to a first doped region of the first strip structure, the polysilicon gate overlapping a well region of the first strip structure; and an eighth doped region of a first conductivity type formed on an outer edge of the polysilicon gate, the eighth doped region located in a conductive region between the first strip structure and the adjacent second strip structure, wherein the polysilicon gate, the first doped region of the first strip structure, and the eighth doped region form a MOS transistor.

20. The transient voltage suppression device of Claim 1, wherein, Further comprising: a ninth doped region of a first conductivity type formed in a current conduction region between the first strip structure and the adjacent second strip structure and overlapping a well region of the first strip structure; and a trench formed adjacent to the ninth doped region and on a direct current path between the first strip structure and the second strip structure, the trench filled with a dielectric layer.

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