A semiconductor structure and a method of fabricating the same

Abstract

The application provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, a germanium virtual substrate layer formed above the substrate, a germanium-silicon inverse graded buffer layer formed above the germanium virtual substrate layer, a first germanium-silicon confinement layer formed above the germanium-silicon inverse graded buffer layer, a germanium quantum well layer formed above the first germanium-silicon confinement layer, a second germanium-silicon confinement layer formed above the germanium quantum well layer, and a silicon cap layer formed above the second germanium-silicon confinement layer. The germanium virtual substrate layer and the germanium-silicon inverse graded buffer layer are sequentially formed, and then the first germanium-silicon confinement layer, the germanium quantum well layer and the second germanium-silicon confinement layer are sequentially formed on the germanium-silicon inverse graded buffer layer. By adjusting the overmodulation degree of the germanium-silicon inverse graded buffer layer, the strain of the germanium quantum well layer can be controlled, a heterojunction structure containing a high-mobility two-dimensional hole gas which can confine carriers is formed, the nuclear spin interference phenomenon is improved, the semiconductor structure is compatible with a large-scale silicon-based CMOS, and the preparation cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Rashba spin-orbit coupling (SOC) is the theoretical basis for realizing gate-controlled quantum computing. Although traditional III–V materials have strong spin-orbit coupling, their spin-orbit coupling is a mixture of Dresselhaus spin-orbit coupling and Rashba spin-orbit coupling. At the same time, III–V materials have strong nuclear spin interference and are difficult to be compatible with large-scale silicon-based CMOS, resulting in high fabrication costs. Summary of the Invention

[0003] This invention provides a semiconductor structure and its fabrication method, which uses a group IV material Ge / GeSi / Si system to form a heterojunction structure containing a high-mobility two-dimensional hole gas that can confine charge carriers, improve nuclear spin interference, facilitate compatibility with large-scale silicon-based CMOS, and reduce fabrication costs.

[0004] In a first aspect, the present invention provides a semiconductor structure comprising a substrate, a germanium virtual substrate layer formed on the substrate, a germanium-silicon inverse gradient buffer layer formed on the germanium virtual substrate layer, a first germanium-silicon confinement layer formed on the germanium-silicon inverse gradient buffer layer, a germanium quantum well layer formed on the first germanium-silicon confinement layer, a second germanium-silicon confinement layer formed on the germanium quantum well layer, and a silicon cap layer formed on the second germanium-silicon confinement layer.

[0005] In the above scheme, a germanium virtual substrate layer and a germanium-silicon inverse graded buffer layer are sequentially formed using a group IV material Ge / GeSi / Si system. Then, a first germanium-silicon confinement layer, a germanium quantum well layer, and a second germanium-silicon confinement layer are sequentially formed on the germanium-silicon inverse graded buffer layer. By adjusting the transition degree of the germanium-silicon inverse graded buffer layer, the strain of the germanium quantum well layer can be controlled, forming a heterojunction structure containing high-mobility two-dimensional hole gas that can confine charge carriers. This improves nuclear spin interference, facilitates compatibility with large-scale silicon-based CMOS, and reduces fabrication costs. Furthermore, the semiconductor structure of this invention can also be applied to the field of solid-state semiconductor quantum computing, enabling the fabrication of large-scale quantum dots on germanium quantum well layers.

[0006] In one specific embodiment, the germanium virtual substrate layer includes: first, a low-temperature germanium virtual substrate layer grown on top of a substrate using low-temperature epitaxy, and then a high-temperature germanium virtual substrate layer grown on top of the low-temperature germanium virtual substrate layer using high-temperature epitaxy. By employing a two-step growth method using high and low temperature epitaxy, the low-temperature germanium virtual substrate layer and the high-temperature germanium virtual substrate layer are formed sequentially. This allows for sufficient strain release in the low-temperature layer and accommodates dislocations caused by strain release, resulting in a fully relaxed germanium virtual substrate layer. Simultaneously, through sufficient strain release with the germanium-silicon inverse gradient buffer layer, the pseudomorphic growth phenomenon in the first germanium-silicon confinement layer in subsequent steps is reduced. This allows for the introduction of sufficient compressive strain into the germanium quantum well layer when growing the germanium quantum well after the first germanium-silicon confinement layer.

[0007] In one specific implementation, the material of the germanium-silicon reverse gradient buffer layer is Ge x Si 1-x Where x ranges from 1.0 to any value between 0.6 and 0.95, from the bottom to the top of the germanium-silicon inverse graded buffer layer. This enables the realization of higher quality, high-mobility two-dimensional hole gas heterojunction structures.

[0008] In one specific embodiment, both the first germanium-silicon confinement layer and the second germanium-silicon confinement layer are made of Ge. y Si 1-y Where y is any value between 0.6 and 0.95. This enables the realization of higher quality, high-mobility two-dimensional hole-gas heterojunction structures.

[0009] In one specific embodiment, the semiconductor structure further includes a dislocation isolation pattern embedded at the bottom of at least one of the layers in the germanium virtual substrate layer, the germanium-silicon inverse gradient buffer layer, and the first germanium-silicon confinement layer. The dislocation isolation pattern at the bottom of the layer structure comprises multiple dislocation isolation structures; any two adjacent dislocation isolation structures are separated by the layer structure. By embedding a dislocation isolation pattern at the bottom of at least one of the layers in the germanium virtual substrate layer, the germanium-silicon inverse gradient buffer layer, and the first germanium-silicon confinement layer, most dislocations and defects in germanium are confined below the dislocation isolation pattern region. Therefore, high-quality germanium material can be grown more effectively above the dislocation isolation pattern region. The dislocation isolation pattern increases dislocation tolerance, enabling dislocation containment, blocking the upward extension of penetrating dislocations, and blocking penetrating dislocations caused by lattice mismatch, thus achieving a higher-quality, high-mobility two-dimensional hole gas heterojunction structure.

[0010] In one specific embodiment, the semiconductor structure further includes a dislocation isolation layer formed between at least one of the following layers: the interlayer between the substrate and the germanium virtual substrate, the interlayer between the germanium virtual substrate and the germanium-silicon inverse graded buffer layer, and the interlayer between the germanium-silicon inverse graded buffer layer and the first germanium-silicon confinement layer. By forming a dislocation isolation layer between at least one of the following layers: the interlayer between the substrate and the germanium virtual substrate, the interlayer between the germanium virtual substrate and the germanium-silicon inverse graded buffer layer, and the interlayer between the germanium-silicon inverse graded buffer layer and the first germanium-silicon confinement layer, it is possible to block the upward extension of penetrating dislocations and block penetrating dislocations generated by lattice mismatch, thereby achieving a higher quality, high-mobility two-dimensional hole gas heterojunction structure.

[0011] In one specific embodiment, the semiconductor structure further includes: a dislocation isolation layer formed between at least one of the layers between the substrate and the germanium virtual substrate layer, between the germanium virtual substrate layer and the germanium-silicon inverse gradient buffer layer, and between the germanium-silicon inverse gradient buffer layer and the first germanium-silicon confinement layer; and a dislocation isolation pattern embedded at the bottom of at least one of the layers in the germanium virtual substrate layer, the germanium-silicon inverse gradient buffer layer, and the first germanium-silicon confinement layer. The dislocation isolation pattern at the bottom of the layer structure includes multiple dislocation isolation structures; any two adjacent dislocation isolation structures are separated by the layer structure. By employing both methods simultaneously, most dislocations and defects in germanium are confined to the dislocation isolation pattern region, thus enabling better growth of high-quality germanium material on top of the dislocation isolation pattern region. The dislocation isolation pattern increases dislocation tolerance, enabling dislocation containment, blocking the upward extension of penetrating dislocations, and blocking penetrating dislocations caused by lattice mismatch, thereby achieving a higher-quality, high-mobility two-dimensional hole gas heterojunction structure.

[0012] In one specific implementation, each dislocation isolation structure in the plurality of dislocation isolation structures is made of oxide, nitride, silicon, or germanium. This improves the dislocation containment effect, enhances the blocking effect on the upward extension of penetrating dislocations, and improves the blocking effect on penetrating dislocations caused by lattice mismatch, thereby achieving a higher quality, high-mobility two-dimensional hole gas heterojunction structure.

[0013] In one specific implementation, each of the multiple dislocation isolation structures is a pillar, frustum, or cone with a rectangular, rhomboid, or circular cross-sectional shape. This improves the dislocation containment effect, enhances the blocking effect on the upward extension of penetrating dislocations, and improves the blocking effect on penetrating dislocations caused by lattice mismatch, thereby achieving a higher quality, high-mobility two-dimensional hole-gas heterojunction structure.

[0014] In one specific implementation, the dislocation isolation layer is a germanium lattice structure layer or a germanium-silicon lattice structure layer. Alternatively, the dislocation isolation layer is a superlattice multilayer structure layer formed by alternating growth of germanium and germanium-silicon lattice structure layers. This improves the dislocation containment effect, enhances the blocking effect on the upward extension of penetrating dislocations, and improves the blocking effect on penetrating dislocations caused by lattice mismatch, thereby achieving a higher quality, high-mobility two-dimensional hole-gas heterojunction structure.

[0015] In a second aspect, the present invention also provides a method for fabricating a semiconductor structure, the method comprising: providing a substrate; forming a germanium virtual substrate layer on the substrate; forming a germanium-silicon inverse gradient buffer layer on the germanium virtual substrate layer; forming a first germanium-silicon confinement layer on the germanium-silicon inverse gradient buffer layer; forming a germanium quantum well layer on the first germanium-silicon confinement layer; forming a second germanium-silicon confinement layer on the germanium quantum well layer; and forming a silicon cap layer on the second germanium-silicon confinement layer.

[0016] In the above scheme, a germanium virtual substrate layer and a germanium-silicon inverse graded buffer layer are sequentially formed using a group IV material Ge / GeSi / Si system. Then, a first germanium-silicon confinement layer, a germanium quantum well layer, and a second germanium-silicon confinement layer are sequentially formed on the germanium-silicon inverse graded buffer layer. By adjusting the transition degree of the germanium-silicon inverse graded buffer layer, the strain of the germanium quantum well layer can be controlled, forming a heterojunction structure containing high-mobility two-dimensional hole gas that can confine charge carriers. This improves nuclear spin interference, facilitates compatibility with large-scale silicon-based CMOS, and reduces fabrication costs. Furthermore, the semiconductor structure of this invention can also be applied to the field of solid-state semiconductor quantum computing, enabling the fabrication of large-scale quantum dots on germanium quantum well layers. Attached Figure Description

[0017] Figure 1 This is a cross-sectional view of a semiconductor structure provided in an embodiment of the present invention;

[0018] Figure 2 This is a cross-sectional view of another semiconductor structure provided in an embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of a structure after depositing a dislocation isolation structure material on a substrate, as provided in an embodiment of the present invention.

[0020] Figure 4 For etching Figure 3 A schematic diagram of the dislocation isolation pattern formed by the structure shown;

[0021] Figure 5 This is a cross-sectional view of another semiconductor structure provided in an embodiment of the present invention;

[0022] Figure 6 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention.

[0023] Figure label:

[0024] 10-Substrate; 20-Germanium virtual substrate layer; 30-Germanium-silicon inverse gradient buffer layer

[0025] 40 - First germanium-silicon confinement layer; 50 - Germanium quantum well layer; 60 - Second germanium-silicon confinement layer

[0026] 70 - Silicon cap layer; 80 - Dislocation isolation structure; 81 - Dislocation isolation structure material

[0027] 90 - Dislocation isolation layer; 91 - Germanium lattice structure layer; 92 - Germanium-silicon lattice structure layer Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] To facilitate understanding of the semiconductor structure provided in the embodiments of the present invention, the application scenarios of the semiconductor structure provided in the embodiments of the present invention will be described first. This semiconductor structure is used in the fabrication process of transistors such as, but not limited to, CMOS. Of course, this semiconductor structure can also be applied to the field of solid-state semiconductor quantum computing for the fabrication of large-scale quantum dots. The semiconductor structure will now be described in detail with reference to the accompanying drawings.

[0030] refer to Figure 1 The semiconductor structure provided in this embodiment of the invention includes a substrate 10, a germanium virtual substrate layer 20 formed on the substrate 10, a germanium-silicon inverse gradient buffer layer 30 formed on the germanium virtual substrate layer 20, a first germanium-silicon confinement layer 40 formed on the germanium-silicon inverse gradient buffer layer 30, a germanium quantum well layer 50 formed on the first germanium-silicon confinement layer 40, a second germanium-silicon confinement layer 60 formed on the germanium quantum well layer 50, and a silicon cap layer 70 formed on the second germanium-silicon confinement layer 60.

[0031] In the above scheme, a germanium virtual substrate layer 20 and a germanium-silicon inverse graded buffer layer 30 are sequentially formed using a group IV material Ge / GeSi / Si system. Then, a first germanium-silicon confinement layer 40, a germanium quantum well layer 50, and a second germanium-silicon confinement layer 60 are sequentially formed on the germanium-silicon inverse graded buffer layer 30. By adjusting the transition degree of the germanium-silicon inverse graded buffer layer 30, the strain of the germanium quantum well layer 50 can be controlled, forming a heterojunction structure containing high-mobility two-dimensional hole gas that can confine charge carriers. This improves nuclear spin interference, facilitates compatibility with large-scale silicon-based CMOS, and reduces fabrication costs. Furthermore, the semiconductor structure provided in this embodiment can also be applied to the field of solid-state semiconductor quantum computing, enabling the fabrication of large-scale quantum dots on the germanium quantum well layer 50. The following is a detailed description of each of the above structures in conjunction with the accompanying drawings.

[0032] When setting the substrate 10, a silicon substrate 10 formed of a material such as, but not limited to, silicon can be used as a carrier for setting other material layers and microelectronic devices.

[0033] refer to Figure 1 A germanium virtual substrate layer 20 is formed above the substrate 10. Specifically, when forming the germanium virtual substrate layer 20 above the substrate 10, a low-temperature epitaxial growth technique can be used to epitaxially grow a low-temperature germanium virtual substrate layer 20 above the substrate 10, followed by a high-temperature epitaxial growth technique to epitaxially grow a high-temperature germanium virtual substrate layer 20 on top of the low-temperature germanium virtual substrate layer 20. By employing a two-step high- and low-temperature epitaxial growth method to form the low-temperature germanium virtual substrate layer 20 and the high-temperature germanium virtual substrate layer 20 sequentially, the strain in the low-temperature layer can be fully released and the dislocations caused by the strain release can be accommodated, resulting in a fully relaxed germanium virtual substrate layer 20. At the same time, through sufficient strain release with the germanium-silicon inverse gradient buffer layer 30, the pseudomorphic growth phenomenon of the first germanium-silicon confinement layer 40 in the subsequent steps can be reduced. Thus, when the germanium quantum well layer 50 is grown after the first germanium-silicon confinement layer 40, sufficient compressive strain can be introduced into the germanium quantum well layer 50. It should be understood that the formation method of the germanium virtual substrate is not limited to the method shown above; other methods can also be used.

[0034] Next, continue to refer to Figure 1 A germanium-silicon inverse gradient buffer layer 30 is formed above the germanium virtual substrate layer 20. Specifically, the germanium-silicon inverse gradient buffer layer 30 can be formed using epitaxial growth processes such as, but not limited to, MBE, UHVCVD, and RPCVD, above the germanium virtual substrate layer 20. When determining the material of the germanium-silicon inverse gradient buffer layer 30, the material is Ge. x Si 1-xWhere x extends from the bottom to the top of the germanium-silicon inverse graded buffer layer 30, ranging from 1.0 to any value between 0.6 and 0.95. Specifically, it can range from 1.0 to any value between 0.6 and 0.95, such as 0.60, 0.65, 0.70, 0.75, 0.80, 0.85, 0.90, and 0.95. That is, in the germanium-silicon inverse graded buffer layer 30, the closer to the bottom, the higher the germanium content; at the lowest point, the germanium content is almost 100%. Conversely, the closer to the top, the lower the germanium content; at the very top, the germanium content drops to almost any value between 60% and 95%, thus achieving a higher quality, high-mobility two-dimensional hole gas heterojunction structure. It should be understood that the above only shows one way of setting the germanium-silicon reverse gradient buffer layer 30. In addition, other ways of forming the germanium-silicon reverse gradient buffer layer 30 can also be used.

[0035] Next, as Figure 1 As shown, a first germanium-silicon confinement layer 40 is formed above the germanium-silicon inverse gradient buffer layer 30, a germanium quantum well layer 50 is formed on the first germanium-silicon confinement layer 40, and a second germanium-silicon confinement layer 60 is formed on the germanium quantum well layer 50. The materials of both the first germanium-silicon confinement layer 40 and the second germanium-silicon confinement layer 60 can be Ge. y Si 1-y Where y is any value between 0.6 and 0.95. Specifically, the value of y can be any value between 0.6 and 0.95, such as 0.60, 0.65, 0.70, 0.75, 0.80, 0.85, 0.90, 0.95, etc. The value of y is generally matched with the inverse graded cutoff composition of the germanium-silicon inverse graded buffer layer 30 to achieve a higher quality, high-mobility two-dimensional hole gas heterojunction structure. In addition, when forming a first germanium-silicon confinement layer 40 above the germanium-silicon inverse gradient buffer layer 30, forming a germanium quantum well layer 50 on the first germanium-silicon confinement layer 40, and forming a second germanium-silicon confinement layer 60 on the germanium quantum well layer 50, epitaxial growth processes such as, but not limited to, MBE (Molecular Beam Epitaxy), UHVCVD (Ultra-High Vacuum Chemical Vapor Deposition), and RPCVD (Reduced Pressure Chemical Vapor Deposition) can be used to sequentially form the first germanium-silicon confinement layer 40 above the germanium-silicon inverse gradient buffer layer 30, form the germanium quantum well layer 50 on the first germanium-silicon confinement layer 40, and form the second germanium-silicon confinement layer 60 on the germanium quantum well layer 50.

[0036] Compared with existing technologies, this application utilizes the characteristics of germanium, a group IV material, which contains only Rashba spin-orbit coupling (SOC), is compatible with large-scale silicon-based integrated circuits, and possesses relatively strong spin-orbit coupling strength, to realize an excellent carrier for gate-controlled quantum computing. This application sequentially forms a germanium virtual substrate layer 20 and a germanium-silicon inverse graded buffer layer 30, and then sequentially forms a first germanium-silicon confinement layer 40, a germanium quantum well layer 50, and a second germanium-silicon confinement layer 60 on the germanium-silicon inverse graded buffer layer 30. By adjusting the transition degree of the germanium-silicon inverse graded buffer layer 30, the strain of the germanium quantum well layer 50 can be controlled, forming a heterojunction structure containing high-mobility two-dimensional hole gas that can confine charge carriers, improving nuclear spin interference, facilitating compatibility with large-scale silicon-based CMOS, and reducing fabrication costs. In other words, utilizing the high hole carrier mobility of germanium, the final GeSi / Ge heterojunction material can form a high-mobility two-dimensional hole gas, which is beneficial for quantum integration. Furthermore, the semiconductor structure provided in this embodiment of the invention can also be applied to the field of solid-state semiconductor quantum computing, enabling the fabrication of large-scale quantum dots in the germanium quantum well layer 50.

[0037] Continue to refer to Figure 1 Furthermore, a silicon cap layer 70 can be formed on the surface of the second germanium-silicon confinement layer 60. The material of the silicon cap layer 70 can be silicon, silicon dioxide, or other materials, to protect the second germanium-silicon confinement layer 60.

[0038] Additionally, refer to Figure 2 The semiconductor structure may further include a dislocation isolation pattern embedded at the bottom of at least one of the following layer structures: a germanium virtual substrate layer 20, a germanium-silicon inverse gradient buffer layer 30, and a first germanium-silicon confinement layer 40. The dislocation isolation pattern at the bottom of the layer structure comprises a plurality of dislocation isolation structures 80, and any two adjacent dislocation isolation structures 80 are separated by the layer structure. The dislocation isolation pattern can be implemented as follows: Figure 2The dislocation isolation pattern shown is embedded only at the bottom of the germanium virtual substrate layer 20. Of course, the dislocation isolation pattern can also be embedded only at the bottom of the germanium-silicon inverse gradient buffer layer 30, or only at the bottom of the first germanium-silicon confinement layer 40. Furthermore, the dislocation isolation pattern can be embedded only at the bottom of any two of the germanium virtual substrate layer 20, the germanium-silicon inverse gradient buffer layer 30, and the first germanium-silicon confinement layer 40; that is, dislocation isolation patterns are embedded at the bottom of any two of the germanium virtual substrate layer 20, the germanium-silicon inverse gradient buffer layer 30, and the first germanium-silicon confinement layer 40. For example, the dislocation isolation pattern can be embedded only at the bottom of the germanium virtual substrate layer 20 and the germanium-silicon inverse gradient buffer layer 30, while no dislocation isolation pattern is embedded at the bottom of the first germanium-silicon confinement layer 40. Furthermore, dislocation isolation patterns can be embedded at the bottom of each of the three layer structures: the germanium virtual substrate 20, the germanium-silicon inverse gradient buffer layer 30, and the first germanium-silicon confinement layer 40. That is, dislocation isolation patterns are embedded at the bottom of all three layer structures. By embedding dislocation isolation patterns at the bottom of at least one of these layer structures, most dislocations and defects in germanium are confined below the dislocation isolation pattern region. Therefore, high-quality germanium materials can be grown more effectively above the dislocation isolation pattern region. The dislocation isolation pattern increases dislocation tolerance, enabling dislocation containment, blocking the upward extension of penetrating dislocations, and preventing penetrating dislocations caused by lattice mismatch, thus achieving a higher-quality, high-mobility two-dimensional hole gas heterojunction structure.

[0039] When setting the dislocation isolation pattern in each layer structure, each dislocation isolation structure 80 in the multiple dislocation isolation structures 80 of the same dislocation isolation pattern can be made of materials such as, but not limited to, oxides, nitrides, silicon, or germanium, wherein the oxide can be an oxide material such as silicon dioxide. This improves the dislocation containment effect, enhances the effect of blocking the upward extension of penetrating dislocations, and enhances the effect of blocking penetrating dislocations caused by lattice mismatch, thereby achieving a higher quality, high-mobility two-dimensional hole gas heterojunction structure.

[0040] Furthermore, each of the multiple dislocation isolation structures 80 can specifically be a cylinder, frustum, or cone with a rectangular, rhomboid, or circular cross-sectional shape. For example, each dislocation isolation structure 80 can be a cylinder with a rectangular cross-sectional shape; specifically, the rectangle can be a rectangle, in which case each dislocation isolation structure 80 is a long strip structure; the rectangle can also be a square, in which case each dislocation isolation structure 80 is a square cylinder structure. When each dislocation isolation structure 80 is a cylinder with a circular cross-sectional shape, each dislocation isolation structure 80 is a cylindrical structure. When each dislocation isolation structure 80 is a cylinder with a rhomboid cross-sectional shape, each dislocation isolation structure 80 is a rhomboid cylinder structure. When each dislocation isolation structure 80 is a frustum with a rectangular cross-sectional shape, the cross-section of each dislocation isolation structure 80 is rectangular, but the area of ​​the cross-section gradually decreases from the bottom to the top. When each dislocation isolation structure 80 is a frustum with a circular cross-sectional shape, each dislocation isolation structure 80 is a frustum structure. When each dislocation isolation structure 80 is a cone with a circular cross-sectional shape, then each dislocation isolation structure 80 is a conical structure. This arrangement improves the dislocation containment effect, enhances the blocking effect on the upward extension of penetrating dislocations, and improves the blocking effect on penetrating dislocations caused by lattice mismatch, resulting in a higher-quality, high-mobility two-dimensional hole-gas heterojunction structure. Furthermore, multiple dislocation isolation structures 80 within the same dislocation isolation pattern can be arranged periodically, making the dislocation isolation effect more uniform at each position within the same dislocation isolation pattern.

[0041] The following is combined with Figure 2 , Figure 3 and Figure 4 This section describes a method for forming dislocation isolation patterns at the bottom of a germanium virtual substrate 20. For details, please refer to [reference needed]. Figure 3 First, a dislocation isolation structure material 81 is deposited on the substrate 10. This dislocation isolation structure material 81 can be an oxide, nitride, silicon, or germanium as shown above. The specific deposition method can be thermal oxidation, PECVD (Plasma Enhanced Chemical Vapor Deposition), ALD (Atom Layer Deposition), or other processes. Then, refer to... Figure 4Dislocation isolation patterns are etched onto the dislocation isolation structure material 81 using methods such as photolithography. Then, a germanium virtual substrate layer 20 is epitaxially grown on the upper surface, sidewalls, and surface of the substrate 10 between adjacent dislocation isolation structures 80, thereby embedding the dislocation isolation pattern at the bottom of the germanium virtual substrate layer 20. This process can also be applied to embedding dislocation isolation patterns at the bottom of the germanium-silicon inverse gradient buffer layer 30 or the first germanium-silicon confinement layer 40. The specific embedding method can be adjusted according to different placement positions, which will not be elaborated further here.

[0042] Furthermore, refer to Figure 5 The semiconductor structure may further include a dislocation isolation layer 90 formed in at least one of the following interlayers: between the substrate 10 and the germanium virtual substrate 20, between the germanium virtual substrate 20 and the germanium-silicon inverse gradient buffer layer 30, and between the germanium-silicon inverse gradient buffer layer 30 and the first germanium-silicon confinement layer 40. By forming the dislocation isolation layer 90 in at least one of the following interlayers: between the substrate 10 and the germanium virtual substrate 20, between the germanium virtual substrate 20 and the germanium-silicon inverse gradient buffer layer 30, and between the germanium-silicon inverse gradient buffer layer 30 and the first germanium-silicon confinement layer 40, it is possible to block the upward extension of penetrating dislocations and block penetrating dislocations generated by lattice mismatch, thereby achieving a higher quality, high-mobility two-dimensional hole gas heterojunction structure.

[0043] For example, it can be like Figure 5 The diagram shows a dislocation isolation layer 90 formed between the substrate 10 and the germanium virtual substrate layer 20, a dislocation isolation layer 90 also formed between the germanium virtual substrate layer 20 and the germanium-silicon inverse gradient buffer layer 30, and a dislocation isolation layer 90 also formed between the germanium-silicon inverse gradient buffer layer 30 and the first germanium-silicon confinement layer 40; that is, in any two adjacent layers of the four layer structures—the substrate 10, the germanium virtual substrate layer 20, the germanium-silicon inverse gradient buffer layer 30, and the first germanium-silicon confinement layer 40—a dislocation isolation layer 90 is set between them. It should be understood that the dislocation isolation layer 90 is not limited to... Figure 5Besides the configuration shown, other configuration methods can also be used. For example, only one dislocation isolation layer 90 can be provided. Specifically, the dislocation isolation layer 90 can be provided only between the substrate 10 and the germanium virtual substrate layer 20, or only between the germanium virtual substrate layer 20 and the germanium-silicon inverse gradient buffer layer 30, or only between the germanium-silicon inverse gradient buffer layer 30 and the first germanium-silicon confinement layer 40. Of course, only two dislocation isolation layers 90 can also be provided. Specifically, dislocation isolation layers 90 may be provided only between the substrate 10 and the germanium virtual substrate layer 20, and between the germanium virtual substrate layer 20 and the germanium-silicon inverse gradient buffer layer 30; dislocation isolation layers 90 may be provided only between the substrate 10 and the germanium virtual substrate layer 20, and between the germanium-silicon inverse gradient buffer layer 30 and the first germanium-silicon confinement layer 40; dislocation isolation layers 90 may be provided only between the germanium virtual substrate layer 20 and the germanium-silicon inverse gradient buffer layer 30, and between the germanium-silicon inverse gradient buffer layer 30 and the first germanium-silicon confinement layer 40.

[0044] When setting each dislocation isolation layer 90, the dislocation isolation layer 90 can be a germanium lattice structure layer, that is, each dislocation isolation layer 90 is formed by only one germanium lattice structure layer. The dislocation isolation layer 90 can also be a germanium-silicon lattice structure layer, that is, each dislocation isolation layer 90 is formed by only one germanium-silicon lattice structure layer. Of course, the arrangement of the dislocation isolation layer 90 is not limited to the methods shown above; other methods can also be used. For example, it can be used as follows... Figure 5 The dislocation isolation layer 90 shown is a superlattice multilayer structure formed by alternating growth of germanium lattice structure layer 91 and germanium-silicon lattice structure layer 92. Specifically, refer to... Figure 5 Each superlattice multilayer structure is formed by alternating growth of germanium lattice structure layer 91 and germanium-silicon lattice structure layer 92. Specifically, the germanium lattice structure layer 91 or germanium-silicon lattice structure layer 92 in the dislocation isolation layer 90 can be epitaxially grown using epitaxial growth processes such as, but not limited to, MBE, UHVCVD, and RPCVD, as described above. By configuring the dislocation isolation layer 90 as shown above, the dislocation containment effect can be improved, the effect of blocking the upward extension of penetrating dislocations can be improved, and the effect of blocking penetrating dislocations caused by lattice mismatch can be improved, thus achieving a higher quality, high-mobility two-dimensional hole gas heterojunction structure.

[0045] Furthermore, both a dislocation isolation layer 90 and a dislocation isolation pattern can be formed in the same semiconductor structure. The dislocation isolation layer 90 is formed between at least one of the following layers: the substrate 10 and the germanium virtual substrate layer 20; the germanium virtual substrate layer 20 and the germanium-silicon inverse gradient buffer layer 30; and the germanium-silicon inverse gradient buffer layer 30 and the first germanium-silicon confinement layer 40. The dislocation isolation pattern is embedded at the bottom of at least one of the germanium virtual substrate layer 20, the germanium-silicon inverse gradient buffer layer 30, and the first germanium-silicon confinement layer 40. The dislocation isolation pattern at the bottom of this layer structure includes a plurality of dislocation isolation structures 80, and any two adjacent dislocation isolation structures 80 are separated by a layer structure. The specific methods for forming the dislocation isolation layer 90 and the dislocation isolation pattern are described above and will not be repeated here. By employing both methods simultaneously, most dislocations and defects in germanium are confined below the dislocation isolation pattern region. Therefore, high-quality germanium materials can be grown more effectively above the dislocation isolation pattern region. The dislocation isolation pattern increases dislocation tolerance, enabling dislocation containment, blocking the upward extension of penetrating dislocations, and preventing penetrating dislocations caused by lattice mismatch, thus achieving a higher-quality, high-mobility two-dimensional hole-gas heterojunction structure.

[0046] By employing a Ge / GeSi / Si system, a germanium virtual substrate layer 20 and a germanium-silicon inverse graded buffer layer 30 are sequentially formed. Then, a first germanium-silicon confinement layer 40, a germanium quantum well layer 50, and a second germanium-silicon confinement layer 60 are sequentially formed on the germanium-silicon inverse graded buffer layer 30. By adjusting the transition degree of the germanium-silicon inverse graded buffer layer 30, the strain of the germanium quantum well layer 50 can be controlled, forming a heterojunction structure containing high-mobility two-dimensional hole gas that can confine charge carriers. This improves nuclear spin interference, facilitates compatibility with large-scale silicon-based CMOS, and reduces fabrication costs. Furthermore, the semiconductor structure provided in this embodiment can also be applied to the field of solid-state semiconductor quantum computing, enabling the fabrication of large-scale quantum dots on the germanium quantum well layer 50.

[0047] In addition, embodiments of the present invention also provide a method for fabricating a semiconductor structure, see reference. Figure 1 and Figure 6 The preparation method includes:

[0048] S10: Provides a substrate 10;

[0049] S20: A germanium virtual substrate layer 20 is formed above the substrate 10;

[0050] S30: A germanium-silicon reverse gradient buffer layer 30 is formed above the germanium virtual substrate layer 20;

[0051] S40: A first germanium-silicon confinement layer 40 is formed above the germanium-silicon inverse gradient buffer layer 30;

[0052] S50: A germanium quantum well layer 50 is formed on the first germanium-silicon confinement layer 40;

[0053] S60: A second germanium-silicon confinement layer 60 is formed on the germanium quantum well layer 50;

[0054] S70: A silicon cap layer 70 is formed on the second germanium-silicon confinement layer 60.

[0055] In the above scheme, a germanium virtual substrate layer 20 and a germanium-silicon inverse graded buffer layer 30 are sequentially formed using a group IV material Ge / GeSi / Si system. Then, a first germanium-silicon confinement layer 40, a germanium quantum well layer 50, and a second germanium-silicon confinement layer 60 are sequentially formed on the germanium-silicon inverse graded buffer layer 30. By adjusting the transition degree of the germanium-silicon inverse graded buffer layer 30, the strain of the germanium quantum well layer 50 can be controlled, forming a heterojunction structure containing high-mobility two-dimensional hole gas that can confine charge carriers. This improves nuclear spin interference, facilitates compatibility with large-scale silicon-based CMOS, and reduces fabrication costs. Furthermore, the semiconductor structure provided in this embodiment can also be applied to the field of solid-state semiconductor quantum computing, enabling the fabrication of large-scale quantum dots on the germanium quantum well layer 50.

[0056] The specific preparation methods for each of the above steps are described in the preceding section on the corresponding parts of the semiconductor structure, and will not be repeated here.

[0057] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A germanium virtual substrate layer is formed above the substrate; A germanium-silicon inverse graded buffer layer is formed above the germanium virtual substrate layer, wherein the material of the germanium-silicon inverse graded buffer layer is Ge. x Si 1-x x is any value between 1.0 and 0.95, from the bottom of the germanium-silicon inverse gradient buffer layer to the top of the germanium-silicon inverse gradient buffer layer. A first germanium-silicon confinement layer is formed above the germanium-silicon inverse gradient buffer layer; A germanium quantum well layer formed on the first germanium-silicon confinement layer; A second germanium-silicon confinement layer is formed on the germanium quantum well layer; A silicon cap layer is formed on the second germanium-silicon confinement layer; Also includes: A dislocation isolation pattern is embedded at the bottom of at least one of the germanium virtual substrate layer, germanium-silicon inverse gradient buffer layer, and first germanium-silicon confinement layer, wherein the dislocation isolation pattern at the bottom of the layer structure includes a plurality of dislocation isolation structures, wherein any two adjacent dislocation isolation structures are separated by the layer structure; and / or, a dislocation isolation layer is formed between at least one of the layers between the substrate and the germanium virtual substrate layer, between the germanium virtual substrate layer and the germanium-silicon inverse gradient buffer layer, and between the germanium-silicon inverse gradient buffer layer and the first germanium-silicon confinement layer.

2. The semiconductor structure as described in claim 1, characterized in that, The germanium virtual substrate layer includes: A low-temperature germanium virtual substrate layer is grown on the substrate using low-temperature epitaxy technology; A high-temperature germanium virtual substrate layer is grown on the low-temperature germanium virtual substrate layer using high-temperature epitaxy technology.

3. The semiconductor structure as described in claim 1, characterized in that, The first germanium-silicon confinement layer and the second germanium-silicon confinement layer are both made of Ge. y Si 1-y , where y is any value between 0.6 and 0.

95.

4. The semiconductor structure as described in claim 1, characterized in that, The material of each of the plurality of dislocation isolation structures is: oxide, nitride, silicon, or germanium.

5. The semiconductor structure as described in claim 1, characterized in that, Each of the multiple dislocation isolation structures is a cylinder, frustum, or cone with a rectangular, rhomboid, or circular cross-sectional shape.

6. The semiconductor structure as described in claim 1, characterized in that, The dislocation isolation layer is a germanium lattice structure layer or a germanium-silicon lattice structure layer; or... The dislocation isolation layer is a superlattice multilayer structure formed by alternating growth of germanium lattice structure layers and germanium-silicon lattice structure layers.

7. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A germanium virtual substrate layer is formed above the substrate; A germanium-silicon inverse graded buffer layer is formed above the germanium virtual substrate layer, wherein the material of the germanium-silicon inverse graded buffer layer is Ge. x Si 1-x x is any value between 1.0 and 0.95, from the bottom of the germanium-silicon inverse gradient buffer layer to the top of the germanium-silicon inverse gradient buffer layer. A first germanium-silicon confinement layer is formed above the germanium-silicon inverse gradient buffer layer; A germanium quantum well layer is formed on the first germanium-silicon confinement layer; A second germanium-silicon confinement layer is formed on the germanium quantum well layer; A silicon cap layer is formed on the second germanium-silicon confinement layer; In this embodiment, a dislocation isolation pattern is embedded at the bottom of at least one of the germanium virtual substrate layer, germanium-silicon inverse gradient buffer layer, and first germanium-silicon confinement layer. The dislocation isolation pattern at the bottom of the layer structure includes a plurality of dislocation isolation structures. Any two adjacent dislocation isolation structures are separated by the layer structure. And / or, a dislocation isolation layer is formed between at least one of the layers between the substrate and the germanium virtual substrate layer, between the germanium virtual substrate layer and the germanium-silicon inverse gradient buffer layer, and between the germanium-silicon inverse gradient buffer layer and the first germanium-silicon confinement layer.

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