A softness modulation type IGBT device and a preparation method and a chip thereof

Abstract

The application belongs to the technical field of power devices, and provides a softness modulation type IGBT device and a preparation method and a chip thereof. A softness modulation zone including an N-type diffusion layer and a local carrier lifetime control layer is formed between an N-type field termination layer and an N-type drift layer, the doping concentration of the N-type diffusion layer is less than the doping concentration of the N-type field termination layer, then a front IGBT structure and a front protective layer are formed on the N-type drift layer, so that when the IGBT device is at a lower working voltage, carrier current can be maintained at the end of device turn-off, and turn-off softness is maintained, turn-off time and turn-off loss are reduced, when the IGBT device is at a higher working voltage, the depletion layer of the device can be cut off in the N-type diffusion layer, so that the turn-off current of the IGBT device will not oscillate, and the problems of long current tail, large loss and high risk of overvoltage failure of the current IGBT device under voltage fluctuation are solved.

Description

Technical Field

[0001] This application belongs to the field of power device technology, and in particular relates to a soft-modulation type IGBT device and its fabrication method and chip. Background Technology

[0002] The Insulated-Gate Bipolar Transistor (IGBT) combines the low on-state voltage drop of the Bipolar Junction Transistor (BJT) with the fast switching and simple control of the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and is widely used in power electronic systems.

[0003] However, IGBT devices actually operate within a relatively wide range. For example, an IGBT with a 1200V voltage withstand capability has a bus voltage that fluctuates between 400V and 800V. When operating at lower voltages, the undepleted region of the IGBT device is wide, resulting in a long current tail, high losses, and the system efficiency not reaching its optimal level. When operating at higher voltages, the current of the IGBT device drops rapidly, leading to high overshoot voltage and an increased risk of overvoltage failure. Summary of the Invention

[0004] The purpose of this application is to provide a soft-modulation IGBT device and its fabrication method and chip, which aims to solve the problems of long current tail, high loss and high risk of overvoltage failure in IGBT devices under voltage fluctuation.

[0005] The first aspect of this application provides a soft-modulation IGBT device, the soft-modulation IGBT device comprising:

[0006] An N-type field termination layer and a P-type collector region, wherein the P-type collector region is formed on the back side of the N-type field termination layer;

[0007] A soft modulation region is formed on the front side of the N-type field termination layer; wherein the soft modulation region includes an N-type diffusion layer and a local carrier lifetime control layer, and the doping concentration of the N-type diffusion layer is less than the doping concentration of the N-type field termination layer.

[0008] An N-type drift layer is formed on the N-type diffusion layer, and the N-type drift layer has a convex structure;

[0009] A gate dielectric layer is located above the horizontal portion of the N-type drift layer and contacts the protrusion of the N-type drift layer; wherein the gate dielectric layer has a concave structure.

[0010] A polysilicon layer is formed within a groove in the gate dielectric layer;

[0011] A P-type well region is formed on the protrusion of the N-type drift layer and is in contact with the gate dielectric layer;

[0012] An N-type source region is formed on the P-type well region;

[0013] An insulating dielectric layer is formed on the polysilicon layer and the N-type source region;

[0014] An emitting metal layer is formed on the insulating dielectric layer, and the emitting metal layer has a convex structure. The protrusion of the emitting metal layer extends into the P-type well region through the through-holes in the insulating dielectric layer and the N-type source region.

[0015] A collector metal layer is formed on the back side of the P-type collector region.

[0016] In one embodiment, the local carrier lifetime control layer is formed in the N-type diffusion layer, or the local carrier lifetime control layer is formed between the N-type diffusion layer and the N-type field termination layer.

[0017] In one embodiment, there are multiple local carrier lifetime control layers, and the multiple local carrier lifetime control layers are isolated from each other by the N-type diffusion layer.

[0018] In one embodiment, the distance between adjacent local carrier lifetime control layers is equal.

[0019] In one embodiment, the thickness of the local carrier lifetime control layer is 50 nm to 1 μm.

[0020] In one embodiment, the distance between the local carrier lifetime control layer and the boundary of the soft modulation region is equal to or less than 5 μm.

[0021] In one embodiment, the local carrier lifetime control layer is formed by injecting hydrogen or helium ions into a designated region of the N-type diffusion layer.

[0022] In one embodiment, the doping concentration of the N-type field termination layer is at least 100 times that of the N-type diffusion layer;

[0023] The doping concentration of the N-type diffusion layer is set in a gradient.

[0024] The second aspect of this application also provides a method for fabricating a soft-modulation IGBT device, including:

[0025] An N-type diffusion layer is grown on the front side of the N-type field termination layer; wherein the doping concentration of the N-type diffusion layer is less than the doping concentration of the N-type field termination layer;

[0026] An N-type drift layer is grown on the N-type diffusion layer;

[0027] The N-type drift layer is etched to form a trench structure on the N-type drift layer, and the N-type drift layer is made to have a convex structure;

[0028] A gate dielectric layer is formed on the inner wall of the trench structure on the N-type drift layer, and a polysilicon layer is filled in the gate dielectric layer; wherein the gate dielectric layer is located above the horizontal portion of the N-type drift layer and contacts the protrusion of the N-type drift layer;

[0029] A P-type well region in contact with the gate dielectric layer is formed on the protrusion of the N-type drift layer;

[0030] An N-type source region is formed on the P-type well region;

[0031] An insulating dielectric layer is formed on the polysilicon layer and the N-type source region;

[0032] The polysilicon layer and the N-type source region are etched to form an etching trench that extends into the P-type well region, and the emitter metal layer is formed within the etching trench; wherein the emitter metal layer has a convex structure, and the protrusion of the emitter metal layer contacts the P-type well region;

[0033] The back side of the N-type field termination layer is thinned, and hydrogen or helium ions are injected into a designated area in the N-type diffusion layer and then annealed to form a local carrier lifetime control layer.

[0034] A P-type collector region is formed on the back side of the N-type field termination layer, and a collector metal layer is formed on the back side of the P-type collector region.

[0035] A third aspect of this application also provides a chip, the chip comprising a soft-modulation IGBT device as described in any of the preceding embodiments; or the chip comprising a soft-modulation IGBT device fabricated by the fabrication method described in any of the preceding embodiments.

[0036] The beneficial effects of the embodiments of the present invention are as follows:

[0037] By forming a soft modulation region comprising an N-type diffusion layer and a localized carrier lifetime control layer between the N-type field termination layer and the N-type drift layer, and setting the doping concentration of the N-type diffusion layer to be lower than that of the N-type field termination layer, and then forming a front-side IGBT structure and a front-side protective layer on the N-type drift layer, it is possible to provide carriers to sustain the turn-off current and maintain turn-off softness at the end of the device's turn-off period when the IGBT device is operating at a lower voltage, thereby reducing turn-off time and turn-off losses. When the IGBT device is operating at a higher voltage, it ensures that the depletion layer of the device can be cut off within the N-type diffusion layer, preventing the turn-off current of the IGBT device from oscillating. This solves the problems of long current tail, high losses, and high risk of overvoltage failure in current IGBT devices under voltage fluctuations. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of a soft-modulation IGBT device provided in an embodiment of this application.

[0039] Figure 2 This is a schematic diagram of another soft-modulation type IGBT device provided in the embodiments of this application.

[0040] Figure 3 yes Figure 1 A schematic diagram of the doping concentration distribution along the dashed line CD of a medium-soft modulation IGBT device and the electric field distribution under high voltage.

[0041] Figure 4 This is a schematic flowchart of the fabrication method of the soft-modulation type IGBT device provided in the embodiments of this application.

[0042] Figure 5 This is a schematic diagram of the formation of an N-type diffusion layer and an N-type drift layer provided in the embodiments of this application.

[0043] Figure 6 This is a schematic diagram of the formation of the gate dielectric layer and the polysilicon layer provided in the embodiments of this application.

[0044] Figure 7 This is a schematic diagram of the formation of a P-type well region provided in an embodiment of this application.

[0045] Figure 8 This is a schematic diagram of the etched trenches formed according to an embodiment of this application.

[0046] Figure 9 This is a schematic diagram of the formation of the emission metal layer provided in the embodiments of this application.

[0047] Figure 10 This is a schematic diagram of the formation of a local carrier lifetime control layer provided in an embodiment of this application;

[0048] Figure 11This is a schematic diagram of the formation of a P-type collector region and a collector metal layer provided in the embodiments of this application. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0050] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0051] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0052] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0053] In some high-end industrial applications, such as photovoltaic inverters, the performance requirements for IGBTs are very high, including a saturation on-state voltage (V). CEsat ) and turn-off loss (E off Both are required to be very small, in reducing V CEsat In this respect, the trench gate IGBT structure reduces the resistance of the junction field-effect transistor (JFET) and thus reduces V without increasing Eoff. CEsat It has been widely used. To reduce E offGenerally, while ensuring withstand voltage, the drift region of the IGBT should be reduced as thin as possible. To achieve this, an N-type field-stop structure is introduced. The N-type field-stop layer is located between the heavily doped P-type collector region and the N-type drift region, with a higher concentration than the N-type drift region. The introduction of the N-type field-stop layer is mainly to make the N-type drift region as thin as possible while ensuring a certain withstand voltage, thereby obtaining good performance.

[0054] However, the introduction of the N-type field-termination layer can cause current oscillations during turn-off at high bus voltages. When selecting IGBTs, the operating voltage should not exceed two-thirds of their withstand voltage. IGBTs with a 1200V withstand capability typically operate at around 600V, and rarely exceed 800V. Otherwise, devices with higher voltage ratings must be selected. When an IGBT turns off, the channel is cut off, the external inductor current remains constant, the drift layer bears the voltage, and the internal depletion layer begins to ionize electrons and holes to maintain the inductor current. As the voltage across the drift region gradually increases, the depletion layer expands inward. In most cases, the electric field drops to zero in the drift region, leaving an undepleted area that ensures sufficient excess minority carrier holes are available at the end of the IGBT turn-off to maintain the tail current, achieving soft turn-off. The wider the undepleted area, the longer the tail current, the slower the turn-off, and the greater the losses. The narrower the undepleted area, the shorter the tail current, the faster the turn-off, and the smaller the turn-off losses. If the drift region thickness is reduced too much, the depletion layer will extend into the N-type field termination layer at the end of the turn-off. The minority carrier concentration in the N-type field termination layer is 1-2 orders of magnitude less than that in the drift region, which cannot maintain the tail current and will cause hard turn-off, resulting in strong oscillations and voltage overshoot spikes, which seriously affect the safety of the system. At the same time, strong oscillations will also greatly increase the turn-off loss.

[0055] In practical applications, IGBT devices operate within a relatively wide range, such as bus voltage fluctuating between 400V and 800V. When operating at lower voltages, the undepleted region of the IGBT device is wide, resulting in long current tails, high losses, and the inability to achieve optimal system efficiency. When operating at higher voltages, the current of the IGBT device drops rapidly, leading to high overshoot voltage and an increased risk of overvoltage failure.

[0056] To address the aforementioned technical problems, this application provides a soft-modulation IGBT device, see [link to relevant documentation]. Figure 1 As shown, the soft-modulation IGBT device in this embodiment includes: an N-type field termination layer 103, a P-type collector region 102, a soft-modulation region (including an N-type diffusion layer 105 and a local carrier lifetime control layer 104), an N-type drift layer 106, a polysilicon layer 107, a gate dielectric layer 108, a P-type well region 109, an N-type source region 110, an insulating dielectric layer 111, an emitter metal layer 112, and a collector metal layer 101.

[0057] In this embodiment, a P-type collector region 102 is formed on the back side of the N-type field-terminating layer 103, and a soft modulation region is formed on the front side of the N-type field-terminating layer 103. The soft modulation region includes an N-type diffusion layer 105 and a localized carrier lifetime control layer 104. The doping concentration of the N-type diffusion layer 105 is less than that of the N-type field-terminating layer 103. An N-type drift layer 106 is formed on the N-type diffusion layer 105 and has a convex structure. The gate dielectric layer 108 is located on the N-type drift layer. Above the horizontal portion of layer 106, and with the gate dielectric layer 108 in contact with the protrusion of the N-type drift layer 106, the gate dielectric layer 108 has a concave structure. A polysilicon layer 107 is located within the groove of the gate dielectric layer 108. A P-type well region 109 is formed on the protrusion of the N-type drift layer 106 and is in contact with the gate dielectric layer 108. An N-type source region 110 is formed on the P-type well region 109. An insulating dielectric layer 111 is formed on the polysilicon layer 107 and the N-type source region 110. An emitter metal layer 112 is formed on the insulating dielectric layer 111 and has a convex structure. The protrusion of the emitter metal layer 112 extends into the P-type well region 109 through vias in the insulating dielectric layer 111 and the N-type source region 110. A collector metal layer 101 is formed on the back side of the P-type collector region 102.

[0058] In this embodiment, a soft modulation region comprising an N-type diffusion layer 105 and a localized carrier lifetime control layer 104 is formed between the N-type field termination layer 103 and the N-type drift layer 106, and the doping concentration of the N-type diffusion layer 105 is set to be less than the doping concentration of the N-type field termination layer 103. Then, a front-side IGBT structure (composed of a gate dielectric layer 108, a P-type well region 109, an N-type source region 110, an insulating dielectric layer 111, and an emitter metal layer 112) and a front-side protective layer are formed on the N-type drift layer 106. This allows the IGBT device to maintain a low operating voltage and minimize power consumption during the final stage of device turn-off. The depletion layer has not yet extended to the bottom of the N-type drift layer 106. There are still many undepleted regions outside the depletion region, which can provide carriers to maintain the turn-off current and maintain the turn-off softness. At the same time, electrons in the undepleted regions of the N-type drift layer 106 can flow to the local carrier lifetime control layer 104 in the form of diffusion flow, recombine with holes and disappear. Meanwhile, a large number of holes stored in the N-type drift layer 106 flow out to the P-type well region 109, enabling the IGBT device to turn off quickly. As long as the carrier lifetime in the carrier lifetime control layer is small enough, the turn-off time of the IGBT device can be very short and the turn-off loss can be very small.

[0059] In this embodiment, when the IGBT device is operating at a higher voltage, the N-type diffusion layer 105 has a wider width and higher concentration, ensuring that the depletion layer can be cut off within the N-type diffusion layer 105. This ensures that when the IGBT device is turned off under higher voltage conditions, the N-type diffusion layer 105 still has some undepleted regions, providing minority carrier maintenance turn-off current. Furthermore, the N-type diffusion layer 105 within the IGBT device is formed by diffusion of the N-type field termination layer 103 during a subsequent high-temperature process, creating a very good concentration gradient (e.g., ...). Figure 2 (As shown). This prevents the turn-off current of the IGBT device from oscillating. At the same time, due to the presence of the carrier lifetime control layer, the IGBT device can be turned off quickly, maintaining low turn-off losses. This ensures that the turn-off current of the IGBT device will not oscillate under both high-voltage and low-voltage operating conditions, solving the problems of long current tail, high losses, and high risk of overvoltage failure in current IGBT devices under voltage fluctuations.

[0060] In one embodiment, the local carrier lifetime control layer 104 is formed in the N-type diffusion layer 105, as shown in the figure.

[0061] In one embodiment, the local carrier lifetime control layer 104 may also be formed between the N-type diffusion layer 105 and the N-type field termination layer 103.

[0062] In one embodiment, see Figure 3 As shown, there are multiple local carrier lifetime control layers 104, and the multiple local carrier lifetime control layers 104 are isolated by N-type diffusion layers 105.

[0063] In one embodiment, adjacent local carrier lifetime control layers 104 are equidistant.

[0064] In one embodiment, the thickness of the local carrier lifetime control layer 104 is 50 nm to 1 μm.

[0065] In this embodiment, the N-type diffusion layer 105 can be formed by N-type doping of intrinsic silicon. For example, in the subsequent high-temperature process of IGBT wafer manufacturing, N-type impurities diffuse from the N-type field termination layer 103 to the intrinsic layer to form the N-type diffusion layer 105.

[0066] In one embodiment, the distance between the local carrier lifetime control layer 104 and the boundary of the soft modulation region is equal to or less than 5 μm.

[0067] In one embodiment, the local carrier lifetime control layer 104 is formed by injecting hydrogen or helium ions into a designated region in the N-type diffusion layer 105.

[0068] In this embodiment, the local carrier lifetime control layer 104 can be formed in the N-type diffusion layer 105, and the carrier lifetime in the N-type diffusion layer 105 can be in the range of 1-50 nanoseconds.

[0069] In one embodiment, the doping concentration of the N-type field termination layer 103 is at least 100 times that of the N-type diffusion layer 105.

[0070] In this embodiment, the N-type diffusion layer 105 is an intrinsic structure, and the doping concentration of N-type dopants in the N-type field termination layer 103 is at least 100 times that of N-type dopants in the N-type diffusion layer 105.

[0071] In one embodiment, the doping concentration of N-type doped ions in the N-type field termination layer 103 is 1*10⁻⁶. 15 cm -3 .

[0072] In one embodiment, the thickness of the N-type diffusion layer 105 is 5-10 μm.

[0073] In one embodiment, the doping concentration of the N-type diffusion layer 105 is set in a gradient.

[0074] In this embodiment, N-type impurities diffuse from the N-type field termination layer 103 to the intrinsic layer to form an N-type diffusion layer 105. Therefore, the N-type diffusion layer 105 has a good N-type doping concentration gradient, and the concentration gradient can be well controlled by mastering the maximum temperature and diffusion time.

[0075] In one specific application embodiment, the doping concentration of N-type doped ions in the N-type diffusion layer 105 is inversely proportional to the distance between it and the N-type field termination layer 103.

[0076] This application also provides a method for fabricating a soft-modulation IGBT device, see [link to relevant documentation]. Figure 4 As shown, the preparation method in this embodiment includes steps S101 to S108.

[0077] In step S101, see Figure 5 As shown, an N-type diffusion layer 105 is grown on the front side of the N-type field termination layer 103.

[0078] In this embodiment, an N-type semiconductor material can be grown on the front side of the N-type field termination layer 103 through a growth process to form an N-type diffusion layer 105. The doping concentration of the N-type diffusion layer 105 is less than that of the N-type field termination layer 103.

[0079] In one specific application embodiment, the doping concentration of the N-type field termination layer 103 is at least 100 times that of the N-type diffusion layer 105.

[0080] In one specific application embodiment, the thickness of the N-type diffusion layer 105 is 5um-10um.

[0081] In one specific application embodiment, the N-type field termination layer 103 can be an N-type silicon substrate.

[0082] In step S102, see Figure 5 As shown, an N-type drift layer 106 is grown on an N-type diffusion layer 105.

[0083] Specifically, an N-type semiconductor material can be grown on the N-type diffusion layer 105 through a growth process to form an N-type drift layer 106.

[0084] In one specific application embodiment, the thickness of the N-type drift layer 106 is greater than the thickness of the N-type diffusion layer 105. Specifically, the growth thickness of the N-type drift layer 106 can be 75µm to 100µm, and the concentration of N-type dopant ions in the N-type drift layer 106 can be 1-5 × 10⁻⁵. 13 .

[0085] In step S103, combined Figure 6 As shown, the N-type drift layer 106 is etched to form a trench structure on the N-type drift layer 106, and the N-type drift layer 106 is made to have a convex structure.

[0086] In this embodiment, a trench structure is formed on the front side of the N-type drift layer 106 by silicon etching. Specifically, the etched area is located at the edge of the front side of the N-type drift layer 106, so that the etched N-type drift layer 106 has a convex structure.

[0087] In one specific application embodiment, the cross-sectional shape of the trench structure is annular, and the annular trench structure surrounds the protrusion of the N-type drift layer 106.

[0088] In step S104, a gate dielectric layer 108 is formed on the inner wall of the trench structure on the N-type drift layer 106, and a polysilicon layer 107 is filled in the gate dielectric layer 108.

[0089] In this embodiment, combined with Figure 6 As shown, a gate dielectric layer 108 can be formed on the surface of the trench structure by a thermal oxidation process. The gate dielectric layer 108 has a concave structure. A polysilicon layer 107 is formed by filling the groove of the gate dielectric layer 108 with polysilicon material. The cross-sectional shape of the polysilicon layer 107 is annular.

[0090] Specifically, the gate dielectric layer 108 is located above the horizontal portion of the N-type drift layer 106 and is in contact with the protrusion of the N-type drift layer 106.

[0091] In step S105, combined Figure 7As shown, a P-type well region 109 is formed on the protrusion of the N-type drift layer 106, which is in contact with the gate dielectric layer 108.

[0092] In this embodiment, P-type doped ions (e.g., P-type impurities) are implanted into the protrusions of the N-type drift layer 106 by an ion implantation process, thereby forming a P-type well region 109 in the protrusions of the N-type drift layer 106. The thickness of the P-type well region 109 is less than the thickness of the polysilicon layer 107.

[0093] In step S106, an N-type source region 110 is formed on the P-type well region 109, and an insulating dielectric layer 111 is formed on the polysilicon layer 107 and the N-type source region 110.

[0094] In this embodiment, an N-type doped ions (e.g., N-type impurities) are implanted into the P-type well region 109 using an ion implantation process, and then an N-type source region 110 is formed on the P-type well region 109 after high-temperature annealing.

[0095] Combination Figure 8 As shown, an insulating dielectric layer 111 can be formed on the upper surface of the wafer using a deposition process. The insulating dielectric layer 111 covers the polysilicon layer 107 and the N-type source region 110, and together with the gate dielectric layer 108, it encapsulates the polysilicon layer 107.

[0096] In step S107, the polysilicon layer 107 and the N-type source region 110 are etched to form an etching trench that extends into the P-type well region 109, and an emission metal layer 112 is formed in the etching trench.

[0097] In this embodiment, combined with Figure 8 As shown, an etching process is used to form an etching trench 201 extending into the P-type well region 109 in the central region of the polysilicon layer 107 and the N-type source region 110. Then, a metal material is deposited on the upper surface of the device using a metal deposition process, and excess metal material is etched away to form an emitter metal layer 112. This emitter metal layer 112 has a convex structure, and the protrusions of the emitter metal layer 112 contact the P-type well region 109. Figure 9 As shown.

[0098] In step S108, combined Figure 10 As shown, the back side of the N-type field termination layer 103 is thinned, and hydrogen or helium ions are injected into a designated area in the N-type diffusion layer 105 and then annealed to form a local carrier lifetime control layer 104.

[0099] In this embodiment, the thickness of the N-type field termination layer 103 is determined according to the requirements of pressure resistance and reliability. Then, after thinning the back side of the N-type field termination layer 103, hydrogen or helium ions are injected into the designated area using a high-energy ion implantation device, and annealed at 320°C to 340°C to form a local lifetime control layer.

[0100] In step S109, combined Figure 11 As shown, a P-type collector region 102 is formed on the back side of the N-type field termination layer 103, and a collector metal layer 101 is formed on the back side of the P-type collector region 102.

[0101] In this embodiment, a P-type impurity can be implanted on the back side of the N-type field termination layer 103 and annealed to form a P-type collector region 102, and then the collector metal layer 101 on the back side can be formed by vapor deposition or sputtering.

[0102] In a specific application embodiment, a Ni / Ti / Ni / Ag multilayer metal can be deposited on the front side of the device as the emitter metal layer, and a Ni / Ti / Ni / Ag multilayer metal can be deposited on the back side of the device as the collector metal layer 101.

[0103] In one specific application embodiment, a gate contact hole can be formed in the insulating dielectric layer 111 to connect to the polysilicon layer 107, and a gate metal layer can be formed by filling the gate contact hole with a metal material.

[0104] This application also provides a chip, which includes the soft-modulation IGBT device described in any of the above embodiments.

[0105] In another embodiment, the chip may further include a soft-modulation IGBT device prepared by any of the above-described preparation methods.

[0106] In this embodiment, the chip includes a chip substrate, on which one or more soft-modulated IGBT devices are disposed. The soft-modulated IGBT devices can be fabricated by the fabrication method in any of the above embodiments, or the soft-modulated IGBT devices in any of the above embodiments can be disposed on the chip substrate.

[0107] In one specific application embodiment, other related semiconductor devices can also be integrated on the chip substrate to form an integrated circuit with the soft-modulation IGBT device.

[0108] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0109] The beneficial effects of the embodiments of the present invention are as follows:

[0110] By forming a soft modulation region comprising an N-type diffusion layer and a localized carrier lifetime control layer between the N-type field termination layer and the N-type drift layer, and setting the doping concentration of the N-type diffusion layer to be lower than that of the N-type field termination layer, and then forming a front-side IGBT structure and a front-side protective layer on the N-type drift layer, it is possible to provide carriers to sustain the turn-off current and maintain turn-off softness at the end of the device's turn-off period when the IGBT device is operating at a lower voltage, thereby reducing turn-off time and turn-off losses. When the IGBT device is operating at a higher voltage, it ensures that the depletion layer of the device can be cut off within the N-type diffusion layer, preventing the turn-off current of the IGBT device from oscillating. This solves the problems of long current tail, high losses, and high risk of overvoltage failure in current IGBT devices under voltage fluctuations.

[0111] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions is used as an example. In practical applications, the above functional areas can be assigned to different doped regions as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above.

[0112] In the embodiments, the doped regions can be integrated into one functional region, or each doped region can exist independently, or two or more doped regions can be integrated into one functional region. The integrated functional region can be implemented using the same type of dopant ion or multiple types of dopant ions. Furthermore, the specific names of each doped region are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the doped region in the fabrication method of the above device can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0113] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A soft-modulation type IGBT device, characterized in that, The soft-modulation type IGBT device includes: An N-type field termination layer and a P-type collector region, wherein the P-type collector region is formed on the back side of the N-type field termination layer; A soft modulation region is formed on the front side of the N-type field termination layer; wherein, the soft modulation region includes an N-type diffusion layer and a local carrier lifetime control layer, the doping concentration of the N-type diffusion layer is less than the doping concentration of the N-type field termination layer; the local carrier lifetime control layer is formed in the N-type diffusion layer, or the local carrier lifetime control layer is formed between the N-type diffusion layer and the N-type field termination layer; An N-type drift layer is formed on the N-type diffusion layer, and the N-type drift layer has a convex structure; A gate dielectric layer is located above the horizontal portion of the N-type drift layer and contacts the protrusion of the N-type drift layer; wherein the gate dielectric layer has a concave structure; A polysilicon layer is formed within a groove in the gate dielectric layer; A P-type well region is formed on the protrusion of the N-type drift layer and is in contact with the gate dielectric layer; An N-type source region is formed on the P-type well region; An insulating dielectric layer is formed on the polysilicon layer and the N-type source region; An emitting metal layer is formed on the insulating dielectric layer, and the emitting metal layer has a convex structure. The protrusion of the emitting metal layer extends into the P-type well region through the through-holes in the insulating dielectric layer and the N-type source region. A collector metal layer is formed on the back side of the P-type collector region.

2. The soft-modulation IGBT device as described in claim 1, characterized in that, There are multiple local carrier lifetime control layers, and the multiple local carrier lifetime control layers are isolated from each other by the N-type diffusion layer.

3. The soft-modulation IGBT device as described in claim 2, characterized in that, The distance between adjacent local carrier lifetime control layers is equal.

4. The soft-modulation IGBT device as described in any one of claims 1-3, characterized in that, The thickness of the local carrier lifetime control layer is 50 nm to 1 μm.

5. The soft-modulation IGBT device as described in any one of claims 1-3, characterized in that, The local carrier lifetime control layer is formed by injecting hydrogen or helium ions into a designated region of the N-type diffusion layer, so that the local carrier lifetime control layer is formed in the N-type diffusion layer, or the local carrier lifetime control layer is formed between the N-type diffusion layer and the N-type field termination layer.

6. The soft-modulation IGBT device according to any one of claims 1-3, characterized in that, The doping concentration of the N-type field termination layer is at least 100 times that of the N-type diffusion layer; The doping concentration of the N-type diffusion layer is set in a gradient.

7. A method for fabricating a soft-modulation IGBT device as described in any one of claims 1-6, characterized in that, include: An N-type diffusion layer is grown on the front side of the N-type field termination layer; wherein the doping concentration of the N-type diffusion layer is less than the doping concentration of the N-type field termination layer; An N-type drift layer is grown on the N-type diffusion layer; The N-type drift layer is etched to form a trench structure on the N-type drift layer, and the N-type drift layer is made into a convex structure. A gate dielectric layer is formed on the inner wall of the trench structure on the N-type drift layer, and a polysilicon layer is filled in the gate dielectric layer; wherein the gate dielectric layer is located above the horizontal portion of the N-type drift layer and contacts the protrusion of the N-type drift layer; A P-type well region in contact with the gate dielectric layer is formed on the protrusion of the N-type drift layer; An N-type source region is formed on the P-type well region, and an insulating dielectric layer is formed on the polysilicon layer and the N-type source region. The polysilicon layer and the N-type source region are etched to form an etching trench that extends into the P-type well region, and an emission metal layer is formed within the etching trench; wherein the emission metal layer has a convex structure, and the protrusion of the emission metal layer contacts the P-type well region; The back side of the N-type field termination layer is thinned, and hydrogen or helium ions are injected into a designated region in the N-type diffusion layer and then annealed to form a local carrier lifetime control layer. A P-type collector region is formed on the back side of the N-type field termination layer, and a collector metal layer is formed on the back side of the P-type collector region.

8. A chip, characterized in that, The chip includes a soft-modulation IGBT device as described in any one of claims 1-6; or the chip includes a soft-modulation IGBT device prepared by the preparation method described in claim 7.

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