Programmable gain amplifier circuit and electronic device

Abstract

The present invention provides a programmable gain amplifier circuit and electronic device, comprising a first amplifier A1, a second amplifier A2, and a third amplifier A3 connected in series; the two input terminals of the first amplifier A1 are connected to a first variable resistor R1 and a second variable resistor R2, respectively, with the other terminals of the first variable resistor R1 and the other terminals of the second variable resistor R2 serving as a first input terminal Vip and a second input terminal Vin, respectively; the two output terminals of the third amplifier A3 serve as a first output terminal Von and a second output terminal Vop, respectively; a first control circuit and a second control circuit are provided between the third amplifier A3 and the first amplifier A1; and a third control circuit and a fourth control circuit are provided between the positive output terminal of the third amplifier A3 and the positive input terminal of the second amplifier A2. The circuit of the present invention uses switched capacitors to simulate a large resistor to form a low-pass filter, thereby achieving low-pass filtering with a small chip area.

Description

Technical Field

[0001] The present invention relates to the technical field of amplifiers, and in particular to a programmable gain amplifier circuit and an electronic device. Background Art

[0002] Generally, a programmable gain amplifier only has an adjustable gain function and does not filter the circuit signal. Or, in order to achieve low-pass filtering, a large resistor is used, which makes the chip area too large and increases the cost.

[0003] Patent document CN205883178U discloses a programmable gain amplifier and electronic device. The programmable gain amplifier includes: two complementary cross-coupled transistor pairs, coupled to each other in a state where each transistor in one pair has a current flow path cascaded with the current flow path of a corresponding transistor in the other pair, with first and second coupling points formed between the pairs; first and second sampling capacitors coupled to the first and second coupling points; first and second input stages having inputs for receiving input signals sampled by the first and second sampling capacitors; a switch component coupling the first and second input stages to the sampling capacitors so that the input signal is sampled as a sampled signal on the sampling capacitors; and the switch component energizing the complementary cross-coupled transistor pair so that the signal sampled on the sampling capacitor undergoes negative resistance regeneration that increases exponentially with time, thereby providing an exponential amplifier gain. However, this patent document still suffers from the drawback of only providing gain adjustment and not filtering circuit signals. Summary of the Invention

[0004] In view of the defects in the prior art, an object of the present invention is to provide a programmable gain amplifier circuit and an electronic device.

[0005] According to the present invention, a programmable gain amplifier circuit is provided, comprising: a first amplifier A1, a second amplifier A2, a third amplifier A3, a first variable resistor R1, and a second variable resistor R2;

[0006] The output end of the first amplifier A1 is connected to the input end of the second amplifier A2, and the output end of the second amplifier A2 is connected to the input end of the third amplifier A3; the non-inverting input end and the inverting input end of the first amplifier A1 are respectively connected to one end of the first variable resistor R1 and one end of the second variable resistor R2, and the other end of the first variable resistor R1 and the other end of the second variable resistor R2 serve as a first input end Vip and a second input end Vin, respectively; the non-inverting output end and the inverting output end of the third amplifier A3 serve as a first output end Von and a second output end Vop, respectively;

[0007] A first control circuit is provided between the inverting output terminal of the third amplifier A3 and the non-inverting input terminal of the first amplifier A1, and a second control circuit is provided between the non-inverting output terminal of the third amplifier A3 and the inverting input terminal of the first amplifier A1; a third control circuit is provided between the inverting output terminal of the third amplifier A3 and the non-inverting input terminal of the second amplifier A2, and a fourth control circuit is provided between the non-inverting output terminal of the third amplifier A3 and the inverting input terminal of the second amplifier A2.

[0008] Preferably, the first control circuit includes a first capacitor C1, a second capacitor C2, a third variable resistor R3, a first switch S1 and a second switch S2;

[0009] One end of the first capacitor C1 is respectively connected to one end of the second capacitor C2, one end of the third variable resistor R3, one end of the first switch S1 and the non-inverting input end of the first amplifier A1;

[0010] The other end of the first capacitor C1 is respectively connected to the other end of the third variable resistor R3, one end of the second switch S2 and the inverting output end of the third amplifier A3;

[0011] The other end of the first switch S1 is connected to the other end of the second capacitor C2 and the other end of the second switch S2 respectively.

[0012] Preferably, the second control circuit includes a third capacitor C3, a fourth capacitor C4, a fourth variable resistor R4, a third switch S3 and a fourth switch S4;

[0013] One end of the third capacitor C3 is respectively connected to one end of the fourth capacitor C4, one end of the fourth variable resistor R4, one end of the third switch S3 and the inverting input end of the first amplifier A1;

[0014] The other end of the third capacitor C3 is respectively connected to the other end of the fourth variable resistor R4, one end of the third switch S3 and the non-inverting output end of the third amplifier A3;

[0015] The other end of the third switch S3 is connected to the other end of the fourth capacitor C4 and the other end of the fourth switch S4 respectively.

[0016] Preferably, the third control resistor includes a fifth capacitor C5, a sixth capacitor C6, a fifth switch S5 and a sixth switch S6;

[0017] One end of the fifth capacitor C5 is connected to one end of the fifth switch S5 and one end of the sixth switch S6 respectively;

[0018] The other end of the fifth capacitor C5 is respectively connected to the other end of the fifth switch S5, one end of the sixth capacitor C6 and the inverting output end of the third amplifier A3;

[0019] The other end of the sixth switch S6 is connected to the other end of the sixth capacitor C6 and the non-inverting input end of the second amplifier A2 respectively.

[0020] Preferably, the fourth control resistor includes a seventh capacitor C7, an eighth capacitor C8, a seventh switch S7 and an eighth switch S8;

[0021] One end of the seventh capacitor C7 is connected to one end of the seventh switch S7 and one end of the eighth switch S8 respectively;

[0022] The other end of the seventh capacitor C7 is respectively connected to the other end of the seventh switch S7, one end of the eighth capacitor C8 and the non-inverting output end of the third amplifier A3;

[0023] The other end of the eighth switch S8 is connected to the other end of the eighth capacitor C8 and the inverting input end of the second amplifier A2 respectively.

[0024] Preferably, the first amplifier A1 is a differential operational amplifier.

[0025] Preferably, the second amplifier A2 is a folded cascode high-gain differential operational amplifier with common-mode negative feedback.

[0026] Preferably, the third amplifier A3 is a class AB output stage amplifier.

[0027] Preferably, the first variable resistor R1 , the second variable resistor R2 , the third variable resistor R3 , and the fourth variable resistor R4 are all resistor arrays whose switches are controlled by digital signals.

[0028] The present invention also provides an electronic device including the programmable gain amplifier circuit.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] 1. The present invention uses a switch capacitor equivalent to a large resistor to achieve frequency compensation and low-pass filtering functions with a minimum layout area, filtering out high-frequency useless signals and achieving the purpose of providing high-quality signals for the subsequent high-precision ADC circuit;

[0031] 2. The circuit of the present invention uses switched capacitors to simulate large resistors to form a low-pass filter, thereby achieving low-pass filtering function in a smaller chip area;

[0032] 3. The circuit of the present invention not only has a gain adjustable function, but also can filter the circuit signal, with a small chip area and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings:

[0034] Figure 1 1 is a circuit diagram of a programmable gain amplifier of the present invention;

[0035] Figure 2 FIG1 is a circuit diagram of a programmable gain amplifier in one embodiment;

[0036] Figure 3 FIG. 4 is a schematic diagram of a zero-frequency gain model of a programmable gain amplifier in an embodiment. DETAILED DESCRIPTION

[0037] The present invention will be described in detail below with reference to specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, without departing from the scope of the present invention, a number of variations and improvements may be made by those skilled in the art. These all fall within the scope of protection of the present invention.

[0038] Example 1:

[0039] like Figure 1 As shown, this embodiment further provides a programmable gain amplifier circuit, including: a first amplifier A1, a second amplifier A2, a third amplifier A3, a first variable resistor R1 and a second variable resistor R2. The output end of the first amplifier A1 is connected to the input end of the second amplifier A2, and the output end of the second amplifier A2 is connected to the input end of the third amplifier A3. The non-inverting input end and the inverting input end of the first amplifier A1 are respectively connected to one end of the first variable resistor R1 and one end of the second variable resistor R2. The other end of the first variable resistor R1 and the other end of the second variable resistor R2 serve as the first input end Vip and the second input end Vin, respectively. The non-inverting output end and the inverting output end of the third amplifier A3 serve as the first output end Von and the second output end Vop, respectively. A first control circuit is provided between the inverting output end of the third amplifier A3 and the non-inverting input end of the first amplifier A1. A second control circuit is provided between the non-inverting output end of the third amplifier A3 and the inverting input end of the first amplifier A1. A third control circuit is provided between the inverting output end of the third amplifier A3 and the non-inverting input end of the second amplifier A2. A fourth control circuit is provided between the non-inverting output end of the third amplifier A3 and the inverting input end of the second amplifier A2.

[0040] The first amplifier A1 is a differential operational amplifier, the second amplifier A2 is a folded cascode high-gain differential operational amplifier with common-mode negative feedback, and the third amplifier A3 is a class AB output stage amplifier.

[0041] The second control circuit includes a third capacitor C3, a fourth capacitor C4, a fourth variable resistor R4, a third switch S3, and a fourth switch S4. One end of the third capacitor C3 is respectively connected to one end of the fourth capacitor C4, one end of the fourth variable resistor R4, one end of the third switch S3, and the inverting input terminal of the first amplifier A1. The other end of the third capacitor C3 is respectively connected to the other end of the fourth variable resistor R4, one end of the third switch S3, and the non-inverting output terminal of the third amplifier A3. The other end of the third switch S3 is respectively connected to the other end of the fourth capacitor C4 and the other end of the fourth switch S4.

[0042] The fourth control resistor includes a seventh capacitor C7, an eighth capacitor C8, a seventh switch S7, and an eighth switch S8. One end of the seventh capacitor C7 is respectively connected to one end of the seventh switch S7 and one end of the eighth switch S8. The other end of the seventh capacitor C7 is respectively connected to the other end of the seventh switch S7, one end of the eighth capacitor C8, and the non-inverting output end of the third amplifier A3. The other end of the eighth switch S8 is respectively connected to the other end of the eighth capacitor C8 and the inverting input end of the second amplifier A2.

[0043] The first control circuit includes a first capacitor C1, a second capacitor C2, a third variable resistor R3, a first switch S1, and a second switch S2. One end of the first capacitor C1 is respectively connected to one end of the second capacitor C2, one end of the third variable resistor R3, one end of the first switch S1, and the positive input terminal of the first amplifier A1. The other end of the first capacitor C1 is respectively connected to the other end of the third variable resistor R3, one end of the second switch S2, and the inverting output terminal of the third amplifier A3. The other end of the first switch S1 is respectively connected to the other end of the second capacitor C2 and the other end of the second switch S2.

[0044] The third control resistor includes a fifth capacitor C5, a sixth capacitor C6, a fifth switch S5, and a sixth switch S6. One end of the fifth capacitor C5 is respectively connected to one end of the fifth switch S5 and one end of the sixth switch S6. The other end of the fifth capacitor C5 is respectively connected to the other end of the fifth switch S5, one end of the sixth capacitor C6, and the inverting output end of the third amplifier A3. The other end of the sixth switch S6 is respectively connected to the other end of the sixth capacitor C6 and the positive input end of the second amplifier A2.

[0045] The first variable resistor R1 , the second variable resistor R2 , the third variable resistor R3 and the fourth variable resistor R4 are all resistor arrays whose switches are controlled by digital signals.

[0046] This embodiment further provides an electronic device including the above-mentioned programmable gain amplifier circuit.

[0047] Example 2:

[0048] Those skilled in the art may understand this embodiment as a more specific description of Embodiment 1.

[0049] like Figure 2 and Figure 3 As shown, the circuit structure of the programmable gain amplifier provided in this embodiment comprises three amplifiers, A1, A2, and A3. Input terminals Vip and Vin are respectively connected to variable resistor R1, the other ends of which are in turn connected to the input terminals of amplifier A1. Between the output terminal Von and the positive input terminal of amplifier A1, capacitor C1, variable resistor R2, and capacitor C2 connected in series with switch / S are connected in parallel. Furthermore, both ends of C2 are connected in parallel with switch S. Between the output terminal Vop and the negative input terminal of amplifier A1, capacitor C1, variable resistor R2, and capacitor C2 connected in series with switch / S are also connected in parallel. Furthermore, both ends of C2 are connected in parallel with switch S. Between the negative output terminal of amplifier A3 and the positive input terminal of amplifier A2, capacitor C4 and capacitor C3 connected in series with switch / S are connected in parallel. Furthermore, both ends of C3 are connected in parallel with switch S. A similar structure also exists between the positive output terminal of amplifier A3 and the negative input terminal of amplifier A2.

[0050] Amplifier A1 is a differential operational amplifier.

[0051] Amplifier A2 is a folded cascode high gain differential operational amplifier with common-mode negative feedback.

[0052] Amplifier A3 is a classAB output stage amplifier.

[0053] The variable resistors R1 and R2 in the circuit are both resistor arrays whose switches are controlled by digital signals.

[0054] Capacitor C2 is periodically switched on and off under the control of switches S and / S, with a switching frequency of f s The switch capacitor is equivalent to a resistor R c2 =1 / C2f s The resistor, and the capacitor C1 in parallel, form a time constant of R C2 C1=C1 / C2f S The capacitor C3 controlled by the switches S and / S is equivalent to a resistor R under the control of the periodic clock. c3 =1 / C3f s, together with the capacitor C4 connected in parallel, frequency compensation is performed on amplifiers A2 and A3.

[0055] The zero-frequency gain of this circuit is equivalent to the circuit structure after the filter in the circuit is removed, such as Figure 3 As shown, at this time, the low-frequency gain of the circuit is achieved by the proportional relationship between the feedback resistor R2 and the input terminal series resistor R1, that is, G0 = R2 / R1.

[0056] And the circuit with passive low-pass filter, such as Figure 2 As shown, the gain function Gain(s) of the circuit is:

[0057]

[0058] Among them, f s is the switching frequency on the switched capacitor, and s is the default expression for describing the transfer function, the Laplace expression.

[0059] It can be seen from the above formula that the circuit has a low-pass characteristic and can filter out high-frequency useless signals.

[0060] The circuit of the present invention adopts a switched capacitor to simulate a large resistor to form a low-pass filter, thereby achieving a low-pass filtering function with a relatively small chip area.

[0061] The above describes specific embodiments of the present invention. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art may make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. The embodiments of this application and the features in the embodiments may be combined with each other in any manner unless there is a conflict.

Claims

1. A programmable gain amplifier circuit, characterized in that: include: A first amplifier A1, a second amplifier A2, a third amplifier A3, a first variable resistor R1, and a second variable resistor R2; The output end of the first amplifier A1 is connected to the input end of the second amplifier A2, and the output end of the second amplifier A2 is connected to the input end of the third amplifier A3; the non-inverting input end and the inverting input end of the first amplifier A1 are respectively connected to one end of the first variable resistor R1 and one end of the second variable resistor R2, and the other end of the first variable resistor R1 and the other end of the second variable resistor R2 serve as a first input end Vip and a second input end Vin, respectively; the non-inverting output end and the inverting output end of the third amplifier A3 serve as a first output end Von and a second output end Vop, respectively; A first control circuit is provided between the inverting output terminal of the third amplifier A3 and the non-inverting input terminal of the first amplifier A1, and a second control circuit is provided between the non-inverting output terminal of the third amplifier A3 and the inverting input terminal of the first amplifier A1; a third control circuit is provided between the inverting output terminal of the third amplifier A3 and the non-inverting input terminal of the second amplifier A2, and a fourth control circuit is provided between the non-inverting output terminal of the third amplifier A3 and the inverting input terminal of the second amplifier A2; The first control circuit includes a first capacitor C1, a second capacitor C2, a third variable resistor R3, a first switch S1 and a second switch S2; One end of the first capacitor C1 is respectively connected to one end of the second capacitor C2, one end of the third variable resistor R3, one end of the first switch S1 and the non-inverting input end of the first amplifier A1; The other end of the first capacitor C1 is respectively connected to the other end of the third variable resistor R3, one end of the second switch S2 and the inverting output end of the third amplifier A3; The other end of the first switch S1 is connected to the other end of the second capacitor C2 and the other end of the second switch S2 respectively.

2. The programmable gain amplifier circuit according to claim 1, wherein: The second control circuit includes a third capacitor C3, a fourth capacitor C4, a fourth variable resistor R4, a third switch S3 and a fourth switch S4; One end of the third capacitor C3 is respectively connected to one end of the fourth capacitor C4, one end of the fourth variable resistor R4, one end of the third switch S3 and the inverting input end of the first amplifier A1; The other end of the third capacitor C3 is respectively connected to the other end of the fourth variable resistor R4, one end of the fourth switch S4 and the non-inverting output end of the third amplifier A3; The other end of the third switch S3 is connected to the other end of the fourth capacitor C4 and the other end of the fourth switch S4 respectively.

3. The programmable gain amplifier circuit according to claim 1, wherein: The third control circuit includes a fifth capacitor C5, a sixth capacitor C6, a fifth switch S5 and a sixth switch S6; One end of the fifth capacitor C5 is connected to one end of the fifth switch S5 and one end of the sixth switch S6 respectively; The other end of the fifth capacitor C5 is respectively connected to the other end of the fifth switch S5, one end of the sixth capacitor C6 and the inverting output end of the third amplifier A3; The other end of the sixth switch S6 is connected to the other end of the sixth capacitor C6 and the non-inverting input end of the second amplifier A2 respectively.

4. The programmable gain amplifier circuit according to claim 3, wherein: The fourth control circuit includes a seventh capacitor C7, an eighth capacitor C8, a seventh switch S7 and an eighth switch S8; One end of the seventh capacitor C7 is connected to one end of the seventh switch S7 and one end of the eighth switch S8 respectively; The other end of the seventh capacitor C7 is respectively connected to the other end of the seventh switch S7, one end of the eighth capacitor C8 and the non-inverting output end of the third amplifier A3; The other end of the eighth switch S8 is connected to the other end of the eighth capacitor C8 and the inverting input end of the second amplifier A2 respectively.

5. The programmable gain amplifier circuit according to claim 1, wherein: The first amplifier A1 is a differential operational amplifier.

6. The programmable gain amplifier circuit according to claim 5, wherein: The second amplifier A2 is a folded cascode high-gain differential operational amplifier with common-mode negative feedback.

7. The programmable gain amplifier circuit according to claim 6, wherein: The third amplifier A3 is a class AB output stage amplifier.

8. The programmable gain amplifier circuit according to claim 2, wherein: The first variable resistor R1 , the second variable resistor R2 , the third variable resistor R3 , and the fourth variable resistor R4 are all resistor arrays whose switches are controlled by digital signals.

9. An electronic device, characterized in that: The programmable gain amplifier circuit comprises the programmable gain amplifier circuit according to any one of claims 1 to 8.

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