Efficient parallel decoding method for BCH codes

Abstract

This invention provides an efficient parallel encoding and decoding method for BCH codes, belonging to the technical field of BCH encoding and decoding circuit implementation in the areas of memory and error correction coding. Unlike previous lookup table methods, for an (n, k, t) BCH code with an n-bit codeword length, k data bits, and t-bit error correction capability, this invention only needs to store the values ​​of k n-k bit parity check matrix column vectors. These k n-k bit parity check matrix column vectors are then XORed with the S-synonym value for t rounds. The error pattern corresponding to the received codeword is obtained from the bitwise XOR value and corrected. This invention is a hardware-level encoding and decoding implementation, which can be completed within one clock cycle, reducing the multi-cycle decoding delay caused by iterative algorithms, achieving parallelization of BCH encoding and decoding, simplifying the encoding and decoding process, and reducing resource consumption.

Description

Technical Field

[0001] This invention belongs to the field of BCH codec circuit implementation technology in the field of memory and error correction coding, specifically relating to a design and verification method for a BCH codec circuit with low latency and low resource consumption. Background Technology

[0002] Memory errors often occur randomly in space due to various factors. These errors, which only affect the correctness of the stored content without damaging the device itself, are called soft errors. Common factors leading to soft errors include single-event upsets (SEUs) and multiple-event upsets (MBUs). SEUs mainly induce single-bit errors in memory, while MBUs induce multi-bit errors. BCH codes are widely used for soft error correction in memory, communication, and embedded systems due to their excellent performance.

[0003] There are many ways to reduce the impact of soft errors. One widely used method in industrial and civilian fields is ECC (Error Correction Code). This method adds a small number of redundant check bits to a fixed number of data bits in each frame using an error correction algorithm. Before being written to memory, the data is encoded according to a predetermined error correction algorithm. After being read from memory, it is decoded to determine whether an error has occurred and to find the corresponding error location for error correction. [1] .

[0004] For single-bit errors, simple error-correcting Hamming codes can be used to correct them, but for multi-bit errors, more powerful error-correcting codes are required.

[0005] For multi-bit random errors, BCH codes, Polar codes, and LDPC codes can be used for error correction coding. The characteristics of these error correction coding schemes for different scenarios in terms of resource consumption, error correction performance, and error correction efficiency can be listed as follows: [2] :

[0006] ECC scheme Hamming code BCH code OLS code Polar codes LDPC code Resource depletion Low high middle high high Error correction performance Low middle middle high high Error correction efficiency high middle high Low Low

[0007] Resource consumption mainly refers to the hardware resources consumed in the hardware implementation of the ECC algorithm. Error correction performance refers to the maximum number of errors that the ECC algorithm can correct under the same number of data bits. Error correction efficiency refers to the ratio of the number of errors corrected to the number of redundant check bits required when the number of data bits is the same.

[0008] Since the Hamming error correction coding was proposed in 1950, research on ECC has been progressing towards higher error correction performance, lower resource consumption, higher error correction efficiency, and the cascading of multiple ECC schemes. [2][3]High error correction performance refers to low latency, high bandwidth, and multi-bit error correction. Low resource consumption refers to low power consumption and small area in the circuit implementation. High error correction efficiency means correcting more data bits with fewer parity bits. Multiple ECC schemes refer to using multiple ECC algorithms for the same memory device to achieve higher error correction performance to meet the needs of specific scenarios. These algorithms can be used in a serial or parallel manner to take advantage of each other's strengths and compensate for each other's weaknesses, while also reusing resources to improve error correction performance.

[0009] Unlike high-performance error correction scenarios, the storage systems of many consumer embedded systems are sensitive to resource consumption, such as flash, SRAM, and ROM in embedded MCUs. These embedded systems also have significant storage error correction requirements, generally demanding low latency and low resource consumption. [3] For parallel ECC encoding and decoding algorithms, their circuit implementation often achieves good results in terms of frequency and latency. However, as the degree of parallelism increases, the resource consumption of parallel ECC encoding and decoding algorithms will increase to some extent. When the number of error correction bits is small, there will also be fewer error patterns, so parallelization will not lead to a surge in resource consumption. However, when the number of error correction bits is large, the parallelized encoding and decoding circuits will experience a significant increase in resource consumption.

[0010] In summary, for embedded memory devices that may experience multiple bit errors in a single frame of data with few error patterns, small storage capacity but important stored content with low fault tolerance, storage close to the kernel, and high memory access speed requirements, the BCH parallel encoding and decoding circuit can be selected as the ECC scheme. After further optimization of the circuit, good latency and frequency performance can be achieved, while resource consumption is controlled within an acceptable range. Summary of the Invention

[0011] This invention proposes an efficient parallel encoding and decoding method for BCH codes, aiming to solve the problems of high latency, multiple clock cycles, and high circuit complexity caused by serial encoding and decoding methods.

[0012] The technical solution adopted in this invention is as follows:

[0013] A parallel encoding and decoding method for BCH codes, characterized by comprising a parallel encoding part and a decoding part, wherein,

[0014] (a) The encoding part includes the following steps:

[0015] (1-1) Construct the generator matrix G based on the known generator polynomial g(x) of the (n, k, t) BCH code. k*n The formula for generating the polynomial is: g(x) = x n-k +g n-k-1 x n-k-1 …+g1x+1;

[0016] (1-2) will generate matrix G k*n Performing row and column transformations according to Galois field addition, it transforms into [E] k*k :H k*(n-k) The form is ], where E matrix is ​​the identity matrix, and then encoding is performed according to formula (1). The encoded codeword c(x) is obtained from the unencoded codeword m(x) matrix:

[0017] c(x) 1*n =m(x) 1*k *[E k*k :H k*(n-k) (1)

[0018] The multiplication and addition involved in the matrix operations mentioned above are Galois field operations. Let the parity bit be p(x) obtained from formula (2).

[0019] p(x) 1*n-k =m(x) 1*k *H k*(n-k) (2)

[0020] For the i-th parity bit, the k-th binary number k'b e in the i-th column of the H matrix. k-1 e k-2 e1 e0 is used as a mask, and is bitwise ANDed with k-bit data d[k-1:0]. The resulting data is then XORed bitwise to obtain a 1-bit parity bit. Other parity bits are generated in the same way to achieve encoding.

[0021] (II) The decoding part includes the following steps:

[0022] (2-1) Let the n-bit received codeword r(x) be r(x) = r n-1 x n-1 ,,,,+r j x j +r i x i ,,,,+r1x+r0, calculate the adjoint equation S according to formula (3):

[0023] S = S(x) (n-k)*1 =[H' (n-k)*k :E (n-k)*(n-k) ]*r(x) n*1 (3)

[0024] Where S is the binary value of the syndrome, S(x) (n-k)*1 H' is a single column matrix in polynomial form of S, and H' is [E k*k :H k*(n-k) In this context, H is the transpose of the matrix, E is the identity matrix, and r(x) is the value of r(x). n*1 It is an n-bit r(x) single-column matrix;

[0025] (2-2) Calculate the Hamming weight of the syndrome S. If the Hamming weight of S is less than the error correction capability t, XOR the lower nk bits of the binary form r of S with r(x).

[0026] (2-3) Calculate the bitwise XOR value of the K column vector values ​​of the S and H' matrices in the t round. Use an OR gate to integrate all the cases that are wrong for that bit into a 1-bit error correction bit. As long as one of the cases is true, perform an XOR flip error correction on that bit to achieve decoding.

[0027] Furthermore, for the (n, k, t) BCH code, n is the length of the encoded codeword, k is the length of the data bits (i.e., the length of the codeword before encoding), t is the error correction capability, and nk is the number of parity bits. The binary values ​​of the n-bit encoded codeword and the k-bit unencoded codeword of the BCH code are expressed in polynomial form. Let c(x) be the polynomial of the encoded codeword and m(x) be the polynomial of the unencoded codeword, then we have:

[0028] Encoded codeword: c(x) = c n-1 x n-1 ,,,,+c j x j +c i x i ,,,,+c1x+c0

[0029] Codeword before encoding: m(x) = m k-1 x k-1 ,,,,+m j x j +m i x i ,,,,+m1x+m0

[0030] Where the coefficients of c(x) are c0, ..., c0. n-1 The coefficients m0, m, m of m(x) k-1 It can only be equal to 1 or 0, representing whether it is 1 at the corresponding binary bit position, thus completing the mapping from polynomial to binary codeword.

[0031] Furthermore, in step (1-1), the binary value represented by g(x) is used to construct a row matrix by shifting each row one bit to the right and padding the excess bits with 0.

[0032] Furthermore, in step (1-2), two-input XOR gates are used. That is, bitwise XOR of k bits requires k-1 XOR gates. If k is even, the k-1 XOR gates are divided into m-1 levels, with each level containing k / 2, k / 4...2, and 1 XOR gates respectively. Each level's XOR gates perform pairwise XOR operations between adjacent bits. If k is odd, the k-2 XOR gates are divided into m-1 levels. m-1-1 <k-1<2 m -1, the number of XOR gates in each stage are (k-1) / 2, (k-1) / 4...2, 1 respectively. Each stage of XOR gates is a pairwise XOR between adjacent bits. The value output by the last stage XOR gate is then XORed with the highest bit of the bitwise ANDed data to obtain a 1-bit parity bit.

[0033] Furthermore, in step (2-3), the bitwise XOR value of the K column vector values ​​of the S and H' matrices in round t is calculated, and the number of bitwise XOR values ​​in round a is C. k a Then, in round t, a total of C needs to be calculated. k 1 +C k 2 +......C k a +.....C k t Each bitwise XOR value, calculated using C from the first t-1 rounds. k 1 +C k 2 +......C k a +.....C k t-1 Hamming weight calculation is performed using a set of bitwise XOR values. If a bitwise XOR value S exists... ij.. If the Hamming weight is less than or equal to t-1, then the error correction process is as follows:

[0034] S ij ....^r[nk:0]

[0035] r[i]^(S ij ...==0)

[0036] r[j]^(S ij ...==0)...

[0037] If S in the first t-1 rounds ij If the Hamming weights of all values ​​are greater than t-1, then check if S exists. ij. If the value is 0, the error correction process is as follows:

[0038] r[i]^(S ij ...==0)

[0039] r[j]^(S ij ...==0)....

[0040] The technical effects of this invention are as follows:

[0041] Unlike previous lookup table methods, this invention, for an (n, k, t) BCH code with an n-bit codeword length, k data bits, and t-bit error correction capability, only needs to store the values ​​of k nk-bit parity check matrix column vectors. These k nk-bit parity check matrix column vectors are then XORed with the S-synonym value for t rounds. The error pattern corresponding to the received codeword is obtained from the bitwise XOR value and corrected. This invention is a hardware-level encoding and decoding implementation, which can be completed within one clock cycle, reducing the multi-cycle decoding delay caused by iterative algorithms, achieving parallelization of BCH encoding and decoding, simplifying the encoding and decoding process, and reducing resource consumption. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the original structure of the matrix G generated by this invention;

[0043] Figure 2 This is a schematic diagram illustrating the process of generating the check bit.

[0044] Figure 3 A schematic diagram of the BCH decoding process;

[0045] Figure 4 This diagram illustrates the bitwise XOR operation of the K column vector values ​​of matrices S and H'. Detailed Implementation

[0046] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0047] For an (n, k, t) BCH code, n is the length of the encoded codeword, k is the length of the data bits (i.e., the length of the codeword before encoding), t is the error correction capability, and nk is the number of parity bits. The binary values ​​of the n-bit encoded codeword and the k-bit unencoded codeword of a BCH code can be expressed in polynomial form. Let c(x) be the polynomial of the encoded codeword and m(x) be the polynomial of the unencoded codeword, then we have:

[0048] Encoded codeword: c(x) = c n-1 x n-1 ,,,,+c j x j +c i x i ,,,,+c1x+c0

[0049] Codeword before encoding: m(x) = m k-1 x k-1 ,,,,+m j x j +m i x i ,,,,+m1x+m0

[0050] Where the coefficients of c(x) are c0, ..., c0.n-1 with the coefficients m0, …, m of m(x) k-1 can only be equal to 1 or 0, representing whether it is 1 in the corresponding binary digit, and in this way, the mapping from the polynomial to the binary codeword is completed. For example, the polynomial x 5 +x 4 +x + 1 represents the binary codeword 110011.

[0051] For the encoding part of the BCH code, the present invention is carried out according to the following steps:

[0052] In the first step, according to the known generating polynomial g(x) of the (n, k, t) BCH code, a generating matrix G k*n is constructed, and the specific construction method is as Figure 1 shown, and the binary values represented by g(x) are constructed into a row matrix in the form of shifting one bit to the right for each row.

[0053] In the second step, the generating matrix G k*n in the first step is transformed into the form of [E k*k :H k*(n-k) according to the Galois field addition for row and column transformation, where the E matrix is the identity matrix, and then the encoding is carried out according to the following calculation formula. The encoded codeword c(x) is obtained from the pre-encoded codeword m(x) matrix:

[0054] c(x) 1*n = m(x) 1*k * [E k*k :H k*(n-k)

[0055] where the multiplication and addition involved in the above matrix operations are both Galois field operations, and the lower n - k bits of c(x) are the parity bits generated by the encoding, and the higher k bits are the same as m(x) and are data bits. Therefore, the encoding process is regarded as the generation process of n - k parity bits. Let the parity bit be p(x), then there is:

[0056] p(x)<{\displaystyle 0000101}>= m(x)<{\displaystyle 0000{102}}>* H<{\displaystyle 0000{103}}>

[0057] The implementation of the above formula is as Figure 2 shown. For the generation of the i-th parity bit (0 ≤ i < n - k), the k-bit binary numbers k’b e k-1 e k-2 ​e1 e0 is used as a mask, and bitwise ANDed with k-bit data d[k-1:0] (the binary numerical form of m(x)). The resulting data is then XORed bitwise. This invention uses two-input XOR gates, so k-1 XOR gates are needed to XOR k-bit data. If k is even, the k-1 XOR gates can be divided into m-1 (2^k XOR gates). m-1 -1 <k<2 m -1) levels, with the number of XOR gates in each level being k / 2, k / 4...2, 1 respectively. Each XOR gate in each level performs pairwise XOR operations between adjacent bits to obtain the value of the i-th parity bit. If k is odd, the k-2 XOR gates can be divided into m-1 (2 m-1 -1 <k-1<2 m The XOR gates in each of the -1 stages are (k-1) / 2, (k-1) / 4...2, and 1, respectively. Each XOR gate performs a pairwise XOR operation between adjacent bits. The output of the last stage XOR gate is then XORed with the most significant bit of the bitwise ANDed data to obtain a 1-bit parity bit. Other parity bits can be generated using the same method.

[0058] The BCH decoding part of this invention is as follows: Figure 3 As shown, the main steps are as follows:

[0059] Let the n-bit received codeword r(x) be:

[0060] r(x)=r n-1 x n-1 ,,,,+r j x j +r i x i ,,,,+r1x+r0

[0061] The first step is to calculate the adjoint equation S according to the formula:

[0062] S = S(x) (n-k)*1 =[H' (n-k)*k :E (n-k)*(n-k) ]*r(x) n*1

[0063] Where S is the binary value of the syndrome, S(x) (n-k)*1 H' is a single column matrix in polynomial form of S, and H' is [E k*k :H k*(n-k) In this context, H is the transpose of the matrix, E is the identity matrix, and r(x) is the value of r(x). n*1 It is an n-bit r(x) single-column matrix.

[0064] In the second step, calculate the Hamming weight of the syndrome S. If the Hamming weight of S is less than the error correction capability t, it means that all errors occur in the parity bits. By performing an exclusive OR operation on S and the lower n - k bits of r (the binary form of r(x)), the error can be corrected successfully:

[0065] S^r[n - k:0]

[0066] In the third step, as Figure 4 shown, calculate the exclusive OR values of S and K column vectors of the H' matrix for t rounds. Use OR gates to integrate all cases where an error occurs in that bit into 1 error correction bit. For example, when an error occurs in the b-th bit (0 <= b < k), there are cases where S b is 0, S bjk is 0, etc. As long as one case is true, perform an exclusive OR flip for that bit to correct the error and achieve decoding. The number of exclusive OR values in the a-th round (a < t) is C k a , so a total of C k 1 +C k 2 +......C k a +.....C k t exclusive OR values need to be calculated for t rounds. Calculate the Hamming weight of the C k 1 +C k 2 +......C k a +.....C k t-1 exclusive OR values calculated in the first t - 1 rounds. If there exists an exclusive OR value S ij .. whose Hamming weight is less than or equal to t - 1, it means that there are errors in both the parity bits and the data bits. Among them, the subscript of S ij .. is a constant less than k and greater than or equal to 0. For this case, the error correction is:

[0067] S ij ....^r[n - k:0]

[0068] r[i]^(S ij ... == 0)

[0069] r[j]^(S ij ... == 0)...

[0070] If the Hamming weight of the values of S ij.. in the first t - 1 rounds is greater than t - 1, then check if there exists S ij. equal to 0. If it is 0, it means that all errors are in the data bits, and the error correction process can be:

[0071] r[i]^(S ij ...==0)

[0072] r[j]^(S ij ...==0)...

[0073] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

[0074] References:

[0075] [1] Error Correction Coding Technology [M]. Posts & Telecom Press, 1987.

[0076] [2] A Review of ECC Error Detection and Correction Technology [C]. Wang Ning. Southeast University Anniversary Graduate Academic Conference. 2020

[0077] [3]1.Liu yang, Li jie, et alA BCH error correction scheme applied to FPGA with embedded memory JL. Frontiers of Information Technology & Electronic Engineering 2021-11).

Claims

1. A parallel encoding and decoding method for BCH codes, characterized in that, It includes a parallel encoding section and a decoding section, wherein (i) the encoding section includes the following steps: (1-1) Constructing a generator matrix G from a known generating polynomial g(x) of an (n, k, t) BCH code k*n ; (1-2) The generator matrix G is generated k*n The row and column are transformed according to the Galois field addition to transform into the form of [E k*k :H k*(n-k) ], where the E matrix is an identity matrix, and then encoding is performed according to the formula (1) to obtain the encoded codeword c(x) from the pre-encoding codeword m(x) matrix: c(x) 1*n = m(x) 1*k * E k*k H k*(n-k) ] (1) The multiplication and addition involved in the matrix operations mentioned above are Galois field operations. Let the parity bit be p(x) obtained by formula (2); p(x) 1*n-k = m(x) 1*k *H k*(n-k) (2) For the i-th parity bit, the k-th binary number k'b e in the i-th column of the H matrix. k-1 e k-2 e1 e0 is used as a mask, and is bitwise ANDed with k-bit data d[k-1:0]. The resulting data is then XORed bitwise to obtain a 1-bit parity bit. Other parity bits are generated in the same way to achieve encoding. (ii) The decoding part includes the following steps: (2-1) Let the n-bit received codeword r(x) be r(x) = r n-1 x n-1 ,,,,+r j x j +r i x i ,,,,+r1x+r0, calculate the adjoint equation S according to formula (3): S=S(x) (n-k)*1 =[H’ (n-k)*k :E (n-k)*(n-k) ]*r(x) n*1 (3) Where S is the binary value of the syndrome, S(x) (n-k)*1 H' is a single column matrix in polynomial form of S, and H' is [E k*k :H k*(n-k) In this context, H is the transpose of the matrix, E is the identity matrix, and r(x) is the value of r(x). n*1 It is an n-bit r(x) single-column matrix; (2-2) Calculate the Hamming weight of the syndrome S. If the Hamming weight of S is less than the error correction capability t, XOR the lower nk bits of S with the binary form r of r(x). (2-3) Calculate the bitwise XOR value of the K column vector values ​​of the S and H' matrices in round t. Use an OR gate to integrate all the cases that are wrong for that bit into a 1-bit error correction bit. As long as one of the cases is true, perform an XOR flip error correction on that bit to achieve decoding. For a (n, k, t) BCH code, where n is the length of the encoded codeword, k is the number of data bits (i.e., the length of the codeword before encoding), t is the error correction capability, and nk is the number of parity bits, the binary values ​​of the n-bit encoded codeword and the k-bit unencoded codeword of the BCH code are expressed in polynomial form. Let c(x) be the polynomial of the encoded codeword and m(x) be the polynomial of the unencoded codeword, then we have: Encoded codeword: c(x) = c n-1 x n-1 ...+c j x j +c i x i ,,,,+c1x+c0 Codeword before encoding: m(x) = m k-1 x k-1 ,,,,+m j x j +m i x i ,,,,+m1x+m0 Where the coefficients of c(x) are c0, ..., c0. n-1 The coefficients m0, m, m of m(x) k-1 It can only be equal to 1 or 0, representing whether it is 1 at the corresponding binary bit position, thus completing the mapping from polynomial to binary codeword.

2. The parallel encoding and decoding method for BCH codes as described in claim 1, characterized in that, In step (1-1), the binary value represented by g(x) is used to construct a row matrix by shifting each row one bit to the right.

3. The parallel encoding and decoding method for BCH codes as described in claim 1, characterized in that, Step (1-2) uses two-input XOR gates. That is, XORing k bits of data bit by bit requires k-1 XOR gates. If k is even, the k-1 XOR gates are divided into m-1 levels, with each level containing k / 2, k / 4...2, and 1 XOR gates respectively. Each level's XOR gates perform pairwise XOR operations between adjacent bits. If k is odd, the k-2 XOR gates are divided into m-1 levels. m-1 -1 <k-1<2 m -1, the number of XOR gates in each stage are (k-1) / 2, (k-1) / 4...2, 1 respectively. Each stage of XOR gates is a pairwise XOR between adjacent bits. The value output by the last stage XOR gate is then XORed with the highest bit of the bitwise ANDed data to obtain a 1-bit parity bit.

4. The parallel encoding and decoding method for BCH codes as described in claim 1, characterized in that, In step (2-3), the bitwise XOR value of the K column vector values ​​of the S and H' matrices in round t is calculated, and the number of bitwise XOR values ​​in round a is C. k a Then, in round t, a total of C needs to be calculated. k 1 +C k 2 +......C k a +.....C k t Each bitwise XOR value, calculated using C from the first t-1 rounds. k 1 +C k 2 +......C k a +.....C k t-1 Hamming weight calculation is performed using a set of bitwise XOR values. If a bitwise XOR value S exists... ij.. If the Hamming weight is less than or equal to t-1, then the error correction process is as follows: S ij.... ^r[n-k:0] r[i]^(S ij... ==0) r[j]^(S ij... ==0)... If S in the first t-1 rounds ij.. If the Hamming weights of all values ​​are greater than t-1, then check if there exists an S. ij. If the value is 0, the error correction process is as follows: r[i]^(S ij... ==0) r[j]^(S ij... ==0)...。

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