A fully differential receiver for receiving a conducted communication signal

Abstract

Described herein is a fully differential receiver that is used in an implantable medical device (IMD) and is configured to receive a conducted communication signal transmitted by another IMD or an external device. The fully differential receiver includes a fully differential preamplifier, a fully differential buffer, a first comparator, a second comparator, and an AC coupling network coupled between differential outputs of the fully differential buffer and a coupled together differential input pair of the first comparator and the second comparator. The differential input pair of the fully differential receiver includes a differential input pair of the fully differential preamplifier, and a differential output pair of the fully differential receiver includes a first output of the first comparator and a second output of the second comparator. To conserve power, the fully differential receiver selectively changes from operating in a first mode to operating in a second mode, and vice versa.

Description

[0001] Related applications

[0002] This application claims priority to U.S. patent application No. 17 / 538,827, filed on November 30, 2021, entitled “FULLY-DIFFERENTIAL PREAMPLIFIER,” and U.S. patent application No. 17 / 538,837, filed on November 30, 2021, entitled “FULLY-DIFFERENTIAL PREAMPLIFIER.” Technical Field

[0003] Embodiments of the present technology relate to fully differential receivers for use in implantable medical devices (IMDs), and IMDs including fully differential receivers. Other embodiments of the present technology relate to fully differential preamplifiers that can be included in fully differential receivers. These embodiments can be used to receive and / or amplify conducted communication signals. Background Art

[0004] In situations where a patient has multiple (i.e., two or more) implantable medical devices (IMDs), it is often beneficial for the IMDs to be able to communicate with each other. For example, in situations where a patient has a leadless pacemaker implanted in or on an atrial cardiac chamber and another leadless pacemaker implanted in or on a ventricular cardiac chamber, it is beneficial for the leadless pacemakers to communicate with each other to provide synchronized dual-chamber pacing.

[0005] To achieve dual-chamber synchronization between an atrial leadless pacemaker and a ventricular leadless pacemaker, an "implant-to-implant" or "i2i" communication scheme can be used. For the i2i communication scheme, a low-voltage pulse is transmitted by a first IMD (e.g., a first leadless pacemaker operating as a transmitting device) through its electrodes and received by a second IMD (e.g., a second leadless pacemaker operating as a receiving device) through its electrodes. A received signal, which is an attenuated version of the transmitted signal, is received as a voltage pulse on two electrodes of the second IMD coupled to its receiver.

[0006] The above-mentioned “i2i” communication scheme may also be referred to as a conducted communication scheme (or equivalently, a conductive communication scheme), and the above-mentioned signal transmitted from the first IMD to the second IMD may also be referred to as a conducted communication signal (or equivalently, a conductive communication signal). Summary of the Invention

[0007] Certain embodiments of the present technology are directed to a fully differential receiver having a differential input pair and a differential output pair, where the fully differential receiver is used in an implantable medical device (IMD) and is configured to receive a conducted communication signal transmitted by another IMD or an external device.

[0008] According to certain embodiments, the fully differential receiver includes a fully differential preamplifier, a fully differential buffer, a first comparator, a second comparator, and an AC coupling network. The fully differential preamplifier includes a differential input pair and a differential output pair. The fully differential buffer includes a differential input pair and a differential output pair, where the differential input pair of the fully differential buffer is coupled to the differential output pair of the preamplifier. The first comparator includes a differential input pair and a first output. The second comparator includes a differential input pair and a second output, where the differential input pair of the second comparator is coupled to the differential input pair of the first comparator such that the differential input pairs of the first and second comparators are coupled to each other. The AC coupling network is coupled between the differential output pair of the fully differential buffer and the coupled together differential input pairs of the first and second comparators. The differential input pair of the fully differential receiver includes the differential input pair of the fully differential preamplifier. The differential output pair of the fully differential receiver includes the first output of the first comparator and the second output of the second comparator.

[0009] According to certain embodiments, the fully differential receiver is configured to operate in a first mode and a second mode. When operating in the first mode, the fully differential receiver draws a first amount of current and monitors for a wake-up signal in a first frequency range. When operating in the second mode, the fully differential receiver draws a second amount of current that is higher than the first amount of current and is configured to receive one or more message content pulses in a second frequency range that is higher than the first frequency range.

[0010] According to certain embodiments, the fully differential receiver is configured to operate in the first mode when the fully differential preamplifier, the fully differential buffer, the first comparator, and the second comparator are provided with respective first bias currents. The fully differential receiver is configured to operate in the second mode when the fully differential preamplifier, the fully differential buffer, the first comparator, and the second comparator are provided with respective second bias currents that are greater than the respective first bias currents.

[0011] According to certain embodiments, the differential input pair of each of the first comparator and the second comparator includes a respective non-inverting (+) input and a respective inverting (-) input. The first comparator is configured to generate an output pulse at the first output when a voltage potential difference between the non-inverting (+) input and the inverting (-) input of the first comparator exceeds a first offset and is positive with respect to a common mode voltage of the fully differential receiver. The second comparator is configured to generate an output pulse at the second output when a voltage potential difference between the non-inverting (+) input and the inverting (-) input of the second comparator exceeds a second offset and is negative with respect to the common mode voltage of the fully differential receiver.

[0012] According to certain embodiments, the input pair of the fully differential receiver is coupled to an electrode pair of the IMD, where the electrode pair is used to sense a conducted communication signal transmitted by another IMD or an external device.

[0013] According to certain embodiments, the differential output pair of the fully differential buffer includes a non-inverting (+) output and an inverting (-) output, and the differential input pair of each of the first comparator and the second comparator includes a respective non-inverting (+) input and a respective inverting (-) input. The non-inverting (+) input of the first comparator is coupled to the inverting (-) input of the second comparator. The inverting (-) input of the first comparator is coupled to the non-inverting (+) input of the second comparator.

[0014] According to certain embodiments, the AC coupling network is configured to remove any DC offset that can be caused by the fully differential preamplifier and the fully differential buffer. The output DC bias point of the AC coupling network is a common mode voltage (VCM) at the vcm node of the fully differential receiver. According to certain embodiments, the AC coupling network includes first and second capacitors and first and second resistors. The first capacitor is coupled between the non-inverting (+) output of the fully differential buffer and the non-inverting (+) input of the first comparator, and between the non-inverting (+) output of the fully differential buffer and the inverting (-) input of the second comparator. The second capacitor is coupled between the inverting (-) output of the fully differential buffer and the inverting (-) input of the first comparator, and between the inverting (-) output of the fully differential buffer and the non-inverting (+) input of the second comparator. The first resistor is coupled between the common mode voltage (vcm) node and the non-inverting (+) input of the first comparator, and between the common mode voltage (vcm) node and the inverting (-) input of the second comparator. The second resistor is coupled between the common mode voltage (vcm) node and the inverting (-) input of the first comparator, and between the common mode voltage (vcm) node and the non-inverting (+) input of the second comparator.

[0015] According to certain embodiments, the differential input pair of the fully differential preamplifier includes a non-inverting (+) input and an inverting (-) input. The first high pass filter is coupled to the non-inverting (+) input of the fully differential preamplifier. The second high pass filter is coupled to the inverting (-) input of the fully differential preamplifier. The first high pass filter and the second high pass filter are configured to filter out one or more signals indicative of cardiac electrical activity.

[0016] According to certain embodiments, the differential input pair of the fully differential preamplifier includes a non-inverting (+) input and an inverting (-) input. The fully differential preamplifier includes a switch pair that, when selectively closed, causes a zero voltage potential difference to exist between the non-inverting (+) input and the inverting (-) input of the fully differential preamplifier, thereby causing a zero voltage potential difference to exist between the input pair of the fully differential receiver.

[0017] According to certain embodiments, the fully differential receiver is configured to operate in a first mode and a second mode, as described above. The fully differential preamplifier includes a switch that is selectively closed for a period of time each time there is a change from the first mode to the second mode, and each time there is a change from the second mode to the first mode to reset the fully differential receiver.

[0018] Certain embodiments of the present technology are directed to an implantable medical device (IMD) configured to communicate with at least one of another IMD or an external device using a conducted communication signal, wherein the IMD includes at least two electrodes, a fully differential receiver, a logic detector, a controller, and a battery. The fully differential receiver has an input pair and an output pair. The input pair of the fully differential receiver is coupled to a pair of electrodes of the at least two electrodes. The logic detector has an input pair and one output. The input pair of the logic detector is coupled to the output pair of the fully differential receiver. The controller, including an input coupled to the output of the logic detector, is configured to decode pulses received from the logic detector. The battery is configured to power components of the IMD, including the fully differential receiver, the logic detector, and the controller.

[0019] According to certain embodiments, the fully differential receiver of the IMD is configured to operate in a first mode and a second mode. When operating in the first mode, the fully differential receiver draws a first amount of current from the battery and monitors for a wake-up signal in a first frequency range. When operating in the second mode, the fully differential receiver draws a second amount of current from the battery that is higher than the first amount of current and is configured to receive one or more message content pulses in a second frequency range that is higher than the first frequency range.

[0020] According to certain embodiments, a fully differential receiver of an IMD includes a fully differential preamplifier, a fully differential buffer, a first comparator and a second comparator, and an AC coupling network. The fully differential preamplifier includes a differential input pair and a differential output pair. The fully differential buffer includes a differential input pair and a differential output pair, where the differential input pair of the fully differential buffer is coupled to the differential output pair of the preamplifier. The first comparator includes a differential input pair and a first output. The second comparator includes a differential input pair and a second output, where the differential input pair of the second comparator is coupled to the differential input pair of the first comparator such that the differential input pairs of the first and second comparators are coupled to each other. The AC coupling network is coupled between the differential output of the fully differential buffer and the coupled together differential input pairs of the first and second comparators. The differential input pair of the fully differential receiver includes the differential input pair of the fully differential preamplifier. The differential output pair of the fully differential receiver includes the first output of the first comparator and the second output of the second comparator.

[0021] According to certain embodiments, a fully differential receiver of an IMD is configured to operate in a first mode when the fully differential preamplifier, the fully differential buffer, the first comparator, and the second comparator are provided with respective first bias currents. The fully differential receiver of the IMD is configured to operate in a second mode when the fully differential preamplifier, the fully differential buffer, the first comparator, and the second comparator are provided with respective second bias currents that are greater than the respective first bias currents.

[0022] Certain embodiments of the present technology are directed to a method for a fully differential receiver of an IMD, where the fully differential receiver is powered by a battery of the IMD. Such a method can include operating the fully differential receiver according to a first mode during which a wake-up signal is monitored over a first frequency range. The method further includes, in response to detecting the wake-up signal while the fully differential receiver is operating in the first mode, changing from operating the fully differential receiver according to the first mode to operating the fully differential receiver according to a second mode during which one or more message content pulses are received over a second frequency range. The method further includes changing back from operating the fully differential receiver according to the second mode to operating the fully differential receiver according to the first mode. According to certain embodiments, the second frequency range is higher than the first frequency range, and the second mode draws more current from the battery, and thus more power, than the first mode. According to certain embodiments, changing back from operating the fully differential receiver according to the second mode to operating the fully differential receiver according to the first mode occurs at the end of a message content window.

[0023] According to embodiments of the present technology, a fully differential preamplifier has a differential input pair including a positive input (INP) and a negative input (INM), and a differential output pair including a positive output (OUTP) and a negative output (OUTM). According to certain embodiments, the fully differential preamplifier includes first and second N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) (Mn1 and Mn2), and first and second P-channel MOSFETs (Mp1 and Mp2), each including a gate, a drain, and a source. The sources of the first and second N-channel MOSFETs (Mn1 and Mn2) are connected to each other. The sources of the first and second P-channel MOSFETs (Mp1 and Mp2) are connected to each other and to a high voltage rail (VPLUS). The fully differential preamplifier further includes a current source connected between the sources of the first and second N-channel MOSFETs (Mn1 and Mn2) connected together and a low voltage rail. The gate of the first N-channel MOSFET (Mn1) constitutes the positive input (INP) of the fully differential preamplifier. The gate of the second N-channel MOSFET (Mn2) constitutes the negative input (INM) of the fully differential preamplifier. The drains of the first N-channel MOSFET (Mn1) and the first P-channel MOSFET (Mp1) are connected to each other and constitute the negative output (OUTM) of the fully differential preamplifier. The drains of the second N-channel MOSFET (Mn2) and the second P-channel MOSFET (Mp2) are connected to each other and constitute the positive output (OUTP) of the fully differential preamplifier.

[0024] According to certain embodiments, the fully differential preamplifier further includes: a first resistor and a first switch connected in parallel to each other between the gate and the drain of the first N-channel MOSFET (Mn1); a second resistor and a second switch connected in parallel to each other between the gate and the drain of the second N-channel MOSFET (Mn2); a third resistor and a third switch connected in parallel to each other between the gate and the drain of the first P-channel MOSFET (Mp1); and a fourth resistor and a fourth switch connected in parallel to each other between the gate and the drain of the second P-channel MOSFET (Mp2). The first, second, third, and fourth switches are configured to reset an operating voltage of the fully differential preamplifier when the first, second, third, and fourth switches are closed simultaneously.

[0025] According to certain embodiments, the fully differential preamplifier further comprises a first capacitor coupled between the gate and the source of the first P-channel MOSFET (Mp1), and a second capacitor coupled between the gate and the source of the second P-channel MOSFET (Mp2). The first and second capacitors are configured to maintain a voltage at the gates of the first and second P-channel MOSFETs (Mp1 and Mp2) such that the first and second P-channel MOSFETs (Mp1 and Mp2) act as current sources and increase the impedance of the fully differential preamplifier compared to a case where the first and second capacitors are not present.

[0026] According to certain embodiments, a differential input pair of the fully differential preamplifier comprising a positive input (INP) and a negative input (INM) is configured to be coupled to a pair of electrodes (E1 and E2) of an implantable medical device (IMD). A first high pass filter (HPF) is coupled between a first one of the electrodes and the positive input (INP). A second high pass filter (HPF) is coupled between a second one of the electrodes and the positive input (INP). The first and second HPFs are configured to filter out one or more signals indicative of cardiac electrical activity that can be sensed by the pair of electrodes. According to certain embodiments, the first HPF comprises a third capacitor comprising a first terminal and a second terminal, the first terminal of the third capacitor being coupled to the first one of the electrodes, and a fifth resistor coupled between the second terminal of the third capacitor and a low voltage rail. The second HPF comprises a fourth capacitor comprising a first terminal and a second terminal, the first terminal of the fourth capacitor being coupled to the second one of the electrodes, and a sixth resistor coupled between the second terminal of the fourth capacitor and the low voltage rail.

[0027] According to certain embodiments, the fully differential preamplifier further comprises a fifth switch connected in parallel with the fifth resistor between the second terminal of the third capacitor and the low voltage rail, and a sixth switch connected in parallel with the sixth resistor between the second terminal of the fourth capacitor and the low voltage rail. The fifth and sixth switches are configured to apply a zero voltage difference between the positive input (INP) and the negative input (INM) when the third and fourth switches are closed at the same time.

[0028] According to certain embodiments, the fully differential preamplifier is configured to be contained within a fully differential receiver. In such embodiments, the fifth and sixth switches, when closed, are configured to blank the fully differential receiver.

[0029] According to certain embodiments, the fully differential preamplifier further comprises a fifth capacitor coupled between the second terminal of the third capacitor and a negative input (INM), and a sixth capacitor coupled between the second terminal of the fourth capacitor and the negative input (INM), wherein the fifth and sixth capacitors comprise direct current (DC) blocking capacitors.

[0030] According to certain embodiments, the current source is configured to change operation of the fully differential preamplifier from a low current mode to a higher current mode in response to a mode control signal received from a controller.

[0031] According to certain embodiments, the fully differential preamplifier comprises a pair of blanking switches configured to apply a zero voltage difference between the positive and negative inputs (INP and INM) in response to the pair of blanking switches being closed simultaneously. Further, a voltage difference between the positive and negative outputs (OUTP and OUTM) is substantially zero when both of the pair of blanking switches are closed.

[0032] According to certain embodiments, the fully differential preamplifier comprises an input differential pair, an output current load, and a current source. The current source is coupled between the input differential pair and a low voltage rail and is configured to control whether the fully differential preamplifier operates in a first mode or a second mode, wherein the preamplifier draws more current when operating in the second mode than when operating in the first mode. The input differential pair is coupled between the output current load and the current source. The output current load is coupled between a high voltage rail and the input differential pair. The input differential pair comprises a positive input and a negative input (INP and INM) of the fully differential preamplifier. Nodes at which the input differential pair and the output current load are coupled to each other comprise a positive output and a negative output (OUTP and OUTM) of the fully differential preamplifier. According to certain embodiments, the input differential pair comprises: a first N-channel metal-oxide-semiconductor field-effect transistor (MOSFET) and a second N-channel MOSFET (Mnl and Mn2), each comprising a gate, a drain, and a source. The sources of the first and second N-channel MOSFETs (Mnl and Mn2) are connected to each other. The drain of the first N-channel MOSFET (Mnl) constitutes the negative output (OUTM) of the fully differential preamplifier. The drain of the second N-channel MOSFET (Mn2) constitutes the positive output (OUTP) of the fully differential preamplifier. The gate of the first N-channel MOSFET (Mnl) constitutes the positive input (INP) of the fully differential preamplifier. The gate of the second N-channel MOSFET (Mn2) constitutes the negative input (INM) of the fully differential preamplifier. The current source is connected between the sources of the first and second N-channel MOSFETs (Mnl and Mn2) that are connected together and the low voltage.

[0033] According to certain embodiments, the output current load includes a first P-channel MOSFET and a second P-channel MOSFET (Mp1 and Mp2), each including a gate, a drain, and a source. The sources of the first P-channel MOSFET and the second P-channel MOSFET (Mp1 and Mp2) are connected to each other and to a high voltage rail. The drain of the first P-channel MOSFET (Mp1) is coupled to the drain of the first N-channel MOSFET (Mn1) and also forms the negative output (OUTM) of the fully differential preamplifier. The drain of the second P-channel MOSFET (Mp2) is coupled to the drain of the second N-channel MOSFET (Mn2) and also forms the positive output (OUTP) of the fully differential preamplifier.

[0034] According to certain embodiments, the fully differential preamplifier further includes: a first resistor and a first switch connected in parallel between the gate and drain of a first N-channel MOSFET (Mn1); a second resistor and a second switch connected in parallel between the gate and drain of a second N-channel MOSFET (Mn2); a third resistor and a third switch connected in parallel between the gate and drain of a first P-channel MOSFET (Mp1); and a fourth resistor and a fourth switch connected in parallel between the gate and drain of a second P-channel MOSFET (Mp2). The first, second, third, and fourth switches are configured to reset an operating voltage of the fully differential preamplifier when the first, second, third, and fourth switches are simultaneously closed.

[0035] According to certain embodiments, the fully differential preamplifier further includes a pair of blanking switches configured to impose a zero voltage difference between the positive input and the negative input (INP and INM) in response to the blanking switches being simultaneously closed. The fully differential amplifier is configured to output a substantially zero voltage difference between the positive output and the negative output (OUTP and OUTM) when both blanking switches are closed.

[0036] According to certain embodiments, a first capacitor is coupled between the gate and source of a first P-channel MOSFET (Mp1), and a second capacitor is coupled between the gate and source of a second P-channel MOSFET (Mp2). The first and second capacitors are configured to maintain a voltage at the gates of the first and second P-channel MOSFETs (Mp1 and Mp2) such that the first and second P-channel MOSFETs (Mp1 and Mp2) act as current sources and increase the impedance of the fully differential preamplifier compared to a case where the first and second capacitors are not present.

[0037] According to certain embodiments, a first high-pass filter and a first direct current (DC) blocking capacitor are coupled between a positive input (INP) and the first electrode, and a second high-pass filter and a second DC blocking capacitor are coupled between a negative input (INM) and the second electrode.

[0038] This summary of the invention is not intended to be a complete description of embodiments of the technology. Other features and advantages of embodiments of the technology will be apparent from the following description, taken in conjunction with the accompanying drawings and claims, in which preferred embodiments of the technology are set forth, and in which it is intended that the description be considered as exemplary rather than as limiting of the technology. BRIEF DESCRIPTION OF DRAWINGS

[0039] Embodiments of the technology, both as to its structure and method of operation, can best be understood by referring to the following description and accompanying drawings in which like reference characters refer to like elements throughout:

[0040] Figure 1 A fully differential receiver according to embodiments of the technology is shown that is used in an implantable medical device (IMD) and is configured to receive a conducted communication signal transmitted by another IMD or an external device.

[0041] Figure 2 An example timing diagram is shown for explaining the operation of the fully differential receiver introduced in Figure 1

[0042] Details of a fully differential preamplifier that can be included in the fully differential receiver introduced in Figure 3 Figure 1 is a high-level block diagram of an example IMD that can include the fully differential receiver introduced in

[0043] Figure 4 Figure 1 Figure 3

[0044] Figure 5 is a high-level flowchart of a method for describing the operation of a fully differential receiver, such as the fully differential receiver introduced in Figure 1 DETAILED DESCRIPTION

[0045] ​​​​​In the case of transmitting a conducted communication signal from a first IMD to a second IMD, each IMD includes two electrodes, and the receiver of the second IMD can be implemented as a single-ended receiver. When the receiver is single-ended, this means that one of the two electrodes is connected to the device ground. This essentially means that only one of the two electrodes is used to monitor and detect the conducted communication signal. Directly grounding one of the two electrodes (through which the conducted communication signal is received) limits the flexibility of how the electrodes must be electrically connected to the receiver to be used as a receiving electrode. Furthermore, the sensitivity of a single-ended receiver is largely dependent on the signal polarity, and more specifically, on how the signal polarity is represented with respect to the input of the receiver. This can be problematic because the polarity of the received conducted communication signal is typically not known a priori as it can change with posture, blood circulation, heart wall motion, and / or IMD implant location. Another issue with single-ended receivers is that they are typically highly sensitive to noise. In fact, power and ground noise often adversely affect single-ended receivers. To reduce the probability of false detection of a conducted communication pulse, a low noise power supply is typically required for single-ended receivers, which can increase the cost, size, and complexity of the power supply.

[0046] Furthermore, in the case of another type of IMD, such as a subcutaneous implantable cardioverter defibrillator (S-ICD), detecting a conducted communication signal on three or more electrodes or a subset thereof, a single-ended receiver would not be usable to detect a conducted communication signal between each possible set of electrodes or electrode subset (e.g., electrode pair) due to its limitations on how the electrodes must be connected to the single-ended receiver.

[0047] As will be described below, certain embodiments of the present technology relate to fully differential receivers that are particularly useful for enabling an IMD to receive a conducted communication signal. The fully differential receiver solutions described herein overcome most of the limitations of single-ended receivers discussed above, namely: 1) sensitivity is independent of the polarity of the received signal, thus less dependent on device orientation or pulse shape (single vs. dual phase); 2) better immunity to power and ground noise because the noise is not seen as a direct differential signal (this provides a cost reduction because no external capacitor is required for a dedicated quiet noise power supply); 3) support for multi-electrode systems (such as S-ICD) because there are no requirements on how the electrodes are electrically connected to the receiver; 4) less frequent need to periodically auto-zero the receiver (this reduces the message loss rate); and 5) the circuit supports multi-mode operation (there is on-demand programmability of low and high bandwidth).

[0048] Figure 1A fully differential receiver 102 according to embodiments of the present technology is shown. The fully differential receiver 102 is shown as including a plurality of stages, including a fully differential preamplifier 112, a fully differential buffer 122, an alternating current (AC) coupling network 132, and two comparators 142, 152. Except for the AC coupling network 132, these stages are active stages, each including one or more active devices, such as transistors. In contrast, the AC coupling network 132 is a passive stage including only passive devices, such as resistors and capacitors. The fully differential input of the receiver 102, and more specifically, the fully differential input of the fully differential preamplifier 112 of the receiver 102, is shown as being coupled to electrodes El, E2. The electrodes El, E2 are used to sense a conducted communication signal transmitted by another IMD, which is significantly attenuated when sensed by the electrodes El, E2, and can include peaks having amplitudes below millivolts (mV). As will be described in further detail below, the same electrodes El, E2 can also be used to transmit a conducted communication signal to another IMD. Depending on the particular implementation, the same electrodes El, E2 can also be used to sense a signal indicative of electrical activity of the heart, such as an electrogram (EGM) or electrocardiogram (ECG). Additionally or alternatively, the same electrodes El, E2 can also be used to deliver cardiac stimulation, more specifically, cardiac pacing pulses and / or defibrillation shocks. The electrodes El, E2 can also be used to sense a conducted communication signal transmitted by an external device, such as an external programmer, and to transmit a conducted communication signal to the external device or another IMD.

[0049] The fully differential preamplifier 112 (which can also be referred to herein more simply as the preamplifier 112) is shown as having differential input terminals, including a negative (-) input terminal and a positive (+) input terminal. The preamplifier 112 is also shown as having differential output terminals, including a positive (+) output terminal and a negative (-) output terminal. The preamplifier 112 amplifies a low amplitude (e.g., below millivolts (mV)) conducted communication signal sensed by the electrodes El, E2. According to certain embodiments of the present technology, the preamplifier 112 has a gain in the range of 50 dB to 70 dB. However, in other embodiments, the preamplifier 112 can have a gain higher or lower than the foregoing range. According to embodiments of the present technology, the specific implementation of the fully differential preamplifier 112 is described below with reference to FIGS. 2A and 2B. Figure 3 The specific implementation of the fully differential preamplifier 112 is described. The receiver 102 can alternatively include a preamplifier different from the one shown. Figure 3 The specific implementation of the fully differential preamplifier 112 is described. The receiver 102 can alternatively include a preamplifier different from the one shown.

[0050] Note that any negative (-) terminal described herein may alternatively be referred to as an inverting (-) terminal, and any positive (+) terminal described herein may alternatively be referred to as a non-inverting (+) terminal. More specifically, each negative (-) input terminal mentioned herein may be more concisely referred to as a negative (-) input, an inverting (-) input terminal, or an inverting (-) input. Similarly, each positive (+) input terminal may also be more concisely referred to as a positive (+) input, a non-inverting (+) input terminal, or a non-inverting (+) input. Each negative (-) output terminal mentioned herein may be more concisely referred to as a negative (-) output, an inverting (-) output terminal, or an inverting (-) output. Similarly, each positive (+) output terminal may also be more concisely referred to as a positive (+) output, a non-inverting (+) output terminal, or a non-inverting (+) output. The positive input may also be referred to as or labeled as INP, and the negative input may also be referred to as or labeled as INM (where "M" represents a minus sign, also referred to as negative). The positive output may also be referred to or labeled as OUTP, and the negative output may also be referred to or labeled as OUTM.

[0051] Fully differential buffer 122 and AC coupling network 132 decouple the differential output of preamplifier 112 from subsequent downstream circuitry (including comparators 142 and 152) to reduce and preferably minimize the loading on the downstream circuitry and remove any preamplifier output offset. Fully differential buffer 122 (also more simply referred to herein as buffer 122) is shown as having differential input terminals, including a negative (-) input terminal and a positive (+) input terminal. Buffer 122 is also shown as having differential output terminals, including a negative (-) output terminal and a positive (+) output terminal. According to one embodiment, buffer 122 has unity gain.

[0052] exist Figure 1 In the illustrated embodiment, AC coupling network 132 is shown as including capacitors 133, 134 and resistors 135, 136. Capacitors 133, 134 are matched, meaning they have substantially the same capacitance value. Resistors 135, 136 are also matched, meaning they have substantially the same resistance value. Between resistors 135, 136 is a common-mode voltage (VCM) node 137, which can be coupled to ground or to a common-mode voltage source, depending on the specific implementation. The voltage at VCM node 137 can be referred to as the common-mode voltage (VCM). AC coupling network 132 is configured to remove any DC offset that may be introduced by fully differential preamplifier 112 and fully differential buffer 122. The output DC bias point of AC coupling network 132 is the common-mode voltage (VCM) at VCM node 137. When two components (e.g., resistors or capacitors) have substantially the same value, this means that one value is within + / - 5% of the other, and / or vice versa.

[0053] Capacitor 133 of AC coupling network 132 is coupled between the positive (+) output terminal of buffer 122 and the positive (+) input terminal of comparator 142, where an offset 141 is specified at the positive (+) input terminal of comparator 142 as discussed in more detail below. Capacitor 133 of AC coupling network 132 is also coupled between the positive (+) output terminal of buffer 122 and the negative (-) input terminal of comparator 152. Capacitor 134 of AC coupling network 132 is coupled between the negative (-) output terminal of buffer 122 and the negative (-) input terminal of comparator 152. Capacitor 134 of AC coupling network 132 is also coupled between the negative (-) output terminal of buffer 122 and the positive (+) input terminal of comparator 152, where an offset 151 is specified at the positive (+) input terminal of comparator 152 as discussed in more detail below. Resistor 135 is coupled between vcm node 137 and the positive (+) input terminal of comparator 142, and between vcm node 137 and the negative (-) input terminal of comparator 152. Resistor 136 is coupled between vcm node 137 and the negative (-) input terminal of comparator 142, and between vcm node 137 and the positive (+) input terminal of comparator 152.

[0054] Each of the two comparators 142, 152 has a programmable threshold specified by the offset 141, 151 at its respective positive (+) input terminal, which is used to detect a conducted communication signal, and the two comparators 142, 152 report detection of positive and negative conducted communication pulses (DETP, DETN) with an indication of the received polarity, respectively. As noted above, the programmable threshold of comparator 142 is specified by the offset 141 of its positive (+) input terminal, and the programmable threshold of comparator 152 is specified by the offset 151 of its positive (+) input terminal. Accordingly, from Figure 2 It will be appreciated that each of the comparators 142, 152 will report a respective detection in response to a bi-phase pulse of a conducted communication signal received by receiver 102, as described below. More specifically, comparator 142 will generate a positive detection pulse (DETP) in response to a positive portion of a bi-phase pulse received at the positive (+) input terminal of comparator 142 that exceeds the offset 141, and comparator 152 will generate a negative detection pulse (DETN) in response to a negative portion of a bi-phase pulse received at the positive (+) input terminal of comparator that exceeds the offset 151.

[0055] The respective offsets 141, 152 or each of the comparators 142, 152 (also referred to as input offset voltage) specifies the voltage potential difference that must exist between the positive (+) input terminal and the negative (-) input terminal of the comparator in order for the output of the comparator to change from one logic level to another (i.e., from LOW to HIGH, or vice versa). According to certain embodiments, each of the comparators 142, 152 includes a respective pair of transistors (also referred to as a pair of load transistors, or input pair) for providing the differential input to the comparator, and in such embodiments, the offset 141, 151 can be implemented by a mismatch in the pair of transistors. The offset 141, 151 can be programmable by utilizing a set of transistors within each pair of transistors, whereby the transistors within the set of transistors can be switched into or out of the pair of transistors, thereby programming the degree of offset 141, 151.

[0056] According to certain embodiments of the present technology, a MODE control signal is used to control the sensitivity of the receiver 102 to various pulse widths by increasing or decreasing the current bias in each active stage of the receiver 102. This mode control signal is labeled as MODE in Figure 1 . The higher the bias current, the more sensitive the receiver 102 is to narrow pulses. The controller Figure 1 (not shown in Figure 4The controller 412 (not limited to, but including the controller 412 in the receiver 102) can control the MODE control signal, for example, can selectively increase and decrease the amplitude of the MODE control signal. Each active stage of the receiver 102 can have its own respective low bias current and high bias current appropriate for the requirements of the active stage, where the respective low bias current is used when the receiver 102 is in the low current LF mode, and the respective high bias current is used when the receiver 102 is in the higher current HF mode. For example, the preamplifier 112 will have its own high bias current and low bias current, the transition between which is based on the MODE control signal provided to the preamplifier 112. Similarly, the buffer 122 will have its own high bias current and low bias current, the transition between which is based on the MODE control signal provided to the buffer 122. Further, the comparators 142 and 152 can have their own high bias current and low bias current, the transition between which is based on the MODE control signal(s) provided to the comparators. If the comparators 142 and 152 include the same circuitry, the high bias current and low bias current can have the same amplitude for the comparators 142 and 152. In other words, when the fully differential receiver 102 is operating in the low current LF mode, the fully differential preamplifier 112, the fully differential buffer 122, the comparator 142, and the comparator 152 are provided with respective first bias currents; and when the fully differential receiver 102 is operating in the higher current HF mode, the fully differential preamplifier 112, the fully differential buffer 122, the comparator 142, and the comparator 152 are provided with respective second bias currents, which collectively draw more power from the battery than the first bias currents. More generally, when the receiver 102 is in the low current LF mode, the receiver draws a first amount of current, and when the receiver 102 is in the higher current HF mode, the receiver draws a second amount of current that is greater than the first amount of current.

[0057] According to embodiments of the present technology, the receiver 102 can selectively be placed in its low current LF mode or its higher current HF mode as needed. The low current LF mode can also be referred to more generally herein as an alert mode or a first operating mode, and the higher current HF mode can be referred to more generally herein as a decode mode or a second operating mode, where the second operating mode draws more current from the battery, and thus more power, than the first operating mode. According to one embodiment, when the receiver 102 is in its low current LF mode, the receiver 102 draws a low current on the order of a few hundred nanoamps (nA). When the receiver 102 is in the low current LF alert mode, the receiver 102 monitors for an LF wake-up signal, which can include an LF wake-up pulse, but is not limited to the same. An example of such an LF wake-up pulse is shown in FIG. 3. Figure 2202, which will be discussed below. Alternatively, the LF wake-up signal may include more than one wake-up pulse. For example, the LF wake-up signal may instead include two or three pulses having the same or different predetermined widths separated by one or more predetermined time gaps. Other variations are possible and are within the scope of the embodiments described herein. For the remainder of this discussion, it is assumed that the LF wake-up signal includes a single LF wake-up pulse (e.g., Figure 2 202 in FIG. 1 ). However, as explained above, this is not necessarily the case.

[0058] Still refer to Figure 1 , in response to detecting a LF wake-up signal (e.g., which may include Figure 2 2), the receiver 102 transitions to the higher current HF mode. According to certain embodiments, when the receiver 102 is in the higher current HF mode, it draws at least twice the current from the power source (e.g., a battery) as it does when the receiver 102 is in the low current LF mode. According to a particular embodiment, when the receiver 102 is in the higher current HF mode, it draws at least an order of magnitude (i.e., at least ten times) the current it draws when the receiver 102 is in the low current LF mode.

[0059] When the receiver 102 is in the higher current HF mode, the receiver 102 is used to monitor and receive HF (e.g., microsecond width) message content pulses, or more generally, message content signals. In this way, the receiver 102 adapts its current consumption to the received conducted communication signals, thereby reducing (and preferably minimizing) battery current consumption where possible.

[0060] Now use Figure 2 The operation of receiver 102 is further explained with reference to the example timing diagrams in FIG. 1 , including how receiver 102 can change its operating mode from the aforementioned low current LF mode to the higher current HF mode, and vice versa. Figure 2 The top waveforms in FIG, labeled E1-E2, show example signals sensed by electrodes E1 and E2. The waveform labeled DETP shows the output of comparator 142 in response to the signals sensed by electrodes E1 and E2, and the waveform labeled DETN shows the output of comparator 152 in response to the signals sensed by electrodes E1 and E2. When a signal is sensed by electrodes E1 and E2, it may alternatively be said that the signal is sensed on electrodes E1 and E2, or that the signal is sensed between electrodes E1 and E2. The waveform labeled HF MODE specifies when the receiver 102 switches from a low current LF mode to a higher current HF mode, and vice versa. More specifically, in FIG, Figure 2In the timing diagram, the receiver 102 is in the low current LF mode when the HF MODE waveform is LOW, and the receiver 102 is in the higher current HF mode when the HF MODE waveform is HIGH.

[0061] The waveform labeled "RESET" specifies when the receiver 102, and more specifically, its preamplifier 112, is reset. According to certain embodiments, a reset pulse is generated whenever there is a transition from the low current LF mode to the higher current HF mode, and whenever there is a transition from the higher current HF mode to the low current LF mode. For example, still referring to Figure 2 A reset pulse 242 is generated when there is a transition from the low current LF mode to the higher current HF mode. A reset pulse 244 is generated when there is a transition from the high current HF mode to the low current LF mode. According to certain embodiments, the reset pulses (e.g., 242, 244) are used to turn on (close) certain switches within the preamplifier 112, thereby resetting the preamplifier 112, and more generally, the receiver 102. The HF mode signal and the reset signal (examples of which are shown in Figure 2 ) can be generated by a controller (e.g., the controller 412 in Figure 4 According to certain embodiments, the reset signal causes certain switches within the preamplifier 112 to be temporarily closed, thereby resetting the operating point voltages within the preamplifier 112, and thereby resetting the operating point voltages within the receiver 102.

[0062] According to certain embodiments, the reset pulse 244 can also be used to reset the operating point voltages within the preamplifier 112, and thereby reset the operating point voltages within the receiver 102, at additional times (in addition to when there is a transition from the low current LF mode to the higher current HF mode, or when there is a transition from the higher current HF mode to the low current LF mode). For example, if the receiver 102 does not detect an LF wake-up signal for at least a specified period of time (e.g., 5 seconds, 10 seconds, 1 minute, 5 minutes, 1 hour, 2 hours, 24 hours, but not limited thereto), then the controller of the receiver 102 can cause an instance of the reset pulse 244 to be generated, thereby resetting the operating point voltages of the receiver 102, in case a drift in one or more of the operating point voltages adversely affects the receiver's ability to detect the LF wake-up signal. Such a period of time (which can have a default or programmed duration) can be tracked using a decrementing or incrementing clock, but is not limited thereto.

[0063] Still referring to Figure 2In the example timing diagram shown therein, while the receiver 102 is in the low current LF mode, the receiver 102 detects the wide LF pulse 202, which causes the receiver 102 to switch to the higher current HF mode. More specifically, the electrodes E1 and E2 detect the wide LF pulse 202 between times tl and t2, which causes a detection pulse 212 to be generated at the output of the comparator 142 between times tl and t2. The wide LF pulse 202 can also be referred to herein as a wake-up pulse, as it serves to wake the receiver 102 from its low current LF mode and transition it to its higher current HF mode. The detection pulse 212 (also referred to as a wake-up detection pulse 212) or an indication of its detection is provided to the controller (e.g., the controller 412 in Figure 4 ), which causes the receiver 102 to transition from its low current LF mode to its higher current HF mode in response to receiving the detection pulse 212 (or an indication of its detection). The controller accomplishes this by selectively increasing Figure 1 the amplitude of the MODE control signal shown. This has the effect of increasing the current, which in turn increases the power consumed by the receiver 102, which in turn enables the receiver 102 to detect narrower and higher frequency pulses, such as Figure 2 the pulses detected between times t5 and tl3 in Figure 2 The timing diagram in Figure 2 , the wide LF pulse 202 (i.e., the wake-up pulse) is shown as a positive pulse and causes the comparator 142 to generate the DETP 212, which in turn causes the receiver 102 to be switched to the higher current HF mode. Alternatively, the wide LF pulse can be a negative pulse, which would cause the comparator 152 to generate the DETN, which would also cause the receiver 102 to be switched to the higher current HF mode. In other words, the receiver 102 can change from its low current LF mode to its higher current HF mode regardless of whether the received wake-up pulse has a positive or negative polarity. Furthermore, as noted above, in certain embodiments, the LF wake-up signal can include more than one wake-up pulse. For example, the LF wake-up signal can instead include two or three pulses having the same or different predetermined widths separated by one or more predetermined time gaps. Other variations are also possible and within the scope of the embodiments described herein.

[0064] When in the higher current HF mode, the receiver 102 is able to detect and distinguish multiple narrow HF biphasic pulses 204, 206, 208 and report detections for both positive polarity (as indicated by the pulses 214, 216, 218 generated at the output of the comparator 142) and negative polarity (as indicated by the pulses 224, 226, 228 generated at the output of the comparator 152). The narrow HF biphasic pulses 204, 206, 208 can be referred to as message content pulses, as they are encoded with a message from another IMD or from an external device. The pulses 214, 216, 218 generated at the output of the comparator 142 can be referred to as positive detection pulses or DETP pulses. The pulses 224, 226, 228 generated at the output of the comparator 152 can be referred to as negative detection pulses or DETN pulses. The DETP pulses can be collectively referred to as a DETP signal, and the DETN pulses can be collectively referred to as a DETN signal. The DETP pulses, the DETN pulses, or preferably both the DETP pulses and the DETN pulses are decoded to determine the message content encoded therein by the IMD or external device that sent the conducted communication signal received by the receiver 102. Such decoding can be implemented by providing the DETP and / or DETN pulses to a microprocessor of a controller 412 in Figure 4 , or alternatively by providing the DETP and / or DETN pulses to a logic detector 421 in Figure 4 that converts the pulses to logic levels (high and low) provided to a controller (e.g., microprocessor) of the IMD. Such a logic detector can be implemented, for example, using logic gates, state machines, etc.

[0065] Still referring to Figure 2 , according to certain embodiments, the duration between the end of the wake-up pulse 202 and the start of the first narrow HF biphasic pulse 204 (i.e., the start of the first message content pulse), i.e., the duration between time t2 and time t5, is a predetermined interval, such that the receiver and / or logic detector (e.g., 421 in Figure 4 knows when to expect a message content pulse following the wake-up pulse 202. According to certain embodiments, the message content pulses are communicated within a time window having a predetermined duration, at the end of which the receiver 102 transitions back to its low current LF mode until another wake-up pulse 202 (or more generally, until another wake-up signal) is received. In other words, at the end of the predetermined duration, there can be a transition from the higher current HF mode back to the low current LF mode, which can be measured using a decrementing or incrementing clock, but is not limited thereto. For example, such a window can have a duration from time t3 to time t14.

[0066] Various techniques can be used to encode information onto the message content pulses, including but not limited to a delay between consecutive message content pulses, a delay between non-consecutive message content pulses (e.g., a delay between a first message content pulse and a last message content pulse within a window), and the like. For example, a first message type (e.g., a first event message) can be represented by a first HF biphasic pulse, followed by a second HF biphasic pulse T time units after the first HF biphasic pulse, followed by a third HF biphasic pulse 3T time units after the second HF biphasic pulse and 5T time units after the first HF biphasic pulse (where T time unit is a predetermined unit of time). A second message type (e.g., a second event message) can be represented as a first HF biphasic pulse, followed by a second HF biphasic pulse 2T time units after the first HF biphasic pulse, followed by a third HF biphasic pulse 4T time units after the second HF biphasic pulse and 7T time units after the first HF biphasic pulse. In this scheme, the receiver, logic detector, and / or controller of the IMD can perform pattern matching to detect the various different message types. This concept can be further extended to handle multiple bit errors by adding more transmitted bits and a larger range of intervals, if desired, but at an additional cost in both transmitted and received currents. Other variations are possible and within the scope of the embodiments described herein.

[0067] In the present disclosure, whenever it is said that a receiver 102 or a stage thereof draws more current and thus more power in one mode than in another mode, it is understood that this comparison is made in terms of a common unit of time, e.g., in terms of microseconds or in terms of seconds. For example, as has been explained above often, the receiver 102 draws more current and thus more power when it is operating in its higher-current HF mode than when it is operating in its lower-current LF mode. For a more specific example, in terms of a common unit of time, the current draw when the receiver 102 is operating in the higher-current HF mode can be at least ten times (i.e., 10x) the current draw when the receiver 102 is operating in the lower-current LF mode. However, because the receiver 102 can spend 99% of its time operating in the lower-current LF mode and only 1% of its time operating in the higher-current HF mode, overall, more current and power of the receiver battery can be consumed over time during the lower-current LF mode than during the higher-current HF mode. However, it is still appropriate to explain that the receiver 102 draws more current and thus more power when it is operating in its higher-current HF mode than when it is operating in its lower-current LF mode because this is true in terms of a common unit of time.

[0068] Pre-amplifier

[0069] Figure 3 A circuit diagram of a fully differential preamplifier 112 according to embodiments of the present technology is shown. Reference is made to Figure 3 The fully differential preamplifier 112 is shown to include an input differential pair 312, an output current load 322, and a current source 332. Inputs or nodes 311P, 311M (also labeled INP and INM) of the input differential pair 312 receive a signal sensed on electrodes El, E2, more specifically, a high-pass filtered version of such a signal. Input INP can also be referred to as the positive input, and input INM can also be referred to as the negative input. The fully differential preamplifier 112 can also be referred to more simply as the preamplifier 112.

[0070] In Figure 3 , a high-pass filter (HPF) 302P and a direct current (DC) blocking capacitor 309 are shown coupled between electrode El and input node 311P (also labeled INP) of the input differential pair 312. Similarly, a high-pass filter (HPF) 302M and a DC blocking capacitor 310 are shown coupled between electrode E2 and input node 311N (also labeled INM) of the input differential pair 312. The HPF 302P and HPF 302M pass signals above a cutoff frequency (which is specified by the values of capacitors 303, 304 and resistors 305, 306) and filter out signals below the cutoff frequency, including low frequency cardiac signals sensed by electrodes El, E2. According to certain embodiments, the cutoff frequency can be in the range of 200 to 500 Hz, for example, can be 250 Hz, but is not limited thereto. Capacitors 303, 304 are matched, meaning they have substantially the same capacitance value, i.e., Cl. Resistors 305, 306 are matched, meaning they have substantially the same resistance value, i.e., Rl. DC blocking capacitors 309, 310 are matched, meaning they have substantially the same capacitance value, i.e., C2. The HPF 302P, 302M also provide a reduction of electromagnetic interference (EMI), as well as complete flexibility in how electrodes El, E2 are electrically connected to the input of the receiver 102. The terminals of capacitors 309, 310 (on the electrode side) are grounded through resistors 305, 306, respectively, regardless of what electrical level electrodes El, E2 are biased at relative to the input of the receiver 102. Capacitors 303, 304 also provide AC coupling from electrodes El, E2, allowing electrodes El, E2 to be biased at any voltage relative to the receiver input.

[0071] In Figure 3In the illustrated embodiment, the input differential pair 312 includes a differential pair of N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) Mn1, Mn2 (which can also be referred to as transistors Mn1, Mn2). Each of the transistors Mn1, Mn2 includes a gate, a drain, and a source. The gate of the transistor Mn1 is coupled to one terminal of the capacitor 309, and the gate of the transistor Mn2 is coupled to one terminal of the capacitor 310. The sources of the transistors Mn1, Mn2 are connected to each other, and a current source 332 is connected between the sources of the transistors Mn1, Mn2 that are connected together and ground (or some other low voltage rail that does not require grounding). The drain of the transistor Mn1 is a negative (-) output terminal of the fully differential preamplifier 112, which is labeled OUTM (also labeled 342M). The drain of the transistor Mn2 is a positive (+) output terminal of the fully differential preamplifier 112, which is labeled OUTP (also labeled 342P). The input differential pair 212 also includes a resistor 313 connected between the gate and the drain of the transistor Mn1, and a resistor 314 connected between the gate and the drain of the transistor Mn2. The resistors 313, 314 are matched, meaning that they have substantially the same resistance value, i.e., R2. A switch 315 is connected in parallel with the resistor 313 between the gate and the drain of the transistor Mn1. Similarly, a switch 316 is connected in parallel with the resistor 314 between the gate and the drain of the transistor Mn2. When the switches 315 and 316 are selectively closed (e.g., by a controller (e.g., the controller 412) in the Figure 4 fully differential preamplifier 112, the transistors Mn1 and Mn2 become diode-connected transistors.

[0072] The output current load 322 includes a differential pair of P-channel MOSFETs Mp1, Mp2 (also referred to as transistors Mp1, Mp2). Each of the transistors Mp1, Mp2 includes a gate, a drain, and a source. The output current load 322 includes a capacitor 323 connected between the high voltage rail (VPLUS) and the gate of transistor Mp1, and another capacitor 324 connected between the high voltage rail (VPLUS) and the gate of transistor Mp2. The sources of the transistors Mn1, MN2 are connected to each other and to the high voltage rail (VPLUS). The drain of transistor Mp1 is the negative (-) output terminal of the fully differential preamplifier 112, labeled OUTM (also labeled 342M). The drain of transistor Mp2 is the positive (+) output terminal of the fully differential preamplifier 112, labeled OUTP (also labeled 342P). The capacitors 323, 324 are matched, meaning that they have substantially the same capacitance value, i.e., C3. The output current load 322 also includes a resistor 325 connected between the gate and the drain of transistor Mp1, and a resistor 326 connected between the gate and the drain of transistor Mp2. The resistors 325, 326 are matched, meaning that they have substantially the same resistance value, i.e., R3. A switch 327 is connected in parallel with the resistor 325 between the gate and the drain of transistor Mp1. Similarly, a switch 328 is connected in parallel with the resistor 326 between the gate and the drain of transistor Mp2. When the switches 327 and 328 are selectively closed (e.g., by the controller 412 in the controller 412), the transistors Mp1 and Mp2 become diode-connected transistors. The switches 315, 316, 327, and 328 are also all labeled R2 to indicate that they are all opened and closed at the same time. According to certain embodiments, each of these switches 315, 316, 327, and 328 is implemented using a respective CMOS transistor that is closed by turning on the transistor and opened by turning off the transistor, under the control of the controller 412 in the controller 412. Figure 4 Figure 4

[0073] ​​The bias points of the input terminals 311P, 311N (i.e., INP, INM) and the output terminals 342M, 342P (i.e., OUTP, OUTM) are directly related to the bias current (Ib) provided by the current source 332. When switching from one mode to another (i.e., whenever the bias current Ib changes), a reset is applied so that the preamplifier operating point is quickly set and the receiver 102 (which includes the preamplifier 112) is ready for detection. This reset can be implemented by simultaneously and temporarily closing these switches 315, 316, 327, and 328, which are also labeled R2 to indicate that they are all simultaneously opened and closed, as described above. The reset event can be applied at any time if needed, although the receiver 102 (which includes the preamplifier 112) cannot detect signals during the duration of the reset.

[0074] The input differential pair 312 (including resistors 313, 314) and the output current load 322 (including resistors 325, 326 and capacitors 323, 324) are used to provide a DC bias point for the DC blocking capacitors 309, 310 on their INP side or INM side. The resistors 313, 314 (with resistance R2) and the resistors 325, 326 (with resistance R3) are very large (e.g., at least 100 MΩ) to provide high gain. The bias current Ib provided by the current source 332 limits the current into the differential pair of transistors Mn1, Mn2 and is controlled by the MODE control signal, so the bias current Ib can be increased or decreased as needed based on the situation. The MODE control signal can be controlled by a controller (e.g., the controller 412 in the receiver 102). Figure 4

[0075] The resistors 325, 326 and capacitors 323, 324 provide a built-in offset and mismatch compensation network for the output current load 322. The DC operating point at the outputs 342P, 342M (i.e., OUTP and OUTM) is based on the electrical parameters of each transistor and the bias current Ib. The outputs 342P, 342M (i.e., OUTP and OUTM) can not be at the same voltage value because of mismatch and other non-ideal factors that can create slight differences in how much current passes on each side of the preamplifier 112. However, this is not critical when the preamplifier 112 is included in the receiver 102 because there is the buffer 122 and the AC coupling network 132 that remove the offset at the outputs of the preamplifier 112. The buffer 122 also reduces the load at the outputs 342P, 342M (i.e., OUTP and OUTM) in order to increase (and preferably maximize) the slew rate of the preamplifier 112.

[0076] Figure 3 ​The MODE control signal in 402 controls the bias current Ib generated by current source 332, which can be implemented as a current sink. The narrower the transmit pulse width or the smaller the interval between transmit pulses, the larger the bias current Ib should be. The consumed current can be adjusted precisely with the intended signal type (e.g., LF wake-up signal or HF message content signal).

[0077] Switches 307 and 308 (which are also labeled as SI and can also be referred to as SI switches) are blanking switches that can be used to blank the input of receiver 102 (i.e., to apply a zero differential voltage between inputs INP and INM) during certain events to avoid false detection of wake-up signals and / or information encoding signals by receiver 102. Examples of such events (during which the SI switches should be closed so as to blank receiver 102) include: during a pacing event when electrodes El, E2 are used for cardiac pacing (which can include discharge of a storage capacitor and output of a pacing pulse); during a transmission event when electrodes El, E2 are used to transmit one or more conducted communication signals; and during a reset event (when the S2 switches are closed). Switches 315, 316, 327, and 328 (which are also labeled as S2 and can be referred to as S2 switches) are used to quickly reset receiver 102 when the operating mode is changed from a low-current LF mode to a higher-current HF mode, or vice versa, so that receiver 102 is ready for reception. The above-mentioned switches can be controlled by a controller (e.g., 412 in 402) of the IMD (e.g., Figure 4 Figure 4

[0078] Example of an IMD

[0079] Figure 4 is a block diagram of an example IMD 402 that can include the above-described fully differential receiver 102. Figure 4 Functional elements of IMD 402 are shown substantially encapsulated in a hermetically sealed housing 410. In certain embodiments, IMD 402 is a leadless pacemaker that includes at least two leadless electrodes configured for delivery of cardiac pacing pulses, sensing of evoked and / or natural cardiac electrical signals, and unidirectional and / or bidirectional conducted communication. Alternatively, IMD 402 can be an implantable cardioverter defibrillator (ICD) (such as a non-vascular ICD (NV-ICD)) or an implantable cardiac monitor (ICM), but is not limited thereto.

[0080] ​​In the case where IMD 402 is a leadless pacemaker, its electrodes 408 (e.g., El and E2) are located within, on, or near the housing 410 for delivering pacing pulses to the muscle of a ventricle and sensing electrical activity from the muscle of a ventricle, and for conductive communication with at least one other device within or outside the body. Sealing feedthroughs 430, 431 conduct electrode signals through the housing 410. The housing 410 contains a primary cell 414 to power pacing, sensing, and communication. The housing 410 also contains circuitry 432 for sensing cardiac activity from electrodes 408, a conductive communication receiver 420 for receiving conductive communication signals from at least one other device via electrodes 408, and a pulse generator 416. The pulse generator 416 can be used to generate pacing pulses delivered via electrodes 408 and / or also to transmit conductive communication signals to at least one other device via electrodes 408. The housing 410 can also contain circuitry for monitoring device health (e.g., a battery current monitor 436 and a battery voltage monitor 438), and can contain circuitry for controlling operation in a predetermined manner.

[0081] In Figure 4 which the two electrodes shown therein labeled 408a and 408b can be the electrodes referenced Figure 1 and Figure 3 above. Such electrodes can be collectively referred to as electrodes 408, or individually as electrodes 408. Depending on the implementation, IMD 402 can also include more than two electrodes. In Figure 4 which IMD 402 is shown as including a conductive communication receiver 420 coupled to electrodes 408 and configured to receive conductive communication signals from another IMD and / or from an external device such as an external programmer. In accordance with certain embodiments of the present technology, conductive communication receiver 420 is implemented using the fully differential receiver 102 described initially above in reference to Figure 1 If IMD 402 includes more than two electrodes, a switch can be included between the electrodes and the inputs of the conductive communication receiver 420 (implemented using the fully differential receiver 102) to select which two electrodes are connected to the differential inputs of the receiver. If IMD 402 includes more than two electrodes, a switch can also be used to connect two or more electrodes together to increase the size of certain electrodes, so long as the electrode(s) connected to the positive input of the receiver are different from the electrode(s) connected to the negative input of the receiver.

[0082] In Figure 4In particular embodiments, the pulse generator 416 can be used as a transmitter to transmit conducted communication signals using the electrodes 408 (which, as noted above, can be electrodes El, E2). Depending on the particular embodiment, a communication channel pair can be used to enable the IMD 402 to communicate with another IMD or an external device, or alternatively a common communication channel can be used. Using the electrodes 408 for communication enables the IMD 402 to perform antenna-less and telemetry coil-less communication. In cases where two IMDs communicate with each other using conducted communication, such conducted communication can be referred to as implant-to-implant (i2i) conducted communication.

[0083] Still referring to Figure 4 , the IMD is shown to include a controller 412 and a pulse generator 416. The controller 412 can include, for example, a microprocessor (or equivalent control circuitry), RAM and / or ROM memory, logic and timing circuitry, state machine circuitry, and I / O circuitry, without limitation. The controller 412 can also include, for example, timing control circuitry to control the timing of conducted communication pulses as well as the timing of stimulation pulses (e.g., pacing rate, atrioventricular (AV) delay, intra-atrial conduction (A-A) delay, or intra-ventricular conduction (V-V) delay, etc.). Such timing control circuitry can also be used for the timing of refractory periods, blanking intervals, noise detection windows, evoked response windows, alert intervals, marker channel timing, etc. The controller 412 can also include other specialized circuitry and / or firmware / software components that help monitor various conditions of the patient’s heart and manage pacing therapy. The controller 412 and the pulse generator 416 can be configured to transmit event messages via the electrodes 408 in a manner that does not inadvertently cause capture of the heart. In certain embodiments, the logic detector 421 can be implemented by the controller 412 itself.

[0084] The electrodes 408 can be configured to communicate bi-directionally between multiple leadless cardiac pacemakers, co-implanted ICDs, and / or co-implanted ICMS to coordinate pacing pulse delivery, and optionally other therapies and / or diagnostic features, using messages that identify events at the single IMD that initiates the message, and the receiving IMDs react in accordance with the instructions of the message depending on the source of the message. The single IMD can be configured to issue a unique code corresponding to the type of event and the location of the transmitting IMD.

[0085] Also as Figure 4As shown, the galvanic cell 414 has a positive terminal 440 and a negative terminal 442. Current from the positive terminal 440 of the galvanic cell 414 flows through a shunt 444 to a regulator circuit 446 to produce a positive voltage source 448 suitable for powering the rest of the circuitry of the IMD 402. The shunt 444 enables the battery current monitor 436 to provide an indication of battery current draw to the controller 412, and indirectly, an indication of device health. The illustrated power source can be the galvanic cell 414.

[0086] Still referring to Figure 4 , the IMD 402 is also shown as including a temperature sensor 452. The temperature sensor 452 can be any of a variety of different types of known temperature sensors, or can be a temperature sensor developed in the future. The temperature sensor 452 can be used in a variety of ways. For example, the temperature sensor 452 can be used to detect a patient's activity level to adjust a pacing rate, i.e., for rate responsive pacing. Accordingly, the controller 412 can be configured to detect a patient's activity level based on core blood temperature measurements obtained using the temperature sensor 452.

[0087] The IMD 402 is also shown as including an accelerometer 454, which can be hermetically contained within the housing 410. The accelerometer 454 can be any of a variety of different types of known accelerometers, or can be an accelerometer developed in the future. The accelerometer 454 can be used to detect a patient's activity level to adjust a pacing rate, i.e., for rate responsive pacing. The outputs of the accelerometer 454 and the temperature sensor 452 can also be used to monitor a patient's activity level.

[0088] The IMD 402 can manage power consumption to draw limited power from the battery 414, thereby reducing device size. Each circuit in the system can be designed to avoid large peak currents. For example, cardiac pacing can be implemented by discharging an energy storage capacitor (not shown) across the pacing electrodes. Recharging of the energy storage capacitor is typically controlled by a charge pump circuit. In particular embodiments, the charge pump circuit is throttled to recharge the energy storage capacitor from the battery at a constant power.

[0089] Method

[0090] A method according to embodiments of the present technology will now be described using a high level flowchart of Figure 5 , the method being for a fully differential receiver (e.g. 102, 420) of an IMD (e.g. 402), wherein the fully differential receiver is powered by a battery (e.g. 414) of the IMD. Reference is made to Figure 5 , step 502 involves operating the fully differential receiver according to a first mode, during which a wake-up signal is monitored within a first frequency range. As described above, such a wake-up signal can comprise LF wake-up pulses (e.g.,Figure 2 Step 506 involves operating the fully differential receiver according to a second mode during which one or more message content pulses are monitored and received in a second frequency range that is higher than the first frequency range. In other words, in response to detecting the wake-up signal while the fully differential receiver is operating according to the first mode, there is a change from operating the fully differential receiver according to the first mode to operating the fully differential receiver according to the second mode. The second mode draws more current from the battery, and thus more power, than the first mode. An example of the first mode is the low current LF mode discussed above, and an example of the second mode is the higher current HF mode discussed above.

[0091] At step 508, a determination is made as to whether the period of monitoring and receiving the message content pulse(s) has ended. If the answer to the determination at step 508 is no, then flow returns to step 506. If the answer to the determination at step 508 is yes, then flow returns to step 502, and there is a change from operating the fully differential receiver according to the second mode back to operating the fully differential receiver according to the first mode, which draws less current from the battery, and thus less power, than the second mode. For example, the answer to the determination at step 508 can be yes because the message content window has ended, because a message end indicator was received, or because a timeout period has expired, but is not limited thereto. Other variations are possible and within the scope of the embodiments described herein.

[0092] It should be understood that the subject matter described herein is not limited to the constructions described in the detailed description or the drawings herein. The subject matter described herein is capable of other embodiments and of being practiced or carried out in various ways. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising" or "having" and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Further, it should be noted that the terms "based on" and "based upon" are intended to be interpreted as meaning at least partially based on, meaning that there can be one or more additional factors. For example, if a decision is based on the results of a comparison, the decision can be based on the results of the comparison in addition to one or more other factors.

[0093] Embodiments of the technology have been described above, by way of example, with reference to functional building blocks of the technology. For purposes of simplicity of the drawings, the boundary between the functional building blocks has been defined as the boundary between the functional building blocks of the technology. In reality, there can be instances where the functional building blocks overlap, where the functional building blocks co- exist on the same boundary, where the functional building blocks are combined, where the functional building blocks are split, or where the functional building blocks are some combination of these. Accordingly, although the illustrated embodiment can have limited the scope of the functional building blocks to drum up an example, other embodiments can define the scope of the functional building blocks in broader scope based on the described features.

[0094] It is to be understood that the above description is intended to be illustrative, and not restrictive. For example, the above-described embodiments (and / or aspects thereof) can be used in combination with each other. In addition, many modifications can be made to adapt a particular situation or material to the teachings of the embodiments of the technology without departing from their scope. While sizes, materials types and coatings described herein are intended to define parameters of embodiments of the technology, they are by no means limiting, but are exemplary embodiments. Many other embodiments will be apparent to those of ordinary skill in the art having the benefit of the above description. The scope of the embodiments of the technology should, therefore, be determined not with reference to the above description, but instead with reference to the appended claims, along with their full scope of equivalents. In the appended claims, the terms “including” and “in which” are used as the plain English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects. Further, the limitations of the claims are not written in means-plus-function format and are not intended to be interpreted based on 35 U.S.C. § 112(f) unless and until such claim limitations expressly use the phrase “means for” followed by structure, material, or acts followed by “to” and are expressly set in three-part form as specified in 35 U.S.C. § 112(f).

Claims

1. A fully differential receiver having a differential input pair and a differential output pair, the fully differential receiver being used in an implantable medical device (IMD) and configured to receive a conducted communication signal transmitted by another IMD or an external device, the fully differential receiver comprising: A fully differential preamplifier including a differential input pair and a differential output pair; a fully differential buffer comprising a differential input pair and a differential output pair, wherein the differential input pair of the fully differential buffer is coupled to the differential output pair of the preamplifier; a first comparator comprising a differential input pair and a first output; a second comparator comprising a differential input pair and a second output, wherein the differential input pair of the second comparator is coupled to the differential input pair of the first comparator such that the differential input pairs of the first comparator and the second comparator are coupled to each other; as well as an AC coupling network coupled between the differential output of the fully differential buffer and the differential input pair coupled together of the first comparator and the second comparator; wherein the differential input pair of the fully differential receiver comprises the differential input pair of the fully differential preamplifier; and The differential output pair of the fully differential receiver includes a first output of the first comparator and a second output of the second comparator.

2. The fully differential receiver of claim 1 , wherein: The fully differential receiver is configured to operate in a first mode and a second mode; When operating in the first mode, the fully differential receiver draws a first amount of current and monitors for a wake-up signal within a first frequency range; and When operating in the second mode, the fully differential receiver draws a second amount of current higher than the first amount of current and is configured to receive one or more message content pulses within a second frequency range higher than the first frequency range.

3. The fully differential receiver of claim 2 , wherein: The fully differential receiver is configured to operate in the first mode when the fully differential preamplifier, the fully differential buffer, the first comparator, and the second comparator are provided with corresponding first bias currents; and The fully differential receiver is configured to operate in the second mode when the fully differential preamplifier, the fully differential buffer, the first comparator, and the second comparator are provided with respective second bias currents greater than the respective first bias currents.

4. The fully differential receiver according to any one of claims 1 to 3, wherein: The differential input pair of each of the first comparator and the second comparator includes a respective non-inverting (+) input and a respective inverting (-) input; the first comparator being configured to generate an output pulse at the first output when a voltage potential difference between a non-inverting (+) input and an inverting (-) input of the first comparator exceeds a first offset and is positive with respect to a common mode voltage of the fully differential receiver; and The second comparator is configured to generate an output pulse at the second output when a voltage potential difference between a non-inverting (+) input and an inverting (−) input of the second comparator exceeds a second offset and is negative with respect to the common mode voltage.

5. The fully differential receiver according to any one of claims 1 to 3, wherein: The pair of inputs of the fully differential receiver are coupled to the pair of electrodes of the IMD; and The electrode pair is used to sense conducted communication signals sent by another IMD or an external device.

6. The fully differential receiver according to any one of claims 1 to 3, wherein: The differential output pair of the fully differential buffer includes a non-inverting (+) output and an inverting (-) output; The differential input pair of each of the first comparator and the second comparator includes a respective non-inverting (+) input and a respective inverting (-) input; The non-inverting (+) input of the first comparator is coupled to the inverting (-) input of the second comparator; and The inverting (-) input of the first comparator is coupled to the non-inverting (+) input of the second comparator.

7. The fully differential receiver according to claim 6, wherein: The AC coupling network includes: a first capacitor coupled between a non-inverting (+) output of the fully differential buffer and a non-inverting (+) input of the first comparator, and coupled between the non-inverting (+) output of the fully differential buffer and an inverting (-) input of the second comparator; a second capacitor coupled between the inverting (-) output of the fully differential buffer and the inverting (-) input of the first comparator, and between the inverting (-) output of the fully differential buffer and the non-inverting (+) input of the second comparator; a first resistor coupled between a common mode voltage Vcm node and a non-inverting (+) input of the first comparator, and coupled between the common mode voltage Vcm node and an inverting (-) input of the second comparator; and A second resistor is coupled between the common mode voltage Vcm node and the inverting (−) input of the first comparator, and is coupled between the common mode voltage Vcm node and the non-inverting (+) input of the second comparator.

8. The fully differential receiver according to claim 7, wherein: The AC coupling network: configured to remove any DC offset that may be caused by the fully differential preamplifier and the fully differential buffer; and The output DC bias point of the AC coupling network is the common mode voltage at the vcm node.

9. The fully differential receiver according to any one of claims 1 to 3, wherein: The differential input pair of the fully differential preamplifier includes a non-inverting (+) input and an inverting (-) input; a first high-pass filter coupled to the non-inverting (+) input of the fully differential preamplifier; A second high pass filter is coupled to the inverting (-) input of the fully differential preamplifier; and The first high pass filter and the second high pass filter are configured to filter out signals indicative of cardiac electrical activity sensed by electrodes coupled to the differential input pair of the fully differential preamplifier.

10. The fully differential receiver according to any one of claims 1 to 3, wherein: The differential input pair of the fully differential preamplifier includes a non-inverting (+) input and an inverting (-) input; and The fully differential preamplifier includes a switch pair that, when selectively closed, enables a zero voltage potential difference between a non-inverting (+) input and an inverting (-) input of the fully differential preamplifier, thereby enabling a zero voltage potential difference between an input pair of the fully differential receiver.

11. The fully differential receiver according to any one of claims 1 to 3, wherein: The fully differential receiver is configured to operate in a first mode and a second mode; and The fully differential preamplifier includes a switch that is selectively closed for a period of time to reset the fully differential receiver whenever changing from the first mode to the second mode or from the second mode to the first mode.

12. A fully differential receiver for use in an implantable medical device (IMD) and configured to receive a conducted communication signal transmitted by another IMD or an external device, the fully differential receiver comprising: a first comparator comprising a differential input pair and a first output; a second comparator comprising a differential input pair and a second output, wherein the differential input pair of the second comparator is coupled to the differential input pair of the first comparator such that the differential input pairs of the first and second comparators are coupled to each other; and The differential input pair of each of the first comparator and the second comparator includes a respective non-inverting (+) input and a respective inverting (-) input; The non-inverting (+) input of the first comparator is coupled to the inverting (-) input of the second comparator; as well as The inverting (-) input of the first comparator is coupled to the non-inverting (+) input of the second comparator.

13. The fully differential receiver of claim 12, wherein: the first comparator being configured to generate an output pulse at the first output when a voltage potential difference between a non-inverting (+) input and an inverting (-) input of the first comparator exceeds a first offset and is positive with respect to a common mode voltage of the fully differential receiver; and The second comparator is configured to generate an output pulse at the second output when a voltage potential difference between a non-inverting (+) input and an inverting (-) input of the second comparator exceeds a second offset and is negative with respect to a common mode voltage of the fully differential receiver.

14. The fully differential receiver according to any one of claims 12 or 13, wherein: The fully differential receiver has a differential input pair and a differential output pair, the fully differential receiver being used in an implantable medical device (IMD) and configured to receive a conducted communication signal transmitted by another IMD or an external device, and further comprising: a fully differential preamplifier including a differential input pair and a differential output pair; and a fully differential buffer comprising a differential input pair and a differential output pair, wherein the differential input pair of the fully differential buffer is coupled to the differential output pair of the preamplifier; wherein the differential input pair of the fully differential receiver comprises the differential input pair of the fully differential preamplifier; and The differential output pair of the fully differential receiver includes a first output of the first comparator and a second output of the second comparator.

15. The fully differential receiver of claim 14 , further comprising: an AC coupling network coupled between the differential output of the fully differential buffer and the differential input pair coupled together of the first comparator and the second comparator; The AC coupling network is configured to remove any DC offset that may be caused by the fully differential preamplifier and the fully differential buffer.

16. The fully differential receiver according to any one of claims 12 or 13, wherein: The fully differential receiver is configured to operate in a first mode and a second mode; When operating in the first mode, the fully differential receiver draws a first amount of current and monitors for a wake-up signal within a first frequency range; and When operating in the second mode, the fully differential receiver draws a second amount of current higher than the first amount of current and monitors for one or more message content pulses within a second frequency range higher than the first frequency range.

17. An implantable medical device (IMD) configured to communicate with at least one of another IMD or an external device using conducted communication signals, the IMD comprising: at least two electrodes; The fully differential receiver according to any one of claims 1 or 12, wherein the input pair of the fully differential receiver is coupled to an electrode pair of the at least two electrodes; a logic detector having an input pair and an output pair, the input pair of the logic detector coupled to the output pair of the fully differential receiver; a controller comprising an input coupled to an output of the logic detector, wherein the controller is configured to decode pulses received from the logic detector; as well as A battery is configured to power components of the IMD, including the fully differential receiver, the logic detector, and the controller.

18. The IMD of claim 17, wherein: The fully differential receiver is configured to operate in a first mode and a second mode; When operating in the first mode, the fully differential receiver draws a first amount of current from the battery and monitors for a wake-up signal within a first frequency range; and When operating in the second mode, the fully differential receiver draws a second amount of current from the battery that is higher than the first amount of current and is configured to receive one or more message content pulses within a second frequency range that is higher than the first frequency range.

19. The IMD of any one of claims 17 or 18, wherein The IMD fully differential receiver includes: A fully differential preamplifier including a differential input pair and a differential output pair; a fully differential buffer comprising a differential input pair and a differential output pair, wherein the differential input pair of the fully differential buffer is coupled to the differential output pair of the preamplifier; a first comparator comprising a differential input pair and a first output; a second comparator comprising a differential input pair and a second output, wherein the differential input pair of the second comparator is coupled to the differential input pair of the first comparator such that the differential input pairs of the first and second comparators are coupled to each other; and an AC coupling network coupled between the differential output of the fully differential buffer and the differential input pair coupled together of the first comparator and the second comparator; wherein the differential input pair of the fully differential receiver comprises the differential input pair of the fully differential preamplifier; and The differential output pair of the fully differential receiver includes a first output of the first comparator and a second output of the second comparator.

20. The IMD of claim 19, wherein: The fully differential receiver is configured to operate in a first mode when the fully differential preamplifier, the fully differential buffer, the first comparator, and the second comparator are provided with corresponding first bias currents; and The fully differential receiver is configured to operate in a second mode when the fully differential preamplifier, the fully differential buffer, the first comparator, and the second comparator are provided with respective second bias currents greater than the respective first bias currents.

21. A method for using a fully differential receiver according to any one of claims 1 or 12 in an implantable medical device (IMD), wherein the fully differential receiver is powered by a battery of the IMD, the method comprising: operating the fully differential receiver according to a first mode during which a wake-up signal is monitored within a first frequency range; in response to receiving the wake-up signal while the fully differential receiver is operating in the first mode, changing from operating the fully differential receiver according to the first mode to operating the fully differential receiver according to a second mode during which one or more message content pulses are received within a second frequency range; as well as changing from operating the fully differential receiver according to the second mode back to operating the fully differential receiver according to the first mode; wherein the second frequency range is higher than the first frequency range; and Compared with the first mode, the second mode draws more current from the battery, thereby drawing more power.

22. The method of claim 21, wherein changing from operating the fully differential receiver according to the second mode back to operating the fully differential receiver according to the first mode occurs at the end of a message content window.

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