An FPGA-based flow table processing method, device, equipment, and storage medium

Abstract

The present invention discloses a flow table processing method, apparatus, device and storage medium based on FPGA. Executed by a field programmable gate array (FPGA) device, the method includes: in response to an Ethernet packet input through an external interface, determining a lookup data packet and a new data packet in the Ethernet packet; based on a preset hash algorithm, performing a flow table update operation and a flow table creation operation in the FPGA storage space according to the five-tuple information in the lookup data packet and the new data packet; after detecting that both the lookup data packet and the new data packet in the Ethernet packet have been processed, integrating and outputting the Ethernet packet. The technical solution of the present invention can, based on the FPGA device, achieve more comprehensive and effective flow table management and improve the processing efficiency of Ethernet packets.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular, to a flow table processing method, apparatus, device, and storage medium based on FPGA. Background Art

[0002] Ethernet packets are transmitted in units of data packets. Performing flow table management on the data packets in network packets can effectively improve the transmission efficiency of network data packets.

[0003] With the continuous development of communication technologies, how to perform comprehensive and effective flow table management based on FPGA devices and improve the processing efficiency of data packets in Ethernet packets is an urgent problem to be solved at present. Summary of the Invention

[0004] The present invention provides a flow table processing method, apparatus, device, and storage medium based on FPGA to achieve more comprehensive and effective flow table management and improve the processing efficiency of Ethernet packets.

[0005] According to one aspect of the present invention, there is provided a flow table processing method based on FPGA, which is executed by a field programmable gate array (FPGA) device. The method includes:

[0006] In response to an Ethernet packet input through an external interface, determining a lookup data packet and a new data packet in the Ethernet packet;

[0007] Based on a preset hash algorithm, performing a flow table update operation and a flow table creation operation in the storage space of the FPGA according to the five-tuple information in the lookup data packet and the new data packet;

[0008] After detecting that both the lookup data packet and the new data packet in the Ethernet packet have been processed, integrating and outputting the Ethernet packet.

[0009] Optionally, based on a preset hash algorithm, performing a flow table update operation in the storage space of the FPGA according to the five-tuple information of the lookup data packet includes:

[0010] Based on a preset hash algorithm, performing a hash calculation on the five-tuple information of the lookup data packet, and determining whether the lookup data packet exists in the storage space of the FPGA according to the calculation result and a pre-stored hash table;

[0011] If not, determining the flow table ID of the lookup data packet and performing an update operation on the flow table in the storage space of the FPGA.

[0012] The above technical solution calculates the hash of the five-tuple information of the lookup packet, and then determines whether the lookup packet already exists in the storage space of the FPGA according to the hash calculation result and the pre-stored hash table, which can quickly and accurately determine whether the lookup packet has been stored. When it is determined that the packet does not exist, an update operation is performed based on the flow table ID, enabling timely update of the flow table and realizing real-time management of the flow table.

[0013] Optionally, based on a preset hash algorithm, calculate the hash of the five-tuple information of the lookup packet, and determine whether the lookup packet exists in the storage space of the FPGA according to the calculation result and the pre-stored hash table, including:

[0014] Based on a preset first hash algorithm and second hash algorithm, calculate the hash of the five-tuple information of the lookup packet respectively to determine a first hash value and a second hash value;

[0015] According to the first hash value, perform a lookup in the pre-stored hash table to determine the corresponding pre-stored hash value, and determine whether the pre-stored hash value is consistent with the second hash value;

[0016] If not, it is determined that the lookup packet does not exist in the storage space of the FPGA.

[0017] The above technical solution calculates the hash of the five-tuple information of the lookup packet through two hash algorithms respectively, and then determines whether the lookup packet already exists in the storage space of the FPGA according to the relationship between the first hash value and the second hash value, providing an implementable way to use the hash algorithm to confirm whether the lookup packet has been stored, which helps to improve the efficiency of subsequent flow table management operations.

[0018] Optionally, after determining whether the pre-stored hash value is consistent with the second hash value, it further includes:

[0019] If the pre-stored hash value is consistent with the second hash value, perform a lookup in the pre-stored hash table according to the first hash value to determine the first flow table ID, and use the first flow table ID as the address to perform a lookup in the storage space of the FPGA to determine the corresponding pre-stored five-tuple information;

[0020] Determine whether the pre-stored five-tuple information is consistent with the five-tuple information of the lookup packet. If not, it is determined that the lookup packet does not exist in the storage space of the FPGA.

[0021] In the above technical solution, when it is determined that the pre-stored hash value is the same as the second hash value, the first flow table ID for the lookup data packet is further determined, and the pre-stored five-tuple information is determined, so that the five-tuple information pre-stored at the flow table ID specified by the lookup data packet can be accurately determined. By judging the consistency between the pre-stored five-tuple information and the five-tuple information of the lookup data packet, it can be further and carefully determined whether the lookup data packet already exists in the storage space of the FPGA, ensuring the accuracy of packet processing.

[0022] Optionally, based on a preset hash algorithm, a flow table creation operation is performed in the storage space of the FPGA according to the five-tuple information of the newly created data packet, including:

[0023] Apply to the ID management module and determine the second flow table ID;

[0024] Based on a preset first hash algorithm and second hash algorithm, perform hash calculation on the five-tuple information corresponding to the newly created data packet to determine the third hash value and the fourth hash value;

[0025] Update the pre-stored hash table according to the third hash value, the fourth hash value, and the second flow table ID, and create a flow table with the second flow table ID in the storage space of the FPGA.

[0026] In the above technical solution, by applying to the ID management module and determining the second flow table ID, and further based on two hash algorithms, the third hash value and the fourth hash value of the five-tuple information of the newly created data packet are determined, so that the pre-stored hash table can be updated in a timely manner, and a flow table is created at the newly applied second flow table ID to complete the flow table creation operation and realize the real-time management of the flow table.

[0027] Optionally, updating the pre-stored hash table according to the third hash value, the fourth hash value, and the second flow table ID includes:

[0028] Determine the target position corresponding to the third hash value in the pre-stored hash table;

[0029] Store the second flow table ID and the fourth hash value at the target position to realize the update of the pre-stored hash table.

[0030] In the above technical solution, by using the third hash value as the storage address and then storing the second flow table ID and the fourth hash value at the position corresponding to the storage address, the update of the pre-stored hash table is realized, further refining the update process of the pre-stored hash table, which can update the pre-stored hash table in a timely and effective manner, and is helpful for the subsequent FPGA device to quickly judge whether the data packet to be looked up has been stored by using the pre-stored hash table.

[0031] Optionally, during the process of performing flow table update operations and flow table creation operations, record the flow table creation time and flow table update time of each flow table;

[0032] If it is detected that the time interval between the flow table creation time and the flow table update time of the target flow table is greater than the preset aging time, then delete the target flow table in the storage space of the FPGA, and feedback to the ID management module, which is used to instruct the ID management module to recycle the flow table ID corresponding to the target flow table.

[0033] By recording the creation time and update time of each flow table in the storage space of the FPGA, the above technical solution can perform aging operations in a timely manner when a long time interval is detected, and recycle the flow table IDs of the aging flow tables, providing an implementable method for aging flow table management in flow table management, and improving the comprehensiveness of flow table management based on the FPGA.

[0034] According to another aspect of the present invention, there is provided a flow table processing device based on an FPGA, which is configured in a field programmable gate array (FPGA) device, and includes:

[0035] A determination module, configured to determine the lookup data packet and the new creation data packet in the Ethernet packet in response to the Ethernet packet input through the external interface;

[0036] A management module, configured to perform flow table update operations and flow table creation operations in the storage space of the FPGA based on a preset hash algorithm according to the five-tuple information in the lookup data packet and the new creation data packet;

[0037] An output module, configured to perform integrated output on the Ethernet packet after detecting that both the lookup data packet and the new creation data packet in the Ethernet packet have been processed.

[0038] According to another aspect of the present invention, there is provided an electronic device, which includes:

[0039] At least one processor; and

[0040] A memory communicatively connected to the at least one processor; wherein,

[0041] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the flow table processing method based on the FPGA according to any embodiment of the present invention.

[0042] According to another aspect of the present invention, there is provided a computer-readable storage medium storing computer instructions for causing a processor to implement the FPGA-based flow table processing method according to any embodiment of the present invention when executed.

[0043] The technical solution of the embodiment of the present invention, in response to an Ethernet packet input through an external interface, determines a lookup packet and a new packet in the Ethernet packet; based on a preset hash algorithm, according to the five-tuple information in the lookup packet and the new packet, performs a flow table update operation and a flow table creation operation in the FPGA storage space; after detecting that both the lookup packet and the new packet in the Ethernet packet have been processed, integrates and outputs the Ethernet packet. By performing packet processing and flow table management only based on FPGA devices, it can effectively avoid the resource consumption of the CPU and improve the overall working efficiency of the computer; by performing a flow table update operation and a flow table creation operation based on the hash algorithm, it can effectively utilize the pre-stored hash table to implement a fast and effective flow table update operation and a flow table creation operation, perform more comprehensive and effective flow table management, and improve the processing efficiency of Ethernet packets.

[0044] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0046] Figure 1 is a flowchart of an FPGA-based flow table processing method according to Embodiment 1 of the present invention;

[0047] Figure 2 is a flowchart of an FPGA-based flow table processing method according to Embodiment 2 of the present invention;

[0048] Figure 3 is a flowchart of an FPGA-based flow table processing method according to Embodiment 3 of the present invention;

[0049] Figure 4 is a schematic structural diagram of an FPGA-based flow table processing device according to Embodiment 4 of the present invention;

[0050] Figure 5It is a schematic structural diagram of an electronic device for implementing the FPGA-based flow table processing method according to an embodiment of the present invention. Detailed implementation manners

[0051] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0052] It should be noted that the terms "first", "second", "target", "candidate", "alternate", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such used data may be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0053] Embodiment 1

[0054] Figure 1 It is a flowchart of an FPGA-based flow table processing method according to Embodiment 1 of the present invention. This embodiment is applicable to the situation where an FPGA is used to manage flow tables for data packets in Ethernet packets and output the packets. This method can be executed by an FPGA-based flow table processing device, which can be implemented in the form of hardware and / or software. The FPGA-based flow table processing device can be configured in an electronic device and executed by a field programmable gate array (FPGA) device. The FPGA device can be a flow table management component implemented using an FPGA. As Figure 1 shown, the FPGA-based flow table processing method includes:

[0055] S101. In response to an Ethernet packet input through an external interface, determine a lookup data packet and a new data packet in the Ethernet packet.

[0056] Among them, the external interface can be a physical interface pre-configured outside the FPGA (Field Programmable Gate Array) device. Ethernet packets are transmitted in units of data packets. The Ethernet packet can contain a search data packet and a newly created data packet. The search data packet refers to the target performing a search operation to determine whether there is already a data packet in the storage space of the FPGA. The newly created data packet refers to the data packet that the target newly creates in the flow table of the FPGA storage space.

[0057] Optionally, the FPGA device can obtain the input Ethernet packet in real time through the external physical interface. If it is detected through the external interface that an Ethernet packet has been received, it is determined that an Ethernet packet has been received through the external interface.

[0058] Optionally, after detecting the Ethernet packet received through the external interface, in response to the Ethernet packet received through the external interface, the Ethernet packet can be parsed, and according to the parsing result, the data packets in the Ethernet packet can be classified into search data packets and newly created data packets; alternatively, the Ethernet packet can be directly input into a pre-trained model to obtain the classification result of the search data packets and newly created data packets in the Ethernet packet, so as to determine the search data packets and newly created data packets from the data packets in the Ethernet packet.

[0059] It should be noted that the search data packets and newly created data packets in the originally obtained Ethernet packet are mixed together, and the processing performance of the newly created data packet is low, which restricts the processing performance of the search data packet. Therefore, the data packets are first distinguished, and the search data packets and newly created data packets are processed independently, so as to effectively improve the processing efficiency of the data packets.

[0060] S102: Based on a preset hash algorithm, perform a flow table update operation and a flow table creation operation in the storage space of the FPGA according to the five-tuple information in the search data packet and the newly created data packet.

[0061] Among them, the Hash algorithm refers to a hashing algorithm that can map an input of any length into an output of a fixed length through a hashing algorithm. The Hash algorithm can be, for example, the division hashing algorithm, the multiplication hashing algorithm, and the Fibonacci hashing method, etc. The five-tuple information refers to the source IP address (SIP), destination IP address (DIP), source port (S-port), destination port (D-port), and protocol number of the data packet. The storage space of the FPGA refers to the space of the internal RAM (Random Access Memory) of the FPGA, that is, the memory space. The flow table update operation refers to the operation of updating the existing flow table in the storage space of the FPGA. The flow table creation operation refers to the operation of creating a new flow table in the storage space of the FPGA.

[0062] Optionally, based on a preset Ethernet packet format, the Ethernet packet can be parsed, and according to the parsing result, the five-tuple information of each data packet can be determined.

[0063] Optionally, based on a preset Hash algorithm, the five-tuple information of the lookup data packet can be processed, and according to the processing result, a flow table update operation can be performed in the storage space of the FPGA; and based on a preset Hash algorithm, the five-tuple information of the newly created data packet can be processed, and according to the processing result, a flow table creation operation can be performed in the storage space of the FPGA.

[0064] Optionally, if the number of lookup data packets is at least two, then based on the feature that the FPGA can perform parallel multi-way lookups, concurrent lookups can be performed on at least two lookup data packets. Specifically, for each lookup data packet, a lookup operation is performed to determine whether the lookup data packet already exists in the storage space of the FPGA. If not, a flow table creation operation is performed, that is, a flow table update operation is executed.

[0065] Optionally, if the number of newly created data packets is at least two, then based on a preset sorting rule, the creation order of the candidate newly created data packets is determined, and according to the creation order, the target newly created data packet is determined; during the process of performing the creation operation of the target newly created data packet, a locking operation is performed, that is, the creation operations of other candidate data packets except the target newly created packet are not executed; when it is detected that the creation of the target new flow table is completed, according to the creation order, a new target new flow table is determined and a creation operation is performed on the new target new flow table. Among them, the candidate data packets refer to all the data packets in the Ethernet packet.

[0066] Optionally, based on a preset hash algorithm, perform a flow table creation operation in the storage space of the FPGA according to the five-tuple information of the newly created data packet, including: applying to the ID management module and determining a second flow table ID; performing hash calculations on the five-tuple information corresponding to the newly created data packet based on the preset first hash algorithm and second hash algorithm to determine a third hash value and a fourth hash value; updating the pre-stored hash table according to the third hash value, the fourth hash value, and the second flow table ID, and creating a flow table with the second flow table ID in the storage space of the FPGA.

[0067] Among them, the ID (Identity document, unique encoding) management module refers to a preset flow table ID management module for operations such as consumption and recycling of flow table IDs. The second flow table ID is a new flow table ID applied to the ID management module. The first hash algorithm and the second hash algorithm are different preset hash algorithms.

[0068] Optionally, the FPGA device can send a flow table ID application request to the ID management module according to the relevant attribute information of the newly created data packet. The ID management module can use the pre-stored flow table ID without stored information as the second flow table ID and send it to the FPGA device, so that the FPGA device determines the successfully applied second flow table ID.

[0069] Optionally, the hash calculation can be performed on the five-tuple information corresponding to the newly created data packet based on the preset first hash algorithm to determine the third hash value, and the hash calculation can be performed on the five-tuple information corresponding to the newly created data packet based on the preset second hash algorithm to determine the fourth hash value.

[0070] Optionally, based on a preset rule, store the fourth hash value and the second flow table ID at the position corresponding to the third hash value in the pre-stored hash table to update the pre-stored hash table, and create a flow table with the second flow table ID in the storage space of the FPGA, and store the five-tuple information of the newly created data packet in the flow table corresponding to the second flow table ID.

[0071] The above technical solution applies to the ID management module and determines the second flow table ID, and further determines the third hash value and the fourth hash value of the five-tuple information of the newly created data packet based on two hash algorithms, so that the pre-stored hash table can be updated in a timely manner, and a flow table is created at the newly applied second flow table ID to complete the flow table creation operation and realize the real-time management of the flow table.

[0072] Optionally, update the pre-stored hash table according to the third hash value, the fourth hash value, and the second flow table ID, including: determining the target position corresponding to the third hash value in the pre-stored hash table; storing the second flow table ID and the fourth hash value at the target position to update the pre-stored hash table.

[0073] Wherein, the target position refers to the hash table position corresponding to the third hash value as the key value in the pre-stored hash table.

[0074] Exemplarily, the third hash value can be used to read the pre-stored hash table, and the position of the third hash value in the pre-stored hash table is used as the target position, that is, the storage address in the pre-stored hash table. Then, the second flow table ID and the fourth hash value are stored in the target position corresponding to the storage address, so as to update the pre-stored hash table.

[0075] The above technical solution updates the pre-stored hash table by using the third hash value as the storage address and then storing the second flow table ID and the fourth hash value at the position corresponding to the storage address, further refining the update process of the pre-stored hash table, and can update the pre-stored hash table in a timely and effective manner, which helps the subsequent FPGA device to quickly determine whether the data packet has been stored by using the pre-stored hash table when looking up the data packet.

[0076] S103. After detecting that both the lookup data packet and the new data packet in the Ethernet packet have been processed, integrate and output the Ethernet packet.

[0077] Optionally, the FPGA device can record the generated communication information during the process of performing the flow table update operation and the flow table creation operation, and finally integrate the Ethernet packet and the generated communication information and output them based on a preset output method. Among them, the communication information can include: the forward and reverse bytes of the flow table, the data packet count statistics, and the ingress port information, etc.

[0078] The technical solution of the embodiment of the present invention responds to the Ethernet packet input through the external interface, determines the lookup data packet and the new data packet in the Ethernet packet; based on a preset hash algorithm, performs a flow table update operation and a flow table creation operation in the FPGA storage space according to the five-tuple information in the lookup data packet and the new data packet; after detecting that both the lookup data packet and the new data packet in the Ethernet packet have been processed, integrate and output the Ethernet packet. By only performing packet processing and flow table management based on the FPGA device, the resource consumption of the CPU can be effectively avoided, and the overall working efficiency of the computer is improved; by performing the flow table update operation and the flow table creation operation based on the hash algorithm, the pre-stored hash table can be effectively utilized to implement a fast and effective flow table update operation and a flow table creation operation, perform more comprehensive and effective flow table management, and improve the processing efficiency of the Ethernet packet.

[0079] Optionally, the FPGA device can also perform aging management on the flow tables in the storage space in real time according to the communication information. Specifically, during the process of performing flow table update operations and flow table creation operations, the flow table creation time and the flow table update time of each flow table can be recorded; if it is detected that the time interval between the flow table creation time and the flow table update time of the target flow table is greater than the preset aging time, the target flow table is deleted from the storage space of the FPGA and feedback is sent to the ID management module to indicate that the ID management module reclaims the flow table ID corresponding to the target flow table.

[0080] Among them, the flow table creation time refers to the time when the flow table creation is completed by executing the flow table creation operation. The flow table update time refers to the time when the flow table update is completed by executing the flow table update operation. The aging time refers to the preset time indicating that the flow table has aged and needs to be deleted. The target flow table refers to the flow table in the storage space of the FPGA that satisfies the condition that the time interval between the flow table creation time and the flow table update time is greater than the preset aging time. One flow table ID corresponds to one flow table.

[0081] Optionally, the aging time can be configured based on the port or protocol to which the Ethernet packet belongs. For example, when the Ethernet packet belongs to a TCP packet, the aging time can be set to 60s, and when the Ethernet packet belongs to a UDP packet, the aging time can be set to 80s.

[0082] Through the above technical solution, by recording the creation time and update time of each flow table in the storage space of the FPGA, when a long time interval is detected, the aging operation can be performed in a timely manner, and the flow table ID of the aging flow table can be reclaimed, providing an implementable method for aging flow table management in flow table management and improving the comprehensiveness of flow table management based on the FPGA.

[0083] Embodiment 2

[0084] Figure 2 FIG. is a flowchart of a flow table processing method based on an FPGA according to Embodiment 2 of the present invention. On the basis of the above technical solutions, this embodiment has been optimized and improved.

[0085] Furthermore, "performing a flow table update operation in the storage space of the FPGA according to the five-tuple information of the lookup packet based on a preset hash algorithm" is refined to "performing a hash calculation on the five-tuple information of the lookup packet based on a preset hash algorithm, and determining whether the lookup packet exists in the storage space of the FPGA according to the calculation result and the pre-stored hash table; if not, determining the first flow table ID of the lookup packet and performing an update operation on the flow table corresponding to the flow table ID in the storage space" to improve the method of performing a flow table update operation in the storage space of the FPGA.

[0086] Further, the step of "performing a hash calculation on the five-tuple information of the lookup data packet based on a preset hash algorithm, and determining whether the lookup data packet exists in the storage space of the FPGA according to the calculation result and the pre-stored hash table" is refined to "performing hash calculations on the five-tuple information of the lookup data packet based on a preset first hash algorithm and a second hash algorithm respectively to determine a first hash value and a second hash value; performing a lookup in the pre-stored hash table according to the first hash value to determine the corresponding pre-stored hash value, and determining whether the pre-stored hash value is the same as the second hash value; if not, determining that the lookup data packet does not exist in the storage space of the FPGA" to improve the specific implementation manner of determining whether the lookup data packet exists in the storage space of the FPGA.

[0087] Further, the steps after "determining whether the pre-stored hash value is the same as the second hash value" are refined to "if the pre-stored hash value is the same as the second hash value, performing a lookup in the pre-stored hash table according to the first hash value to determine a first flow table ID, and performing a lookup in the storage space of the FPGA with the first flow table ID as the address to determine the corresponding pre-stored five-tuple information; determining whether the pre-stored five-tuple information is the same as the five-tuple information of the lookup data packet, and if not, determining that the lookup data packet does not exist in the storage space of the FPGA." to improve the specific implementation manner of determining whether the lookup data packet exists in the storage space of the FPGA when the pre-stored hash value is the same as the second hash value.

[0088] As Figure 2 shown, the method includes the following specific steps:

[0089] S201. In response to an Ethernet packet input through an external interface, determine the lookup data packet and the newly created data packet in the Ethernet packet.

[0090] S202. Based on a preset hash algorithm, perform a hash calculation on the five-tuple information of the lookup data packet, and determine whether the lookup data packet exists in the storage space of the FPGA according to the calculation result and the pre-stored hash table.

[0091] Among them, the calculation result may include the hash value obtained by performing a hash calculation on the five-tuple information of the lookup data packet through the hash algorithm. The pre-stored hash table refers to a pre-stored hash table with the hash value determined by the first hash algorithm as the key, and the hash value determined by the second hash algorithm and the second flow table ID as the value.

[0092] Optionally, based on a preset hash algorithm, perform a hash calculation on the five-tuple information of the lookup data packet, and determine whether the lookup data packet exists in the storage space of the FPGA according to the calculation result and the pre-stored hash table, including: performing a hash calculation on the five-tuple information of the lookup data packet respectively based on the preset first hash algorithm and the second hash algorithm to determine a first hash value and a second hash value; performing a lookup in the pre-stored hash table according to the first hash value to determine the corresponding pre-stored hash value, and determining whether the pre-stored hash value is consistent with the second hash value; if not, it is determined that the lookup data packet does not exist in the storage space of the FPGA.

[0093] It should be noted that if the pre-stored hash value is inconsistent with the second hash value, it can be directly determined that the lookup data packet does not exist in the storage space of the FPGA. At this time, it is not necessary to further determine whether the five-tuple information corresponding to the lookup data packet is the same, avoiding resource waste.

[0094] The above technical solution performs a hash calculation on the five-tuple information of the lookup data packet respectively through two hash algorithms, and thus determines whether the lookup data packet already exists in the storage space of the FPGA according to the relationship between the first hash value and the second hash value, providing an implementable way to confirm whether the lookup data packet has been stored using the hash algorithm, which helps to improve the efficiency of subsequent flow table management operations.

[0095] Optionally, after determining whether the pre-stored hash value is consistent with the second hash value, it further includes: if the pre-stored hash value is consistent with the second hash value, performing a lookup in the pre-stored hash table according to the first hash value to determine a first flow table ID, and performing a lookup in the storage space of the FPGA with the first flow table ID as the address to determine the corresponding pre-stored five-tuple information; determining whether the pre-stored five-tuple information is consistent with the five-tuple information of the lookup data packet, and if not, it is determined that the lookup data packet does not exist in the storage space of the FPGA.

[0096] Exemplarily, if the pre-stored hash value is consistent with the second hash value, it can be initially considered that the first flow table ID and the currently looked-up data stream may be the same flow. To ensure accuracy, some five-tuple information stored during the creation of the internal RAM of the FPGA can be further obtained with the first flow table ID as the address, that is, the corresponding pre-stored five-tuple information is determined.

[0097] Optionally, if the pre-stored five-tuple information is consistent with the five-tuple information of the lookup data packet, it can be considered that the lookup data packet is the same flow, that is, the lookup data packet already exists in the storage space of the FPGA. At this time, a statistical accumulation operation can be performed to facilitate the generation of subsequent communication information.

[0098] Optionally, if the pre-stored five-tuple information is inconsistent with the five-tuple information of the lookup data packet, it can be determined that the lookup data packet does not exist in the storage space of the FPGA.

[0099] It should be noted that the flow table update operation and the flow table creation operation in the embodiments of the present invention can be concurrently performed simultaneously based on the characteristics of the FPGA's parallel multi-channel processing, thereby improving the packet processing efficiency of the FPGA device.

[0100] Through the above technical solution, when it is determined that the pre-stored hash value is the same as the second hash value, the first flow table ID for searching for the packet is further determined, and the pre-stored five-tuple information is determined, so that the five-tuple information pre-stored at the specified flow table ID for searching for the packet can be accurately determined. By judging the consistency between the pre-stored five-tuple information and the five-tuple information of the searching packet, it can be further and carefully determined whether the searching packet already exists in the storage space of the FPGA, ensuring the accuracy of packet processing.

[0101] S203. If not, determine the flow table ID corresponding to the searching packet, and perform an update operation on the flow table in the storage space of the FPGA.

[0102] It should be noted that the flow table ID corresponding to the searching packet may be the first flow table ID that has stored the relevant information of the old searching packet, or may be the second flow table ID applied to the ID management module when there is no storage of the old searching packet.

[0103] Optionally, if the searching packet does not exist in the storage space of the FPGA, the five-tuple information of the searching packet can be hashed based on the first hash algorithm, and a search is performed in the pre-stored hash table according to the determined first hash value to determine whether the first flow table ID is stored in the hash table. If so, determine that the first flow table ID is the flow table ID corresponding to the searching packet, determine the second hash value corresponding to the five-tuple information of the searching packet according to the second hash algorithm, and update the determined second hash value and the first flow table ID to the position corresponding to the first flow table ID in the storage space of the FPGA, that is, update the second hash value stored at the storage position corresponding to the first flow table ID; if the first flow table ID is not stored in the hash table, it means that the relevant information of the old searching packet is not stored under the first flow table ID. At this time, the new searching packet determined by the Ethernet packet can be used as a newly created packet, apply for the second flow table ID as the flow table ID corresponding to the searching packet, and perform a flow table creation operation to implement the update operation on the flow table in the storage space of the FPGA.

[0104] S204. Based on a preset hash algorithm, perform a flow table creation operation in the storage space of the FPGA according to the five-tuple information of the newly created packet.

[0105] S205. After detecting that both the searching packet and the newly created packet in the Ethernet packet have been processed, perform an integrated output on the Ethernet packet.

[0106] The technical solution of the present invention calculates the hash value of the five-tuple information of the lookup data packet, and determines whether the lookup data packet already exists in the storage space of the FPGA according to the hash calculation result and the pre-stored hash table, so as to quickly and accurately determine whether the lookup data packet has been stored. When it is determined that it does not exist, an update operation is performed based on the flow table ID, so that the flow table can be updated in a timely manner, realizing the real-time management of the flow table.

[0107] Embodiment III

[0108] Figure 3 It is a flowchart of a flow table processing method based on FPGA provided in Embodiment III of the present invention. On the basis of the above embodiment, a preferred example is provided.

[0109] As Figure 3 shown, the method includes the following specific steps:

[0110] S301. In response to the Ethernet packet input through the external interface, determine the lookup data packet and the newly created data packet in the Ethernet packet.

[0111] S302. Based on the preset first hash algorithm and second hash algorithm, calculate the hash values of the five-tuple information of the lookup data packet respectively to determine the first hash value and the second hash value.

[0112] S303. According to the first hash value, search in the pre-stored hash table to determine the corresponding pre-stored hash value, and determine whether the pre-stored hash value is consistent with the second hash value.

[0113] Optionally, if the pre-stored hash value is consistent with the second hash value, search in the pre-stored hash table according to the first hash value to determine the first flow table ID, and search in the storage space of the FPGA with the first flow table ID as the address to determine the corresponding pre-stored five-tuple information. Determine whether the pre-stored five-tuple information is consistent with the five-tuple information of the lookup data packet. If not, it is determined that the lookup data packet does not exist in the storage space of the FPGA.

[0114] S304. If the pre-stored hash value is inconsistent with the second hash value, it is determined that the lookup data packet does not exist in the storage space of the FPGA.

[0115] S305. If the lookup data packet does not exist in the storage space of the FPGA, determine the flow table ID corresponding to the lookup data packet, and perform an update operation on the flow table in the storage space of the FPGA.

[0116] S306. Apply to the ID management module and determine the second flow table ID.

[0117] S307. Based on a preset first hash algorithm and second hash algorithm, perform hash calculation on the five-tuple information corresponding to the newly created data packet to determine a third hash value and a fourth hash value.

[0118] S308. Update the pre-stored hash table according to the third hash value, the fourth hash value, and the second flow table ID, and create a flow table with the flow table ID being the second flow table ID in the storage space of the FPGA.

[0119] Optionally, updating the pre-stored hash table according to the third hash value, the fourth hash value, and the second flow table ID includes: determining a target position corresponding to the third hash value in the pre-stored hash table; storing the second flow table ID and the fourth hash value at the target position to implement the update of the pre-stored hash table.

[0120] S309. During the process of performing the flow table update operation and the flow table creation operation, record the flow table creation time and the flow table update time of each flow table.

[0121] S310. If it is detected that the time interval between the flow table creation time and the flow table update time of the target flow table is greater than the preset aging time, delete the target flow table in the storage space of the FPGA and feedback to the ID management module, which is used to instruct the ID management module to recycle the flow table ID corresponding to the target flow table.

[0122] S311. After it is detected that both the lookup data packet and the newly created data packet in the Ethernet packet are processed, integrate and output the Ethernet packet.

[0123] Embodiment 4

[0124] Figure 4 is a schematic structural diagram of a flow table processing device based on an FPGA according to Embodiment 4 of the present invention. The flow table processing device based on an FPGA provided by the embodiments of the present invention is applicable to the situation of performing flow table management on data packets in an Ethernet packet based on an FPGA and outputting the packet. The flow table processing device based on an FPGA can be implemented in the form of hardware and / or software. The flow table processing device based on an FPGA can be configured in an electronic device and executed by a field programmable gate array (FPGA) device. The FPGA device can be a flow table management component implemented by an FPGA, such as Figure 4 shown, the device specifically includes: a determination module 401, a management module 402, and an output module 403.

[0125] Among them,

[0126] The determination module 401 is configured to determine the lookup data packet and the newly created data packet in the Ethernet packet in response to the Ethernet packet input through an external interface;

[0127] The management module 402 is configured to perform a flow table update operation and a flow table creation operation in the storage space of the FPGA based on a preset hash algorithm according to the five-tuple information in the lookup data packet and the new data packet;

[0128] The output module 403 is configured to perform integrated output on the Ethernet packet after detecting that both the lookup data packet and the new data packet in the Ethernet packet are processed.

[0129] The technical solution of the embodiment of the present invention responds to an Ethernet packet input through an external interface, determines the lookup data packet and the new data packet in the Ethernet packet; performs a flow table update operation and a flow table creation operation in the FPGA storage space based on a preset hash algorithm according to the five-tuple information in the lookup data packet and the new data packet; and performs integrated output on the Ethernet packet after detecting that both the lookup data packet and the new data packet in the Ethernet packet are processed. By only performing packet processing and flow table management based on the FPGA device, the resource consumption of the CPU can be effectively avoided, and the overall working efficiency of the computer is improved; by performing a flow table update operation and a flow table creation operation based on the hash algorithm, the pre-stored hash table can be effectively utilized to implement a fast and effective flow table update operation and a flow table creation operation, perform more comprehensive and effective flow table management, and improve the processing efficiency of the Ethernet packet.

[0130] Further, the management module 402 may include:

[0131] The packet judgment unit is configured to perform hash calculation on the five-tuple information of the lookup data packet based on a preset hash algorithm, and determine whether the lookup data packet exists in the storage space of the FPGA according to the calculation result and the pre-stored hash table;

[0132] The flow table update unit is configured to, if not, determine the flow table ID corresponding to the lookup data packet, and perform an update operation on the flow table in the storage space of the FPGA.

[0133] Further, the packet judgment unit is specifically configured to:

[0134] Perform hash calculation on the five-tuple information of the lookup data packet based on a preset first hash algorithm and a second hash algorithm respectively to determine a first hash value and a second hash value;

[0135] Perform a lookup in the pre-stored hash table according to the first hash value, determine the corresponding pre-stored hash value, and determine whether the pre-stored hash value is consistent with the second hash value;

[0136] If not, it is determined that the lookup data packet does not exist in the storage space of the FPGA.

[0137] Further, the packet judgment unit is further configured to:

[0138] If the pre-stored hash value is consistent with the second hash value, look up in the pre-stored hash table according to the first hash value to determine the first flow table ID, and use the first flow table ID as the address to look up in the storage space of the FPGA to determine the corresponding pre-stored five-tuple information;

[0139] Determine whether the pre-stored five-tuple information is consistent with the five-tuple information of the lookup data packet. If not, it is determined that the lookup data packet does not exist in the storage space of the FPGA.

[0140] Furthermore, the management module 402 further includes:

[0141] An application unit for applying to the ID management module to determine the second flow table ID;

[0142] A hash value determination unit for performing hash calculations on the five-tuple information corresponding to the newly created data packet based on a preset first hash algorithm and a second hash algorithm to determine the third hash value and the fourth hash value;

[0143] A flow table creation unit for updating the pre-stored hash table according to the third hash value, the fourth hash value, and the second flow table ID, and creating a flow table with the second flow table ID in the storage space of the FPGA.

[0144] Furthermore, the flow table creation unit is specifically used for:

[0145] Determine the target position corresponding to the third hash value in the pre-stored hash table;

[0146] Store the second flow table ID and the fourth hash value at the target position to implement the update of the pre-stored hash table.

[0147] Furthermore, the above device is also used for:

[0148] During the process of performing the flow table update operation and the flow table creation operation, record the flow table creation time and the flow table update time of each flow table;

[0149] If it is detected that the time interval between the flow table creation time and the flow table update time of the target flow table is greater than the preset aging time, delete the target flow table in the storage space of the FPGA and feedback to the ID management module to instruct the ID management module to recycle the flow table ID corresponding to the target flow table.

[0150] Embodiment 5

[0151] Figure 5 It is a schematic structural diagram of an electronic device for implementing the FPGA-based flow table processing method of the embodiments of the present invention. Figure 5The structural schematic diagram of an electronic device 10 that can be used to implement the embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0152] As Figure 5 shown, the electronic device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc. Among them, the memory stores a computer program executable by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. The input / output (I / O) interface 15 is also connected to the bus 14.

[0153] Multiple components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disc, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0154] The processor 11 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the flow table processing method based on FPGA.

[0155] In some embodiments, the FPGA-based flow table processing method may be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed onto the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the above-described FPGA-based flow table processing method may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the FPGA-based flow table processing method by any other suitable means (e.g., by means of firmware).

[0156] The various embodiments of the systems and techniques described above in this document may be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGA), application specific integrated circuits (ASIC), application specific standard products (ASSP), systems on a chip (SOC), complex programmable logic devices (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs executable and / or interpretable on a programmable system including at least one programmable processor, which may be a special-purpose or general-purpose programmable processor that receives data and instructions from a storage system, at least one input device, and at least one output device, and transmits the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0157] The computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that the computer programs, when executed by the processor, cause the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The computer programs may be executed entirely on the machine, partially on the machine, as a stand-alone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0158] In the context of the present invention, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer-readable storage medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, the computer-readable storage medium can be a machine-readable signal medium. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0159] To provide for interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can also be used to provide for interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, speech input, or tactile input).

[0160] The systems and techniques described herein can be implemented in a computing system that includes backend components (such as, for example, a data server), or a computing system that includes middleware components (such as, for example, an application server), or a computing system that includes frontend components (such as, for example, a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected by any form or medium of digital data communication (such as, for example, a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0161] A computing system may include a client and a server. The client and the server are generally far from each other and usually interact via a communication network. The client-server relationship is created by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system, solving the defects of difficult management and weak business scalability existing in traditional physical hosts and VPS services.

[0162] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0163] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A flow table processing method based on FPGA, characterized in that, Executed by a Field Programmable Gate Array (FPGA) device, the method includes: In response to an Ethernet packet input through an external interface, parsing the Ethernet packet and, based on the parsing result, determining a lookup data packet and a new data packet in the Ethernet packet; wherein, the lookup data packet refers to a data packet for which a lookup operation is to be performed to determine whether it already exists in the storage space of the FPGA, and the new data packet refers to a data packet that is to be newly created in the flow table in the FPGA storage space; Based on a preset hash algorithm, performing a flow table update operation and a flow table creation operation in the storage space of the FPGA according to the five-tuple information in the lookup data packet and the new data packet, including: Based on the preset hash algorithm, performing a hash calculation on the five-tuple information of the lookup data packet, and determining whether the lookup data packet exists in the storage space of the FPGA according to the calculation result and a pre-stored hash table; if not, determining the flow table ID corresponding to the lookup data packet and performing an update operation on the flow table in the storage space of the FPGA; wherein, the pre-stored hash table refers to a hash table pre-stored with the hash value determined by the first hash algorithm as the key value and the hash value determined by the second hash algorithm and the second flow table ID as the value; After detecting that both the lookup data packet and the new data packet in the Ethernet packet have been processed, integrating and outputting the Ethernet packet.

2. The method according to claim 1, wherein The step of performing a hash calculation on the five-tuple information of the lookup data packet based on the preset hash algorithm and determining whether the lookup data packet exists in the storage space of the FPGA according to the calculation result and the pre-stored hash table includes: Based on a preset first hash algorithm and second hash algorithm, respectively performing a hash calculation on the five-tuple information of the lookup data packet to determine a first hash value and a second hash value; Looking up in the pre-stored hash table according to the first hash value to determine the corresponding pre-stored hash value, and determining whether the pre-stored hash value is the same as the second hash value; If not, determining that the lookup data packet does not exist in the storage space of the FPGA.

3. The method according to claim 2, wherein After determining whether the pre-stored hash value is the same as the second hash value, it further includes: If the pre-stored hash value is the same as the second hash value, looking up in the pre-stored hash table according to the first hash value to determine a first flow table ID, and looking up at the address of the first flow table ID in the storage space of the FPGA to determine the corresponding pre-stored five-tuple information; Determining whether the pre-stored five-tuple information is the same as the five-tuple information of the lookup data packet, if not, determining that the lookup data packet does not exist in the storage space of the FPGA.

4. The method according to claim 1, wherein Based on the preset hash algorithm, performing a flow table creation operation in the storage space of the FPGA according to the five-tuple information of the new data packet, including: Applying to the ID management module and determining a second flow table ID; Based on the preset first hash algorithm and second hash algorithm, performing a hash calculation on the five-tuple information corresponding to the new data packet to determine a third hash value and a fourth hash value; Update the pre-stored hash table according to the third hash value, the fourth hash value, and the second flow table ID, and create a flow table with the flow table ID of the second flow table ID in the storage space of the FPGA.

5. The method according to claim 4, characterized in that, Updating the pre-stored hash table according to the third hash value, the fourth hash value, and the second flow table ID includes: Determine the target position corresponding to the third hash value in the pre-stored hash table; Store the second flow table ID and the fourth hash value at the target position to update the pre-stored hash table.

6. The method according to claim 1, characterized in that It further includes: During the process of performing the flow table update operation and the flow table creation operation, record the flow table creation time and the flow table update time of each flow table; If it is detected that the time interval between the flow table creation time and the flow table update time of the target flow table is greater than the preset aging time, delete the target flow table in the storage space of the FPGA and feedback to the ID management module, which is used to instruct the ID management module to recycle the flow table ID corresponding to the target flow table.

7. A flow table processing device based on FPGA, characterized in that, The device is configured in a Field Programmable Gate Array (FPGA) device and includes: A determination module, configured to parse an Ethernet packet in response to an Ethernet packet input through an external interface, and determine a lookup data packet and a new data packet in the Ethernet packet according to the parsing result; wherein, the lookup data packet refers to a data packet for which a lookup operation is to be performed to determine whether it already exists in the storage space of the FPGA, and the new data packet refers to a data packet that is to be newly created in the flow table in the FPGA storage space; A management module, configured to perform a flow table update operation and a flow table creation operation in the storage space of the FPGA based on a preset hash algorithm according to the five-tuple information in the lookup data packet and the new data packet; An output module, configured to integrate and output the Ethernet packet after detecting that both the lookup data packet and the new data packet in the Ethernet packet have been processed; Among them, the management module includes: a data packet judgment unit, configured to perform a hash calculation on the five-tuple information of the lookup data packet based on a preset hash algorithm, and determine whether the lookup data packet exists in the storage space of the FPGA according to the calculation result and the pre-stored hash table; a flow table update unit, configured to, if not, determine the flow table ID corresponding to the lookup data packet and perform a flow table update operation on the flow table in the storage space of the FPGA; wherein, the pre-stored hash table refers to a pre-stored hash table with the hash value determined by the first hash algorithm as the key value and the hash value determined by the second hash algorithm and the second flow table ID as the value.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the FPGA-based flow table processing method according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the processor to implement the FPGA-based flow table processing method according to any one of claims 1-6 when executed.

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