Pixel circuit, driving method thereof, and display device

Abstract

A pixel circuit, a driving method thereof, and a display device, the pixel circuit including a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a first reset sub-circuit, a second reset sub-circuit, and an emitting element (EL), the driving sub-circuit configured to provide a driving signal to a third node (N3) in response to signals of a first node (N1) and a second node (N2); the writing sub-circuit configured to write a signal of a data signal line (Data) to the second node (N2) or the third node (N3) under control of a signal of a first scan signal line (Gate1); the compensation sub-circuit configured to compensate a voltage of the first node (N1) under control of the signal of the first scan signal line (Gate1); the first reset sub-circuit configured to reset the first node (N1) under control of a signal of a reset control signal line (Reset); and the second reset sub-circuit configured to reset an anode terminal of the emitting element (EL) under control of a signal of a second scan signal line (Gate2).

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a pixel circuit and its driving method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and extremely fast response speed. They are widely used in display products such as mobile phones, tablets, and digital cameras. OLED displays are current-driven, requiring current to be output to the OLED through pixel circuits to drive it to emit light. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] An exemplary embodiment of this disclosure provides a pixel circuit, including a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a first reset sub-circuit, a second reset sub-circuit, and a light-emitting element, wherein: the driving sub-circuit is configured to provide a driving signal to a third node in response to signals from a first node and a second node; the writing sub-circuit is configured to write a signal from a data signal line to the second node or the third node under the control of a signal from a first scan signal line; the compensation sub-circuit is configured to compensate the voltage of the first node under the control of a signal from the first scan signal line; the first reset sub-circuit is configured to reset the first node under the control of a signal from a reset control signal line; and the second reset sub-circuit is configured to reset the anode of the light-emitting element under the control of a signal from the second scan signal line.

[0005] In an exemplary embodiment, the first reset sub-circuit includes a first transistor; the control electrode of the first transistor is connected to a reset control signal line, the first electrode of the first transistor is connected to a first power supply line or a reference power supply line, and the second electrode of the first transistor is connected to the first node.

[0006] In an exemplary embodiment, the second reset sub-circuit includes a second transistor; the control electrode of the second transistor is connected to a second scan signal line, the first electrode of the second transistor is connected to an initial signal line, and the second electrode of the second transistor is connected to the anode of the light-emitting element.

[0007] In an exemplary embodiment, the compensation sub-circuit includes a third transistor and a first capacitor, the driving sub-circuit includes a fourth transistor, and the writing sub-circuit includes a fifth transistor; the control electrode of the third transistor is connected to a first scan signal line, the first electrode of the third transistor is connected to the third node, and the second electrode of the third transistor is connected to the first node; one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the anode of the light-emitting element; the control electrode of the fourth transistor is connected to the first node, the first electrode of the fourth transistor is connected to the second node, and the second electrode of the fourth transistor is connected to the third node; the control electrode of the fifth transistor is connected to the first scan signal line, the first electrode of the fifth transistor is connected to the data signal line, and the second electrode of the fifth transistor is connected to the second node.

[0008] In an exemplary embodiment, the compensation sub-circuit includes a third transistor and a first capacitor, the driving sub-circuit includes a fourth transistor, and the writing sub-circuit includes a fifth transistor; the control electrode of the third transistor is connected to a first scan signal line, the first electrode of the third transistor is connected to a second node, and the second electrode of the third transistor is connected to the first node; one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the anode of the light-emitting element; the control electrode of the fourth transistor is connected to the first node, the first electrode of the fourth transistor is connected to the second node, and the second electrode of the fourth transistor is connected to the third node; the control electrode of the fifth transistor is connected to the first scan signal line, the first electrode of the fifth transistor is connected to the data signal line, and the second electrode of the fifth transistor is connected to the third node.

[0009] In an exemplary embodiment, the pixel circuit further includes a first light-emitting control sub-circuit and a second light-emitting control sub-circuit; the first light-emitting control sub-circuit is configured to write a signal from a first power line into a second node under the control of a signal from a light-emitting control signal line; the second light-emitting control sub-circuit is configured to form a current path between the third node and the anode of the light-emitting element under the control of a signal from the light-emitting control signal line.

[0010] In an exemplary embodiment, the first light-emitting control sub-circuit includes a sixth transistor, and the second light-emitting control sub-circuit includes a seventh transistor; the control electrode of the sixth transistor is connected to the light-emitting control signal line, the first electrode of the sixth transistor is connected to the first power supply line, and the second electrode of the sixth transistor is connected to the second node; the control electrode of the seventh transistor is connected to the light-emitting control signal line, the first electrode of the seventh transistor is connected to the third node, and the second electrode of the seventh transistor is connected to the anode of the light-emitting element.

[0011] In an exemplary embodiment, the pixel circuit further includes a first light-emitting control sub-circuit and a second light-emitting control sub-circuit, wherein the first reset sub-circuit includes a first transistor, the second reset sub-circuit includes a second transistor, the compensation sub-circuit includes a third transistor and a first capacitor, the driving sub-circuit includes a fourth transistor, the writing sub-circuit includes a fifth transistor, the first light-emitting control sub-circuit includes a sixth transistor, and the second light-emitting control sub-circuit includes a seventh transistor.

[0012] The control electrode of the first transistor is connected to the reset control signal line, the first electrode of the first transistor is connected to the first power supply line or the reference power supply line, and the second electrode of the first transistor is connected to the first node; the control electrode of the second transistor is connected to the second scan signal line, the first electrode of the second transistor is connected to the initial signal line, and the second electrode of the second transistor is connected to the fourth node, which is connected to the anode of the light-emitting element; the control electrode of the third transistor is connected to the first scan signal line, the first electrode of the third transistor is connected to the third node or the second node, and the second electrode of the third transistor is connected to the first node; one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the fourth node; the third... The control electrode of the fourth transistor is connected to the first node; the first electrode of the fourth transistor is connected to the second node; and the second electrode of the fourth transistor is connected to the third node. The control electrode of the fifth transistor is connected to the first scan signal line; the first electrode of the fifth transistor is connected to the data signal line; and the second electrode of the fifth transistor is connected to either the second or third node. The control electrode of the sixth transistor is connected to the light emission control signal line; the first electrode of the sixth transistor is connected to the first power supply line; and the second electrode of the sixth transistor is connected to the second node. The control electrode of the seventh transistor is connected to the light emission control signal line; the first electrode of the seventh transistor is connected to the third node; and the second electrode of the seventh transistor is connected to the fourth node.

[0013] In an exemplary embodiment, the first transistor to the seventh transistor are either all N-type transistors or all P-type transistors.

[0014] In an exemplary embodiment, the second transistor, the fourth transistor to the seventh transistor are all low-temperature polycrystalline silicon thin-film transistors, and the first transistor and the third transistor are all indium gallium zinc oxide thin-film transistors.

[0015] In an exemplary embodiment, the reset control signal line, the first scan signal line, and the second scan signal line are further configured to receive signals of different frequencies according to the display mode of the display panel.

[0016] In an exemplary embodiment, receiving signals of different frequencies according to the display mode of the display panel includes: when the display panel is in a first display mode, the data refresh frequency of the pixel circuit is a first frequency, and the reset control signal line, the first scan signal line, and the second scan signal line are configured to receive signals of the first frequency; when the display panel is in a second display mode, the data refresh frequency of the pixel circuit is a second frequency, the reset control signal line and the first scan signal line are configured to receive signals of the second frequency, the second scan signal line is configured to receive signals of a third frequency, wherein the third frequency is greater than the second frequency, and the first frequency is greater than the second frequency.

[0017] In an exemplary embodiment, the signals of the reset control signal line and the first scan signal line are cascaded signals.

[0018] In an exemplary embodiment, the second reset sub-circuit includes a second transistor and an eighth transistor; the control electrode of the second transistor is connected to the second scan signal line, the first electrode of the second transistor is connected to the initial signal line, and the second electrode of the second transistor is connected to the anode of the light-emitting element; the control electrode of the eighth transistor is connected to the third scan signal line, the first electrode of the eighth transistor is connected to the anode of the light-emitting element, and the second electrode of the eighth transistor is connected to the compensation sub-circuit.

[0019] In an exemplary embodiment, the pixel circuit further includes a first light-emitting control sub-circuit and a second light-emitting control sub-circuit, wherein the first reset sub-circuit includes a first transistor, the second reset sub-circuit includes a second transistor and an eighth transistor, the compensation sub-circuit includes a third transistor and a first capacitor, the driving sub-circuit includes a fourth transistor, the writing sub-circuit includes a fifth transistor, the first light-emitting control sub-circuit includes a sixth transistor, and the second light-emitting control sub-circuit includes a seventh transistor.

[0020] The control electrode of the first transistor is connected to the reset control signal line, the first electrode of the first transistor is connected to the first power supply line or the reference power supply line, and the second electrode of the first transistor is connected to the first node; the control electrode of the second transistor is connected to the second scan signal line, the first electrode of the second transistor is connected to the initial signal line, and the second electrode of the second transistor is connected to the fourth node, which is connected to the anode of the light-emitting element; the control electrode of the third transistor is connected to the first scan signal line, the first electrode of the third transistor is connected to the third node or the second node, and the second electrode of the third transistor is connected to the first node; one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the second electrode of the eighth transistor; the control electrode of the eighth transistor is connected to the third scan signal line. Then, the first electrode of the eighth transistor is connected to the fourth node; the control electrode of the fourth transistor is connected to the first node, the first electrode of the fourth transistor is connected to the second node, and the second electrode of the fourth transistor is connected to the third node; the control electrode of the fifth transistor is connected to the first scan signal line, the first electrode of the fifth transistor is connected to the data signal line, and the second electrode of the fifth transistor is connected to the second node or the third node; the control electrode of the sixth transistor is connected to the light emission control signal line, the first electrode of the sixth transistor is connected to the first power supply line, and the second electrode of the sixth transistor is connected to the second node; the control electrode of the seventh transistor is connected to the light emission control signal line, the first electrode of the seventh transistor is connected to the third node, and the second electrode of the seventh transistor is connected to the fourth node.

[0021] In an exemplary embodiment, when the display panel is in the refresh phase, the signal of the third scan signal line is the same as the signal of the second scan signal line; when the display panel is in the hold phase, the signal of the third scan signal line is opposite to the signal of the second scan signal line; or, when the display panel is in the hold phase, the signal of the third scan signal line causes the eighth transistor to remain off.

[0022] Exemplary embodiments of this disclosure also provide a display device including the pixel circuit described in any of the foregoing embodiments.

[0023] An exemplary embodiment of this disclosure also provides a driving method for a pixel circuit, used to drive the pixel circuit described in any of the preceding claims, the pixel circuit operating in a first display mode or a second display mode, the first display mode including a plurality of first display cycles, and within one first display cycle, the driving method includes: in a reset phase, a first reset sub-circuit resetting a first node under the control of a reset control signal line signal; a second reset sub-circuit resetting the anode of the light-emitting element under the control of a second scan signal line signal; in a data writing phase, a writing sub-circuit writing a data signal line signal to a second node or a third node under the control of a first scan signal line signal; a compensation sub-circuit compensating the voltage of the first node under the control of a first scan signal line signal; and in a light-emitting phase, a driving sub-circuit providing a driving signal to a third node in response to the signals of the first node and the second node.

[0024] In an exemplary embodiment, the second display mode includes a plurality of second display cycles, the second display cycle including a refresh phase and a hold phase; the refresh phase includes a reset phase, a data writing phase and a light-emitting phase arranged sequentially; the hold phase includes a plurality of light-emitting phases and a plurality of extinguishing phases, the light-emitting phases and the extinguishing phases being spaced apart; in the extinguishing phase, the second reset sub-circuit resets the anode terminal of the light-emitting element under the control of the signal of the second scan signal line.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0027] Figure 1 This is a schematic diagram of the waveform change of screen brightness voltage over time when data is refreshed in low-frequency mode.

[0028] Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0029] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present disclosure;

[0030] Figure 4 This is a schematic diagram showing the screen brightness voltage changing over time in low-frequency mode of the pixel circuit according to an embodiment of the present disclosure.

[0031] Figure 5 An equivalent circuit diagram of a first reset circuit provided in an embodiment of this disclosure;

[0032] Figure 6 An equivalent circuit diagram of a second reset circuit provided in an embodiment of this disclosure;

[0033] Figure 7 An equivalent circuit diagram of a compensation sub-circuit, a driving sub-circuit, and a writing sub-circuit provided in an embodiment of this disclosure;

[0034] Figure 8 An equivalent circuit diagram of another compensation sub-circuit, driving sub-circuit, and writing sub-circuit provided in an embodiment of this disclosure;

[0035] Figure 9 An equivalent circuit diagram of a first light-emitting control sub-circuit and a second light-emitting control sub-circuit provided in the embodiments of this disclosure;

[0036] Figure 10 An equivalent circuit diagram of a pixel circuit provided in an embodiment of this disclosure;

[0037] Figure 11 An equivalent circuit diagram of another pixel circuit provided in an embodiment of this disclosure;

[0038] Figure 12 An equivalent circuit diagram of another pixel circuit provided in an embodiment of this disclosure;

[0039] Figure 13 An equivalent circuit diagram of another pixel circuit provided in an embodiment of this disclosure;

[0040] Figure 14 for Figures 10 to 13 The diagram shown is a timing diagram of the pixel circuit operating in normal display mode.

[0041] Figure 15 for Figures 10 to 13 The diagram shown is a timing diagram of the pixel circuit operating in low-frequency display mode.

[0042] Figure 16 An equivalent circuit diagram of another pixel circuit provided in an embodiment of this disclosure;

[0043] Figure 17 for Figure 16 The diagram shown is a timing diagram of the pixel circuit operating in normal display mode.

[0044] Figure 18 for Figure 16 The diagram shows the timing of the pixel circuit in low-frequency display mode. Detailed Implementation

[0045] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0046] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" always cover the elements or objects listed after the term and their equivalents, without excluding other elements or objects, provided that the element or object preceding the term is included.

[0047] In the embodiments of this disclosure, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0048] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0049] In this specification, "connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0050] OLED displays possess numerous advantages, including self-emissiveness, low driving voltage, high luminous efficiency, short response time, and a wide operating temperature range, making them widely recognized as the most promising display devices. OLEDs are categorized by driving method into Passive Matrix OLED (PMOLED) and Active Matrix OLED (AMOLED). AMOLED displays contain an array of pixels, each driven by a separate pixel driving circuit. For dynamic images, increasing the refresh rate can improve image quality. For relatively static images, since high refresh rates are unnecessary, reducing the refresh rate can conserve power. To ensure AMOLED displays can accommodate both high refresh rates and low power consumption, they must support dynamic refresh rates.

[0051] Currently, Always On Display (AOD) has become a standard feature in many smartphones, smartwatches, and other portable devices. In AOD mode, the screen displays only the time and simple information, without the need for high-speed refresh rates. Since AOD is used for extended periods, low refresh rates help save power and extend battery life.

[0052] In pixel circuits employing Low Temperature Polycrystalline Oxide (LTPO) technology, the Thin Film Transistor (TFT) connected to the control electrode of the Drive Thin Film Transistor (DTFT) is replaced with a low-leakage oxide TFT. This is because the leakage current of an oxide TFT can reach 10... -16 A and below ensure that the brightness change of OLED is minimal over a long period of time (>0.1s, or even more than 1s), thereby enabling low frame rate display and high brightness retention.

[0053] like Figure 1 As shown, in the normal low-frequency operating mode, assuming a driving frequency of 1Hz, the times ... -1s, 0s, 1s ... are all data update times. At these times, the data update frame will be refreshed to the control electrode of the driving transistor (DTFT), thereby controlling the driving current flowing through the OLED. The other times are the brightness maintenance phase. At this time, no high-frequency anode reset is performed, and a significant decrease in brightness can be seen at the frame period boundary, which is easily perceived by the human eye and manifests as screen flicker.

[0054] This disclosure provides a pixel circuit. Figure 2 and Figure 3 Here are schematic diagrams of the structures of two pixel circuits provided in the embodiments of this disclosure, such as... Figure 2 and Figure 3 As shown, the pixel circuit provided in this embodiment includes: a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a first reset sub-circuit, a second reset sub-circuit, and a light-emitting element.

[0055] The driving sub-circuit is connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide a driving signal to the third node N3 in response to the signals of the first node N1 and the second node N2. For example, the driving signal is a driving current.

[0056] The write sub-circuit is connected to the first scan signal line Gate1 and the data signal line Data, and is also connected to the second node N2 or the third node N3. It is configured to write the signal of the data signal line Data to the second node N2 or the third node N3 under the control of the signal of the first scan signal line Gate1.

[0057] The compensation sub-circuit is connected to the first scan signal line Gate1, the first node N1 and the fourth node N4 respectively, and is also connected to the third node N3 or the second node N2. It is configured to compensate the threshold voltage of the driving sub-circuit to the first node N1 under the control of the signal of the first scan signal line Gate1.

[0058] The first reset sub-circuit is connected to the reset control signal line Reset and the first node N1, and is also connected to the reference power line REF or the first power line VDD. It is configured to reset the first node N1 using the signal of the reference power line REF or the first power line VDD under the control of the signal of the reset control signal line Reset.

[0059] The second reset circuit is connected to the second scan signal line Gate2, the initial signal line INIT, and the anode of the light-emitting element (i.e., the fourth node N4), and is configured to reset the anode of the light-emitting element using the signal of the initial signal line INIT under the control of the signal of the second scan signal line Gate2.

[0060] The pixel circuit provided in this embodiment resets the first node N1 using the signal of the reference power line REF or the first power line VDD under the control of the reset control signal line Reset. The second reset sub-circuit resets the anode of the light-emitting element using the signal of the initial signal line INIT under the control of the second scan signal line Gate2. This achieves separate resets of the first node N1 and the anode of the light-emitting element, and extends the reset time, thus improving the image retention problem.

[0061] During the low-frequency brightness maintenance phase, the pixel circuit provided in this embodiment does not require periodic control of the signals of the first scan signal line Gate1 and the reset control signal line Reset. Instead, it only needs to periodically control the signals of the second scan signal line Gate2 and the light emission control signal line EM to periodically reset / adjust the brightness of the light-emitting element, thereby achieving brightness balance. For example... Figure 4 As shown, when the light emission control signal line EM is turned off, the signal of the second scan signal line Gate2 is turned on. The signal of the initial signal line INIT resets the anode of the light emission element, so that the brightness trough of the holding phase is the same as the refresh frame, thus eliminating the flickering phenomenon.

[0062] The pixel circuit of this embodiment only requires three sets of shift registers: a light emission control signal line, a first scan signal line, and a second scan signal line. The cascaded array substrate row drive (GOA) circuit occupies a small area, which can further reduce the display area occupied by the display panel, thereby achieving high resolution and narrow bezel of the display device.

[0063] The pixel circuit of this disclosure has a simple driving timing, which can avoid the use of complex external compensation circuits and reduce the use of integrated circuits, thereby reducing manufacturing costs.

[0064] Furthermore, the pixel circuit in this embodiment compensates for the control electrode voltage of the driving sub-circuit through a compensation sub-circuit, thereby avoiding the influence of the threshold voltage drift of the driving sub-circuit on the driving current of the light-emitting element and improving the uniformity of the displayed image and the display quality of the display panel.

[0065] In one exemplary embodiment, such as Figure 2 and Figure 3 As shown, the pixel circuit provided in this embodiment further includes: a first light-emitting control sub-circuit and a second light-emitting control sub-circuit, wherein:

[0066] The first light-emitting control sub-circuit is connected to the first power line VDD, the light-emitting control signal line EM, and the second node N2, respectively, and is configured to write the signal of the first power line VDD into the second node N2 under the control of the signal of the light-emitting control signal line EM.

[0067] The second light-emitting control sub-circuit is connected to the light-emitting control signal line EM, the third node N3, and the fourth node, respectively, and is configured to form a path between the third node N3 and the fourth node N4 under the control of the signal of the light-emitting control signal line EM.

[0068] In one exemplary embodiment, such as Figure 2 and Figure 3As shown, one end of the light-emitting element is connected to the fourth node N4, and the other end is connected to the second power line VSS.

[0069] In one exemplary embodiment, Figure 5 An equivalent circuit diagram of the first reset sub-circuit provided in the embodiments of this disclosure is shown below. Figure 5 As shown, the first reset circuit provided in this embodiment includes a first transistor T1.

[0070] In this configuration, the control electrode of the first transistor T1 is connected to the reset control signal line Reset, the first electrode of the first transistor T1 is connected to the first power supply line VDD or the reference power supply line REF, and the second electrode of the first transistor T1 is connected to the first node N1.

[0071] Figure 5 An exemplary structure of the first reset circuit is shown. It will be readily understood by those skilled in the art that the implementation of the first reset circuit is not limited to this, as long as its function is achieved.

[0072] In one exemplary embodiment, Figure 6 An equivalent circuit diagram of the second reset sub-circuit provided in the embodiments of this disclosure is shown below. Figure 6 As shown, the second reset circuit provided in this embodiment includes a second transistor T7.

[0073] In this configuration, the control electrode of the second transistor T2 is connected to the second scan signal line Gate2, the first electrode of the second transistor T2 is connected to the initial signal line INIT, and the second electrode of the second transistor T2 is connected to the fourth node N4.

[0074] Figure 6 An exemplary structure of the second reset circuit is shown. It will be readily understood by those skilled in the art that the implementation of the second reset circuit is not limited to this, as long as its function is achieved.

[0075] In one exemplary embodiment, Figure 7 An equivalent circuit diagram of the driving sub-circuit, writing sub-circuit, and compensation sub-circuit provided in the embodiments of this disclosure is shown below. Figure 7 As shown, the compensation sub-circuit provided in this embodiment includes a third transistor T3 and a first capacitor C1, the driving sub-circuit includes a fourth transistor T4, and the writing sub-circuit includes a fifth transistor T5.

[0076] Among them, the control electrode of the third transistor T3 is connected to the first scan signal line Gate1, the first electrode of the third transistor T3 is connected to the third node N3, and the second electrode of the third transistor T3 is connected to the first node N1;

[0077] One end of the first capacitor C1 is connected to the first node N1, and the other end of the first capacitor C1 is connected to the fourth node N4.

[0078] The control electrode of the fourth transistor T4 is connected to the first node N1, the first electrode of the fourth transistor T4 is connected to the second node N2, and the second electrode of the fourth transistor T4 is connected to the third node N3.

[0079] The control electrode of the fifth transistor T5 is connected to the first scan signal line Gate1, the first electrode of the fifth transistor T5 is connected to the data signal line Data, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0080] In another exemplary embodiment, Figure 8 Another equivalent circuit diagram of the driving sub-circuit, writing sub-circuit, and compensation sub-circuit provided in the embodiments of this disclosure is shown below. Figure 8 As shown, the compensation sub-circuit provided in this embodiment includes a third transistor T3 and a first capacitor C1, the driving sub-circuit includes a fourth transistor T4, and the writing sub-circuit includes a fifth transistor T5.

[0081] Among them, the control electrode of the third transistor T3 is connected to the first scan signal line Gate1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the first node N1;

[0082] One end of the first capacitor C1 is connected to the first node N1, and the other end of the first capacitor C1 is connected to the fourth node N4.

[0083] The control electrode of the fourth transistor T4 is connected to the first node N1, the first electrode of the fourth transistor T4 is connected to the second node N2, and the second electrode of the fourth transistor T4 is connected to the third node N3.

[0084] The control electrode of the fifth transistor T5 is connected to the first scan signal line Gate1, the first electrode of the fifth transistor T5 is connected to the data signal line Data, and the second electrode of the fifth transistor T5 is connected to the third node N3.

[0085] Figure 7 and Figure 8 Two exemplary structures for the driver sub-circuit, the write sub-circuit, and the compensation sub-circuit are shown. It will be readily understood by those skilled in the art that the implementation of the driver sub-circuit, the write sub-circuit, and the compensation sub-circuit is not limited to these, as long as their respective functions are achieved.

[0086] In one exemplary embodiment, Figure 9 The equivalent circuit diagrams of the first light-emitting control sub-circuit and the second light-emitting control sub-circuit provided in the embodiments of this disclosure are as follows: Figure 9As shown, the first light-emitting control sub-circuit provided in this embodiment includes a sixth transistor T6, and the second light-emitting control sub-circuit includes a seventh transistor T7.

[0087] Among them, the control electrode of the sixth transistor T6 is connected to the light emission control signal line EM, the first electrode of the sixth transistor T6 is connected to the first power supply line VDD, and the second electrode of the sixth transistor T6 is connected to the second node N2.

[0088] The control electrode of the seventh transistor T7 is connected to the light emission control signal line EM, the first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0089] Figure 9 The diagram illustrates an exemplary structure of a first light-emitting control sub-circuit and a second light-emitting control sub-circuit. It will be readily understood by those skilled in the art that the implementation of the first and second light-emitting control sub-circuits is not limited to this, as long as their respective functions are achieved.

[0090] Figure 10 and Figure 11 Two equivalent circuit diagrams of the pixel circuit provided in the embodiments of this disclosure are as follows: Figure 10 and Figure 11 As shown, in the pixel circuit provided in this embodiment, the first reset sub-circuit includes a first transistor T1, the second reset sub-circuit includes a second transistor T2, the compensation sub-circuit includes a third transistor T3 and a first capacitor C1, the driving sub-circuit includes a fourth transistor T4, the writing sub-circuit includes a fifth transistor T5, the first light emission control sub-circuit includes a sixth transistor T6, and the second light emission control sub-circuit includes a seventh transistor T7.

[0091] Among them, the control electrode of the first transistor T1 is connected to the reset control signal line Reset, the first electrode of the first transistor T1 is connected to the first power supply line VDD or the reference power supply line REF, and the second electrode of the first transistor T1 is connected to the first node N1.

[0092] The control electrode of the second transistor T2 is connected to the second scan signal line Gate2, the first electrode of the second transistor T2 is connected to the initial signal line INIT, and the second electrode of the second transistor T2 is connected to the fourth node N4.

[0093] The control electrode of the third transistor T3 is connected to the first scan signal line Gate1, the first electrode of the third transistor T3 is connected to the third node N3, and the second electrode of the third transistor T3 is connected to the first node N1.

[0094] One end of the first capacitor C1 is connected to the first node N1, and the other end of the first capacitor C1 is connected to the fourth node N4.

[0095] The control electrode of the fourth transistor T4 is connected to the first node N1, the first electrode of the fourth transistor T4 is connected to the second node N2, and the second electrode of the fourth transistor T4 is connected to the third node N3.

[0096] The control electrode of the fifth transistor T5 is connected to the first scan signal line Gate1, the first electrode of the fifth transistor T5 is connected to the data signal line Data, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0097] The control electrode of the sixth transistor T6 is connected to the light emission control signal line EM, the first electrode of the sixth transistor T6 is connected to the first power supply line VDD, and the second electrode of the sixth transistor T6 is connected to the second node N2.

[0098] The control electrode of the seventh transistor T7 is connected to the light emission control signal line EM, the first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0099] Figure 12 and Figure 13 Two other equivalent circuit diagrams for the pixel circuits provided in the embodiments of this disclosure, such as Figure 12 and Figure 13 As shown, in the pixel circuit provided in this embodiment, the first reset sub-circuit includes a first transistor T1, the second reset sub-circuit includes a second transistor T2, the compensation sub-circuit includes a third transistor T3 and a first capacitor C1, the driving sub-circuit includes a fourth transistor T4, the writing sub-circuit includes a fifth transistor T5, the first light emission control sub-circuit includes a sixth transistor T6, and the second light emission control sub-circuit includes a seventh transistor T7.

[0100] Among them, the control electrode of the first transistor T1 is connected to the reset control signal line Reset, the first electrode of the first transistor T1 is connected to the first power supply line VDD or the reference power supply line REF, and the second electrode of the first transistor T1 is connected to the first node N1.

[0101] The control electrode of the second transistor T2 is connected to the second scan signal line Gate2, the first electrode of the second transistor T2 is connected to the initial signal line INIT, and the second electrode of the second transistor T2 is connected to the fourth node N4.

[0102] The control electrode of the third transistor T3 is connected to the first scan signal line Gate1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the first node N1.

[0103] One end of the first capacitor C1 is connected to the first node N1, and the other end of the first capacitor C1 is connected to the fourth node N4.

[0104] The control electrode of the fourth transistor T4 is connected to the first node N1, the first electrode of the fourth transistor T4 is connected to the second node N2, and the second electrode of the fourth transistor T4 is connected to the third node N3.

[0105] The control electrode of the fifth transistor T5 is connected to the first scan signal line Gate1, the first electrode of the fifth transistor T5 is connected to the data signal line Data, and the second electrode of the fifth transistor T5 is connected to the third node N3.

[0106] The control electrode of the sixth transistor T6 is connected to the light emission control signal line EM, the first electrode of the sixth transistor T6 is connected to the first power supply line VDD, and the second electrode of the sixth transistor T6 is connected to the second node N2.

[0107] The control electrode of the seventh transistor T7 is connected to the light emission control signal line EM, the first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0108] Figures 10 to 13 Exemplary structures of a first reset sub-circuit, a second reset sub-circuit, a drive sub-circuit, a write sub-circuit, a compensation sub-circuit, a first light-emitting control sub-circuit, and a second light-emitting control sub-circuit are shown. It will be readily understood by those skilled in the art that the implementation of each of the above sub-circuits is not limited to these examples, as long as their respective functions are achieved.

[0109] In one exemplary embodiment, the light-emitting element EL can be an organic light-emitting diode (OLED) or any other type of light-emitting diode.

[0110] In one exemplary embodiment, the first transistor T1 to the seventh transistor T7 are all N-type thin-film transistors, or the first transistor T1 to the seventh transistor T7 are all P-type thin-film transistors.

[0111] In this embodiment, the first transistor T1 to the seventh transistor T7 are all N-type or P-type thin-film transistors, which can unify the process flow, reduce process steps, and help improve product yield. Furthermore, the control signal lines of multiple transistors in the layout can be shared. In addition, considering the low leakage current of low-temperature polycrystalline silicon thin-film transistors, this embodiment of the invention preferably uses low-temperature polycrystalline silicon thin-film transistors for all transistors. Specifically, the thin-film transistors can be either bottom-gate or top-gate structures, as long as they can achieve the switching function.

[0112] In one exemplary embodiment, the first capacitor C1 may be a liquid crystal capacitor composed of a pixel electrode and a common electrode, or it may be an equivalent capacitor composed of a liquid crystal capacitor composed of a pixel electrode and a common electrode and a storage capacitor. The present invention does not limit this.

[0113] In one exemplary embodiment, the second transistor T2, the fourth transistor T4 to the seventh transistor T7 are all low-temperature polysilicon (LTPS) thin film transistors (TFTs), and the first transistor T1 and transistor T3 are indium gallium zinc oxide (IGZO) thin film transistors.

[0114] In this embodiment, the indium gallium zinc oxide thin film transistor generates less leakage current compared to the low-temperature polycrystalline silicon thin film transistor. Therefore, the pixel circuit of this embodiment can significantly reduce leakage current by setting the first transistor T1 and the third transistor T3 as indium gallium zinc oxide thin film transistors, thereby achieving a high brightness retention rate of the light-emitting element.

[0115] The pixel circuit of this embodiment connects the control electrode of the second transistor T2 to the second scan signal line Gate2. During the low-frequency refresh stage, it is not necessary to periodically control the signals of the first scan signal line Gate1 and the reset control signal line Reset. Instead, it is only necessary to periodically control the signals of the light emission control signal line EM and the second scan signal line to periodically reset / adjust the brightness of the light-emitting element, thereby achieving brightness balance.

[0116] In one exemplary embodiment, the reset control signal line, the first scan signal line, the light emission control signal line, and the second scan signal line are further configured to receive signals of different frequencies according to the display mode of the display panel.

[0117] In one exemplary embodiment, receiving signals of different frequencies according to the display mode of the display panel includes:

[0118] When the display panel is in the first display mode, the data refresh frequency of the pixel circuit is the first frequency, and the signals of the reset control signal line, the first scan signal line, the light emission control signal line and the second scan signal line are configured to receive the first frequency signal.

[0119] When the display panel is in the second display mode, the data refresh frequency of the pixel circuit is the second frequency, the reset control signal line and the first scan signal line are configured to receive the signal of the second frequency, and the light emission control signal line and the second scan signal line are configured to receive the signal of the third frequency, the third frequency being greater than the second frequency, and the first frequency being greater than the second frequency.

[0120] In this embodiment, when the display panel is in the first display mode, the data refresh frequency of the pixel circuit is the first frequency, the reset control signal line is configured to receive the reset control signal of the first frequency, the first scan signal line is configured to receive the first scan signal of the first frequency, the light emission control signal line is configured to receive the light emission control signal of the first frequency, and the second scan signal line is configured to receive the second scan signal of the first frequency.

[0121] When the display panel is in the second display mode, the data refresh frequency of the pixel circuit is the second frequency, the reset control signal line is configured to receive the reset control signal of the second frequency, the first scan signal line is configured to receive the first scan signal of the second frequency, the light emission control signal line is configured to receive the light emission control signal of the third frequency, and the second scan signal line is configured to receive the second scan signal of the third frequency.

[0122] In one exemplary embodiment, the first display mode is a normal display mode, and the second display mode is a low-frequency display mode or an AOD mode.

[0123] In one exemplary embodiment, the first frequency can be 60Hz or 120Hz. The second frequency can be 1Hz or 0.1Hz. The third frequency can be 60Hz or 120Hz.

[0124] In one exemplary embodiment, the signal of the reset control signal line Reset and the signal of the first scan signal line Gate1 are cascaded signals, that is, the signal of the reset control signal line Reset and the signal of the first scan signal line Gate1 can originate from a set of cascaded array substrate gate driver on array (GOA) circuits.

[0125] The following example uses the pixel circuit provided in this disclosure, where the second transistor T2 to the first transistor T1 are all N-type thin-film transistors, as an example. Figure 10 The pixel circuit shown and Figure 14 The timing diagram shown provides a detailed description of the operation of a pixel circuit unit within one frame cycle in normal display mode, where 1H represents one horizontal scan cycle. Figure 10As shown, the pixel circuit provided in this embodiment includes seven transistor units (T1-T7), one capacitor unit (C1), and four power lines (VDD, VSS, Data, and INIT). The first power line VDD continuously provides a high-level signal, and the second power line VSS continuously provides a low-level signal. In an exemplary embodiment, in normal display mode, as... Figure 14 As shown, the operation of this pixel circuit within one frame period includes:

[0126] In the first stage, t1, also known as the reset stage, the signals on the first scan signal line Gate1 and the light-emitting control signal line EM are low, while the signals on the reset control signal line Reset and the second scan signal line Gate2 are high. The low-level signal on the light-emitting control signal line EM turns off the sixth transistor T6 and the seventh transistor T7. The high-level signal on the second scan signal line Gate2 turns on the second transistor T2, resetting the voltage at the fourth node N4 to the initial voltage provided by the initial voltage line INIT. The high-level signal on the reset control signal line Reset turns on the first transistor T1, thus resetting the voltage at the first node N1 to the first voltage Vdd provided by the first power supply line VDD. The low-level signal on the first scan signal line Gate1 turns off the third transistor T3 and the fifth transistor T5. Because the sixth transistor T6 and the seventh transistor T7 are off, the light-emitting element EL does not emit light during this stage.

[0127] In the second stage, t2, known as the data writing stage, the reset control signal line Reset and the light emission control signal line EM are at low levels, while the first scan signal line Gate1 and the second scan signal line Gate2 are at high levels. The high level signal on the first scan signal line Gate1 turns on the fifth transistor T5 and the third transistor T3, and the data signal line Data outputs a data voltage. During this stage, since the first node N1 is at a high level, the fourth transistor T4 is turned on. The data voltage output from the data signal line Data is supplied to the first node N1 via the turned-on fifth transistor T5, the third node N3, the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3. The sum of the data voltage output from the data signal line Data and the threshold voltage of the fourth transistor T4 is charged into the first capacitor C1. The voltage at the second terminal of the first capacitor C1 (first node N1) is Vdata + Vth, where Vdata is the data voltage output from the data signal line Data, and Vth is the threshold voltage of the fourth transistor T4. A low-level signal on the light-emitting control signal line EM turns off the sixth transistor T6 and the seventh transistor T7, ensuring that the light-emitting element EL does not emit light.

[0128] The third stage, t3, is called the light-emitting stage. During this stage, the reset control signal line Reset, the first scan signal line Gate1, and the second scan signal line Gate2 are all at low levels, while the light-emitting control signal line EM is at a high level. The high-level signal on the light-emitting control signal line EM turns on the sixth transistor T6 and the seventh transistor T7. The power supply voltage output from the first power supply line VDD then provides a driving voltage to the first terminal (i.e., the fourth node N4) of the light-emitting element EL through the conducting sixth transistor T6, fourth transistor T4, and seventh transistor T7, driving the light-emitting element EL to emit light.

[0129] The voltage values ​​of the first node N1 to the fourth node N4 at each stage are shown in Table 1. Among them, when the fourth node N4 (i.e., the anode of the light-emitting element EL) changes from the initial voltage Vinit provided by the initial voltage line INIT to the anode voltage Vanode, the difference between the anode voltage Vanode and the initial voltage Vinit is set as X. During this process, the first node N1 and the third node N3 also change by X.

[0130]

[0131] Table 1

[0132] During the pixel circuit driving process, the driving current flowing through the fourth transistor T4 (i.e., the driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage of the first node N1 is Vdata + Vth, the driving current of the fourth transistor T4 is:

[0133] I = K * (Vgs - Vth) 2 =K*[(Vdata+Vth-Vinit)-Vth] 2 =K*[(Vdata -Vinit)] 2

[0134] Where I is the driving current flowing through the fourth transistor T4, which is the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the fourth transistor T4, Vth is the threshold voltage of the fourth transistor T4, Vdata is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply line VDD.

[0135] As can be seen from the above formula, the current I flowing through the light-emitting element EL is independent of the threshold voltage Vth of the fourth transistor T4, thus eliminating the influence of the threshold voltage Vth of the fourth transistor T4 on the current I and ensuring the uniformity of brightness.

[0136] Based on the above working timing, the pixel circuit eliminates the residual positive charge of the light-emitting element EL after the last emission, realizes the compensation of the gate voltage of the driving transistor, avoids the influence of the threshold voltage drift of the driving transistor on the driving current of the light-emitting element EL, and improves the uniformity of the displayed image and the display quality of the display panel.

[0137] like Figure 15 As shown, in low-frequency display mode, a display cycle is divided into one refresh frame stage and several hold frame stages. The refresh frame is the screen refresh frame, i.e., the data update frame. In the hold frame, the data is held and locked at the first node N1 (the control electrode of the driving transistor), and no refresh occurs. However, to keep flicker invisible, the light-emitting element EL is usually continuously reset to form a display frequency of 60Hz or higher. Therefore, during the hold frame stage, the anode of the light-emitting element EL is also reset at a frequency of 60Hz or higher, meaning the light-emitting control signal line EM needs to be continuously refreshed.

[0138] like Figure 15 As shown, the first scan signal line Gate1 and the reset control signal line Reset work in conjunction with the data signal line Data to achieve low-frequency refresh, refreshing pixels line by line only during the refresh frame phase. Meanwhile, the light emission control signal line EM and the second scan signal line continue to refresh line by line at 60Hz or 120Hz, thus achieving high-frequency refresh of the light-emitting elements (ELs) and mitigating flicker caused by differences in EL brightness during data refresh. Since the signals of the first scan signal line Gate1 and the reset control signal line Reset share a common array substrate row driver (GOA), and both signals remain unchanged during the low-frequency hold frame phase, the array substrate row driver (GOA) circuits of the first scan signal line Gate1 and the reset control signal line Reset do not refresh during the low-frequency hold frame phase, thereby reducing power consumption.

[0139] When the display frequency is 60Hz, data can be updated in 1 / 60s (timing includes the aforementioned reset phase, data writing phase, and light-up phase), and the data is held for the remaining 59 / 60s (timing includes the sequentially repeated light-up and light-down phases). That is, the timing of each control signal in the remaining 59 / 60s is the same as the timing of each control signal in the hold frame phase. Using this method, the screen is updated every minute.

[0140] In another exemplary embodiment, Figure 16 Another equivalent circuit diagram provided for embodiments of this disclosure, such as Figure 16 As shown, in the pixel circuit of this embodiment, the second reset sub-circuit includes a second transistor T2 and an eighth transistor T8.

[0141] One end of the first capacitor C1 is connected to the first node N1, and the other end of the first capacitor C1 is connected to the second terminal of the eighth transistor T8.

[0142] The control electrode of the second transistor T2 is connected to the second scan signal line Gate2, the first electrode of the second transistor T2 is connected to the initial signal line INIT, and the second electrode of the second transistor T2 is connected to the fourth node N4.

[0143] The control electrode of the eighth transistor T8 is connected to the third scan signal line Gate3, and the first electrode of the eighth transistor T8 is connected to the fourth node.

[0144] Figure 16 Another exemplary structure of the second reset sub-circuit is shown. Compared with the pixel circuit of the aforementioned embodiment, Figure 16 The pixel circuit shown is equivalent to in Figure 10 In the pixel circuit shown, an eighth transistor T8 has been added. Those skilled in the art will readily understand that for… Figure 11 , Figure 12 and Figure 13 The structure of the second reset circuit in this embodiment is also applicable to the pixel circuit shown.

[0145] In an exemplary embodiment, in normal display mode, the signal of the third scan signal line Gate3 is the same as the signal of the second scan signal line Gate2. During the hold frame phase, the signal of the third scan signal line Gate3 is the same as the signal of the light emission control signal line EM. Alternatively, the third scan signal line Gate3 continuously provides a low-level signal so that the eighth transistor T8 is turned off during the hold frame phase.

[0146] In an exemplary implementation, in normal display mode, such as Figure 17 As shown, Figure 16 The operation of the pixel circuit shown within one frame period includes:

[0147] In the first stage, A1, also known as the reset stage, the signals on the first scan signal line Gate1 and the light-emitting control signal line EM are low, while the signals on the reset control signal line Reset, the second scan signal line Gate2, and the third scan signal line Gate3 are high. The low-level signal on the light-emitting control signal line EM turns off the sixth transistor T6 and the seventh transistor T7. The high-level signal on the second scan signal line Gate2 turns on the second transistor T2, and the high-level signal on the third scan signal line Gate3 turns on the eighth transistor T8. The voltage at the fourth node N4 and the first terminal (lower plate of the first capacitor C1) is reset to the initial voltage provided by the initial voltage line INIT. The high-level signal on the reset control signal line Reset turns on the first transistor T1, thus resetting the voltage at the first node N1 to the first voltage Vdd provided by the first power supply line VDD. The low-level signal on the first scan signal line Gate1 turns off the third transistor T3 and the fifth transistor T5. Because the sixth transistor T6 and the seventh transistor T7 are off, the light-emitting element EL does not emit light during this stage.

[0148] In the second stage, A2, known as the data writing stage, the reset control signal line Reset and the light emission control signal line EM are at low levels, while the first scan signal line Gate1, the second scan signal line Gate2, and the third scan signal line Gate3 are at high levels. The high level signal on the first scan signal line Gate1 turns on the fifth transistor T5 and the third transistor T3, and the data signal line Data outputs a data voltage. Since the first node N1 is at a high level during this stage, the fourth transistor T4 is turned on. The data voltage output from the data signal line Data is supplied to the first node N1 via the turned-on fifth transistor T5, the third node N3, the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3. The sum of the data voltage output from the data signal line Data and the threshold voltage of the fourth transistor T4 is charged into the first capacitor C1. The voltage at the second terminal of the first capacitor C1 (first node N1) is Vdata + Vth, where Vdata is the data voltage output from the data signal line Data, and Vth is the threshold voltage of the fourth transistor T4. A low-level signal on the light-emitting control signal line EM turns off the sixth transistor T6 and the seventh transistor T7, ensuring that the light-emitting element EL does not emit light.

[0149] The third stage, t3, is called the light-emitting stage. During this stage, the reset control signal line Reset, the first scan signal line Gate1, the second scan signal line Gate2, and the third scan signal line Gate3 are all low-level signals, while the light-emitting control signal line EM is high-level. The high-level signal on the light-emitting control signal line EM turns on the sixth transistor T6 and the seventh transistor T7. The power supply voltage output from the first power line VDD provides a driving voltage to the first terminal (i.e., the fourth node N4) of the light-emitting element EL through the turned-on sixth transistor T6, fourth transistor T4, and seventh transistor T7, driving the light-emitting element EL to emit light.

[0150] like Figure 18 As shown, the first scan signal line Gate1 and the reset control signal line Reset work in conjunction with the data signal line Data to perform low-frequency refresh, refreshing pixels line by line only during the refresh frame phase. Meanwhile, the light emission control signal line EM, the second scan signal line Gate2, and the third scan signal line Gate3 still refresh line by line at 60Hz or 120Hz, thereby achieving high-frequency refresh of the light-emitting elements (ELs) and mitigating flicker caused by differences in EL brightness during data refresh. Since the signals of the first scan signal line Gate1 and the reset control signal line Reset share a common array substrate row driver (GOA), and both signals remain unchanged during the low-frequency hold frame phase, the array substrate row driver (GOA) circuits of the first scan signal line Gate1 and the reset control signal line Reset do not refresh during the low-frequency hold frame phase, thus reducing power consumption. In this embodiment, since the signals of the second scan signal line Gate2 and the third scan signal line Gate3 are exactly opposite during the hold frame phase, the second reset circuit (the second transistor T2 and the eighth transistor T8) is turned off, and the voltage of the first terminal (the lower plate of the first capacitor C1) is not affected by the initial signal line INIT. In some other exemplary embodiments, during the hold frame phase, the third scan signal line Gate3 can also continuously provide a low-level signal, thereby keeping the eighth transistor T8 off during the hold frame phase, which also makes the voltage of the first terminal (the lower plate of the first capacitor C1) unaffected by the initial signal line INIT.

[0151] In this embodiment, the eighth transistor T8 acts as a blocking transistor to prevent the second transistor T2 from periodically turning on due to the signal of the second scan signal line during the holding frame stage, thereby causing the voltage of the first terminal (lower plate of the first capacitor C1) to be periodically reset.

[0152] Some embodiments of this disclosure also provide a driving method for a pixel circuit, applied to the pixel circuit provided in the foregoing embodiments. The pixel circuit operates in a first display mode or a second display mode. The first display mode includes a plurality of first display cycles. Within one first display cycle, the driving method includes:

[0153] During the reset phase, the first reset sub-circuit resets the first node under the control of the reset control signal line; the second reset sub-circuit resets the anode of the light-emitting element under the control of the second scan signal line.

[0154] During the data writing phase, the writing sub-circuit, under the control of the signal of the first scan signal line, writes the signal of the data signal line to the second or third node; the compensation sub-circuit, under the control of the signal of the first scan signal line, compensates the voltage of the first node.

[0155] During the light-emitting phase, the driving sub-circuit responds to the signals from the first and second nodes by providing a driving signal to the third node. For example, this driving signal is a driving current.

[0156] In one exemplary embodiment, the driving method further includes:

[0157] During the light-emitting stage, the first light-emitting control sub-circuit, under the control of the light-emitting control signal line, writes the signal of the first power line into the second node; the second light-emitting control sub-circuit, under the control of the light-emitting control signal line, forms a current path between the third and fourth nodes.

[0158] In one exemplary embodiment, the second display mode includes a plurality of second display cycles, and one second display cycle includes a refresh phase and a plurality of hold phases;

[0159] The refresh phase includes a reset phase, a data writing phase, and a light emission phase, which are set sequentially.

[0160] The holding phase includes a light-emitting phase and an extinguishing phase, with the light-emitting phase and the extinguishing phase being set at intervals;

[0161] During the extinction phase, the second reset circuit, under the control of the signal from the second scan signal line, resets the anode of the light-emitting element.

[0162] In one exemplary embodiment, the first display mode may be a normal display mode, and the second display mode may be a low-frequency display mode or an AOD mode.

[0163] In one exemplary embodiment, the first frequency can be 60Hz or 120Hz. The second frequency can be 1Hz or 0.1Hz. The third frequency can be 60Hz or 120Hz.

[0164] This disclosure also provides a display device, which includes the pixel circuit provided in the above embodiments. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. In an exemplary embodiment, the display device can be a wearable display device, which can be worn on the human body in some way, such as a smartwatch or smart bracelet.

[0165] The following points need to be explained:

[0166] The accompanying drawings of the embodiments disclosed herein only involve the structures involved in the embodiments of this disclosure; other structures can be referred to in the general design.

[0167] Where there is no conflict, the embodiments of this disclosure, i.e. the features in the embodiments, can be combined with each other to obtain new embodiments.

[0168] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel circuit, comprising a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a first reset sub-circuit, a second reset sub-circuit, a first light emission control sub-circuit, a second light emission control sub-circuit, and a light emission element, wherein: The driving sub-circuit is connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node in response to the signals of the first node and the second node; The writing sub-circuit is connected to the first scan signal line and the data signal line respectively, and is also connected to the second node or the third node. It is configured to write the signal of the data signal line to the second node or the third node under the control of the signal of the first scan signal line. The compensation sub-circuit is connected to the first scan signal line and the first node respectively, and is configured to compensate the voltage of the first node under the control of the signal of the first scan signal line. The first reset sub-circuit is connected to the reset control signal line and the first node respectively, and is also connected to the reference power line or the first power line. It is configured to reset the first node under the control of the signal of the reset control signal line. The second reset sub-circuit is connected to the second scan signal line, the initial signal line, and the anode of the light-emitting element, respectively, and is configured to reset the anode of the light-emitting element under the control of the signal of the second scan signal line. The first light-emitting control sub-circuit is connected to the first power line, the light-emitting control signal line and the second node respectively, and is configured to write the signal of the first power line into the second node under the control of the signal of the light-emitting control signal line; The second light-emitting control sub-circuit is connected to the light-emitting control signal line, the third node, and the anode of the light-emitting element, respectively, and is configured to form a current path between the third node and the anode of the light-emitting element under the control of the signal of the light-emitting control signal line. The second reset sub-circuit includes a second transistor and an eighth transistor, and the compensation sub-circuit includes a third transistor and a first capacitor; the control electrode of the second transistor is connected to the second scan signal line, the first electrode of the second transistor is connected to the initial signal line, and the second electrode of the second transistor is connected to the anode of the light-emitting element; the control electrode of the eighth transistor is connected to the third scan signal line, and the first electrode of the eighth transistor is connected to the anode of the light-emitting element. The control electrode of the third transistor is connected to the first scan signal line, the first electrode of the third transistor is connected to the third node or the second node, and the second electrode of the third transistor is connected to the first node; one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the second electrode of the eighth transistor.

2. The pixel circuit according to claim 1, wherein, The first reset circuit includes a first transistor; The control electrode of the first transistor is connected to the reset control signal line, the first electrode of the first transistor is connected to the first power supply line or the reference power supply line, and the second electrode of the first transistor is connected to the first node.

3. The pixel circuit according to claim 1, wherein, The driving sub-circuit includes a fourth transistor, and the writing sub-circuit includes a fifth transistor; The control electrode of the fourth transistor is connected to the first node, the first electrode of the fourth transistor is connected to the second node, and the second electrode of the fourth transistor is connected to the third node; The control electrode of the fifth transistor is connected to the first scan signal line, the first electrode of the fifth transistor is connected to the data signal line, and the second electrode of the fifth transistor is connected to the second node.

4. The pixel circuit according to claim 3, wherein, The first light-emitting control sub-circuit includes a sixth transistor, and the second light-emitting control sub-circuit includes a seventh transistor; The control electrode of the sixth transistor is connected to the light-emitting control signal line, the first electrode of the sixth transistor is connected to the first power supply line, and the second electrode of the sixth transistor is connected to the second node; The control electrode of the seventh transistor is connected to the light-emitting control signal line, the first electrode of the seventh transistor is connected to the third node, and the second electrode of the seventh transistor is connected to the anode of the light-emitting element.

5. The pixel circuit according to claim 1, wherein: The reset control signal line, the first scan signal line, and the second scan signal line are also configured to receive signals of different frequencies according to the display mode of the display panel.

6. The pixel circuit according to claim 5, wherein receiving signals of different frequencies according to the display mode of the display panel includes: When the display panel is in the first display mode, the data refresh frequency of the pixel circuit is the first frequency, and the reset control signal line, the first scan signal line and the second scan signal line are configured to receive signals of the first frequency. When the display panel is in the second display mode, the data refresh frequency of the pixel circuit is the second frequency, the reset control signal line and the first scan signal line are configured to receive signals at the second frequency, the second scan signal line is configured to receive signals at a third frequency, the third frequency is greater than the second frequency, and the first frequency is greater than the second frequency.

7. The pixel circuit according to claim 1, wherein: The signals of the reset control signal line and the first scan signal line are cascaded signals.

8. The pixel circuit according to claim 1, wherein, The first reset sub-circuit includes a first transistor, the driving sub-circuit includes a fourth transistor, the writing sub-circuit includes a fifth transistor, the first light-emitting control sub-circuit includes a sixth transistor, and the second light-emitting control sub-circuit includes a seventh transistor. The control electrode of the first transistor is connected to the reset control signal line, the first electrode of the first transistor is connected to the first power supply line or the reference power supply line, and the second electrode of the first transistor is connected to the first node. The control electrode of the fourth transistor is connected to the first node, the first electrode of the fourth transistor is connected to the second node, and the second electrode of the fourth transistor is connected to the third node; The control electrode of the fifth transistor is connected to the first scan signal line, the first electrode of the fifth transistor is connected to the data signal line, and the second electrode of the fifth transistor is connected to the second node or the third node. The control electrode of the sixth transistor is connected to the light emission control signal line, the first electrode of the sixth transistor is connected to the first power supply line, and the second electrode of the sixth transistor is connected to the second node; The control electrode of the seventh transistor is connected to the light-emitting control signal line, the first electrode of the seventh transistor is connected to the third node, and the second electrode of the seventh transistor is connected to the anode of the light-emitting element.

9. The pixel circuit according to claim 8, wherein, When the display panel is in the refresh phase, the signal of the third scan signal line is the same as the signal of the second scan signal line; When the display panel is in the hold phase, the signal of the third scan signal line is opposite to the signal of the second scan signal line; or, when the display panel is in the hold phase, the signal of the third scan signal line causes the eighth transistor to remain off.

10. A display device comprising the pixel circuitry according to any one of claims 1 to 9.

11. A driving method for a pixel circuit, used to drive the pixel circuit as described in any one of claims 1 to 9, the pixel circuit operating in a first display mode or a second display mode, the first display mode including a plurality of first display cycles, wherein within one first display cycle, the driving method includes: During the reset phase, the first reset sub-circuit resets the first node under the control of the reset control signal line. The second reset circuit resets the anode of the light-emitting element under the control of the signal from the second scan signal line. During the data writing phase, the writing sub-circuit, under the control of the signal of the first scan signal line, writes the signal of the data signal line to the second or third node. The compensation sub-circuit compensates for the voltage of the first node under the control of the signal from the first scan signal line; During the light-emitting phase, the driving sub-circuit responds to the signals of the first node and the second node and provides a driving signal to the third node. Under the control of the signal of the light-emitting control signal line, the first light-emitting control sub-circuit writes the signal of the first power line into the second node. Under the control of the signal of the light-emitting control signal line, the second light-emitting control sub-circuit forms a current path between the third node and the anode of the light-emitting element.

12. The driving method according to claim 11, wherein, The second display mode includes multiple second display cycles, each including a refresh phase and a hold phase; The refresh phase includes the reset phase, the data writing phase, and the light emission phase, which are set sequentially. The holding phase includes multiple light-emitting phases and multiple extinguishing phases, with the light-emitting phases and extinguishing phases spaced apart. During the extinguishing phase, the second reset sub-circuit resets the anode terminal of the light-emitting element under the control of the signal from the second scan signal line.

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