Low dropout linear voltage regulator and chip
By combining error amplifiers, compensation capacitors, feedback resistors, and other structures, the problem of strong output capacitor dependence in low dropout linear regulators is solved, achieving fast response and stable output across the entire load range and ensuring loop stability.
Patent Information
- Application Number
- CN202310250523.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-03-14
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2043-03-14
AI Technical Summary
Existing low-dropout linear regulators suffer from the problem that the output capacitor cannot be omitted and that stability is difficult to compensate for across the entire load range. This results in a strong dependence of the output voltage on the output capacitor, making it difficult to achieve fast response and stable output.
The system employs a combination of an error amplifier, a first compensation capacitor, a comparator amplifier, a second compensation capacitor, an output power transistor, a first feedback resistor, a second feedback resistor, a load capacitor, and a load resistor to eliminate the dependence of the output voltage on the output capacitor. Through the design of the dominant and secondary poles, it achieves fast response and stable output across the entire load variation range.
It effectively eliminates the dependence of the output voltage on the output capacitor, ensures loop stability in the absence of an output capacitor, and achieves fast response and stable output across the entire load range.
Smart Images
Figure CN116225127B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically to a low-dropout linear regulator and its chip. Background Technology
[0002] In large-scale integrated circuit systems, low-dropout linear regulators (LDLs) are an essential part of power management. LDLs provide integrated circuit systems with stable supply voltage and load current with high accuracy and high power supply rejection ratio (PSRR). Furthermore, in power management applications for mobile terminals, low voltage, low power consumption, and simplified peripheral components are increasingly becoming mainstream requirements.
[0003] However, existing low-dropout linear regulator architectures suffer from problems such as the inability to omit the output capacitor and difficulty in compensating for stability across the entire load range. Summary of the Invention
[0004] The purpose of this invention is to provide a low dropout linear regulator and chip that can effectively eliminate the dependence of the output voltage on the output capacitor and can achieve fast response and stable output across the entire load range, thereby ensuring loop stability in the absence of an output capacitor.
[0005] To achieve the above objectives, a first aspect of the present invention provides a low-dropout linear regulator, comprising: an error amplifier, a first compensation capacitor, a comparator amplifier, a second compensation capacitor, an output power transistor, a first feedback resistor, a second feedback resistor, a load capacitor, and a load resistor, wherein the high-impedance output terminal of the error amplifier is connected to the input terminal of the comparator amplifier; one plate of the first compensation capacitor is connected to the high-impedance output terminal of the error amplifier, and the other plate of the first compensation capacitor is connected to the output terminal of the output power transistor; the output terminal of the comparator amplifier is connected to the input terminal of the output power transistor; one plate of the second compensation capacitor is connected to the low-impedance output terminal of the error amplifier, and the other plate of the second compensation capacitor is connected to the output terminal of the comparator amplifier.
[0006] Preferably, the low dropout linear regulator further includes: a third compensation capacitor, one plate of which is connected to the output terminal of the comparator amplifier, and the other plate of which is connected to the output terminal of the output power transistor.
[0007] Preferably, the error amplifier includes: a first P-type MOS transistor, a second P-type MOS transistor, a first N-type MOS transistor, and a second N-type MOS transistor, wherein the source of the first P-type MOS transistor is connected to the source of the second P-type MOS transistor, and the drain of the first P-type MOS transistor, the drain and gate of the first N-type MOS transistor, and the gate of the second N-type MOS transistor are connected to each other; and the drain of the second P-type MOS transistor is connected to the drain of the second N-type MOS transistor, wherein the source of the first N-type MOS transistor is connected to the source of the second N-type MOS transistor.
[0008] Preferably, the comparator amplifier is a current comparator.
[0009] Preferably, the current comparator includes: a third P-type MOSFET, a fourth P-type MOSFET, a fifth P-type MOSFET, a sixth P-type MOSFET, a seventh P-type MOSFET, an eighth P-type MOSFET, a ninth P-type MOSFET, a third N-type MOSFET, a fourth N-type MOSFET, a fifth N-type MOSFET, a sixth N-type MOSFET, a seventh N-type MOSFET, and an eighth N-type MOSFET, wherein the sources of the third P-type MOSFET, the fourth P-type MOSFET, the fifth P-type MOSFET, the sixth P-type MOSFET, the seventh P-type MOSFET, the eighth P-type MOSFET, and the ninth P-type MOSFET are connected to each other, and the gate and drain of the third P-type MOSFET, the gate of the fourth P-type MOSFET, and the drain of the third N-type MOSFET are connected to each other; the drain of the fourth P-type MOSFET, the drain of the fifth P-type MOSFET, and the gate of the fifth P-type MOSFET are connected to each other. The gates of the sixth P-type MOS transistor, the seventh P-type MOS transistor, and the drain of the fourth N-type MOS transistor are connected to each other; the drains of the sixth P-type MOS transistor, the fifth N-type MOS transistor, the seventh N-type MOS transistor, and the eighth N-type MOS transistor are connected to each other; and the drains of the seventh P-type MOS transistor, the eighth P-type MOS transistor, the ninth P-type MOS transistor, and the sixth N-type MOS transistor are connected to each other, wherein the sources of the third N-type MOS transistor, the fourth N-type MOS transistor, the fifth N-type MOS transistor, the sixth N-type MOS transistor, the seventh N-type MOS transistor, and the eighth N-type MOS transistor are connected to each other, and the gates of the third N-type MOS transistor, the fifth N-type MOS transistor, and the sixth N-type MOS transistor are connected to each other.
[0010] Preferably, the low-dropout linear regulator further includes a current source connected in series between the source of the third P-type MOSFET and the source of the first P-type MOSFET.
[0011] Preferably, the output power transistor is a 10P type MOS transistor.
[0012] Preferably, the first feedback resistor and the second feedback resistor are connected in series, one end of the first feedback resistor is connected to the output terminal of the output power transistor, and the other end of the first feedback resistor is connected to the inverting input terminal of the error amplifier.
[0013] Preferably, the load capacitor, the load resistor, and the series circuit of the first feedback resistor and the second feedback resistor are connected in parallel.
[0014] Through the above technical solution, this invention creatively sets up an error amplifier, a first compensation capacitor, a comparator amplifier, a second compensation capacitor, an output power transistor, a first feedback resistor, a second feedback resistor, a load capacitor, and a load resistor to form a low-dropout linear regulator. The high-impedance output terminal of the error amplifier is connected to the input terminal of the comparator amplifier; one plate of the first compensation capacitor is connected to the high-impedance output terminal of the error amplifier, and the other plate of the first compensation capacitor is connected to the output terminal of the output power transistor; the output terminal of the comparator amplifier is connected to the input terminal of the output power transistor; one plate of the second compensation capacitor is connected to the low-impedance output terminal of the error amplifier, and the other plate of the second compensation capacitor is connected to the output terminal of the comparator amplifier. Therefore, the above-mentioned capacitor-free low-dropout linear regulator effectively eliminates the dependence of the output voltage on the output capacitor and generates a dominant pole and a secondary pole associated with the load capacitor, thereby achieving fast response and stable output across the entire load variation range, and ensuring loop stability in the absence of an output capacitor.
[0015] A second aspect of the present invention provides a chip, the chip comprising: the aforementioned low-dropout linear regulator.
[0016] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description
[0017] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:
[0018] Figure 1 This is a schematic diagram of the structure of a low-dropout linear regulator provided in an embodiment of the present invention;
[0019] Figure 2 This is a schematic diagram of the structure of a low-dropout linear regulator provided in an embodiment of the present invention; and
[0020] Figure 3 This is a schematic diagram of a low-dropout linear regulator provided in an embodiment of the present invention. Detailed Implementation
[0021] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.
[0022] Figure 1 This is a schematic diagram of a low-dropout linear regulator provided in an embodiment of the present invention. Figure 1 As shown, the low dropout linear regulator may include: an error amplifier 10 (i.e., S1), a first compensation capacitor 20 (i.e., CM1), a comparator amplifier 30 (i.e., S2), a second compensation capacitor 40 (i.e., CM2), an output power transistor 50 (i.e., S3), a first feedback resistor 60 (i.e., R1), a second feedback resistor 70 (i.e., R2), a load capacitor 80 (i.e., CLOAD), and a load resistor 90 (i.e., RLOAD).
[0023] In this configuration, the high-impedance output terminal of the error amplifier 10 (i.e., S1) is connected to the input terminal of the comparator amplifier 30 (i.e., S2); one plate of the first compensation capacitor 20 (i.e., CM1) is connected to the high-impedance output terminal (i.e., high-impedance point v1) of the error amplifier 10 (i.e., S1), and the other plate of the first compensation capacitor 20 (i.e., CM1) is connected to the output terminal (i.e., VOUT) of the output power transistor 50 (i.e., S3); the output terminal of the comparator amplifier 30 (i.e., S2) is connected to the input terminal of the output power transistor 50 (i.e., S3); one plate of the second compensation capacitor 40 (i.e., CM2) is connected to the low-impedance output terminal (i.e., low-impedance point v2) of the error amplifier 10 (i.e., S1), and the other plate of the second compensation capacitor 40 (i.e., CM2) is connected to the output terminal of the comparator amplifier 30 (i.e., S2).
[0024] The comparator amplifier can be a current comparator. That is, the second amplification stage can adopt the structure of a current comparator, which can bring better matching and help to quickly transmit the feedback signal when the output load changes, thereby improving the transient response of the loop.
[0025] The schematic diagram of the novel low-dropout linear regulator without output capacitor provided in this embodiment is as follows: Figure 1As shown. The open-loop gain of the error amplifier 10 consists of an input amplification stage S1, a current amplification stage S2, and an output amplifier S3. CM1 serves as the Miller capacitor that generates the dominant pole; CM2 serves as the adjustment compensation capacitor that generates the secondary pole when there is no output capacitor. Specifically, the locations of the dominant and secondary poles are described below.
[0026] The location of the dominant pole is determined by the Miller capacitance CM1 and the output impedance of the high-impedance point v1 of the input amplifier stage S1. The location of this dominant pole is fixed.
[0027] The location of the secondary pole is determined by the load capacitance CLOAD at the output terminal VOUT and the output impedance. This secondary pole's location changes with the load capacitance CLOAD. Since the output capacitor COUT is eliminated, the capacitance of the output terminal VOUT depends on the capacitance value CLOAD, and therefore the equivalent value of this output capacitor may have a large range of variation. Thus, when the CLOAD value is small, a low-impedance point v2 is introduced at the first stage output. The output impedance at v2 and the adjustment compensation capacitor CM2 form an adjustment pole. In other words, when the CLOAD value is small, this adjustment pole acts as the location of the secondary pole, thereby adjusting the gain-bandwidth product (GBW) frequency point and ensuring loop stability without an output capacitor; and the location of this adjustment pole is fixed. In summary, when the CLOAD value is large, the location of the secondary pole is determined by CLOAD and the output impedance; when the CLOAD value is small, the location of the secondary pole is determined by CM2 and the output impedance of the low-impedance point v2.
[0028] In one embodiment, the low-dropout linear regulator may further include: a third compensation capacitor 100 (i.e., CM3), one plate of which is connected to the output terminal of the comparator amplifier 30 (i.e., S2), and the other plate of which is connected to the output terminal (i.e., VOUT) of the output power transistor 50 (i.e., S3). Figure 2 As shown.
[0029] Specifically, the location of the third pole is determined by the output impedance of the current amplification stage S2 and the adjustment compensation capacitor CM3. The location of this pole will change accordingly with the load, but in any case, its frequency is far beyond the gain-bandwidth product GBW. It is only used to adjust the gain margin at high frequencies and does not affect the normal operation of the loop.
[0030] The specific structures of the first amplification stage (i.e., error amplifier 10), the second amplification stage (i.e., comparator amplifier 30), and the third amplification stage (i.e., output power transistor 50) are described below.
[0031] like Figure 3 As shown, the error amplifier 10 (i.e., S1) may include: a first P-type MOS transistor 1 (i.e. MP1), a second P-type MOS transistor 2 (i.e. MP2), a first N-type MOS transistor 11 (i.e. MN1), and a second N-type MOS transistor 12 (i.e. MN2).
[0032] The source of the first P-type MOSFET 1 (MP1) is connected to the source of the second P-type MOSFET 2 (MP2); the drain of the first P-type MOSFET 1 (MP1), the drain and gate of the first N-type MOSFET 11 (MN1), and the gate of the second N-type MOSFET 12 (MN2) are connected to each other. The drain of the second P-type MOSFET 2 (MP2) is connected to the drain of the second N-type MOSFET 12 (MN2).
[0033] The source of the first N-type MOS transistor 11 (MN1) is connected to the source of the second N-type MOS transistor 12 (MN2).
[0034] Specifically, the gate of the second P-type MOSFET 2 (MP2) can be used as the non-inverting input of the error amplifier 10 (S1); the gate of the first P-type MOSFET 1 (MP1) can be used as the inverting input of the error amplifier 10 (S1). The drain of the second P-type MOSFET 2 (MP2) or the drain of the second N-type MOSFET 12 (MN2) can be used as the high-impedance output (high-impedance point v1) of the error amplifier 10 (S1); and the drain of the first P-type MOSFET 1 (MP1), the drain or gate of the first N-type MOSFET 11 (MN1), or the gate of the second N-type MOSFET 12 (MN2) can be used as the low-impedance output (low-impedance point v2) of the error amplifier 10 (S1).
[0035] like Figure 3 As shown, when the comparator amplifier 20 adopts a current comparator structure, the current comparator may include: a third P-type MOSFET 3 (i.e., MP3), a fourth P-type MOSFET 4 (i.e., MP4), a fifth P-type MOSFET 5 (i.e., MP5), a sixth P-type MOSFET 6 (i.e., MP6), a seventh P-type MOSFET 7 (i.e., MP7), an eighth P-type MOSFET 8 (i.e., MP8), a ninth P-type MOSFET 9 (i.e., MP9), a third N-type MOSFET 13 (i.e., MN3), a fourth N-type MOSFET 14 (i.e., MN4), a fifth N-type MOSFET 15 (i.e., MN5), a sixth N-type MOSFET 16 (i.e., MN6), a seventh N-type MOSFET 17 (i.e., MN7), and an eighth N-type MOSFET 18 (i.e., MN8).
[0036] The sources of the third P-type MOS transistor 3 (MP3), the fourth P-type MOS transistor 4 (MP4), the fifth P-type MOS transistor 5 (MP5), the sixth P-type MOS transistor 6 (MP6), the seventh P-type MOS transistor 7 (MP7), the eighth P-type MOS transistor 8 (MP8), and the ninth P-type MOS transistor 9 (MP9) are connected to each other; the gate and drain of the third P-type MOS transistor 3 (MP3), the gate of the fourth P-type MOS transistor 4 (MP4), and the drain of the third N-type MOS transistor 13 (MN3) are connected to each other. The drain of the fourth P-type MOSFET 4 (MP4), the drain and gate of the fifth P-type MOSFET 5 (MP5), the gate of the sixth P-type MOSFET 6 (MP6), the gate of the seventh P-type MOSFET 7 (MP7), and the drain of the fourth N-type MOSFET 14 (MN4) are connected to each other. The drain of the sixth P-type MOSFET 6 (MP6), the drain of the fifth N-type MOSFET 15 (MN5), the drain and gate of the seventh N-type MOSFET 17 (MN7), and the gate of the eighth N-type MOSFET 18 (MN8) are connected to each other. The drain of the seventh P-type MOSFET 7 (MP7), the drain and gate of the eighth P-type MOSFET 8 (MP8), the gate of the ninth P-type MOSFET 9 (MP9), and the drain of the sixth N-type MOSFET 16 (MN6) are connected to each other.
[0037] The sources of the third N-type MOS transistor 13 (MN3), the fourth N-type MOS transistor 14 (MN4), the fifth N-type MOS transistor 15 (MN5), the sixth N-type MOS transistor 16 (MN6), the seventh N-type MOS transistor 17 (MN7), and the eighth N-type MOS transistor 18 (MN8) are connected to each other; and the gates of the third N-type MOS transistor 13 (MN3), the fifth N-type MOS transistor 15 (MN5), and the sixth N-type MOS transistor 16 (MN6) are connected to each other.
[0038] Specifically, the drain of the third N-type MOSFET 13 (MN3) can be used as the input terminal of the current comparator 20 (S2), which is connected to the high-impedance output terminal (high-impedance point v1) of the error amplifier 10 (S1); the drain of the ninth P-type MOSFET 9 (MP9) can be used as the output terminal of the current comparator 20 (S2). The gate of the fourth N-type MOSFET 14 (MN4) can be connected to the low-impedance output terminal (low-impedance point v2) of the error amplifier 10 (S1).
[0039] like Figure 3 As shown, the output power transistor 50 (i.e., S3) is the tenth P-type MOSFET 101 (i.e., MP10).
[0040] Specifically, the gate of the tenth P-type MOS transistor 101 (i.e., MP10) can be used as the input terminal of the output power transistor 50; the drain of the tenth P-type MOS transistor 101 (i.e., MP10) can be used as the output terminal (i.e., VOUT) of the output power transistor 50.
[0041] In one embodiment, the first feedback resistor 60 (i.e., R1) and the second feedback resistor 70 (i.e., R2) are connected in series. One end of the first feedback resistor 60 (i.e., R1) is connected to the output terminal (i.e., VOUT) of the output power transistor 50 (i.e., S3), and the other end of the first feedback resistor 50 (i.e., S3) is connected to the inverting input terminal of the error amplifier 10 (i.e., S1). Figure 3 As shown.
[0042] In one embodiment, the load capacitor 80 (i.e., CLOAD), the load resistor 90 (i.e., RLOAD), and the series circuit of the first feedback resistor 60 (i.e., R1) and the second feedback resistor 70 (i.e., R2) are connected in parallel, as follows: Figure 3 As shown, the feedback resistor network composed of R1 and R2 feeds back the output voltage VOUT divided signal to the input amplifier stage S1 to maintain stable loop operation.
[0043] In one embodiment, the low dropout linear regulator may further include a current source 102 (i.e., I1), wherein the current source 102 is connected in series between the source of the third P-type MOSFET 3 (i.e., MP3) and the source of the first P-type MOSFET 1 (i.e., MP1).
[0044] Therefore, the above embodiments of the present invention can ensure working response and stability across the entire load variation range by setting the positions of two or three poles.
[0045] In summary, this invention creatively configures an error amplifier, a first compensation capacitor, a comparator amplifier, a second compensation capacitor, an output power transistor, a first feedback resistor, a second feedback resistor, a load capacitor, and a load resistor to form a low-dropout linear regulator. The high-impedance output terminal of the error amplifier is connected to the input terminal of the comparator amplifier; one plate of the first compensation capacitor is connected to the high-impedance output terminal of the error amplifier, and the other plate of the first compensation capacitor is connected to the output terminal of the output power transistor; the output terminal of the comparator amplifier is connected to the input terminal of the output power transistor; one plate of the second compensation capacitor is connected to the low-impedance output terminal of the error amplifier, and the other plate of the second compensation capacitor is connected to the output terminal of the comparator amplifier. Therefore, this capacitor-free low-dropout linear regulator effectively eliminates the dependence of the output voltage on the output capacitor and generates a dominant pole and a secondary pole associated with the load capacitor, thereby achieving fast response and stable output across the entire load range and ensuring loop stability even without an output capacitor.
[0046] One embodiment of the present invention also provides a chip, which may include: the low dropout linear regulator described above.
[0047] For specific details and benefits of the chip provided by this invention, please refer to the above description of the low dropout linear regulator, which will not be repeated here.
[0048] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention.
[0049] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the embodiments of the present invention will not describe the various possible combinations separately.
[0050] Furthermore, various different implementations of the present invention can be combined arbitrarily, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed in the present invention.
Claims
1. A low-dropout linear regulator, characterized in that, The low-dropout linear regulator includes: an error amplifier, a first compensation capacitor, a comparator amplifier, a second compensation capacitor, an output power transistor, a first feedback resistor, a second feedback resistor, a load capacitor, and a load resistor. In this configuration, the high-impedance output terminal of the error amplifier is connected to the input terminal of the comparator amplifier; one plate of the first compensation capacitor is connected to the high-impedance output terminal of the error amplifier, and the other plate of the first compensation capacitor is connected to the output terminal of the output power transistor; the output terminal of the comparator amplifier is connected to the input terminal of the output power transistor; one plate of the second compensation capacitor is connected to the low-impedance output terminal of the error amplifier, and the other plate of the second compensation capacitor is connected to the output terminal of the comparator amplifier. Wherein, the comparator amplifier is a current comparator, and the current comparator includes: The third P-type MOSFET, the fourth P-type MOSFET, the fifth P-type MOSFET, the sixth P-type MOSFET, the seventh P-type MOSFET, the eighth P-type MOSFET, the ninth P-type MOSFET, the third N-type MOSFET, the fourth N-type MOSFET, the fifth N-type MOSFET, the sixth N-type MOSFET, the seventh N-type MOSFET, and the eighth N-type MOSFET. The sources of the third, fourth, fifth, sixth, seventh, eighth, and ninth P-type MOS transistors are interconnected, as are the gate and drain of the third P-type MOS transistor, the gate of the fourth P-type MOS transistor, and the drain of the third N-type MOS transistor. The drain and gate of the sixth P-type MOS transistor, the gate of the seventh P-type MOS transistor, and the drain of the fourth N-type MOS transistor are connected to each other; the drain of the sixth P-type MOS transistor, the drain of the fifth N-type MOS transistor, the drain and gate of the seventh N-type MOS transistor, and the gate of the eighth N-type MOS transistor are connected to each other; and the drain of the seventh P-type MOS transistor, the drain and gate of the eighth P-type MOS transistor, the gate of the ninth P-type MOS transistor, and the drain of the sixth N-type MOS transistor are connected to each other. The sources of the third, fourth, fifth, sixth, seventh, and eighth N-type MOS transistors are connected to each other, and the gates of the third, fifth, and sixth N-type MOS transistors are connected to each other.
2. The low-dropout linear regulator according to claim 1, characterized in that, The low-dropout linear regulator also includes: The third compensation capacitor has one plate connected to the output terminal of the comparator amplifier, and the other plate connected to the output terminal of the output power transistor.
3. The low-dropout linear regulator according to claim 1 or 2, characterized in that, The error amplifier includes: a first P-type MOS transistor, a second P-type MOS transistor, a first N-type MOS transistor, and a second N-type MOS transistor. In this configuration, the source of the first P-type MOS transistor is connected to the source of the second P-type MOS transistor; the drain of the first P-type MOS transistor, the drain and gate of the first N-type MOS transistor, and the gate of the second N-type MOS transistor are connected to each other; and the drain of the second P-type MOS transistor is connected to the drain of the second N-type MOS transistor. The source of the first N-type MOS transistor is connected to the source of the second N-type MOS transistor.
4. The low-dropout linear regulator according to claim 3, characterized in that, The low-dropout linear regulator also includes: A current source is connected in series between the source of the third P-type MOS transistor and the source of the first P-type MOS transistor.
5. The low-dropout linear regulator according to claim 1 or 2, characterized in that, The output power transistor is a 10P type MOS transistor.
6. The low-dropout linear regulator according to claim 1 or 2, characterized in that, The first feedback resistor and the second feedback resistor are connected in series. One end of the first feedback resistor is connected to the output terminal of the output power transistor, and the other end of the first feedback resistor is connected to the inverting input terminal of the error amplifier.
7. The low-dropout linear regulator according to claim 6, characterized in that, The load capacitor, the load resistor, and the series circuit of the first feedback resistor and the second feedback resistor are connected in parallel.
8. A chip, characterized in that, The chip includes: a low-dropout linear regulator according to any one of claims 1-7.
Citation Information
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