A method, system, device and medium for automated chip verification

Abstract

This invention relates to the field of chip verification, and more particularly to an automated chip verification method, system, device, and medium. The method includes: requesting a preset-size address range from the host's memory or the chip's memory as shared memory; in response to the need for the host and chip to transmit test cases to each other, the sending end performs a first verification operation on the test cases to generate a first verification value, initiates a handshake operation with the receiving end, and writes the test cases and the first verification value into the shared memory after the handshake operation is completed; the receiving end reads the test cases and the first verification value from the shared memory, performs a second verification operation on the test cases to generate a second verification value, and compares the second verification value with the first verification value; in response to the comparison results being the same, the receiving end is allowed to execute the test cases. The solution of this invention achieves automated verification by introducing shared memory, and makes test case execution more reliable through transmission verification and handshake mechanisms.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip verification, and in particular to a chip automatic verification method, system, device and medium. BACKGROUND

[0002] In the chip verification process, the host needs to transmit data and configuration instructions to the chip, or the chip needs to notify the host to initiate read and write after configuration is completed. The current common technology will manually configure on the host side and the chip side respectively, which will lead to low verification efficiency, and manual configuration is prone to errors, and the reliability of the verification result is low. SUMMARY

[0003] Therefore, it is necessary to provide a chip automatic verification method, system, device and medium to solve the above technical problems.

[0004] According to a first aspect of the present application, a chip automatic verification method is provided, the method comprising:

[0005] Applying a preset size address segment as a shared memory from the memory of the host or the memory of the chip;

[0006] In response to the host and the chip needing to transmit test cases to each other, the sending end performs a first verification operation on the test case to generate a first verification value, initiates a handshake operation with the receiving end, and writes the test case and the first verification value into the shared memory after the handshake operation is completed;

[0007] The receiving end reads the test case and the first verification value from the shared memory, performs a second verification operation on the test case to generate a second verification value, and compares the second verification value with the first verification value;

[0008] In response to the second verification value being the same as the first verification value, the receiving end is allowed to execute the test case.

[0009] In some embodiments, the host and the chip perform a handshake operation according to the following rules:

[0010] In response to the sending end completing the first verification operation, the sending end pulls the valid signal high;

[0011] In response to the receiving end detecting that the valid signal is pulled high, the receiving end pulls the ready signal high;

[0012] In response to the sending end detecting that the ready signal is pulled high, the sending end and the receiving end complete the handshake operation.

[0013] In some embodiments, the sending end performs a first verification operation on the test case to generate a first verification value, comprising:

[0014] hashing the test case by the sending end to generate the first check value;

[0015] performing a second check operation on the test case to generate a second check value, comprising:

[0016] hashing the test case read from the shared memory by the receiving end to generate the second check value.

[0017] In some embodiments, the method further comprises:

[0018] collecting, by the host and / or the chip, an execution result of the test case at the receiving end, and analyzing the execution result to determine whether the test case is executed correctly.

[0019] In some embodiments, the method further comprises:

[0020] in response to determining that the test case is executed incorrectly, storing, by the host and / or the chip, a log of the test case executed at the receiving end.

[0021] In some embodiments, the test case comprises a test command and test data.

[0022] In some embodiments, the sending end and the receiving end use the shared memory in compliance with the following rules when the sending end writes data into the shared memory and the receiving end reads data from the shared memory:

[0023] in response to the shared memory belonging to the host and the sending end being the host, converting, by an Outbound register group of the iATU, a space address of the shared memory into a PCI bus address for use by the chip;

[0024] in response to the shared memory belonging to the chip and the sending end being the chip, converting, by an Inbound register group of the iATU, a PCI bus address into a bus address accessible by the host for use by the host.

[0025] According to a second aspect of the present application, there is provided a chip automatic verification system, the system comprising:

[0026] an application module configured to apply a preset size of address segment from a memory of the host or a memory of the chip as a shared memory;

[0027] a first check module configured to, in response to the host and the chip needing to transmit test cases to each other, perform a first check operation on the test case by the sending end to generate a first check value, initiate a handshake operation with the receiving end, and write the test case and the first check value into the shared memory after the handshake operation is completed;

[0028] a second checking module configured to read the test case and the first checking value from the shared memory by the receiving end, perform a second checking operation on the test case to generate a second checking value, and compare the second checking value with the first checking value;

[0029] a performing module configured to allow the receiving end to execute the test case in response to the second checking value being the same as the first checking value.

[0030] According to a third aspect of the present application, a computer device is also provided, which comprises:

[0031] at least one processor; and

[0032] a memory storing a computer program capable of running on the processor, and the processor executes the program to perform the chip automatic verification method.

[0033] According to a fourth aspect of the present application, a computer readable storage medium is also provided, which stores a computer program, and the computer program is executed by the processor to perform the chip automatic verification method.

[0034] The chip automatic verification method can realize bidirectional communication between the host and the chip through the introduction of the shared memory, achieve the purpose of automatic verification, make the test case execution and test data input more reliable through the encryption check and handshaking mechanism, and significantly improve the transmission rate and transmission reliability.

[0035] In addition, the present application also provides a chip automatic verification system, a computer device and a computer readable storage medium, which can also achieve the above technical effects, and will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other embodiments can also be obtained from these drawings without creative labor.

[0037] Figure 1 a flow chart of a chip automatic verification method provided by an embodiment of the present application;

[0038] Figure 2A a schematic diagram of setting a shared memory on the chip side provided by an embodiment of the present application;

[0039] Figure 2BA schematic diagram of setting up shared memory on the host side according to an embodiment of the present application is provided;

[0040] Figure 3 A flowchart of the host initiating a handshake operation to the chip according to an embodiment of the present application is provided;

[0041] Figure 4 A schematic diagram of the encoding encryption process according to an embodiment of the present application is provided;

[0042] Figure 5 A schematic diagram of the decoding verification process according to an embodiment of the present application is provided;

[0043] Figure 6 A schematic diagram of the shared memory storage format according to an embodiment of the present application is provided;

[0044] Figure 7 A schematic diagram of the process of the host sending test cases to the chip according to an embodiment of the present application is provided;

[0045] Figure 8 A schematic diagram of the structure of a chip automatic verification system according to another embodiment of the present application is provided;

[0046] Figure 9 An internal structure diagram of a computer device according to another embodiment of the present application is provided. DETAILED DESCRIPTION

[0047] To make the objectives, technical solutions and advantages of the present application clearer, further detailed description of the embodiments of the present application is made below with reference to the accompanying drawings.

[0048] It should be noted that all the expressions of "first" and "second" in the embodiments of the present application are used to distinguish two same-named different entities or different parameters, and "first" and "second" are only used for the convenience of description, and should not be understood as a limitation of the embodiments of the present application. The subsequent embodiments will not be described one by one.

[0049] In one embodiment, referring to Figure 1 , the present application provides a chip automatic verification method 100, specifically comprising the following steps:

[0050] Step 101, a memory of a host or a memory of a chip is applied for a preset size address segment as a shared memory;

[0051] In the specific implementation process, referring to Figure 2A , the shared memory can be applied for from the DDR on the chip side, referring to Figure 2B , the shared memory can also be applied for from the DDR on the host side.

[0052] Step 102, in response to the host and the chip needing to transmit test cases to each other, the sending end performs a first verification operation on the test case to generate a first verification value, initiates a handshake operation with the receiving end, and writes the test case and the first verification value into the shared memory after the handshake operation is completed;

[0053] In the embodiment, the host and the chip can both act as the sending end and the receiving end. Specifically, when the host acts as the sending end, the chip acts as the receiving end; when the chip acts as the sending end, the host acts as the receiving end.

[0054] Step 103, the receiving end reads the test case and the first verification value from the shared memory, performs a second verification operation on the test case to generate a second verification value, and compares the second verification value with the first verification value;

[0055] Step 104, in response to the second verification value being the same as the first verification value, the receiving end is allowed to execute the test case.

[0056] The chip automatic verification method can realize bidirectional communication between the host and the chip through the shared memory, achieve the purpose of automatic verification, and make the test case execution and test data input more reliable through the encryption verification and handshake mechanism, thereby significantly improving the transmission rate and transmission reliability.

[0057] In some embodiments, the host and the chip perform a handshake operation according to the following rules:

[0058] In response to the sending end completing the first verification operation, the sending end pulls the valid signal high;

[0059] In response to the receiving end detecting that the valid signal is pulled high, the receiving end pulls the ready signal high;

[0060] In response to the sending end detecting that the ready signal is pulled high, the sending end and the receiving end complete the handshake operation.

[0061] In some embodiments, the first verification operation performed by the sending end on the test case in step 102 to generate a first verification value includes:

[0062] The sending end performs a hash operation on the test case to generate the first verification value. The hash operation is a method of calculating a string output result by using a set algorithm (MD5, SHA1, SHA256) on input data. One of the characteristics of the hash algorithm is high sensitivity, that is, a slight change in the input data will result in a completely different output result of the hash algorithm.

[0063] The second verification operation on the test case in the aforementioned step 103 to generate a second verification value, comprising:

[0064] Hashing the test case read from the shared memory by the receiving end to generate the second verification value.

[0065] In some embodiments, the method further comprises:

[0066] Collecting, by the host and / or the chip, the execution result of the test case at the receiving end, and analyzing the execution result to determine whether the test case is executed correctly.

[0067] In some embodiments, the method further comprises:

[0068] In response to determining that the test case is executed incorrectly, storing, by the host and / or the chip, the log of the test case executed at the receiving end.

[0069] In some embodiments, the test case comprises a test command and test data.

[0070] In some embodiments, the sending end writes data into the shared memory, and the receiving end reads the shared data, following the rules below to use the shared memory:

[0071] In response to the shared memory belonging to the host and the sending end being the host, converting the space address of the shared memory into a PCI bus address for the chip to use through the Outbound register group of the iATU (Internal Address Translation Unit).

[0072] In response to the shared memory belonging to the chip and the sending end being the chip, converting the PCI bus address into a bus address accessible by the host for the host to use through the Inbound register group of the iATU.

[0073] In yet another embodiment for facilitating the understanding of the scheme of the present application, the scheme of the present application is described in detail below with the host as the sending end and the chip as the receiving end. The present embodiment provides another kind of chip automatic verification method, specifically comprising the following functional modules at the host side and the chip side: sending, receiving, encoding encryption, decoding verification, result determination, and log collection, and applying a piece of storage space as a shared memory in the memory at the host side or the memory at the chip side. The above functional modules are described in detail below:

[0074] I. Sending and receiving

[0075] Please refer to Figure 3As shown, the sending and receiving modules are implemented consistently on the host side and the chip side, and the transceiving adopts a handshake mechanism, and the instruction data or address data to be transmitted is written to the shared memory for communication. The sending module controls the valid signal, and the receiving module controls the ready signal. When the host sends data (here, the data is the data prepared by the encoding encryption module) to the chip, the receiving module of the chip continuously detects the valid signal, the sending module of the host pulls the valid signal high, and if the chip can receive data, the receiving module pulls the ready signal high. After the sending module of the host detects the high level of the ready signal, the data is written to the shared memory, the receiving module of the chip reads the data and performs verification (here, the decoding module works), and an ack message is returned to the host after the verification is successful. In addition, it needs to be noted that the process of the chip sending data and the host receiving data is the same, and will not be described here.

[0076] II. Encoding encryption

[0077] Please refer to Figure 4 As shown, the data transmitted as test cases can include instruction data and address data, and both need to be encoded and encrypted, and the encryption algorithm adopts hash. The following will be described in detail with respect to the above two kinds of transmission data:

[0078] Instruction data encoding and encryption, after the sending end prepares the instruction, the encoding and encryption module will calculate a set of check values through the hash algorithm, and write the original instruction and the check data into the shared memory and return to the sending module.

[0079] Address data encoding and encryption, the sending end should write the data to be transmitted to the shared memory in advance, and send the address and size to the encoding and encryption module. The encoding and encryption module will calculate a set of check values through the hash algorithm, and return the original data and the check data to the sending module.

[0080] III. Decoding and verification

[0081] Please refer to Figure 5 As shown, when the data is transmitted to the opposite end, the receiving module sends the data to the decoding and verification module, which parses the original data, calculates the hash value of the original data, and compares it with the received hash value. If they are the same, the corresponding instruction is executed or the corresponding address data is read. It needs to be noted that the execution steps of different instructions are pre-encoded on the host side and the chip side, and when the instruction is received, the corresponding code is selected for execution.

[0082] IV. Result judgment

[0083] When the test case is executed, the result is judged on the host side or the chip side or both sides. The judgment standard can be flexibly coded, and the result is finally returned.

[0084] V. Log collection

[0085] Based on the return value of the result judgment module, log collection is performed. Logs can be collected on the host side, chip side, or both sides. The collection standards and types can be flexibly encoded, and the collected logs are saved.

[0086] VI. Shared Memory

[0087] Shared memory is a memory space accessible to both the host and the chip. It can be peripheral memory on the host side, such as DDR, or a memory address within the chip. For host-side DDR memory, the host can access it directly. When the chip accesses it, it can use the iATU module. The iATU module has Inbound and Outbound register groups. The Outbound register group translates the DDR space address into a PCI bus address for chip access. For chip-side memory, the chip can access it directly. When the host accesses it, the Inbound register group translates the PCI bus address into a host-accessible bus address.

[0088] The planning of shared memory space is as follows Figure 6 As shown, the chip or host computer stores and retrieves data according to a specified format. If a large amount of data is being transmitted between the two sides, the data can be placed in... Figure 6 The address corresponds to the data segment, and the address and size of the data segment are written to the corresponding location. The other end only needs to obtain the address and size to read the data. This method can reduce the transmission waiting time between the two sides and improve transmission efficiency.

[0089] Please combine Figure 7 As shown, let's assume the host acts as the sender and the chip acts as the receiver to transmit a test case. The specific data transmission process is as follows:

[0090] Step 1: First, the host computer prepares the test case data;

[0091] Step two: The host's encoding and encryption module performs a hash operation on the prepared data to generate a verification value;

[0092] Step 3: The host's transmitting module pulls the valid signal high;

[0093] Step four: After the chip receiving module detects the valid signal, it pulls the ready signal high;

[0094] Step 5: After the host's receiving module detects the ready signal, it writes the original data and the checksum together into the shared memory.

[0095] Step six, the chip receiving module initiates reading shared memory, reads out original data and check value, and the decoding check module of the chip performs hash operation on the read original data again to generate a new check value, compares the read check value with the newly calculated check value, and if they are the same, allows the chip to execute the test case;

[0096] Step seven, the result judging module of the host and / or the chip judges the test case execution result according to the preset condition;

[0097] Step eight, the log collecting module of the host and / or the chip collects and stores the logs corresponding to the test cases with execution errors according to the test case execution result.

[0098] It should be noted that the data transmission process of the chip as the sending end and the host as the receiving end is the same as above, and will not be repeated here.

[0099] The chip automatic verification method of the embodiment has at least the following beneficial technical effects: the host and the chip can independently and bidirectionally transmit and communicate, the transmission of test instructions and test data between the host and the chip is checked and encrypted, the safe and reliable verification purpose is achieved, the test result comparison and test log collection after the execution of the test case are completed, and the chip verification task can be automatically completed.

[0100] In some embodiments, referring to FIG. 2, Figure 8 The chip automatic verification system 200 provided by the present application comprises:

[0101] The application module 201 is configured to apply a preset size address segment as shared memory from the memory of the host or the memory of the chip;

[0102] The first check module 202 is configured to, in response to the host and the chip needing to transmit test cases to each other, perform a first check operation on the test case to generate a first check value, initiate a handshake operation with the receiving end, and write the test case and the first check value into the shared memory after the completion of the handshake operation;

[0103] The second check module 203 is configured to read the test case and the first check value from the shared memory by the receiving end, perform a second check operation on the test case to generate a second check value, and compare the second check value with the first check value;

[0104] The execution module 204 is configured to, in response to the second check value being the same as the first check value, allow the receiving end to execute the test case.

[0105] The chip automatic verification system can realize bidirectional communication between the host and the chip through the introduction of the shared memory, achieve the purpose of automatic verification, make the test case execution and test data input more reliable through encryption verification and handshaking mechanism, and significantly improve the transmission rate and transmission reliability.

[0106] In some embodiments, the host and the chip perform a handshaking operation according to the following rules:

[0107] In response to the completion of the first verification operation by the sending end, the sending end pulls up the valid signal;

[0108] In response to the detection of the pulling up of the valid signal by the receiving end, the receiving end pulls up the ready signal;

[0109] In response to the detection of the pulling up of the ready signal by the sending end, the sending end and the receiving end complete the handshaking operation.

[0110] In some embodiments, the first verification module 202 is further configured to:

[0111] The sending end performs a hash operation on the test case to generate the first verification value;

[0112] The second verification module 203 is further configured to:

[0113] The receiving end performs a hash operation on the test case read from the shared memory to generate the second verification value.

[0114] In some embodiments, the system further includes a module configured to perform the following steps:

[0115] The host and / or the chip collect the execution results of the test case at the receiving end, and analyze the execution results to determine whether the test case is executed correctly.

[0116] In some embodiments, the system further includes a module configured to perform the following steps:

[0117] In response to determining that the test case is executed incorrectly, the host and / or the chip store the log of the execution of the test case by the receiving end.

[0118] In some embodiments, the test case includes a test command and test data.

[0119] In some embodiments, the sending end writes data to the shared memory, and the receiving end reads the shared data in accordance with the following rules:

[0120] In response to the shared memory belonging to the host and the sending end being the host, the space address of the shared memory is converted into a PCI bus address for the chip by the Outbound register group of the iATU;

[0121] In response to the shared memory belonging to the chip and the sending end being the chip, the PCI bus address is converted into a bus address accessible by the host for the host by the Inbound register group of the iATU.

[0122] It should be noted that the specific definition of the chip automatic verification system can refer to the definition of the chip automatic verification method in the foregoing, which will not be described here. Each module in the chip automatic verification system described above can be realized by software, hardware and combinations thereof in whole or in part. The above-mentioned modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so as to call and execute the operations corresponding to each module by the processor.

[0123] According to another aspect of the present application, a computer device, which can be a server, is provided, and its internal structure diagram is shown in Figure 9 The computer device includes a processor, a memory, a network interface and a database connected by a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with external terminals through network connection. The computer program is executed by the processor to implement the chip automatic verification method described above. Specifically, the method includes the following steps:

[0124] A preset size address segment is applied from the memory of the host or the memory of the chip as a shared memory;

[0125] In response to the host and the chip needing to transmit test cases to each other, a first verification operation is performed on the test cases by the sending end to generate a first verification value, a handshake operation with the receiving end is initiated, and the test cases and the first verification value are written into the shared memory after the handshake operation is completed;

[0126] The test cases and the first verification value are read from the shared memory by the receiving end, a second verification operation is performed on the test cases to generate a second verification value, and the second verification value and the first verification value are compared;

[0127] In response to the second check value being the same as the first check value, the receiving end is allowed to execute the test case.

[0128] According to yet another aspect of the present application, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the chip automatic verification method as described above, in particular comprising performing the following steps:

[0129] Applying a preset size address segment from the memory of the host or the memory of the chip as the shared memory;

[0130] In response to the host and the chip needing to transmit test cases to each other, the sending end performs a first check operation on the test case to generate a first check value, initiates a handshake operation with the receiving end, and writes the test case and the first check value into the shared memory after the handshake operation is completed;

[0131] The receiving end reads the test case and the first check value from the shared memory, performs a second check operation on the test case to generate a second check value, and compares the second check value with the first check value;

[0132] In response to the second check value being the same as the first check value, the receiving end is allowed to execute the test case.

[0133] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiments. Any reference to memory, storage, database or other medium used in the embodiments provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0134] Any combination of the technical features in the above embodiments can be made, and for the sake of brevity, not all possible combinations are described above, however, as long as the combination of the technical features does not exist in contradiction, it shall be considered within the scope of the present disclosure.

[0135] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it shall not be understood as a limitation on the patent scope of the present application. It shall be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these shall be within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method of automated validation of a chip, characterized in that, The method comprises: applying a preset size address segment from the memory of the host or the memory of the chip as a shared memory; in response to the host and the chip needing to transmit test cases to each other, performing a first check operation on the test case by the sending end to generate a first check value, initiating a handshake operation with the receiving end, and writing the test case and the first check value into the shared memory after the handshake operation is completed; reading the test case and the first check value from the shared memory by the receiving end, performing a second check operation on the test case to generate a second check value, and comparing the second check value with the first check value; in response to the second check value being the same as the first check value, allowing the receiving end to execute the test case; wherein the sending end writes data into the shared memory and the receiving end reads the shared data in accordance with the following rules: in response to the shared memory belonging to the host and the sending end being the host, converting the space address of the shared memory into a PCI bus address for the chip to use through the Outbound register group of the iATU; in response to the shared memory belonging to the chip and the sending end being the chip, converting the PCI bus address into a bus address accessible by the host for the host to use through the Inbound register group of the iATU.

2. The chip automatic verification method of claim 1, wherein, The host and the chip perform a handshake operation in accordance with the following rules: in response to the sending end completing the first check operation, the sending end pulls up the valid signal; in response to the receiving end detecting that the valid signal is pulled up, the receiving end pulls up the ready signal; in response to the sending end detecting that the ready signal is pulled up, the sending end and the receiving end complete the handshake operation.

3. The method of claim 1, wherein, The first check operation on the test case by the sending end to generate a first check value comprises: performing a hash operation on the test case by the sending end to generate the first check value; The second check operation on the test case to generate a second check value comprises: performing a hash operation on the test case read from the shared memory by the receiving end to generate the second check value.

4. The method of claim 1, wherein, The method further comprises: collecting, by the host and / or the chip, an execution result of the test case at the receiving end, and analyzing the execution result to determine whether the test case is executed correctly.

5. The method of claim 4, wherein, The method further comprises: in response to determining that the test case is executed incorrectly, storing, by the host and / or the chip, a log when the receiving end executes the test case.

6. The method of claim 1, wherein, The test case comprises a test command and test data.

7. An automated chip validation system, characterized by, The system comprises: an application module configured to apply a preset size address segment from the memory of the host or the memory of the chip as a shared memory; a first check module configured to, in response to the host and the chip needing to transmit test cases to each other, perform a first check operation on the test case by the sending end to generate a first check value, initiate a handshake operation with the receiving end, and write the test case and the first check value into the shared memory after the handshake operation is completed; a second checking module, configured to read the test case and the first checking value from the shared memory by the receiving end, perform a second checking operation on the test case to generate a second checking value, and compare the second checking value with the first checking value; an execution module, configured to allow the receiving end to execute the test case in response to the second checking value being the same as the first checking value. In the process of writing data into the shared memory by the sending end and reading data from the shared memory by the receiving end, the shared memory is used according to the following rules: in response to the shared memory belonging to the host and the sending end being the host, the space address of the shared memory is converted into a PCI bus address by the Outbound register group of the iATU for use by the chip; in response to the shared memory belonging to the chip and the sending end being the chip, the PCI bus address is converted into a bus address accessible by the host by the Inbound register group of the iATU for use by the host.

8. A computer device, characterized by comprise: at least one processor; and a memory storing a computer program capable of running in the processor, wherein the processor executes the program to perform the chip automatic verification method according to any one of claims 1-6.

9. A computer-readable storage medium storing a computer program, the computer program comprising instructions that, when executed by a computer, cause the computer to perform the method of any one of claims 1 to 8. The computer program is executed by the processor to perform the chip automatic verification method according to any one of claims 1-6.

Images