Process for improving the uniformity of selective window diffusion of wafers
By forming diffusion windows and diffusion rings on the wafer surface and adjusting the position and size of the diffusion rings, the problem of uneven impurity diffusion on the wafer is solved, thus improving the performance consistency of optoelectronic devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHAN OPTICS VALLEY QUANTUM TECH CO LTD
- Filing Date
- 2023-01-05
- Publication Date
- 2026-05-12
AI Technical Summary
Inconsistent impurity diffusion depths in different regions of a wafer lead to poor performance consistency in optoelectronic devices.
A diffusion window and diffusion ring are formed on the wafer surface. By adjusting the position and size of the diffusion ring, the inconsistency of diffusion depth in different regions is compensated, and a gaseous impurity source is used for diffusion.
This improves the uniformity of impurity diffusion depth across different regions of the wafer, thereby enhancing the performance consistency of fabricated single-tube devices or array pixels.
Smart Images
Figure CN116230503B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of optoelectronic device technology, and in particular to a process for improving the diffusion uniformity of wafer selective windows. Background Technology
[0002] Impurity diffusion is a crucial method for forming pn junctions, making it a standard fabrication process for some optoelectronic devices. To achieve impurity diffusion, a diffusion mask is typically grown on the surface of the crystal to be diffused. Diffusion windows are then formed through photolithography, RIE etching, and resist removal. Acceptor or donor impurities diffuse through these windows into the crystal to form the pn junction. For APD devices and other optoelectronic devices, the pn junction depth is a critical parameter, determining characteristic values such as the reverse turn-on voltage (Vpt) and breakdown voltage (Vbr). Therefore, controlling the pn junction depth is a key technology for achieving high-performance optoelectronic devices.
[0003] Typically, the diffusion process for APD devices or other optoelectronic devices is carried out by equipment such as MOCVD and diffusion furnaces. The diffusion rate of impurities is affected by parameters such as the temperature distribution on the wafer surface and the concentration distribution of gaseous impurities. Different regions on the same wafer have different diffusion depths due to the inconsistency of the above parameters, which limits the performance consistency of single-tube devices (or array pixels) fabricated on the wafer. Summary of the Invention
[0004] This application provides a process for improving the uniformity of selective window diffusion in wafers, in order to solve the problem of uneven diffusion of wafer impurities in related technologies.
[0005] The specific technical solution provided in this application is as follows:
[0006] This application provides a process for improving the diffusion uniformity of a wafer selective window, comprising the following steps:
[0007] Deposit a diffusion mask on the wafer surface;
[0008] Photolithography is used to form diffusion windows and diffusion rings surrounding the diffusion windows on the surface of a diffusion mask.
[0009] Impurities diffuse within the diffusion window and diffusion ring to form a diffusion region.
[0010] In some embodiments, "photolithography to form a diffusion window and a diffusion ring surrounding the diffusion window on the surface of the diffusion mask" specifically includes:
[0011] Photoresist is spin-coated onto the surface of a diffusion mask, and then pre-baking, exposure, development, hardening, and etching processes are performed sequentially to form diffusion windows and diffusion rings surrounding the diffusion windows on the surface of the diffusion mask.
[0012] In some embodiments, the following steps are included prior to "impurity diffusion within the diffusion window and diffusion ring":
[0013] Remove the photoresist.
[0014] In some embodiments, the diffusion mask is a SiNx or SiO2 dielectric film, and the growth temperature of the SiNx or SiO2 dielectric film is 200–300°C.
[0015] In some embodiments, the wafer comprises, from top to bottom, a cap layer, a charge layer, a gradient layer, an absorption layer, a buffer layer, and a substrate, with the diffusion region distributed within the cap layer.
[0016] In some embodiments, the diffusion window is coaxially arranged with the diffusion ring.
[0017] In some embodiments, the pre-baking temperature is 95-100°C and the time is 60 seconds.
[0018] In some embodiments, the optical power of the exposure process is 12.5 mw / cm². 2 The time is 2 seconds.
[0019] In some embodiments, the development time is 20-25 seconds;
[0020] And / or, the baking temperature for the film hardening process is 105-115℃, and the baking time is 90s.
[0021] In some embodiments, a gaseous impurity source is used for diffusion.
[0022] The beneficial effects of the technical solution provided in this application include:
[0023] This application adds a diffusion ring around the diffusion window, which plays an auxiliary diffusion role. By adjusting the position and size of the auxiliary diffusion ring in different regions of the pixel, the diffusion depth in different regions of the wafer can be corrected and compensated, so that the impurity diffusion depth in each region of the wafer is close to uniform, thereby improving the performance consistency of the fabricated single-tube device or array pixel. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a top view of the wafer after the diffusion window and diffusion ring have been formed, as provided in an embodiment of this application.
[0026] Figure 2 A cross-sectional view of the wafer after the diffusion window and diffusion ring are formed, provided in an embodiment of this application;
[0027] Figure 3 This is a Vpt distribution map of each pixel on a wafer after diffusion using existing diffusion processes.
[0028] Figure 4 The photolithography pattern provided for the photolithography process in the embodiments of this application;
[0029] Figure 5 This is a Vpt distribution map of each pixel of a wafer after diffusion using the process provided in the embodiments of this application;
[0030] Figure 6 The relationship between the center distance D and the turn-on voltage Vpt;
[0031] Figure 7 This is a schematic diagram of the epitaxial structure of the InP / InGaAs APD device provided in an embodiment of this application;
[0032] Figure 8 This relates the thickness of the multiplication layer to the turn-on voltage Vpt.
[0033] Figure 9 This is a general flow chart of the process for improving the uniformity of wafer selective window diffusion provided in the embodiments of this application.
[0034] Figure reference numerals: 1. Wafer; 101. Cap layer; 102. Charge layer; 103. Gradient layer; 104. Absorption layer; 105. Buffer layer; 106. Substrate; 107. Diffusion region; 2. Diffusion window; 3. Diffusion ring; 4. Diffusion mask. Detailed Implementation
[0035] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0036] See Figure 1-2 and Figure 9 As shown in the figure, this application provides a process for improving the diffusion uniformity of a wafer selective window, including the following steps:
[0037] S1: Deposit diffusion mask 4 on the surface of wafer 1;
[0038] S2: Photolithography to form a diffusion window 2 and a diffusion ring 3 surrounding the diffusion window 2 on the surface of the diffusion mask 4;
[0039] S3: Impurity diffusion occurs within diffusion window 2 and diffusion ring 3 to form diffusion region 107.
[0040] Specifically, the diffusion window 2 is a circular structure, and the diffusion ring 3 is a ring-shaped structure. See [link to documentation]. Figure 2 As shown, Figure 2 The diagram shows the Vpt distribution of each pixel after diffusion of a 2-inch wafer using existing diffusion technology. The diagram shows that the diffusion depth is not consistent among the pixels of the 2-inch wafer, and the distribution pattern shows that the diffusion depth gradually decreases from the outer side to the inner side of the wafer.
[0041] This application is based on Figure 2 The diffusion pattern was redesigned using the process provided in this application. The diffusion pattern is designed as three layers from the outside to the inside. The diffusion pattern of the pixels within the three layers of the photomask is shown below. Figure 3 As shown, using Figure 3 The Vpt distribution of each pixel in the photolithography pattern after impurity diffusion is shown below. Figure 4 As shown, the diffusion depth consistency among pixels in the wafer fabricated using the process described in this application is significantly improved. Since the total amount of impurities per unit area is constant, during selective window diffusion, the smaller the proportion of the diffusion mask window per unit area, the faster the diffusion rate within the window. However, when performing diffusion on the entire wafer, the uneven distribution of temperature and airflow within the wafer leads to inconsistent diffusion depths between the central and edge regions when using identical diffusion windows (as per existing conventional techniques). This invention proposes using a diffusion ring located around the central active region window. By setting different diffusion ring areas in the wafer's center and edge regions, the duty cycle of the diffusion windows in different regions is changed, neutralizing the differences caused by airflow and temperature, thereby improving the diffusion depth consistency within the central active region window. This, in turn, enhances the performance consistency of the fabricated single-cell chip across all units within the wafer or the performance consistency of each pixel in an array chip.
[0042] Furthermore, the size and position of the diffusion ring 3 on the wafer surface can be reasonably designed according to actual conditions. The difference between the radius of the diffusion window 2 and the inner ring radius of the diffusion ring 3 is defined as the center distance D. The relationship between the center distance D and the turn-on voltage Vpt is as follows: Figure 6 As shown.
[0043] This application allows for the design of the size and position of the diffusion ring based on the expected turn-on voltage value.
[0044] In some embodiments, "photolithography to form a diffusion window 2 and a diffusion ring 3 surrounding the diffusion window 2 on the surface of the diffusion mask 4" specifically includes:
[0045] Photoresist is spin-coated onto the surface of diffusion mask 4, and then pre-baking, exposure, development, hardening, and etching processes are performed sequentially to form diffusion window 2 and diffusion ring 3 surrounding diffusion window 2 on the surface of diffusion mask 4.
[0046] Furthermore, the photoresist includes, but is not limited to, S1805. Specifically, the diffusion mask 4 obtains the required patterned film layer by spin-coating photoresist, pre-baking, exposure, development, and hardening processes, and then etches the diffusion mask 4 by RIE to form the diffusion window 2 and diffusion ring 3 in the diffusion mask 4.
[0047] In some embodiments, the following steps are included before "impurity diffusion within diffusion window 2 and diffusion ring 3":
[0048] Remove the photoresist.
[0049] Furthermore, "removing photoresist" specifically includes:
[0050] Wafer 1 was immersed in acetone solution for 5 minutes to remove photoresist.
[0051] In some embodiments, the diffusion mask 4 is a SiNx or SiO2 dielectric film, and the growth temperature of the SiNx or SiO2 dielectric film is 200-300°C, more preferably 300°C.
[0052] Specifically, a SiNx dielectric film can be grown on the surface of the cap layer 101 using PECVD technology.
[0053] Furthermore, it is preferred that the thickness of the SiNx dielectric film is 200 nm.
[0054] See Figure 7 As shown, in some embodiments, the wafer 1 includes, from top to bottom, a cap layer 101, a charge layer 102, a gradient layer 103, an absorption layer 104, a buffer layer 105, and a substrate 106, and the diffusion region 107 is distributed within the cap layer 101.
[0055] The epitaxial structure of the wafer is not limited to this. Figure 7 As an example, the wafer structure of an InP / InGaAs APD device is shown, wherein the diffusion region 107 is the doped region formed by impurities diffusing into the cap layer 101.
[0056] Specifically, the difference d between the thickness of the cap layer 101 and the thickness of the diffusion layer 107 is the multiplication layer thickness.
[0057] Furthermore, the relationship between the multiplication layer thickness and the turn-on voltage Vpt of the InP / InGaAs APD device is as follows: Figure 8As shown.
[0058] In some embodiments, the diffusion window 2 is coaxially arranged with the diffusion ring 3.
[0059] It helps to improve the uniformity of diffusion.
[0060] In some embodiments, the pre-baking temperature is 95-100°C and the time is 60 seconds.
[0061] Pre-baking aims to ensure the solvent within the photoresist film fully evaporates, drying the film to increase its adhesion to the diffusion mask surface and improve its abrasion resistance. The main factors affecting pre-baking quality are drying temperature and drying time. Insufficient baking (too low a temperature or too short a time) results in incomplete solvent evaporation, causing the unexposed areas to dissolve and form loose photoresist or deform the pattern during exposure and development. Excessive baking time or temperature leads to warping and hardening of the photoresist film, resulting in the pattern not showing up during development or leaving a base film. Therefore, a pre-baking temperature of 95-100°C and a time of 60 seconds are preferred.
[0062] In some embodiments, the optical power of the exposure process is 12.5 mw / cm². 2 The time is 2 seconds.
[0063] Exposure involves covering the surface of a wafer coated with photoresist with a photomask. The photomask is designed with several diffusion windows and diffusion rings according to the desired pattern. Selective irradiation with ultraviolet light causes a chemical reaction in the illuminated areas of the photoresist, altering the solubility of this portion of the film in the developer. After development, the photosensitive film reveals a pattern corresponding to the photomask. The exposure time and intensity are determined based on factors such as the quality of the photomask, the properties of the photoresist, the strength of the light source, and the distance between the light source and the wafer. If the exposure time is too short, the photoresist is insufficiently exposed, resulting in incomplete chemical reaction and incomplete dissolution of the illuminated areas during development, easily leaving a substrate film. If the exposure time is too long, even the edges of areas that should not be exposed are weakly exposed, leading to blurred pattern boundaries and severe blurring of fine lines after etching. Therefore, a preferred light power for the exposure process is 12.5 mW / cm². 2 The time is 2 seconds.
[0064] In some embodiments, the development time is 20-25 seconds;
[0065] And / or, the baking temperature for the film hardening process is 105-115℃, and the baking time is 90s.
[0066] Development is the process of dissolving the photoresist in the photosensitive areas, leaving the unexposed areas as a photoresist film to reveal the desired diffusion windows and ring patterns. The development process involves placing the exposed wafer into a developing tank, where the developer is sprayed onto the photoresist surface through a oscillating nozzle. After a certain time, once the pattern has developed, the wafer is washed with water to remove the developer. Temperature and time directly affect the development quality. Insufficient development time or low temperature will prevent the photoresist from completely dissolving, leaving a layer that protects the diffusion mask during etching, ensuring the mask is preserved. Conversely, excessive development time or high temperature will cause the unexposed photoresist to melt from the edges inwards, resulting in poor pattern edges and, in severe cases, large areas of photoresist may peel off.
[0067] Hardening: Because the photoresist film softens and expands after development, affecting its resistance to etching, the wafer must be baked at an appropriate temperature after development to remove moisture and enhance its adhesion to the diffusion mask. The effect on hardening quality is the same as that of pre-baking, and generally the hardening conditions are slightly higher than the pre-baking conditions.
[0068] Etching involves using a specific proportion of acid to etch away the diffusion mask on the wafer that is not protected by photoresist, while preserving the diffusion mask protected by photoresist. The etched portion forms the diffusion window and diffusion ring. Furthermore, this application can use a RIE etching process to etch the diffusion mask.
[0069] In some embodiments, a gaseous impurity source is used for diffusion.
[0070] Furthermore, in some embodiments, the diffusion impurity is a zinc source, and the zinc diffusion process is a conventional existing technology, such as being completed by MOCVD equipment and a diffusion furnace.
[0071] Furthermore, it is preferable to use a gaseous zinc source for diffusion.
[0072] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two elements. For those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.
[0073] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0074] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.
Claims
1. A process for improving the diffusion uniformity of a wafer selective window, characterized in that, Includes the following steps: A diffusion mask (4) is deposited on the surface of the wafer (1); Photolithography is used to form a diffusion window (2) and a diffusion ring (3) surrounding the diffusion window on the surface of the diffusion mask (4). Impurities diffuse within the diffusion window (2) and diffusion ring (3) to form a diffusion region (107). "Photolithography, to form a diffusion window (2) and a diffusion ring (3) surrounding the diffusion window on the surface of the diffusion mask (4)" specifically includes: Photoresist is spin-coated on the surface of the diffusion mask (4), and then pre-baking, exposure, development, hardening and etching processes are performed in sequence to form a diffusion window (2) and a diffusion ring (3) surrounding the diffusion window (2) on the surface of the diffusion mask (4). The pre-baking temperature is 95-100℃, and the time is 60 seconds; The optical power for the exposure process is 12.5 mw / cm². 2 The time is 2 seconds; The development time is 20-25 seconds; The baking temperature for the film hardening process is 105-115℃, and the baking time is 90s.
2. The process for improving wafer selective window diffusion uniformity as described in claim 1, characterized in that, Before "diffusion of impurities within the diffusion window (2) and diffusion ring (3)", the following steps are also included: Remove the photoresist.
3. The process for improving wafer selective window diffusion uniformity as described in claim 1, characterized in that, The diffusion mask (4) is a SiNx or SiO2 dielectric film, and the growth temperature of the SiNx or SiO2 dielectric film is 200~300℃.
4. The process for improving wafer selective window diffusion uniformity as described in claim 1, characterized in that, The wafer (1) comprises, from top to bottom, a cap layer (101), a charge layer (102), a gradient layer (103), an absorption layer (104), a buffer layer (105), and a substrate (106), and the diffusion region (107) is distributed within the cap layer (101).
5. The process for improving wafer selective window diffusion uniformity as described in claim 1, characterized in that, The diffusion window (2) is coaxially arranged with the diffusion ring (3).
6. The process for improving wafer selective window diffusion uniformity as described in claim 1, characterized in that, Diffusion is achieved using a gaseous impurity source.