Semiconductor element and method for producing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a substrate; a drain region disposed in the substrate; a common source region disposed in the substrate and opposite the drain region; a bit line structure including a bit line conductive layer disposed on the substrate and electrically connected to the common source region; a memory cell contact disposed on the substrate, adjacent to the bit line structure, and electrically connected to the drain region; a landing pad disposed over the bit line conductive layer and electrically connected to the cell contact; and an air gap disposed between the landing pad and the bit line conductive layer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application Nos. 17 / 540,795 and 17 / 542,758 (i.e., priority dates of December 2, 2021 and December 6, 2021, respectively), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure provides a semiconductor element and a method for fabricating the same, particularly a semiconductor element with an air gap and a method for fabricating the same. Background Technology

[0003] Semiconductor components are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is continuously shrinking to meet the ever-increasing demands for computing power. However, various problems have arisen in the manufacturing process of shrinking these components, and these problems are increasing. Therefore, challenges remain in achieving improvements in quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a semiconductor device including a substrate; a drain region disposed in the substrate; a common source region disposed in the substrate and opposite to the drain region; a bit line structure including a bit line conductive layer disposed on the substrate and electrically coupled to the common source region; a memory cell contact disposed on the substrate, adjacent to the bit line structure and electrically coupled to the drain region; a landing pad disposed above the bit line conductive layer and electrically coupled to the cell contact; and an air gap disposed between the landing pad and the bit line conductive layer.

[0006] Another embodiment of this disclosure provides a semiconductor device including a bitline structure, the bitline structure comprising: a bitline conductive layer and a bitline internal capping layer, the bitline internal capping layer including a lower portion disposed on the bitline conductive layer and an upper portion disposed on the lower portion; a landing pad disposed above the bitline internal capping layer; and an air gap disposed between the landing pad and the bitline conductive layer, adjacent to the upper portion of the bitline internal capping layer. The width of the upper portion of the bitline internal capping layer is smaller than the width of the bitline conductive layer.

[0007] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a bit-line conductive layer and a bit-line internal capping layer on the substrate, wherein the bit-line conductive layer and the bit-line internal capping layer are configured together to form a bit-line structure; forming a bit-line spacer capping layer covering the bit-line structure; forming a cell contact adjacent to the bit-line structure. A blanket-like pad layer is formed on the bit-line spacer capping layer and the cell contact; a plurality of pad openings are formed along the blanket-like pad layer and extend to the bit-line spacer capping layer and the bit-line internal capping layer, such that the blanket-like pad layer becomes a plurality of landing pads; and selectively forming a sealing layer on the plurality of landing pads and covering the upper part of the plurality of pad openings to form a plurality of air gaps between the bit-line conductive layer and the plurality of landing pads.

[0008] Due to the design of the semiconductor device disclosed herein, an air gap can be formed between the landing pad and the bitline conductive layer. Therefore, the parasitic capacitance between the landing pad and the bitline conductive layer can be reduced. Consequently, the power consumption of the semiconductor device can be reduced.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0010] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0011] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor element according to an embodiment of the present disclosure.

[0012] Figure 2 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0013] Figure 3 This is a cross-sectional view illustrating a semiconductor element along an embodiment of the present disclosure. Figure 2 Part of the preparation process for A-A' line imaging.

[0014] Figure 4 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0015] Figure 5 and Figure 6 This is a cross-sectional view illustrating a semiconductor element along an embodiment of the present disclosure. Figure 4 Part of the preparation process for A-A' line imaging.

[0016] Figure 7 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0017] Figures 8 to 11 This is a cross-sectional view illustrating a semiconductor element along an embodiment of the present disclosure. Figure 7 Part of the preparation process for A-A' line imaging.

[0018] Figure 12 This is a cross-sectional view illustrating a semiconductor element along an embodiment of the present disclosure. Figure 7 Part of the preparation process for B-B' line imaging.

[0019] Figure 13 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0020] Figure 14 This is a cross-sectional view illustrating a semiconductor element along an embodiment of the present disclosure. Figure 13 Part of the preparation process for A-A' line imaging.

[0021] Figure 15 and Figure 16 This is a cross-sectional view illustrating a semiconductor element along an embodiment of the present disclosure. Figure 13 Part of the preparation process for B-B' line imaging.

[0022] Figure 17 The diagram illustrates an example of the preparation conditions for the sealing layer of a semiconductor element according to an embodiment of the present disclosure.

[0023] Figures 18 to 20 This is a cross-sectional view illustrating part of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0024] The reference numerals in the attached figures are explained as follows:

[0025] 1A: Semiconductor components

[0026] 10: Preparation method

[0027] 101: Base

[0028] 103: Isolation layer

[0029] 105: Well Area

[0030] 107: Drain region

[0031] 109: Common-source polar region

[0032] 111: First dielectric layer

[0033] 113: Second dielectric layer

[0034] 115: Third dielectric layer

[0035] 200: Character Line Structure

[0036] 200T: Trench

[0037] 201: Insulation layer of character lines

[0038] 203: Character line conductive layer

[0039] 205: Character Line Capping Layer

[0040] 300: Bitline Structure

[0041] 301: Bit line conductive layer

[0042] 303: Bottom conductive part

[0043] 305: Intermediate conductive part

[0044] 307: Top conductive portion

[0045] 309: Internal capping layer of the bit line

[0046] 309-1: Lower part

[0047] 309-3: Upper part

[0048] 311: Bit line spacer capping layer

[0049] 313: Bit line contact

[0050] 411: Storage cell contact

[0051] 413: Landing mat

[0052] 413SW: Sidewall

[0053] 413TS: Top surface

[0054] 415: Sealing layer

[0055] 415BS: Bottom surface

[0056] 417: Air gap

[0057] 419: Capacitor Contact

[0058] 501: First Silicon Precursor Supply Step

[0059] 503: First nitrogen precursor supply step

[0060] 601: First conductive material

[0061] 603: Second conductive material

[0062] 605: Third conductive material

[0063] 607: Blanket-like cushioning

[0064] 607O: Bedding layer opening

[0065] 609: First Insulation Material

[0066] 611: Interstitial layer

[0067] 701: First precursor molecule

[0068] 703: Second precursor molecule

[0069] AA: Active Zone

[0070] A-A': line

[0071] B-B': Line

[0072] CL1: Centerline

[0073] CL2: Centerline

[0074] S11: Steps

[0075] S13: Steps

[0076] S15: Steps

[0077] S17: Steps

[0078] VL1: Vertical horizontal plane

[0079] VL1: Vertical horizontal plane

[0080] VL2: Vertical horizontal plane

[0081] W1: Width

[0082] W2: Width

[0083] X: Direction

[0084] Y: direction

[0085] Z: Direction Detailed Implementation

[0086] The following disclosure provides numerous different embodiments or examples of various features of this disclosure as implementations. Specific embodiments or examples of elements and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the size of an element is not limited to the disclosed range or values, but may depend on process conditions and / or the desired properties of the element. Furthermore, the description of a first feature being formed "above" or "on" a second feature in the following description can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features may be formed between the first and second features, thereby allowing the first and second features to not be in direct contact. For simplicity and clarity, some features may be drawn at various scales. In the drawings, some layers / features may be omitted for simplicity.

[0087] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figure and another (other) element or feature. These spatial relative terms are intended to encompass not only the orientation shown in the figure but also different orientations of the element during use or operation. The element may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be translated accordingly.

[0088] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be directly connected to or coupled to another component or layer, or there may be an intermediate component or layer.

[0089] It should be understood that although various elements may be described using terms such as first, second, etc., these elements should not be limited by the terms. Unless otherwise stated, terms are used only to distinguish one element from another. Thus, for example, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part without departing from the teachings of this disclosure.

[0090] Unless the context otherwise requires, when referring to orientation, layout, location, shape, size, quantity, or other measures, the terms such as “identical,” “equal,” “planar,” or “coplanar” do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measures, but rather that they are substantially identical, including such similar orientation, layout, location, shape, size, quantity, or other measures, within the range of acceptable variations that may occur, such as due to manufacturing processes. The term “substantially” may be used to reflect this meaning. For example, items described as “substantially identical,” “substantially equal,” or “substantially planar” can be exactly the same, equal, or planar, or they can be identical, equal, or planar within the range of acceptable variations, such as those that may occur due to manufacturing processes.

[0091] In this disclosure, semiconductor components generally refer to components that function by utilizing the properties of semiconductors. Electro-optical components, light-emitting display components, semiconductor circuits, and electronic components are all included in the scope of semiconductor components.

[0092] It should be understood that in the description of this disclosure, "above" (or "above") corresponds to the direction of the arrow in direction Z, and "below" (or "below") corresponds to the opposite direction of the arrow in direction Z.

[0093] It should be understood that, in the description of this disclosure, the terms “forming,” “formed,” and “form” can refer to and include any method of building, constructing, patterning, implanting, or depositing elements, dopants, or materials. Examples of forming methods may include, but are not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, co-sputtering, spin-coating, diffusion, deposition, growing, implantation, photolithography, dry etching, and wet etching.

[0094] It should be understood that the functions or steps described in this disclosure may occur in a different order than those shown in the figures. For example, two figures shown consecutively may actually be performed simultaneously, or sometimes in reverse order, depending on the functions or steps involved.

[0095] Figure 1 This is a flowchart illustrating a method 10 for fabricating a semiconductor element 1A according to an embodiment of the present disclosure. Figure 2 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 3This is a cross-sectional view illustrating a semiconductor element 1A along an embodiment of the present disclosure. Figure 2 The image shows part of the preparation process captured by the A-A' line. It should be understood that some elements have been omitted in the top view for clarity.

[0096] Reference Figures 1 to 3 In step S11, a substrate 101 can be provided, an isolation layer 103 can be formed in the substrate 101 to define multiple active areas AA, multiple character line structures 200 can be formed in the substrate 101, and multiple drain regions 107 and multiple common source regions 109 can be formed in the multiple active areas AA.

[0097] Reference Figure 2 and Figure 3 The substrate 101 may include a bulk semiconductor substrate composed of at least one semiconductor material. The fabrication techniques for the bulk semiconductor substrate may be, for example, elementary semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductors, or group II-VI compound semiconductors; or combinations thereof.

[0098] In some embodiments, substrate 101 may include a semiconductor-on-insulator (SOI) structure comprising, from bottom to top, a processing substrate, an insulating layer, and an uppermost semiconductor material layer. The processing substrate and the uppermost semiconductor material layer can be fabricated using the same materials as the bulk semiconductor substrate described above. The insulating layer may be a crystalline or amorphous dielectric material, such as oxides and / or nitrides. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. Alternatively, the insulating layer may be a dielectric nitride, such as silicon nitride or boron nitride. Yet another example is that the insulating layer may comprise a stack of dielectric oxides and dielectric nitrides, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The thickness of the insulating layer may range from 10 nanometers (nm) to 200 nanometers. The insulating layer can eliminate leakage current between adjacent elements in substrate 101 and reduce parasitic capacitance associated with the source and / or drain.

[0099] It should be understood that in the description of this disclosure, the term "about" refers to changes in the quantity of ingredients, components, or reactants of this disclosure, which may occur due to variations in numerical values, for example, through typical measurements and liquid processing procedures used to manufacture concentrates or solutions. Furthermore, variations may occur due to negligence in measurement procedures, differences in the manufacture, source, or purity of the ingredients used to manufacture the composition or perform the method. In one embodiment, the term "about" refers to a range of 10% of the disclosed value. In another embodiment, the term "about" refers to a range of 5% of the disclosed value. In yet another embodiment, the term "about" refers to a range of 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the disclosed value.

[0100] Reference Figure 2 and Figure 3 A series of deposition processes can be performed to deposit a pad oxide layer (not shown for clarity) and a pad nitride layer (not shown for clarity) on the substrate 101. A photolithography process can be performed to define the location of the isolation layer 103. After the photolithography process, an etching process, such as anisotropic dry etching, can be performed to form trenches penetrating the pad oxide layer, the pad nitride layer, and the substrate 101. An insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide, can be deposited into the trenches. Subsequently, a planarization process, such as chemical mechanical polishing, can be performed to remove excess filler material until the top surface of the substrate 101 is exposed, thus forming the isolation layer 103. The top surface of the isolation layer 103 and the top surface of the substrate 101 can be substantially coplanar. The isolation layer 103 may define a plurality of active regions AA in the substrate 101. In some embodiments, the plurality of active regions AA may extend along inclined directions corresponding to the X and Y directions.

[0101] It should be understood that, in the description of this disclosure, the surface of an element (or feature) disposed on the highest vertical horizontal plane along the Z direction is referred to as the top surface of the element (or feature). The surface of an element (or feature) disposed on the lowest vertical horizontal plane along the Z direction is referred to as the bottom surface of the element (or feature).

[0102] It should be understood that, in the description of this disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0103] For the sake of brevity, clarity, and ease of description, only the elements of one active region AA are described. All other active regions AA may have the same elements and the same configuration.

[0104] Reference Figure 2 and Figure 3 Well region 105 can be formed in the active region AA. The fabrication technique for well region 105 can be achieved using, for example, an implantation process using p-type dopant. Well region 105 can have a first electrical type (i.e., p-type). The term "p-type dopant" refers to an impurity that, when added to an intrinsic semiconductor material, results in a deficiency of valence electrons. Examples of p-type dopants in silicon-containing semiconductor materials include, but are not limited to, boron, aluminum, gallium, and / or indium.

[0105] Reference Figure 2 and Figure 3 Impurity zones can form in the active zone AA and well zone 105 (in Figure 2 and Figure 3 (Not shown in the text). The impurity region will become the drain region 107 and the common source region 109, which will be described later. The impurity region can be fabricated using, for example, an implantation process using an n-type dopant. The term "n-type dopant" refers to an impurity that, when added to an intrinsic semiconductor material, contributes free electrons to the intrinsic semiconductor material. Examples of n-type dopants in silicon-containing materials include, but are not limited to, antimony, arsenic, and / or phosphorus. The impurity region may have a second electrical type (i.e., n-type) different from the first electrical type of the well region 105. In some embodiments, the dopant concentration of the impurity region may be greater than the dopant concentration of the well region 105. In some embodiments, the dopant concentration within the impurity region may be in the range of 4 × 10^20 atoms / cm³ to 2 × 10^21 atoms / cm³; although other dopant concentrations less than or greater than the above ranges may also be used in this disclosure.

[0106] In some embodiments, an annealing process can be performed to enable well region 105 and the impurity region. The annealing process can have a process temperature ranging from approximately 800°C to approximately 1250°C. The process duration of the annealing process can range from approximately 1 millisecond to approximately 500 milliseconds. The annealing process can be, for example, rapid thermal annealing, laser spike annealing, or flash lamp annealing.

[0107] Reference Figure 2 and Figure 3Multiple trenches 200T can be formed in the substrate 101 to define the positions of multiple character line structures 200. The multiple trenches 200T can be fabricated using an etching process that uses a mask pattern (not shown for clarity) formed on the substrate 101 as an etching mask. In some embodiments, the multiple trenches 200T can be linear and extend along the X direction and traverse multiple active regions AA. For example, each active region AA can intersect with two trenches 200T.

[0108] Reference Figure 2 and Figure 3 The impurity region can be divided into two drain regions 107 and a common source region 109 by two trenches 200T. The two drain regions 107 can be formed between the two trenches 200T and the isolation layer 103, respectively. The common source region 109 can be formed between the two trenches 200T. The electrical type and doping concentration of the two drain regions 107 and the common source region 109 are the same as those of the impurity region.

[0109] Reference Figure 2 and Figure 3 Multiple character line structures 200 (e.g., two character line structures 200) may be formed respectively and correspondingly in two trenches 200T. For the sake of brevity, clarity and convenience, only one character line structure 200 will be described. Multiple character line structures 200 may include a character line insulating layer 201, a character line conductive layer 203 and a character line capping layer 205.

[0110] Reference Figure 2 and Figure 3 The character line insulating layer 201 can be conformally formed on the surface of the trench 200T. The character line insulating layer 201 can have a U-shaped cross-sectional profile. In other words, the character line insulating layer 201 can be formed inward in the substrate 101. In some embodiments, the character line insulating layer 201 can be fabricated by a thermal oxidation process. For example, the character line insulating layer 201 can be fabricated by oxidizing the surface of the trench 200T. In some embodiments, the character line insulating layer 201 can be fabricated by a deposition process, such as chemical vapor deposition or atomic layer deposition. The character line insulating layer 201 can include a high-k (dielectric constant) material, oxide, nitride, oxynitride, or a combination thereof. In some embodiments, after depositing a pad polysilicon layer, the character line insulating layer 201 can be formed by radical-oxidizing the pad polysilicon layer. In some embodiments, after the pad silicon nitride layer is formed, the character line insulation layer 201 can be formed by free radical oxidation of the pad silicon nitride layer.

[0111] In some embodiments, the high-k material may include a hafnium-containing material. The hafnium-containing material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium oxynitride, or a combination thereof. In some embodiments, the high-k material may be, for example, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, silicon zirconium oxide, silicon zirconium oxynitride, aluminum oxide, or a combination thereof. Other high-k materials may be selectively used in the high-k material.

[0112] Reference Figure 2 and Figure 3 The character line conductive layer 203 can be formed on the character line insulating layer 201. In some embodiments, to form the character line conductive layer 203, a conductive layer (not shown for clarity) can be formed to fill the trench 200T, followed by a recessing process. This recessing process can be performed as an etch-back process, or as a planarization process and an etching process performed consecutively. The character line conductive layer 203 can have a recessed shape that partially fills the trench 200T. That is, the top surface of the character line conductive layer 203 can be located on a vertical horizontal plane VL1 that is lower than the top surface of the substrate 101.

[0113] In some embodiments, the character line conductive layer 203 may include a metal, a metal nitride, or a combination thereof. For example, the character line conductive layer 203 may be fabricated using titanium nitride, tungsten, or titanium nitride / tungsten. After conformally forming titanium nitride, the titanium nitride / tungsten may have a structure in which the trench 200T is partially filled with tungsten. Titanium nitride or tungsten may be used entirely for the character line conductive layer 203. In some embodiments, the character line conductive layer 203 may be fabricated using a conductive material, such as polycrystalline silicon, polycrystalline silicon germanium, or a combination thereof. In some embodiments, the character line conductive layer 203 may be doped with dopants such as phosphorus, arsenic, antimony, or boron. In some embodiments, the character line conductive layer 203 may be fabricated using, for example, tungsten, aluminum, titanium, copper, or a combination thereof.

[0114] Reference Figure 2 and Figure 3 A first dielectric layer 111 can be formed to completely fill the plurality of trenches 200T and cover the top surface of the substrate 101. A planarization process, such as chemical mechanical polishing, can be performed to provide a substantially flat surface for subsequent process steps. The portion of the first dielectric layer 111 filling the plurality of trenches 200T can be referred to as the word line capping layer 205. In some embodiments, the fabrication techniques for the first dielectric layer 111 and the word line capping layer 205 are, for example, silicon oxide or silicon nitride, and can be deposited by, for example, a chemical vapor deposition technique.

[0115] Figure 2 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 3 and Figure 4This is a cross-sectional view illustrating a semiconductor element 1A along an embodiment of the present disclosure. Figure 5 Part of the preparation process for A-A' line imaging.

[0116] Figure 6 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 4 This is a cross-sectional view illustrating a semiconductor element 1A along an embodiment of the present disclosure. Figure 7 Part of the preparation process for A-A' line imaging. Figures 8 to 11 This is a cross-sectional view illustrating a semiconductor element 1A along an embodiment of the present disclosure. Figure 7 Part of the preparation process for B-B' line imaging.

[0117] Reference Figure 12 and Figure 7 In step S13, multiple bit line contacts 313 can be formed to electrically connect to multiple common source regions 109, multiple bit line structures 300 can be formed on the multiple bit line contacts 313, and multiple bit line spacer capping layers 311 can be formed to cover the multiple bit line structures 300.

[0118] For the sake of brevity, clarity and ease of description, only one bit line contact 313, one bit line structure 300 and one bit line spacer capping layer 311 are described.

[0119] Reference Figure 1 and Figures 4 to 12 The bit line contact 313 can be formed along the first dielectric layer 111, extending to the common source region 109 and electrically connected to it. The bit line contact 313 can be fabricated using, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. The bit line contact 313 can be fabricated using, for example, damascene techniques.

[0120] Reference Figure 4A first conductive material layer 601, a second conductive material layer 603, a third conductive material layer 605, and a first insulating material layer 609 can be sequentially formed on the first dielectric layer 111. The first conductive material 601 can be, for example, a doped semiconductor material, such as doped silicon or doped germanium. The second conductive material 603 can be, for example, a conductive metal nitride (e.g., titanium nitride or tantalum nitride). The third conductive material 605 can be, for example, a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum), or a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide). The first insulating material 609 can be, for example, silicon nitride, silicon oxynitride, silicon nitride oxide, or combinations thereof. The fabrication techniques for the first conductive material layer 601, the second conductive material layer 603, the third conductive material layer 605, and the first insulating material layer 609 can be employed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or other suitable deposition processes.

[0121] Reference Figure 5 and Figure 6 A bitline mask (not shown for clarity) can be used as a pattern guide to perform the etching process, such as an anisotropic dry etching process, to remove a portion of the first insulating material 609 layer, a portion of the third conductive material 605 layer, a portion of the second conductive material 603 layer, and a portion of the first conductive material 601 layer. In some embodiments, the etching process can be a multi-step etching process. After the etching process, the first conductive material 601 layer can become the bottom conductive portion 303, the second conductive material 603 layer can become the middle conductive portion 305, the third conductive material 605 layer can become the top conductive portion 307, and the first insulating material 609 layer can become the bitline inner capping layer 309. The bottom conductive portion 303, the middle conductive portion 305, and the top conductive portion 307 are collectively configured to form the bitline conductive layer 301. The bitline conductive layer 301 and the bitline inner capping layer 309 are collectively configured to form the bitline structure 300. In some embodiments, the bitline structure 300 may extend along the Y direction from a top-down view.

[0122] Reference Figure 7 An interstitial layer 611 can be conformally formed to cover the first dielectric layer 111 and the bit line structure 300. In some embodiments, the interstitial layer 611 may include silicon dioxide, silicon nitride, boron nitride, semiconductor carbide, semiconductor oxide nitride, or dielectric metal oxide. In some embodiments, the interstitial layer 611 may be a stacked structure composed of silicon oxide-silicon nitride-silicon oxide. The interstitial layer 611 can be fabricated by deposition processes, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or atomic layer deposition.

[0123] Reference Figure 8An interstitial layer etching process can be performed to remove a portion of the interstitial layer 611 formed on the top surface of the first dielectric layer 111. The remaining interstitial layer 611 can be referred to as a bit-line spacer capping layer 311 covering the bit-line structure 300. The interstitial layer etching process can be, for example, an anisotropic etching process, such as reactive ion etching. In some embodiments, the thickness of the bit-line spacer capping layer 311 can range from approximately 200 angstroms to approximately 1000 angstroms. In some embodiments, the thickness of the plurality of bit-line structures 300 can range from approximately 400 angstroms to approximately 800 angstroms.

[0124] It should be understood that, in order to emphasize the presence of the bit line spacer capping layer 311, the thickness of the bit line spacer capping layer 311 is not shown to scale.

[0125] Reference Figure 9 and Figure 10 A second dielectric layer 113 can be formed on the first dielectric layer 111 to cover the bit line structure 300. The second dielectric layer 113 may include, for example, silicon oxide, undoped silicate glass, fluorosilicate glass, borosilicate glass, spin-on low-k dielectric layer, chemical vapor deposition low-k dielectric layer, or combinations thereof. In some embodiments, the second dielectric layer 113 may include a self-planarizing material, such as spin glass or a spin low-k dielectric material, such as SiLKTM. In some embodiments, the fabrication technique of the second dielectric layer 113 may be by deposition processes, including, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, planarization processes, such as chemical mechanical polishing, may be performed to provide a substantially flat surface for subsequent process steps.

[0126] Figure 11 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 12 This is a cross-sectional view illustrating a semiconductor element 1A along an embodiment of the present disclosure. Figure 13 Part of the preparation process for A-A' line imaging. Figure 14 and Figure 13 This is a cross-sectional view illustrating a semiconductor element 1A along an embodiment of the present disclosure. Figure 15 Part of the preparation process for B-B' line imaging.

[0127] Reference Figure 16 and Figure 13 In step S15, a plurality of storage cell contacts 411 may be formed to be electrically connected to a plurality of drain regions 107, a blanket-like pad 607 may be formed on the plurality of cell contacts 411 and bit line structure 300, and a plurality of pad openings 607O may be formed to divide the blanket-like pad 607 into a plurality of landing pads 413.

[0128] Reference Figure 1 Multiple cell contacts 411 (e.g., two cell contacts 411) can be formed respectively and correspondingly along the penetration of the second dielectric layer 113 and the first dielectric layer 111, and on the two drain regions 107. The fabrication techniques for the two cell contacts 411 can be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. The fabrication techniques for the two cell contacts 411 can be, for example, damascene techniques.

[0129] Reference Figures 13 to 16 The blanket-like pad 607 can be formed on the second dielectric layer 113, the two cell contacts 411, and the bit line spacer capping layer 311. The blanket-like pad 607 can be fabricated using, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. The blanket-like pad 607 can be fabricated using, for example, chemical vapor deposition, physical vapor deposition, or other suitable deposition processes.

[0130] Reference Figures 13 to 15 A pad etching process can be performed to remove a portion of the blanket pad 607, a portion of the bit line spacer capping layer 311, a portion of the bit line inner capping layer 309, and a portion of the second dielectric layer 113. In some embodiments, the pad etching process can be, for example, an isotropic etching process. In some embodiments, pad etching can include multiple etching steps to etch different materials separately and accordingly.

[0131] After the pad etching process, multiple pad openings 607O can be formed, and the blanket-like pad 607 can be divided into multiple landing pads 413 through the multiple pad openings 607O. The second dielectric layer 113, the bit line internal capping layer 309, and the bit line spacer capping layer 311 can be exposed in the pad openings 607O. In some embodiments, the bit line internal capping layer 309 may include a lower portion 309-1 and an upper portion 309-3. The lower portion 309-1 may be disposed on the bit line conductive layer 301. The top surface of the lower portion 309-1 and the bottom surface of the pad opening 607O are substantially coplanar. The upper portion 309-3 may be disposed on the lower portion 309-1 and adjacent to the pad opening 607O. The width W1 of the upper portion 309-3 may be smaller than the width W2 of the bit line conductive layer 301.

[0132] Figures 13 to 15 The diagram illustrates an example of the fabrication conditions for the sealing layer 415 of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 16This is a cross-sectional view illustrating part of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure.

[0133] Reference Figure 17 and Figures 18 to 20 In step S17, a sealing layer 415 may be formed to seal multiple pad openings 607O and form multiple air gaps 417, and multiple capacitor contacts 419 may be formed on multiple landing pads 413.

[0134] For the sake of brevity, clarity and ease of description, only one air gap, 417, will be described.

[0135] Reference Figure 1 , Figures 17 to 20 and Figure 17 The sealing layer 415 can be fabricated using silicon nitride. The sealing layer 415 can be fabricated using a first deposition process. This first deposition process can be an atomic layer deposition (ALD) process. Typically, in an ALD process, under predetermined process conditions, two (or more) different source gases are alternately supplied to the workpiece, causing chemical species in the source gases to be adsorbed onto the workpiece at a single atomic layer level and deposited onto the workpiece through surface reactions. For example, a first source gas and a second source gas are alternately supplied to the workpiece and flow along its surface, causing molecules (or chemical species) in the first source gas to be adsorbed onto the surface of the workpiece, and molecules (or chemical species) in the second source gas to react with the adsorbed molecules from the first source gas, forming a monolayer-thick film. These process steps are repeated, thus allowing the formation of a high-quality film on the workpiece.

[0136] In some embodiments, during the atomic layer deposition process of this embodiment, the supply of the first source gas can be limited so that the first precursor molecules 701 in the first source gas are adsorbed only on the upper part of the pad opening 607O and the top surface of the landing pad 413. Therefore, the thin film formed by the reaction of the second precursor molecules 703 in the second source gas with the adsorbed first precursor molecules 701 can be located only on the upper part of the pad opening 607O (i.e., the upper part of the sidewall 413SW of the landing pad 413) and the top surface of the landing pad 413, and not on the lower part of the pad opening 607O. In some embodiments, the limited supply of the first source gas can be achieved by precisely controlling the transfer time of the first source gas. For example, the transfer time of the first source gas can be in the range of approximately 0.15 s to approximately 0.50 s, in the range of approximately 0.15 s to approximately 0.30 s, or approximately 0.2 s. In some embodiments, the limited supply of the first source gas can be achieved by controlling the flow rate of the first source gas.

[0137] In some embodiments, the first deposition process may include a first silicon precursor supply step 501 and a first nitrogen precursor supply step 503, performed sequentially. In the first silicon precursor supply step 501, a first silicon precursor (i.e., a first source gas) may be supplied to the reaction chamber, and chemical species from the first silicon precursor (e.g., first precursor molecule 701) may be adsorbed at the monolayer level onto the upper surface of the pad opening 607O and the top surface of the landing pad 413. In the first nitrogen precursor supply step 503, a first nitrogen precursor (i.e., a second source gas) may be excited and supplied to the reaction chamber, and chemical species contained in the first nitrogen precursor (e.g., second precursor molecule 703) may react with the adsorbed chemical species from the first silicon precursor to form a silicon nitride film of monomolecular thickness. The silicon nitride film may be formed on the upper surface of the pad opening 607O and the top surface of the landing pad 413.

[0138] The first silicon precursor supply step 501 may include a stabilization stage, a flow stage, and a purge and vacuuming stage.

[0139] Reference Figure 18 , Figure 19 and Figure 17 In the stabilization stage of the first silicon precursor supply step 501, a dilution gas (or carrier gas), such as nitrogen, may be supplied to the reaction chamber. The flow rate of the dilution gas may be in the range of approximately 0.3 slm (standard liters per minute) to approximately 0.7 slm. For example, in this embodiment, the flow rate of the dilution gas may be 0.5 slm. The process temperature of the stabilization stage may be in the range of approximately 25°C to approximately 700°C, approximately 50°C to approximately 600°C, approximately 100°C to approximately 500°C, approximately 200°C to approximately 450°C, or approximately 350°C to approximately 425°C. For example, in this embodiment, the process temperature of the stabilization stage may be 400°C. The process pressure of the stabilization stage may be in the range of approximately 200 Pa to approximately 600 Pa, approximately 300 Pa to approximately 500 Pa, or approximately 350 Pa to approximately 450 Pa. For example, in this embodiment, the process pressure during the stabilization stage can be 400 Pa.

[0140] Reference Figure 18 , Figure 19 and Figure 17In the flow-through stage of the first silicon precursor supply step 501, the first silicon precursor may be supplied to the reaction chamber while a dilution gas is supplied. Chemical species from the first silicon precursor may be adsorbed at the monolayer level onto the upper portion of the pad opening 607O and the top surface of the landing pad 413. In some embodiments, the first silicon precursor may include halides such as iodine (I) or chlorine (Cl). In this embodiment, the first silicon precursor may be, for example, dichlorosilane. The reaction between the first silicon precursor and the adsorption surface (i.e., the upper portion of the pad opening 607O and the top surface of the landing pad 413) can be shown in Formula 1. In some embodiments, the first silicon precursor may include, for example, silicon tetrachloride, trichlorosilane, dichlorosilane, or hexachlorodisil. In some embodiments, the first silicon precursor may include, for example, silicon tetraiodide, triiodosilane, diiodosilane, iodosilane, disilicate hexaiodide, triiodosilane octaiodide, H₂Si₂I₄, H₃Si₂I₃, H₄Si₂I₂, H₅Si₂I₂, or HSi₂I₅. In some embodiments, the first silicon precursor may include one of triiodosilane, diiodosilane, iodosilane, H₂Si₂I₄, H₄Si₂I₂, and H₅Si₂I. In some embodiments, the first silicon precursor may include two, three, four, five, or six of triiodosilane, diiodosilane, iodosilane, H₂Si₂I₄, H₄Si₂I₂, and H₅Si₂I, including any combination thereof.

[0141] -NH₂ + SiH₂Cl₂ → -NH₄⁻SiH₂Cl + HCl (Equation 1)

[0142] Reference Figure 18 Figure 19 and Figure 17 During the flow-through stage of the first silicon precursor supply step 501, the flow rate of the first silicon precursor can be in the range of approximately 1 slm to approximately 5 slm, or in the range of approximately 3 slm to approximately 4.5 slm. For example, in this embodiment, the flow rate of the first silicon precursor can be 1 slm. If the flow rate of the first silicon precursor is less than 1 slm, the amount of the first silicon precursor may be insufficient to supply nitrogen atoms to the adsorption surface. If the flow rate of the first silicon precursor is greater than 5 slm, the chemical species contained in the first silicon precursor may adsorb at the lower part of the pad opening 607O, thus causing the formed silicon nitride film to cover the lower part of the pad opening 607O. Therefore, the space of the air gap 417 may be reduced due to the formed silicon nitride film located at the lower part of the pad opening 607O. The flow rate of the dilution gas can be in the range of approximately 0.3 slm to approximately 0.7 slm. For example, in this embodiment, the flow rate of the dilution gas can be 0.5 slm.

[0143] Reference Figure 18 , Figure 19 and Figure 17In the flow-through stage of the first silicon precursor supply step 501, the process temperature of the flow-through stage can be in the range of approximately 200°C to approximately 550°C. For example, in this embodiment, the process temperature of the flow-through stage can be approximately 400°C. If the process temperature is below 200°C, chemical species from the first silicon precursor may not adsorb onto the adsorption surface. If the process temperature is above 550°C, the reliability of the bit line structure 300 may be affected. In some embodiments, the process temperature of the flow-through stage can be in the range of approximately 390°C to approximately 410°C. By using the above temperature range, the deposition rate can be improved, and various properties of the resulting silicon nitride layer, such as thickness uniformity, wet erosion resistance, and film stress, can be improved.

[0144] Reference Figure 18 , Figure 19 and Figure 17 In the flow-through stage of the first silicon precursor supply step 501, the process pressure of the flow-through stage can be in the range of approximately 400 Pa to approximately 1200 Pa, approximately 600 Pa to approximately 1100 Pa, or approximately 800 Pa to approximately 1000 Pa. For example, in this embodiment, the process pressure of the flow-through stage can be 850 Pa. By using the above pressure range, the reaction rate between nitrogen atoms and the first silicon precursor can be increased, and the pressure can be adjusted at any time.

[0145] Reference Figure 18 , Figure 19 and Figure 17 During the blowing and vacuuming stage of the first silicon precursor supply step 501, the supply of the first silicon precursor can be stopped. The flow rate of the dilution gas can be increased to blow the reaction chamber. For example, the flow rate of the dilution gas can be in the range of about 3 slm to about 7 slm. In the embodiment described, the flow rate of the dilution gas can be 5 slm.

[0146] In some embodiments, the first nitrogen precursor supply step 503 may include a stabilization stage, a flow stage, and a blowing and vacuuming stage.

[0147] Reference Figure 18 , Figure 19 and Figure 17In the stabilization stage of the first nitrogen precursor supply step 503, a dilution gas, such as nitrogen, may be supplied to the reaction chamber. The flow rate of the dilution gas may be in the range of approximately 0.3 slm to approximately 0.7 slm. For example, in this embodiment, the flow rate of the dilution gas may be 0.5 slm. The process temperature of the stabilization stage may be in the range of approximately 25°C to approximately 700°C, approximately 50°C to approximately 600°C, approximately 100°C to approximately 500°C, approximately 200°C to approximately 450°C, or approximately 350°C to approximately 425°C. For example, in this embodiment, the process temperature of the stabilization stage may be 400°C. The process pressure of the stabilization stage may be in the range of approximately 10 Pa to approximately 70 Pa, approximately 20 Pa to approximately 60 Pa, or approximately 30 Pa to approximately 50 Pa. For example, in this embodiment, the process pressure of the stabilization stage may be 50 Pa.

[0148] Reference Figure 18 , Figure 19 and Figure 17 In the flow stage of the first nitrogen precursor supply step 503, the first nitrogen precursor may be excited in the plasma generating element and then supplied to the reaction chamber simultaneously with the supply of dilution gas. The chemical species contained in the excited first nitrogen precursor may react with chemical species adsorbed from the first silicon precursor to form a silicon nitride film on the adsorption surface. The first nitrogen precursor may be, for example, ammonia.

[0149] Reference Figure 18 , Figure 19 and Figure 17 During the flow-through stage of the first nitrogen precursor supply step 503, the radio frequency (RF) circuit in the plasma generation unit can be turned on to excite the first nitrogen precursor. The RF power during the flow-through stage can be in the range of approximately 50 W to approximately 1000 W, or approximately 100 W to approximately 300 W. If the RF power during the flow-through stage exceeds 1000 W, the quartz walls of the plasma generation unit may be damaged. The RF power density during the flow-through stage can be approximately 0.02 W / cm². 2 (Watts per square centimeter) to approximately 2.0 W / cm² 2 Within that range, or at approximately 0.05 W / cm 2 Up to approximately 1.5 W / cm 2The process frequency of the plasma generation unit can be in the range of approximately 10.00 MHz (megahertz) to approximately 15.00 MHz. For example, in this embodiment, the process frequency of the plasma generation unit in the flow stage can be 13.56 MHz. In the embodiment described, the excited first nitrogen precursor can be an ammonia radical (NH3*). The excited first nitrogen precursor can be provided to the reaction chamber in the form of plasma.

[0150] Reference Figure 18 , Figure 19 and Figure 17 In the flow-through stage of the first nitrogen precursor supply step 503, the flow rate of the excited first nitrogen precursor can be in the range of approximately 0.5 slm to approximately 5 slm, or in the range of 3 slm to approximately 5 slm. By using the above flow rate range, plasma of the excited first nitrogen precursor can be easily generated, and the amount of the excited first nitrogen precursor can be sufficient to react with the chemical species adsorbed from the first silicon precursor. In this embodiment, the flow rate of the excited first nitrogen precursor can be, for example, 3 slm. It should be understood that the dilution gas can still be supplied in the flow-through stage, and the flow rate of the dilution gas can be in the range of approximately 0.3 slm to approximately 0.7 slm. For example, in the embodiment described, the flow rate of the dilution gas is still 0.5 slm.

[0151] Reference Figure 18 , Figure 19 and Figure 17 During the flow-through stage of the first nitrogen precursor supply step 503, the process pressure in the reaction chamber can be in the range of approximately 40 Pa to approximately 100 Pa, or approximately 50 Pa to approximately 70 Pa. For example, in this embodiment, the process pressure in the reaction chamber can be 50 Pa. The process pressure in the plasma generation unit can be in the range of approximately 70 Pa to approximately 600 Pa, or approximately 280 Pa to approximately 330 Pa. By using the above-mentioned process pressure range in the plasma generation unit, plasma of the excited first nitrogen precursor can be easily generated, and the amount of the excited first nitrogen precursor can be sufficient to react with the chemical species adsorbed from the first silicon precursor.

[0152] Reference Figure 18 , Figure 19 and Figure 17 In the flow stage of the first nitrogen precursor supply step 503, the reaction between the excited first nitrogen precursor and the chemical species derived from the first silicon precursor after adsorption can be represented by Formulas 2 and 3.

[0153] -NH-SiH2Cl+NH*3→-NH-SiH2(NH2)+HCl (Equation 2)

[0154] -NH-SiH2Cl+NH*3→-NH-SiHCl(NH2)+H2 (Equation 3)

[0155] In some embodiments, the transfer time of the first nitrogen precursor may be in the range of about 0.40 s to about 0.70 s, about 0.45 s to about 0.65 s, or about 0.6 s.

[0156] Reference Figure 18 , Figure 19 and Figure 17 During the blowing and vacuuming phase of the first nitrogen precursor supply step 503, the supply of the first nitrogen precursor can be stopped, and the radio frequency of the plasma generation unit can be turned off. The flow rate of the dilution gas can be increased to blow the reaction chamber. For example, the flow rate of the dilution gas can be in the range of approximately 3 slm to approximately 7 slm. In the embodiment described, the flow rate of the dilution gas can be 5 slm.

[0157] Following this first deposition process, a silicon nitride thin film can be formed. This first deposition process can be repeated multiple times (only four times are shown for clarity) to form a silicon nitride thin film layer of the desired thickness. This silicon nitride thin film layer of the desired thickness can be referred to as sealing layer 415. In some embodiments, the number of repetitions of the first deposition process can range from approximately 20 to approximately 60, from approximately 30 to approximately 50, or from approximately 34 to 40. Sealing layer 415 can cover the upper portion of pad opening 607O and the top surface of landing pad 413. Pad opening 607O can be sealed by sealing layer 415, and the sealed pad opening 607O can be referred to as air gap 417. In some embodiments, the bottom surface 415BS of sealing layer 415 lies on the vertical horizontal plane VL2 between the top surface 413TS and the bottom surface 413BS of landing pad 413.

[0158] In some embodiments, planarization processes, such as chemical mechanical polishing, can be performed to provide a substantially flat surface for subsequent processing steps.

[0159] In some embodiments, the center line CL1 of the air gap 417 may be misaligned with the center line CL2 of the bit line structure 300.

[0160] In some embodiments, an air gap 417 may be formed between the landing pad 413 and the bit line conductive layer 301, and adjacent to the upper portion 309-3 of the bit line inner capping layer 309. The width W1 of the upper portion 309-3 of the bit line inner capping layer 309 may be smaller than the width W2 of the bit line conductive layer 301.

[0161] Reference Figure 18A third dielectric layer 115 can be formed on the sealing layer 415. The third dielectric layer 115 may include, for example, silicon oxide, undoped silicate glass, fluorosilicate glass, borosilicate glass, spin low-k dielectric layer, chemical vapor deposition low-k dielectric layer, or combinations thereof. In some embodiments, the third dielectric layer 115 may include a self-planarizing material, such as spin glass or a spin low-k dielectric material, such as SiLKTM. In some embodiments, the fabrication technique for the third dielectric layer 115 may be by deposition processes, including, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating.

[0162] For the sake of brevity, clarity and ease of description, Figure 19 Only one capacitor contact 419 is described and shown.

[0163] Reference Figure 17 Figure 18 Figure 19 Figure 17 Figure 18 Figure 19 Figure 17 Figure 18 Figure 19 Figure 17 Figure 18 Figure 19 Figure 17 Figure 18 Figure 19 Figure 17 Figure 18 Figure 19 Figure 17 Figure 18 Figure 19 Figure 17 Figure 18 Figure 19 Figure 20 Figure 20 Figure 20 The capacitor contact 419 can be formed along the third dielectric layer 115, along the sealing layer 415, and on the landing pad 413. The capacitor contact 419 can be manufactured using, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. The capacitor contact 419 can be manufactured using, for example, an inlay technique.

[0164] One embodiment of this disclosure provides a semiconductor device including a substrate; a drain region disposed in the substrate; a common source region disposed in the substrate and opposite to the drain region; a bit line structure including a bit line conductive layer disposed on the substrate and electrically coupled to the common source region; a memory cell contact disposed on the substrate, adjacent to the bit line structure and electrically coupled to the drain region; a landing pad disposed above the bit line conductive layer and electrically coupled to the cell contact; and an air gap disposed between the landing pad and the bit line conductive layer.

[0165] Another embodiment of this disclosure provides a semiconductor device including a bitline structure, the bitline structure comprising: a bitline conductive layer and a bitline internal capping layer, the bitline internal capping layer including a lower portion disposed on the bitline conductive layer and an upper portion disposed on the lower portion; a landing pad disposed above the bitline internal capping layer; and an air gap disposed between the landing pad and the bitline conductive layer, adjacent to the upper portion of the bitline internal capping layer. The width of the upper portion of the bitline internal capping layer is smaller than the width of the bitline conductive layer.

[0166] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a bit-line conductive layer and a bit-line internal capping layer on the substrate, wherein the bit-line conductive layer and the bit-line internal capping layer are configured together to form a bit-line structure; forming a bit-line spacer capping layer covering the bit-line structure; forming a cell contact adjacent to the bit-line structure. A blanket-like pad layer is formed on the bit-line spacer capping layer and the cell contact; a plurality of pad openings are formed along the blanket-like pad layer and extend to the bit-line spacer capping layer and the bit-line internal capping layer, such that the blanket-like pad layer becomes a plurality of landing pads; and selectively forming a sealing layer on the plurality of landing pads and covering the upper part of the plurality of pad openings to form a plurality of air gaps between the bit-line conductive layer and the plurality of landing pads.

[0167] Due to the design of the semiconductor device disclosed herein, an air gap 417 can be formed between the landing pad 413 and the bit line conductive layer 301. Therefore, the parasitic capacitance between the landing pad 413 and the bit line conductive layer 301 can be reduced. Consequently, the power consumption of the semiconductor device 1A can be reduced.

[0168] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined by the scope of the disclosed patent. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0169] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of this document that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used in accordance with this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the patent disclosed in this disclosure.

Claims

1. A method for fabricating a semiconductor device, comprising: Provide a base; A bit line conductive layer is formed on the substrate, and a bit line internal capping layer is formed on the bit line conductive layer, wherein the bit line conductive layer and the bit line internal capping layer are configured together to form a bit line structure. A bit-line spacer capping layer is formed to cover the bit-line structure; A one-cell contact is formed adjacent to the bit line structure; A blanket-like pad is formed at the junction of the bit line spacer capping layer and the cell contact; Multiple mat openings are formed along the blanket-like mat layer and extend to the bit line spacer capping layer and the bit line inner capping layer, so that the blanket-like mat layer becomes multiple landing mats; as well as A sealing layer is selectively formed on the plurality of landing pads, covering the upper part of the plurality of pad openings, to create a plurality of air gaps between the bit-wire conductive layer and the plurality of landing pads. The process includes performing a first deposition process to selectively form the sealing layer, and the first deposition process includes: A first silicon precursor supply step to supply a first silicon precursor; as well as A first nitrogen precursor supply step, to supply a first nitrogen precursor. The first silicon precursor supply step includes a stabilization stage, a flow stage, and a blow-and-vacuum stage, wherein the transfer time of the first silicon precursor in the flow stage is between approximately 0.15 s and approximately 0.50 s.

2. The method for preparing a semiconductor device as described in claim 1, wherein the first silicon precursor is dichlorosilane, and the first nitrogen precursor is ammonia.

3. The method for fabricating a semiconductor device as claimed in claim 1, wherein a process temperature of the fluidization stage of the first silicon precursor supply step is between approximately 200°C and approximately 550°C.

4. The method for fabricating a semiconductor device as claimed in claim 1, wherein a process pressure in the flow stage of the first silicon precursor supply step is between approximately 400 Pa and approximately 1200 Pa.

5. The method for fabricating a semiconductor device as claimed in claim 1, wherein the flow rate of the dilution gas in the fluidization stage of the first silicon precursor supply step is in the range of approximately 0.3 standard liters per minute to approximately 0.7 standard liters per minute.

6. The method for preparing a semiconductor device as claimed in claim 1, wherein the dilution gas in the stabilization stage of the first silicon precursor supply step is nitrogen.

7. The method for fabricating a semiconductor device as claimed in claim 1, wherein the flow rate of the dilution gas in the stabilization stage of the first silicon precursor supply step is in the range of approximately 0.3 standard liters per minute to approximately 0.7 standard liters per minute.

8. The method for fabricating a semiconductor device as claimed in claim 1, wherein the process temperature of the stabilization stage of the first silicon precursor supply step is between about 25°C and about 700°C.

9. The method for fabricating a semiconductor device as claimed in claim 1, wherein the process pressure of the stabilization stage of the first silicon precursor supply step is between approximately 200 Pa and approximately 600 Pa.

10. The method for fabricating a semiconductor device as claimed in claim 1, wherein the flow rate of the dilution gas in the blowing and vacuuming stage of the first silicon precursor supply step is in the range of approximately 3 standard liters per minute to approximately 7 standard liters per minute.

11. The method for fabricating a semiconductor device as claimed in claim 1, wherein the first nitrogen precursor supply step includes a stabilization stage, a flow stage, and a blowing and vacuuming stage, wherein the transfer time of the first nitrogen precursor in the flow stage is in the range of about 0.40 s to about 0.70 s.

12. The method for fabricating a semiconductor device as claimed in claim 1, wherein the flow rate of the fluidization stage of the first nitrogen precursor supply step is in the range of approximately 0.5 standard liters per minute to approximately 5 standard liters per minute.

13. The method for fabricating a semiconductor device as claimed in claim 1, wherein the process pressure of the fluidization stage of the first nitrogen precursor supply step is in the range of about 40 Pa to about 100 Pa.

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