Integrated mos transistor package structure and battery management system

Abstract

The present disclosure provides an integrated MOS transistor packaging structure and a battery management system. The integrated MOS transistor packaging structure comprises: N MOS transistors, each of which comprises a gate, a drain and a source, wherein N>1; a packaging carrier, which is provided with a gate pin, a source pin and a drain pin, each gate of the N MOS transistors is connected to the gate pin by wire bonding, and each source of the N MOS transistors is connected to the source pin by wire bonding, copper strip or copper sheet; and a printed circuit board, which is provided with a copper-clad area, the copper-clad area is connected to the drains of the N MOS transistors, wherein the number of the copper-clad area is one or more than two, each copper-clad area is connected to the drains of n MOS transistors, so that the drains of the n MOS transistors are connected through the corresponding copper-clad area, wherein 1≤n≤N, and the printed circuit board is arranged in the packaging carrier and is used for arranging the N MOS transistors.

Description

Technical Field

[0001] This disclosure relates to an integrated MOS transistor package structure and a battery management system. Background Technology

[0002] Currently used charge / discharge switches are typically discrete. In industry, each switch needs to be soldered onto a corresponding circuit board, which is costly and requires ensuring reliability during manufacturing. For example, the technical solutions provided in US Patent Publication US20220190629A1...

[0003] The adoption of integrated power switches is becoming an industry trend. Since integrated power switches are located between the battery and the load / charger, they consume power, which generates heat. If this heat is not dissipated effectively, it will affect the operation of the power devices. Summary of the Invention

[0004] To address one of the aforementioned technical problems, this disclosure provides an integrated MOS transistor package structure and a battery management system. According to the power integrated chip of this disclosure, the chip's own resistance can be effectively reduced, and heat dissipation can be achieved.

[0005] According to one aspect of this disclosure, an integrated MOS transistor package structure includes: N MOS transistors, each of the N MOS transistors including a gate, a drain, and a source, wherein N > 1; a package carrier having gate pins, source pins, and drain pins, wherein the gates of the N MOS transistors are connected to the gate pins by wire bonding, and the sources of the N MOS transistors are connected to the source pins by wire bonding, copper strip bonding, or copper sheet bonding; and a printed circuit board having copper-clad regions connected to the drains of the N MOS transistors, wherein the number of copper-clad regions is one or more, and each copper-clad region is connected to the drains of the n MOS transistors, such that the drains of the n MOS transistors are connected through corresponding copper-clad regions, wherein 1 ≤ n ≤ N, wherein the printed circuit board is disposed within the package carrier and is used to house the N MOS transistors.

[0006] According to at least one embodiment of the integrated MOS transistor package structure of the present disclosure, the copper plating area is disposed on a printed circuit board, and the copper plating area is set to a predetermined size to facilitate heat dissipation.

[0007] According to at least one embodiment of the integrated MOS transistor package structure of this disclosure, the number of copper-clad regions is one, and the drains of N MOS transistors are all connected to the one copper-clad region in order to connect the drains of the N MOS transistors.

[0008] According to at least one embodiment of the integrated MOS transistor package structure of the present disclosure, the number of copper-clad regions is two, the drains of N / 2 of the N MOS transistors are all connected to one copper-clad region, and the remaining N / 2 of the N MOS transistors are all connected to the other copper-clad region.

[0009] According to at least one embodiment of the integrated MOS transistor package structure of this disclosure, the printed circuit board is provided with a source potential region. The sources of m MOS transistors out of the N MOS transistors are connected to a first source potential region of the source potential region through wire bonding, copper strip bonding, or copper sheet bonding. The sources of Nm MOS transistors out of the N MOS transistors are connected to a second source potential region of the source potential region through wire bonding, copper strip bonding, or copper sheet bonding. The first source potential region is connected to a first source pin, and the second source potential region is connected to a second source pin, wherein 1≤m≤N-1.

[0010] According to at least one embodiment of the integrated MOS transistor package structure of the present disclosure, the number of source potential regions is two or more, and each source potential region is connected to the source of at least one MOS transistor.

[0011] According to at least one embodiment of the integrated MOS transistor package structure of the present disclosure, the n MOS transistors are connected to two or more sub-copper regions, and the two or more sub-copper regions are connected by printed wires to connect the drains of the n MOS transistors.

[0012] The integrated MOS transistor package structure according to at least one embodiment of the present disclosure further includes one or more thermistors disposed within the package carrier and connected to thermistor pins.

[0013] According to at least one embodiment of the integrated MOS transistor package structure of this disclosure, N MOS transistors are divided into N / 2 charging MOS transistors and N / 2 discharging MOS transistors. The drains of the N / 2 charging MOS transistors are connected to the drains of the N / 2 discharging MOS transistors and connected to drain pins. The sources of the N / 2 charging MOS transistors are interconnected and connected to a first source pin or individually connected to the first source pin. The sources of the N / 2 discharging MOS transistors are interconnected and connected to a second source pin or individually connected to the second source pin. The gates of the N / 2 charging MOS transistors are interconnected and connected to a charging gate pin or individually connected to a charging gate pin. The gates of the N / 2 discharging MOS transistors are interconnected and connected to a discharging gate pin or individually connected to a charging gate pin.

[0014] According to at least one embodiment of the integrated MOS transistor package structure of the present disclosure, a pre-charge / discharge MOS transistor is further provided. The pre-charge / discharge MOS transistor includes a pre-charge MOS transistor and a pre-discharge MOS transistor. The drains of the pre-charge MOS transistor and the pre-discharge MOS transistor are interconnected. The gate of the pre-charge MOS transistor is connected to a pre-charge gate pin, the source of the pre-charge MOS transistor is connected to a pre-charge source pin, the gate of the pre-discharge MOS transistor is connected to a pre-discharge gate pin, and the source of the pre-discharge MOS transistor is connected to a pre-discharge power supply pin.

[0015] According to an integrated MOS transistor package structure of at least one embodiment of the present disclosure, the precharged MOS transistor includes a pair of precharged MOS transistors, and the pre-discharged MOS transistor includes a pair of pre-discharged MOS transistors.

[0016] According to at least one embodiment of the integrated MOS transistor package structure of the present disclosure, the gate includes a control gate and a discrete gate, the gate pin includes a control gate pin and a discrete gate pin, the control gate is connected to the control gate pin, and the discrete gate is connected to the discrete gate pin.

[0017] According to another aspect of this disclosure, a battery management system includes:

[0018] The integrated MOS transistor package structure as described in any of the preceding items; and

[0019] A driving unit, which is connected to the gate pin.

[0020] According to at least one embodiment of the battery management system of this disclosure, the source pin of the integrated MOS transistor package structure is connected between the low-voltage side of the battery pack and the low-voltage side of the load / charger, or between the high-voltage side of the battery pack and the high-voltage side of the load / charger. Attached Figure Description

[0021] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0022] Figure 1 This is a schematic diagram of the packaging structure according to one embodiment of the present disclosure.

[0023] Figure 2 This is a schematic diagram of a copper-clad area according to one embodiment of the present disclosure.

[0024] Figure 3This is a schematic diagram of a copper-clad area according to one embodiment of the present disclosure.

[0025] Figure 4 This is a schematic diagram of a copper-clad area according to one embodiment of the present disclosure.

[0026] Figure 5 This is a schematic diagram of the packaging structure according to one embodiment of the present disclosure.

[0027] Figure 6 This is a schematic diagram of the packaging structure according to one embodiment of the present disclosure.

[0028] Figure 7 This is a schematic diagram of the packaging structure according to one embodiment of the present disclosure.

[0029] Figure 8 This is a schematic diagram of the packaging structure according to one embodiment of the present disclosure.

[0030] Figure 9 This is a schematic diagram of the packaging structure according to one embodiment of the present disclosure.

[0031] Figure 10 This is a schematic diagram of the packaging structure according to one embodiment of the present disclosure.

[0032] Figure 11 This is a schematic diagram of the packaging structure according to one embodiment of the present disclosure.

[0033] Figure 12 This is a schematic diagram of the packaging structure according to one embodiment of the present disclosure.

[0034] Figure 13 This is a schematic diagram of the packaging structure according to one embodiment of the present disclosure.

[0035] Figure 14 This is a circuit diagram according to one embodiment of the present disclosure.

[0036] Figure 15 This is a schematic diagram of the packaging structure according to one embodiment of the present disclosure.

[0037] Figure 16 This is a schematic diagram of the structure of a battery management system according to one embodiment of the present disclosure.

[0038] Figure 17 This is a schematic diagram of the structure of a battery management system according to one embodiment of the present disclosure. Detailed Implementation

[0039] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0040] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0041] Unless otherwise stated, the exemplary implementations / embodiments shown are to be understood as providing exemplary features of various details that provide ways in which the technical concepts of this disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of various implementations / embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of this disclosure.

[0042] The use of crosshairs and / or shading in the accompanying drawings is generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities between the illustrated components, or any other characteristics, properties, etc., of the components. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0043] When a component is referred to as being "on" or "above" another component, "connected to," or "joined to" another component, the component may be directly on, directly connected to, or directly joined to the other component, or there may be intermediate components. However, when a component is referred to as being "directly on" another component, "directly connected to," or "directly joined to" another component, there are no intermediate components. Therefore, the term "connection" can refer to a physical connection, an electrical connection, etc., and may or may not have intermediate components.

[0044] For descriptive purposes, this disclosure may use spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side (e.g., in a “sidewall”)” to describe the relationship between one component and another component as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, a component described as “below” or “under” another component or feature would subsequently be positioned “above” said other component or feature. Thus, the exemplary term “below” can encompass both “above” and “below” orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0045] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, parts, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, parts, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0046] According to one embodiment of this disclosure, an integrated MOS transistor package structure is provided. This integrated MOS transistor package structure can be used in a battery management system as a charge / discharge switch, whereby external control causes the MOS transistor in the power integrated chip to turn on or off, thereby controlling the charging and discharging of the battery. Of course, based on the concept of this disclosure, this power integrated chip can also be used in other application scenarios outside of battery management systems.

[0047] According to the packaging structure disclosed herein, a packaging carrier may be included, and the various pins described below may be disposed on the packaging carrier. Furthermore, devices such as MOS transistors, printed circuit boards, and thermistors may be disposed within the packaging carrier. The MOS transistors may be surface-mounted on the printed circuit board and disposed within the packaging carrier. In this disclosure, the packaging carrier may be in the form of a packaging frame or a packaging substrate.

[0048] According to embodiments of this disclosure, the integrated MOS transistor package structure can integrate N MOS transistors, where N > 1. In this disclosure, the MOS transistors can be in the form of MOS transistors. The types of MOS transistors can be trench-gate MOS transistors, planar-gate MOS transistors, superjunction MOS transistors, or split-gate MOS transistors, etc. Each MOS transistor includes its own gate, drain, and source.

[0049] Figure 1 An integrated MOS transistor package structure according to an embodiment of the present disclosure is shown. Figure 1 As shown, this integrated MOS transistor package structure may include multiple MOS transistors 100. For example... Figure 1 As shown, the number of MOS transistors 100 can be eight, but those skilled in the art will understand that other numbers are also possible. This disclosure will use eight MOS transistors as an example. The integrated MOS transistor package structure may include gate pins GC and GD, which can be one or two. The gate pins can be connected to the gate of the MOS transistor 100 via wire bonding. In this disclosure, the gate of each MOS transistor 100 can be connected to its own gate pin via wire bonding, or the gates of two or more MOS transistors 100 can be interconnected via wire bonding, and then the connected gates can be connected to the gate pin via wire bonding. The source pins PSC and PSD can be connected to the source of each MOS transistor via wire bonding, copper strip, or copper sheet. The copper strip connection method is shown in the figure. Alternatively, a source pin can be provided relative to the source of each MOS transistor, or a single source pin can be provided relative to the sources of two or more MOS transistors. For example, in… Figure 1 In this configuration, a source pin is provided for each of the two MOS transistors.

[0050] exist Figure 1 In one embodiment, the drains of all MOS transistors are connected to a copper plating region 200, and the number of copper plating regions is one, thus enabling the connection of the drains of N MOS transistors. According to various embodiments of this disclosure, the number of copper plating regions is one or more, and each copper plating region is connected to the drains of n MOS transistors, so that the drains of n MOS transistors are connected through corresponding copper plating regions, where 1 ≤ n ≤ N.

[0051] Those skilled in the art will understand that an internal impedance is generated during the conduction process of a MOS transistor, which consumes the internal current flowing through it, resulting in unnecessary power consumption. By connecting the drains of multiple MOS transistors through a copper-clad region, the overall impedance of the MOS transistors can be reduced, thereby reducing the power consumed by the MOS transistors. In addition, the area occupied by the copper-clad region can be significantly larger than the area without a copper-clad region, which can effectively dissipate heat.

[0052] In embodiments of this disclosure, a copper-clad area is disposed on a printed circuit board, and the copper-clad area is set to a predetermined size for easy heat dissipation. The copper-clad area can be configured in various suitable shapes. Figures 2 to 4 The image shows three shapes of the copper-clad area. Figure 2 As shown, the copper-clad area is in a straight line shape. Figure 3 The image shows that the copper cladding area is H-shaped. Figure 4 The copper cladding area is shown as an angled H-shape. Those skilled in the art will understand that... Figures 2 to 4 The shape shown is merely an example and can be configured in other ways. The shape should facilitate heat dissipation. The printed circuit board has a source potential region. The sources of the N MOS transistors are connected to the source potential region via wire bonding, copper strip, or copper sheet, and the source potential region is connected to the source pin. There are two or more source potential regions, and each source potential region is connected to the source of at least one MOS transistor. In a preferred embodiment, the sources of m of the N MOS transistors are connected to a first source potential region of the source potential region via wire bonding, copper strip, or copper sheet, and the sources of Nm MOS transistors are connected to a second source potential region of the source potential region via wire bonding, copper strip, or copper sheet, with the first source potential region connected to a first source pin and the second source potential region connected to a second source pin, where 1 ≤ m ≤ N-1.

[0053] Furthermore, the integrated MOS transistor package structure according to this disclosure may also include a location for a thermistor, thereby further including one or more thermistors for measuring the temperature of the MOS transistor. The thermistor is disposed within the package carrier, for example, in a corner area of ​​the package carrier. In this application, the thermistor may also be disposed at other locations within the package carrier.

[0054] Figure 5 A second embodiment of the integrated MOS transistor package structure is shown, which is similar to... Figure 1The difference in this embodiment is that the printed circuit board has two copper-clad regions 200. The drains of N / 2 of the N MOS transistors are connected to one copper-clad region, and the remaining N / 2 of the N MOS transistors are connected to the other copper-clad region. Gate pins are located on opposite sides of the integrated MOS transistor package structure. Source pins are located on the other opposite sides of the integrated MOS transistor package structure.

[0055] Figure 6 A third embodiment of the integrated MOS transistor package structure is shown, which is similar to... Figure 1 The difference in this embodiment is that two copper-clad regions 200 are provided. The drains of N / 2 of the N MOS transistors are connected to one copper-clad region, and the remaining N / 2 MOS transistors are connected to the other copper-clad region. Gate pins are located on opposite sides of the integrated MOS transistor package structure. Source pins are located on the other opposite sides of the integrated MOS transistor package structure. Furthermore, the gate of each MOS transistor is connected to the gate pin via wire bonding.

[0056] Figure 7 A fourth embodiment of the integrated MOS transistor package structure is shown, which is similar to... Figure 1 The difference in this embodiment is that two copper-clad regions 200 are provided. The drains of N / 2 of the N MOS transistors are connected to one copper-clad region, and the remaining N / 2 MOS transistors are connected to the other copper-clad region. Gate pins are located on opposite sides of the integrated MOS transistor package structure. Source pins are located on the other opposite sides of the integrated MOS transistor package structure. Furthermore, the gate of each MOS transistor is connected to the gate pin via wire bonding.

[0057] Figure 8 A fifth embodiment of the integrated MOS transistor package structure is shown, which is similar to... Figure 1 The difference in the embodiment is that two copper-clad regions 200 are provided. The drains of N / 2 of the N MOS transistors are all connected to one copper-clad region, and the remaining N / 2 of the N MOS transistors are all connected to the other copper-clad region.

[0058] Figure 9 A sixth embodiment of the integrated MOS transistor package structure is shown, which is similar to... Figure 1The difference in this embodiment is that two copper-clad regions 200 are provided. The drains of N / 2 of the N MOS transistors are connected to one copper-clad region, and the remaining N / 2 of the N MOS transistors are connected to the other copper-clad region. The gate pins are located on opposite sides of the integrated MOS transistor package structure. The source pins are located on the same side as the gate pins, and the gate pins are located outside the source pins.

[0059] Figure 10 A seventh embodiment of the integrated MOS transistor package structure is shown, which is similar to... Figure 1 The difference in this embodiment is that a copper-clad region 200 is provided, which does not extend to the edge of the package structure, but rather extends to the edge via printed conductors. Gate pins are located on opposite sides of the integrated MOS transistor package structure. Source pins are located on the other opposite sides of the integrated MOS transistor package structure.

[0060] Figure 11 An eighth embodiment of the integrated MOS transistor package structure is shown, which is similar to... Figure 1 The difference in this embodiment is that a copper-clad region 200 is provided, and the two sides of the copper-clad region do not extend to the edge of the package structure, but extend to the edge through printed wires. Gate pins are located on opposite sides of the integrated MOS transistor package structure. Source pins are located on the other opposite sides of the integrated MOS transistor package structure. The gate of each MOS transistor is connected to the gate pin via wire bonding.

[0061] Figure 12 A ninth embodiment of the integrated MOS transistor package structure is shown, which is similar to... Figure 1 The difference in this embodiment is that a copper-clad region 200 is provided. One side of the copper-clad region does not extend to the edge of the package structure, but extends to the edge through printed wires. The other side of the copper-clad region extends entirely to the edge of the package structure. Gate pins are located on opposite sides of the integrated MOS transistor package structure. Source pins are located on the other opposite sides of the integrated MOS transistor package structure.

[0062] As shown in the figure, this disclosure provides various configurations for integrated MOS transistor package structures. Those skilled in the art will understand that the number of copper-clad areas and the pin positions can be configured according to specific circumstances. The gates of each MOS transistor can be interconnected and connected to gate pins, and the number of source pins can be one or more, etc.

[0063] in addition, Figure 13 A tenth embodiment of the integrated MOS transistor package structure is shown, which is similar to... Figure 1The difference in the embodiments is that the copper-clad area for interconnecting the n MOS transistors may include two or more sub-copper-clad areas 210 and 220, and the two or more sub-copper-clad areas are connected by printed wires 230 to connect the drains of the n MOS transistors. Furthermore, the gates of different MOS transistors can be connected to gate pins via printed wires, and the sources of different MOS transistors can be connected to source pins via printed wires.

[0064] The packaging structure according to the above embodiments of this disclosure also provides good heat dissipation. Typically, chip heat dissipation is achieved through air contact. In this air contact heat dissipation process, the chip's plastic casing contacts the air for heat dissipation, but this method is not ideal. However, in this disclosure, heat dissipation can be achieved through metal (copper-clad area) in addition to air contact heat dissipation. In this disclosure, the length and width of the copper-clad area are set to be relatively long, for example, equal to or close to the length (width) of the packaging structure. This allows for a large contact area with the copper-clad area of ​​the printed circuit board (PCB) after the chip is soldered, thus enabling heat dissipation through the copper-clad area. In other words, the relevant pins of the chip in this disclosure can be set to be very long, connecting to the printed circuitry of the PCB through the pins, thereby achieving metal heat dissipation.

[0065] Based on the design concept of this disclosure, a packaging structure for a battery management system is provided. Figure 14 The diagram shows a circuit diagram of the battery management system. This circuit diagram enables functions such as charge / discharge control and temperature detection for the battery management system, and also allows for pre-charge and pre-discharge functions.

[0066] like Figure 14 As shown, the circuit may include a first group of MOS transistors 310 and a second group of MOS transistors 320. The first group of MOS transistors 310 may include multiple MOS transistors connected in parallel, thereby reducing the on-resistance during charging and discharging, and correspondingly reducing the power consumption generated by the MOS transistors. The first group of MOS transistors 310 includes source interconnects, drain interconnects, and gate interconnects. The second group of MOS transistors 320 may include multiple MOS transistors connected in parallel, thereby reducing the on-resistance during charging and discharging, and correspondingly reducing the power consumption generated by the MOS transistors. The second group of MOS transistors 320 includes source interconnects, drain interconnects, and gate interconnects.

[0067] The drain of the first group of MOS transistors 310 can be connected to the drain of the second group of MOS transistors 320. The first group of MOS transistors 310 can function as a charge / discharge transistor, while the second group of MOS transistors 320 can function as a discharge / charge transistor. The source of each MOS transistor in the first group of MOS transistors 310 can be connected to pin S2M, and the source of each MOS transistor in the second group of MOS transistors 310 can be connected to pin S1M.

[0068] The first group of MOS transistors 310 and the second group of MOS transistors 320 can be dual-gate MOS transistors. The first gate of the first group of MOS transistors 310 can be connected to pin SG2M, and the second gate can be connected to pin G2M. The first gate of the second group of MOS transistors 320 can be connected to pin SG1M, and the second gate can be connected to pin G1M. In this disclosure, the first gate can be a control gate or a discrete gate, and the second gate can be a discrete gate or a control gate. Pins SG1M and G1M are one of the control gate pin and the discrete gate pin, respectively.

[0069] The drains of the interconnects between the first group of MOS transistors 310 and the second group of MOS transistors 320 can be connected to pin DM.

[0070] In addition, a pre-charge / discharge MOS transistor 330 may be provided. The pre-charge / discharge MOS transistor 330 may include two MOS transistors connected in series. The drain of the first MOS transistor can be connected to the drain of the second MOS transistor, the source of the first MOS transistor can be connected to pin S2DLC, and the source of the second MOS transistor can be connected to pin S1BLC. The gate of the first MOS transistor can be connected to pin G2DLC, and the gate of the second MOS transistor can be connected to pin G1BLC. The drains of the first and second MOS transistors can be connected to pin DM. Furthermore, as shown in the figure, in this disclosure, two sets of pre-charge / discharge MOS transistors 330 may be provided. In the second set of pre-charge / discharge MOS transistors 330, the source of the first MOS transistor can be connected to pin S2CLC, and the source of the second MOS transistor can be connected to pin S1ALC. The gate of the first MOS transistor can be connected to pin G2CLC, and the gate of the second MOS transistor can be connected to pin G1ALC.

[0071] A thermistor 340 can also be included in the circuit for temperature detection. The two ends of the first thermistor are connected to pins NTC2P and NTC2N, respectively. The two ends of the second thermistor are connected to pins NTC1P and NTC1N, respectively.

[0072] Figure 15 It shows Figure 14The circuit structure shown is a schematic diagram of its package structure. Only the first group of MOS transistors 310 (M1, M3, M5 and M7) and the second group of MOS transistors 320 (M2, M4, M6 and M8) are shown. The pre-charge / discharge MOS transistors 330 can be placed in the four corners. Figure 15 The pins shown are Figure 14 The pins are the same. Additionally, in... Figure 15 The gates of the transistors in the first group of MOS transistors are interconnected, the sources of the transistors in the first group of MOS transistors are interconnected, the drains of the transistors in the first group of MOS transistors are interconnected, the drains of the transistors in the second group of MOS transistors are interconnected, the sources of the transistors in the second group of MOS transistors are interconnected, and the gates of the transistors in the second group of MOS transistors are interconnected.

[0073] According to a further embodiment of this disclosure, a battery management system is also provided. Figure 10 A schematic diagram of the battery management system is shown.

[0074] Figure 16 The diagram illustrates a package structure positioned on the low-voltage side (B-) of the battery and the low-voltage side (P-) of the power supply / load. The package structure may include a drive unit that receives control signals from an MCU to control the MOS transistors within the package structure, thereby controlling the current flowing between B- and P-, and thus controlling the charging and discharging current. The MCU may communicate with external devices via a communication IC. These features are described in the prior art and are not part of the invention described herein, and will not be repeated here. Figure 17 The diagram shows the case where the packaging structure is set on the high-voltage side B+ of the battery and the high-voltage side P+ of the power supply / load. The principle is the same as that of the low-voltage side setting, so it will not be described again.

[0075] In existing technologies, using power switches as charge / discharge switches requires soldering each power switch onto a printed circuit board, resulting in high cost and low reliability. In this disclosure, power MOSFETs are integrated into a single chip, significantly reducing assembly costs and time. Crucially, the design of this disclosure allows for extremely low power consumption of the integrated chip itself.

[0076] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0077] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0078] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. An integrated MOS transistor package structure, characterized in that, include: N MOS transistors, wherein each of the N MOS transistors includes a gate, a drain, and a source, where N > 1; The packaging carrier is provided with gate pins, source pins and drain pins. The gates of the N MOS transistors are connected to the gate pins by wire bonding. The sources of the N MOS transistors are connected to the source pins by wire bonding, copper strip bonding or copper sheet bonding. as well as A printed circuit board (PCB) has copper-clad areas connected to the drains of N MOS transistors. The number of copper-clad areas is one or more, and each copper-clad area is connected to the drains of the n MOS transistors, such that the drains of the n MOS transistors are connected through corresponding copper-clad areas, where 1 ≤ n ≤ N. The printed circuit board is disposed within the packaging carrier and is used to house the N MOS transistors; The n MOS transistors are connected to two or more sub-copper regions, and the two or more sub-copper regions are connected by printed wires to connect the drains of the n MOS transistors. The N MOS transistors are divided into N / 2 charging MOS transistors and N / 2 discharging MOS transistors. The drains of the N / 2 charging MOS transistors are connected to the drains of the N / 2 discharging MOS transistors and connected to the drain pins. The sources of the N / 2 charging MOS transistors are interconnected and connected to the first source pin or individually connected to the first source pin. The sources of the N / 2 discharging MOS transistors are interconnected and connected to the second source pin or individually connected to the second source pin. The gates of the N / 2 charging MOS transistors are interconnected and connected to the charging gate pin or individually connected to the charging gate pin. The gates of the N / 2 discharging MOS transistors are interconnected and connected to the discharging gate pin or individually connected to the charging gate pin.

2. The integrated MOS transistor package structure as described in claim 1, characterized in that, The copper-clad area is set to a predetermined size to facilitate heat dissipation.

3. The integrated MOS transistor package structure as described in claim 1 or 2, characterized in that, The number of copper-clad regions is one, and the drains of N MOS transistors are all connected to this one copper-clad region in order to connect the drains of N MOS transistors.

4. The integrated MOS transistor package structure as described in claim 1 or 2, characterized in that, There are two copper-clad regions. The drains of N / 2 of the N MOS transistors are connected to one copper-clad region, and the remaining N / 2 of the N MOS transistors are connected to the other copper-clad region.

5. The integrated MOS transistor package structure as described in claim 2, characterized in that, The printed circuit board is provided with a source potential region. The sources of m MOS transistors out of the N MOS transistors are connected to the first source potential region of the source potential region through wire bonding, copper strip bonding, or copper sheet bonding. The sources of Nm MOS transistors out of the N MOS transistors are connected to the second source potential region of the source potential region through wire bonding, copper strip bonding, or copper sheet bonding. The first source potential region is connected to the first source pin, and the second source potential region is connected to the second source pin, where 1≤m≤N-1.

6. The integrated MOS transistor package structure as described in claim 5, characterized in that, The number of source potential regions is two or more, and each source potential region is connected to the source of at least one MOS transistor.

7. The integrated MOS transistor package structure as described in claim 1 or 2, characterized in that, It also includes one or more thermistors, which are disposed within the package structure and connected to thermistor pins.

8. The integrated MOS transistor package structure as described in claim 1, characterized in that, It also includes a pre-charge / discharge MOS transistor, which includes a pre-charge MOS transistor and a pre-discharge MOS transistor. The drains of the pre-charge MOS transistor and the pre-discharge MOS transistor are interconnected, and the gate of the pre-charge MOS transistor is connected to the pre-charge gate pin, the source of the pre-charge MOS transistor is connected to the pre-charge source pin, the gate of the pre-discharge MOS transistor is connected to the pre-discharge gate pin, and the source of the pre-discharge MOS transistor is connected to the pre-discharge power supply pin.

9. The integrated MOS transistor package structure as described in claim 8, characterized in that, The precharged MOS transistor includes a pair of precharged MOS transistors, and the pre-discharged MOS transistor includes a pair of pre-discharged MOS transistors.

10. The integrated MOS transistor package structure as described in claim 1 or 2, characterized in that, The gate includes a control gate and a disconnect gate, and the gate pins include a control gate pin and a disconnect gate pin. The control gate is connected to the control gate pin, and the disconnect gate is connected to the disconnect gate pin.

11. A battery management system, characterized in that, include: The integrated MOS transistor package structure as described in any one of claims 1 to 10; as well as A driving unit, which is connected to the gate pin.

12. The battery management system as described in claim 11, characterized in that, The source pin of the integrated MOS transistor package structure is connected between the low-voltage side of the battery pack and the low-voltage side of the load / charger, or between the high-voltage side of the battery pack and the high-voltage side of the load / charger.

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