Display panel and display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes a substrate and a boss structure arranged on the substrate. The boss structure includes at least two stacked ohmic contact layers and at least one insulating layer, and an insulating layer is arranged between two adjacent ohmic contact layers; at least part of the semiconductor layer is located on the side wall of the boss structure, and the side wall includes a first side wall of the ohmic contact layer and a second side wall of the insulating layer arranged on the same side; the semiconductor layer includes at least one channel, and the channel is located on the second side wall. The channel length can be controlled by adjusting the length and the inclination angle of the second side wall, which not only reduces the channel length, but also realizes the superposition of multiple thin film transistors in the thickness direction of the display panel, reduces the volume of thin devices, reduces the device footprint, is conducive to improving the device integration, and is conducive to realizing IC circuit integration on the substrate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Integrating pixel drive circuits, gate drive circuits, multiplexed power circuits, source drive circuits, timing controllers and other circuits on a glass substrate (system on glass, SOG) can greatly improve the integration of display panels, reduce dependence on integrated circuit chips, and thus reduce costs. To achieve SOG, it is necessary to improve the integration, maximum operating frequency and current density of thin film transistors in existing display panels, all of which require thin film transistors to have shorter channel lengths, higher mobility and smaller volumes.

[0003] However, the architecture of the thin film transistor of the existing display panel cannot further reduce the footprint of the thin film transistor, and the device integration level needs to be improved. Summary of the invention

[0004] Embodiments of the present invention provide a display panel and a display device to solve the technical problem that the thin film transistors of the existing display panel occupy a large area.

[0005] To solve the above problems, the technical solution provided by the present invention is as follows:

[0006] The present invention provides a display panel, comprising a substrate and a boss structure arranged on the substrate, wherein the boss structure comprises at least two ohmic contact layers and at least one insulating layer stacked together, and an insulating layer is arranged between two adjacent ohmic contact layers;

[0007] The display panel also includes a semiconductor layer, at least part of which is located on the sidewalls of the boss structure, and the sidewalls include a first sidewall of the ohmic contact layer and a second sidewall of the insulating layer arranged on the same side; the semiconductor layer includes at least one channel, and the channel is located on the second sidewall.

[0008] According to the display panel provided by the present invention, the display panel further comprises a gate, the gate is located on a side of the semiconductor layer away from the boss structure, and the orthographic projection of the gate on the side wall covers the orthographic projection of the channel on the side wall.

[0009] According to the display panel provided by the present invention, the at least two ohmic contact layers include a first ohmic contact layer and a second ohmic contact layer sequentially stacked on the substrate, and the at least one insulating layer includes a first insulating layer, and the first insulating layer is located between the first ohmic contact layer and the second ohmic contact layer;

[0010] The at least one channel includes a first channel, and the first channel is located on the second sidewall of the first insulating layer.

[0011] According to the display panel provided by the present invention, the at least two ohmic contact layers further include a third ohmic contact layer disposed on the second ohmic contact layer, and the at least one insulating layer further includes a second insulating layer, and the second insulating layer is located between the second ohmic contact layer and the third ohmic contact layer;

[0012] The at least one channel further includes a second channel, and the second channel is located on the second side wall of the second insulating layer.

[0013] According to the display panel provided by the present invention, the display panel further includes:

[0014] A gate insulating layer, disposed between the gate and the semiconductor layer;

[0015] An interlayer dielectric layer, disposed on a side of the gate away from the substrate, the interlayer dielectric layer covering the gate and the gate insulating layer;

[0016] a source-drain metal layer, disposed on a side of the interlayer dielectric layer away from the substrate, the source-drain metal layer comprising a first drain, a source, and a second drain; and

[0017] A first contact hole, a second contact hole and a third contact hole penetrate the interlayer dielectric layer and the gate insulating layer;

[0018] The source electrode is connected to the second ohmic contact layer through the first contact hole, the first drain electrode is connected to the first ohmic contact layer by penetrating the second contact hole, and the second drain electrode is connected to the third ohmic contact layer through the third contact hole.

[0019] According to the display panel provided by the present invention, the first ohmic contact layer, the second ohmic contact layer and the third ohmic contact layer are in a stepped shape;

[0020] The first ohmic contact layer includes a first protrusion, and the orthographic projection of the second ohmic contact layer on the substrate does not overlap with the orthographic projection of the first protrusion on the substrate; the second ohmic contact layer includes a second protrusion, and the orthographic projection of the third ohmic contact layer on the substrate does not overlap with the orthographic projection of the second protrusion on the substrate.

[0021] According to the display panel provided by the present invention, the first drain electrode and the second drain electrode are respectively located on two opposite sides of the source electrode.

[0022] According to the display panel provided by the present invention, the orthographic projections of the first drain electrode, the second drain electrode and the source electrode on the substrate are all located on the same side of the orthographic projection of the gate electrode on the substrate.

[0023] According to the display panel provided by the present invention, the side wall, the first side wall and the second side wall are located in the same plane.

[0024] According to the display panel provided by the present invention, the semiconductor layer includes an inclined portion, a first horizontal portion and a second horizontal portion, the inclined portion is a portion of the semiconductor layer located on the side wall of the boss structure, the inclined portion is located between the first horizontal portion and the second horizontal portion, the first horizontal portion is located on one side of the substrate, and the second horizontal portion is located on a side of the boss structure away from the substrate.

[0025] According to the display panel provided by the present invention, the angle between the first horizontal portion and the inclined portion is 90° to 135°; and the thickness of each insulating layer is in the range of 0.0071 to 1 micrometer.

[0026] The present invention provides a display device, comprising the above-mentioned display panel.

[0027] The beneficial effects of the present invention are as follows: the display panel and display device provided by the present invention form a boss structure by stacking an ohmic contact layer and an insulating layer on a substrate, the boss structure includes at least two stacked ohmic contact layers and at least one insulating layer, an insulating layer is arranged between two adjacent ohmic contact layers, at least part of the semiconductor layer is located on the side wall of the boss structure, the semiconductor layer contacts the first side wall of the ohmic contact layer, and the channel of the semiconductor is located on the second side wall of the insulating layer, so that the channel length can be controlled by adjusting the length and inclination angle of the second side wall, which not only reduces the channel length, but also realizes the superposition of multiple thin film transistors in the thickness direction of the display panel, reduces the volume of thin devices, reduces the device footprint, is conducive to improving the device integration, and is conducive to realizing IC circuit integration on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A schematic diagram of a planar structure of a thin film transistor provided by an embodiment of the present invention;

[0030] Figure 2 for Figure 1Schematic diagram of the cross section along the BB direction;

[0031] Figure 3 for Figure 1 Schematic diagram of the cross section along the AA direction;

[0032] Figure 4 A schematic diagram of a planar structure of another thin film transistor provided by an embodiment of the present invention;

[0033] Figure 5 for Figure 4 Schematic diagram of the cross section along the BB direction;

[0034] Figure 6 for Figure 4 Schematic diagram of the cross section along the AA direction;

[0035] Figures 7A to 7G A structural schematic diagram of a process for preparing a display panel provided by an embodiment of the present invention.

[0036] Description of reference numerals:

[0037] 10. substrate; 11. underlayer; 12. light shielding layer; 13. buffer layer; 20. boss structure; 20a. side wall; 21. ohmic contact layer; 21a. first side wall; 211. first ohmic contact layer; 2111. first protrusion; 212. second ohmic contact layer; 2121. second protrusion; 213. third ohmic contact layer; 22. insulating layer; 22a. second side wall; 221. first insulating layer; 222. A second insulating layer; 30, a semiconductor layer; 31, a channel; 32, a first channel; 33, a second channel; 34, an inclined portion; 35, a first horizontal portion; 36, a second horizontal portion; 40, a gate insulating layer; 50, a gate; 60, an interlayer dielectric layer; 70, a source-drain metal layer; 71, a source; 72, a first drain; 73, a second drain; 701, a first contact hole; 702, a second contact hole; 703, a third contact hole. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device.

[0039] See also Figure 1 to Figure 3 , Figure 1 A schematic diagram of a planar structure of a thin film transistor provided by an embodiment of the present invention; Figure 2 for Figure 1 Schematic diagram of the cross section along the BB direction; Figure 3 for Figure 1 A cross-sectional schematic diagram along the AA direction in FIG. An embodiment of the present invention provides a display panel, the display panel comprising a substrate 10 and a thin film transistor disposed on the substrate 10. The thin film transistor can be applied to a pixel driving circuit, a gate driving circuit, a source driving circuit, a timing controller, a multiplexing circuit and many other circuits in the display panel.

[0040] The display panel includes a substrate 10 and a boss structure 20 disposed on the substrate 10. The boss structure 20 includes at least two stacked ohmic contact layers 21 and at least one insulating layer 22, with one insulating layer 22 disposed between two adjacent ohmic contact layers 21; the display panel also includes a semiconductor layer 30, at least part of which is located on a side wall 20a of the boss structure 20, and the side wall 20a includes a first side wall 21a of the ohmic contact layer 21 and a second side wall 22a of the insulating layer 22 disposed on the same side; the semiconductor layer 30 includes at least one channel 31, and the channel 31 is located on the second side wall 22a.

[0041] The active layers of thin film transistors in the prior art are prepared on the same plane, and multiple thin film transistors are laid flat, resulting in a large circuit footprint. In addition, due to the limitations of exposure and etching processes, the length of the channel 31 is generally more than 2 microns, and the transistor size cannot be further reduced. In view of this, the display panel provided by the embodiment of the present invention forms a boss structure 20 by stacking the ohmic contact layer 21 and the insulating layer 22 on the substrate 10, the boss structure 20 includes at least two stacked layers of the ohmic contact layer 21 and at least one insulating layer 22, a layer of the insulating layer 22 is arranged between two adjacent layers of the ohmic contact layer 21, at least part of the semiconductor layer 30 is located on the side wall 20a of the boss structure 20, the semiconductor layer 30 is in contact with the first side wall 21a of the ohmic contact layer 21, and the channel 31 of the semiconductor layer 30 is located on the second side wall 22a of the insulating layer 22. In this way, the channel length can be controlled by adjusting the length and inclination angle of the second side wall 22a, which not only reduces the channel length, but also realizes the superposition of multiple thin film transistors in the thickness direction of the display panel, reduces the volume of thin devices, reduces the device footprint, is conducive to improving the device integration, and is conducive to realizing IC circuit integration on the substrate 10.

[0042] In this embodiment, the substrate 10 includes a substrate 11 , a light shielding layer 12 and a buffer layer 13 . The light shielding layer 12 is disposed on the substrate 11 , and the buffer layer 13 covers the substrate 11 and the light shielding layer 12 .

[0043] The substrate 11 may be a glass substrate 11, but is not limited thereto. The substrate 11 may also be a flexible substrate 11. The light shielding layer 12 is used to shield the ambient light incident on the semiconductor layer 30. Specifically, the light shielding layer 12 is used to shield the ambient light incident on the channel 31 to prevent the external light from causing adverse effects on the device performance. Optionally, the light shielding layer 12 is made of a metal material, which includes but is not limited to at least one of molybdenum, aluminum, titanium, copper and silver; the light shielding layer 12 may also be made of a black matrix or the like. Optionally, the buffer layer 13 is made of at least one of silicon nitride or silicon oxide. The thickness of the buffer layer 13 is greater than or equal to 2500 angstroms and less than or equal to 3500 angstroms, for example, 2500 angstroms, 2800 angstroms, 3000 angstroms, 3200 angstroms or 3500 angstroms.

[0044] In this embodiment, the material of the ohmic contact layer 21 can be the same as the material of the semiconductor layer 30. The ohmic contact layer 21 is doped with ions. The ohmic contact layer 21 is all N-type heavily doped amorphous silicon material. The ohmic contact layer 21 can also be doped with impurity elements such as phosphorus or arsenic. The insulating layer 22 is used to separate two adjacent layers of the ohmic contact layer 21. Optionally, the insulating layer 22 includes at least one of an inorganic insulating layer and an organic insulating layer. The inorganic insulating layer is made of materials including but not limited to silicon oxide or silicon nitride. The organic insulating layer is made of materials including but not limited to polyimide, polyacrylate, and silicone.

[0045] The semiconductor layer 30 at least covers the first side walls 21a of the at least two layers of the ohmic contact layer 21 and the second side wall 22a of the at least one layer of the insulating layer 22. In the present embodiment, the first side wall 21a and the second side wall 22a are located on the same side of the boss structure 20, and the side wall 20a, the first side wall 21a and the second side wall 22a are located on the same plane, that is, the angles between the side wall 20a, the first side wall 21a and the second side wall 22a and the substrate 10 are equal.

[0046] Specifically, the semiconductor layer 30 includes an inclined portion 34, a first horizontal portion 35 and a second horizontal portion 36. The inclined portion 34 is a portion of the semiconductor layer 30 located on the side wall 20a of the boss structure 20. The inclined portion 34 is located between the first horizontal portion 35 and the second horizontal portion 36. The first horizontal portion 35 is located on one side of the substrate 10, and the second horizontal portion 36 is located on a side of the boss structure 20 away from the substrate 10. The side of the inclined portion 34 close to the substrate 10 is connected to the first horizontal portion 35, and the side of the inclined portion 34 away from the substrate 10 is connected to the second horizontal portion 36.

[0047] The reason for such arrangement is that, on the one hand, the material of the first horizontal portion 35 is amorphous silicon material. In the process of crystallization to form the semiconductor layer 30, the semiconductor layer 30 before crystallization is more likely to form a seed crystal at the corner between the buffer layer 13 and the side wall 20a, that is, the semiconductor layer 30 before crystallization is more likely to form a seed crystal at the corner between the first horizontal portion 35 and the inclined portion 34. When the seed crystal grows along the side wall 20a to form a single grain, the length of the channel 31 located on the side wall 20a is less than 1 micron, which provides formation conditions for the channel 31 on the side wall 20a to be composed of a single grain. In this way, there is only one grain in one channel 31, that is, the channel 31 is composed of a single grain and there is no grain boundary, thereby providing formation conditions for forming a semiconductor device including a single grain channel and having high mobility. Compared with existing thin film transistor devices with polycrystalline boundaries, while reducing the size of the device, the mobility of the device is greatly improved, which is beneficial to improving the driving capability of the device.

[0048] On the other hand, by extending the inclined portion 34 to form the first horizontal portion 35 and the second horizontal portion 36, the adhesion between the semiconductor layer 30 and the film layer can be increased, thereby improving the stability of the thin film transistor device. In addition, the preparation of the semiconductor layer 30 of a small size can be achieved with the accuracy of the existing exposure machine without changing the process.

[0049] Specifically, in this embodiment, the angle between the first horizontal portion 35 and the inclined portion 34 is 90° to 135°, and the angle θ is also the angle between the side wall 20a and the substrate 10, and is also the angle between the first side wall 21a and the second side wall 22a and the substrate 10. In this embodiment, the thickness of each insulating layer 22 is in the range of 0.0071 to 1 micron. By controlling the above angle and thickness, the length of the channel 31 can be controlled to be less than 1 micron.

[0050] The display panel further includes a gate 50, which is located on a side of the semiconductor layer 30 away from the boss structure 20, and the orthographic projection of the gate 50 on the side wall 20a covers the orthographic projection of the channel 31 on the side wall 20a, so as to facilitate the control of the formation position and length of the channel 31. Optionally, the gate 50 is made of at least one material selected from molybdenum, aluminum, titanium, copper and silver.

[0051] In one embodiment, please refer to Figure 1 to Figure 3The boss structure 20 is composed of two layers of the ohmic contact layer 21 and one layer of the insulating layer 22, that is, the device includes a thin film transistor. Specifically, the at least two layers of the ohmic contact layer 21 include a first ohmic contact layer 211 and a second ohmic contact layer 212 stacked in sequence on the substrate 10, the at least one insulating layer 22 includes a first insulating layer 221, and the first insulating layer 221 is located between the first ohmic contact layer 211 and the second ohmic contact layer 212; the at least one channel includes a first channel 32, and the first channel 32 is located on the second sidewall 22a of the first insulating layer 221.

[0052] It can be understood that, in the present embodiment, the semiconductor layer 30 is in contact with the first ohmic contact layer 211 and the second ohmic contact layer 212, and the portion of the semiconductor layer 30 located between the first ohmic contact layer 211 and the second ohmic contact layer 212 forms the first channel 32 of a thin film transistor, that is, the length of the first channel 32 can be determined by the length and inclination angle of the second side wall 22a of the first insulating layer 221 between the first ohmic contact layer 211 and the second ohmic contact layer 212. The lengths of the first channel 32 and the second channel 33 can be controlled by adjusting the length and inclination angle of the second side wall 22a of the first insulating layer 221, and the length of the first channel 32 can be easily controlled to be less than 1 micron under the existing process.

[0053] Furthermore, in other embodiments, two thin film transistors may be stacked, but the present invention is not limited thereto, and three, four or more thin film transistors may be stacked. The embodiment of the present invention is described by taking the stacking of two thin film transistors as an example.

[0054] See also Figures 4 to 6 , Figure 4 A schematic diagram of a planar structure of another thin film transistor provided by an embodiment of the present invention; Figure 5 for Figure 4 Schematic diagram of the cross section along the BB direction; Figure 6 for Figure 4 Schematic diagram of the cross section along the AA direction. Figures 4 to 6 and Figure 1 to Figure 3 The difference is that the at least two ohmic contact layers 21 also include a third ohmic contact layer 213 arranged on the second ohmic contact layer 212, and the at least one insulating layer also includes a second insulating layer 222, and the second insulating layer 222 is located between the second ohmic contact layer 212 and the third ohmic contact layer 213; the at least one channel 31 also includes a second channel 33, and the second channel 33 is located on the second side wall 22a of the second insulating layer 222.

[0055] In this embodiment, the boss structure 20 is composed of three layers of the ohmic contact layer and three layers of the insulating layer. Specifically, the boss structure 20 includes a first ohmic contact layer 211, a first insulating layer 221, a second ohmic contact layer 212, a second insulating layer 222 and a third ohmic contact layer 213 which are sequentially stacked on the substrate 10. The device in this embodiment includes two thin film transistors stacked in the thickness direction of the display panel, and each of the two thin film transistors has a channel 31.

[0056] It can be understood that, in this embodiment, the semiconductor layer 30 is in contact with the first ohmic contact layer 211, the second ohmic contact layer 212 and the third ohmic contact layer 213, the portion of the semiconductor layer 30 located between the first ohmic contact layer 211 and the second ohmic contact layer 212 forms the first channel 32 of a thin film transistor, and the portion of the semiconductor layer 30 located between the second ohmic contact layer 212 and the third ohmic contact layer 213 forms the second channel 33 of another thin film transistor, that is, the length of the first channel 32 can be determined by the length of the first ohmic contact layer 211 and the second ohmic contact layer 212. The length of the second channel 32 and the second channel 33 can be determined by the length and the tilt angle of the second side wall 22a of the first insulating layer 221 between the second ohmic contact layer 212 and the third ohmic contact layer 213. Therefore, in this embodiment, the lengths of the first channel 32 and the second channel 33 can be controlled by adjusting the lengths and the tilt angles of the second side walls 22a of the first insulating layer 221 and the second side walls 22a of the second insulating layer 222. In this way, the lengths of the first channel 32 and the second channel 33 can be easily controlled to be less than 1 micron under the existing process.

[0057] The display panel further includes a gate insulating layer 40, an interlayer dielectric layer 60, a source-drain metal layer 70, a first contact hole 701, a second contact hole 702, and a third contact hole 703. The gate insulating layer 40 is disposed between the gate 50 and the semiconductor layer 30; the interlayer dielectric layer 60 is disposed on a side of the gate insulating layer 40 away from the substrate 10, and the interlayer dielectric layer 60 covers the gate 50 and the gate insulating layer 40; the source-drain metal layer 70 is disposed on a side of the interlayer dielectric layer 60 away from the substrate 10, and the source-drain metal layer 70 includes a first drain 72, a source 71, and a second drain 73; the first contact hole 701, the second contact hole 702, and the third contact hole 703 penetrate the interlayer dielectric layer 60 and the gate insulating layer 40.

[0058] In order to realize the parallel connection of two thin film transistors, the two thin film transistors in this embodiment share one source electrode 71. Since the second ohmic contact layer 212 is located between the first ohmic contact layer 211 and the second ohmic contact layer 212, in order to facilitate wiring, in this embodiment, the source electrode 71 is in contact with the second ohmic contact layer 212, and the drain electrodes (the first drain electrode 72 and the second drain electrode 73) of the two thin film transistors are respectively in contact with the first ohmic contact layer 211 and the second ohmic contact layer 212. Specifically, the source electrode 71 is connected to the second ohmic contact layer 212 through the first contact hole 701, the first drain electrode 72 is connected to the first ohmic contact layer 211 by penetrating the second contact hole 702, and the second drain electrode 73 is connected to the third ohmic contact layer 213 through the third contact hole 703.

[0059] It can be understood that in this embodiment, by connecting two stacked thin film transistors in parallel, that is, two channels 31 (the first channel 32 and the second channel 33) are arranged in parallel, therefore, the actual width of the device in this embodiment is the sum of the width of the first channel 32 and the width of the second channel 33, so that the width of the device can be increased in a limited space, which is conducive to increasing the on-state current and improving the driving ability of the device. In addition, the two thin film transistors are superimposed in the thickness direction of the display panel, which is conducive to reducing the volume of the device and reducing the footprint of the device, thereby improving the integration of the device.

[0060] It should be noted that in order to connect the source 71, the first drain 72 and the second drain 73 to the corresponding ohmic contact layer 21 through the contact hole, the multi-layer ohmic contact layer needs to be adaptively designed. Specifically, in this embodiment, the first ohmic contact layer 211, the second ohmic contact layer 212 and the third ohmic contact layer 213 are stepped; the first ohmic contact layer 211 includes a first protrusion 2111, and the orthographic projection of the second ohmic contact layer 212 on the substrate 10 does not overlap with the orthographic projection of the first protrusion 2111 on the substrate 10; the second ohmic contact layer 212 includes a second protrusion 2121, and the orthographic projection of the third ohmic contact layer 213 on the substrate 10 does not overlap with the orthographic projection of the second protrusion 2121 on the substrate 10. In this embodiment, the first ohmic contact layer 211 is made to protrude beyond the second ohmic contact layer 212 and the third ohmic contact layer 213, so that the first drain electrode 72 can be prevented from passing through the second ohmic contact layer 212 and the third ohmic contact layer 213; and the second ohmic contact layer 212 is made to protrude beyond the third ohmic contact layer 213, so that the source electrode 71 can be prevented from passing through the third ohmic contact layer 213.

[0061] In this embodiment, the first drain electrode 72 and the second drain electrode 73 are respectively located on two opposite sides of the source electrode 71 to facilitate wiring design.

[0062] In this embodiment, the orthographic projections of the first drain 72, the second drain 73 and the source 71 on the substrate 10 are all located on the same side of the orthographic projection of the gate 50 on the substrate 10 to ensure that the position of the formed channel is located on the second side wall 22a.

[0063] It should be noted that the above embodiment is a superposition of one or two thin film transistors, and other embodiments of superposition of more thin film transistors are similar to the above embodiment, and reference may be made to the above description.

[0064] Referring to the figure, an embodiment of the present invention also provides a preparation method, comprising the following steps:

[0065] S10: providing a substrate 10.

[0066] Specifically, Fig. 7A As shown, the S10 includes the following steps: providing a substrate 11 ; forming a light shielding layer 12 on the substrate 11 ; and forming a buffer layer 13 covering the substrate 11 and the light shielding layer 12 .

[0067] S20: forming a boss structure 20 on the substrate 10, wherein the boss structure 20 comprises at least two stacked ohmic contact layers and at least one insulating layer 22, wherein one insulating layer 22 is disposed between two adjacent ohmic contact layers.

[0068] Specifically, taking two thin film transistors as an example, Figure 7B As shown, the material of the first ohmic contact layer 211, the material of the first insulating layer 221, the material of the second ohmic contact layer 212, the material of the second insulating layer 222, the material of the third ohmic contact layer 213, the material of the third insulating layer and the material of the fourth ohmic contact layer are sequentially stacked on the buffer layer 13; then etching of different depths is performed to form the first ohmic contact layer 211, the first insulating layer 221, the second ohmic contact layer 212, the second insulating layer 222 and the third ohmic contact layer 213. It should be noted that the etching process of different depths can be performed through the same grayscale mask or in multiple maskings, which is not limited here.

[0069] S30: forming a semiconductor layer 30 at least partially located on the sidewall 20a of the boss structure 20, wherein the sidewall 20a includes the first sidewall 21a of the ohmic contact layer 21 and the second sidewall 22a of the insulating layer 22 arranged on the same side.

[0070] Specifically, Figure 7CAs shown, an amorphous silicon material is deposited on the third ohmic contact layer 213, and the amorphous silicon is crystallized, and then the amorphous silicon material is etched to form the pattern of the semiconductor layer 30. The amorphous silicon material can be crystallized by an excimer laser annealing process. Since the energy of the excimer laser annealing process is limited and is completely absorbed by the amorphous silicon, when the amorphous silicon layer is crystallized, the ohmic contact layer 21 can still maintain the amorphous silicon structure. The crystallization of amorphous silicon can also be performed after the oxidation treatment, which is not limited here.

[0071] The preparation method also includes: Fig.7D As shown, S40: forming a gate insulating layer 40 covering the substrate 10 and the boss structure 20; Fig. 7E As shown, S50: forming a gate 50 on a side of the gate insulating layer 40 away from the boss structure 20; Figure 7F As shown, S60: forming an interlayer dielectric layer 60 covering the gate 50 and the gate insulating layer 40; Figure 7F As shown, S70: forming a first contact hole 701, a second contact hole 702 and a third contact hole 703 penetrating the interlayer dielectric layer 60 and the gate insulating layer 40; as shown Figure 7G As shown, S80: a source-drain metal layer 70 is formed on the side of the interlayer dielectric layer 60 away from the substrate 10, and the source-drain metal layer 70 includes a first drain 72, a source 71 and a second drain 73, the first drain 72 is connected to the first ohmic contact layer 211 by penetrating the first contact hole 701, the source 71 is connected to the second ohmic contact layer 212 through the second contact hole 702, and the second drain 73 is connected to the third ohmic contact layer 213 through the third contact hole 703.

[0072] An embodiment of the present invention further provides a display device, which includes the display panel in the above embodiment. The display device includes but is not limited to electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc.

[0073] The beneficial effects are as follows: the display panel and the display device provided by the embodiments of the present invention form a boss structure by stacking an ohmic contact layer and an insulating layer on a substrate, the boss structure includes at least two stacked ohmic contact layers and at least one insulating layer, an insulating layer is arranged between two adjacent ohmic contact layers, at least part of the semiconductor layer is located on the side wall of the boss structure, the semiconductor layer contacts the first side wall of the ohmic contact layer, and the channel of the semiconductor is located on the second side wall of the insulating layer, so that the channel length can be controlled by adjusting the length and inclination angle of the second side wall, which not only reduces the channel length, but also realizes the superposition of multiple thin film transistors in the thickness direction of the display panel, reduces the volume of thin devices, reduces the device footprint, is conducive to improving the device integration, and is conducive to realizing IC circuit integration on the substrate.

[0074] In summary, although the present invention has been disclosed as above in terms of preferred embodiments, the above preferred embodiments are not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined in the claims.

Claims

1. A display panel, characterized in that: It comprises a substrate and a boss structure arranged on the substrate, wherein the boss structure comprises at least two ohmic contact layers and at least one insulating layer stacked and arranged, and an insulating layer is arranged between two adjacent ohmic contact layers; The display panel further comprises a semiconductor layer, at least a portion of which is located on a sidewall of the boss structure, the sidewall comprising a first sidewall of the ohmic contact layer and a second sidewall of the insulating layer disposed on the same side; the semiconductor layer comprises at least one channel, and the channel is located on the second sidewall; The at least two ohmic contact layers include a first ohmic contact layer, a second ohmic contact layer, and a third ohmic contact layer stacked in sequence on the substrate, and the at least one insulating layer includes a first insulating layer and a second insulating layer, the first insulating layer is located between the first ohmic contact layer and the second ohmic contact layer, and the second insulating layer is located between the second ohmic contact layer and the third ohmic contact layer; The at least one channel includes a first channel and a second channel, the first channel is located on the second side wall of the first insulating layer, the second channel is located on the second side wall of the second insulating layer, and the first channel and the second channel are arranged in parallel.

2. The display panel according to claim 1, characterized in that: The display panel further includes a gate, which is located at a side of the semiconductor layer away from the boss structure, and an orthographic projection of the gate on the side wall covers an orthographic projection of the channel on the side wall.

3. The display panel according to claim 2, characterized in that: The display panel further includes: A gate insulating layer, disposed between the gate and the semiconductor layer; An interlayer dielectric layer, disposed on a side of the gate away from the substrate, the interlayer dielectric layer covering the gate and the gate insulating layer; a source-drain metal layer, disposed on a side of the interlayer dielectric layer away from the substrate, the source-drain metal layer comprising a first drain, a source, and a second drain; and A first contact hole, a second contact hole and a third contact hole penetrate the interlayer dielectric layer and the gate insulating layer; The source electrode is connected to the second ohmic contact layer through the first contact hole, the first drain electrode is connected to the first ohmic contact layer by penetrating the second contact hole, and the second drain electrode is connected to the third ohmic contact layer through the third contact hole.

4. The display panel according to claim 3, characterized in that: The first ohmic contact layer, the second ohmic contact layer and the third ohmic contact layer are in a stepped shape; The first ohmic contact layer includes a first protrusion, and the orthographic projection of the second ohmic contact layer on the substrate does not overlap with the orthographic projection of the first protrusion on the substrate; the second ohmic contact layer includes a second protrusion, and the orthographic projection of the third ohmic contact layer on the substrate does not overlap with the orthographic projection of the second protrusion on the substrate.

5. The display panel according to claim 4, characterized in that: The first drain electrode and the second drain electrode are respectively located at two opposite sides of the source electrode.

6. The display panel according to claim 5, characterized in that: The orthographic projections of the first drain, the second drain, and the source on the substrate are all located on the same side of the orthographic projection of the gate on the substrate.

7. The display panel according to claim 1, characterized in that: The side wall, the first side wall and the second side wall are located in the same plane.

8. The display panel according to claim 7, characterized in that: The semiconductor layer includes an inclined portion, a first horizontal portion, and a second horizontal portion. The inclined portion is the portion of the semiconductor layer located on the side wall of the boss structure, and the inclined portion is located between the first horizontal portion and the second horizontal portion. The first horizontal portion is located on one side of the substrate, and the second horizontal portion is located on a side of the boss structure away from the substrate.

9. The display panel according to claim 8, characterized in that: The angle between the first horizontal portion and the inclined portion is 90° to 135°; the thickness of each insulating layer is in the range of 0.0071 to 1 micrometer.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 9.

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