Groove type field effect transistor and manufacturing method thereof

Abstract

The invention provides a trench type field effect transistor and a manufacturing method thereof, and the trench type field effect transistor is provided with a gate trench structure and a source trench structure at one side, deviating from a substrate, of a second conductive type drift region, and the source trench structure is introduced below a source metal layer. A high electric field peak value exists at the bottoms of the gate trench structure and the source trench structure at the same time, and an avalanche breakdown current generated at the bottom of the source trench structure directly flows to the first conduction type ohmic contact region along the source trench, so that the avalanche breakdown current can be reduced without changing the channel density and the voltage endurance capability of the field effect transistor. And the current proportion of the first conduction type body region below the second conduction type source region is reduced, so that the avalanche energy of the field effect transistor is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a trench field effect transistor and a manufacturing method thereof. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is widely used in various power systems due to its advantages of fast switching speed, low power consumption, easy gate drive, low drive power, high input impedance and fast frequency response. In order to further reduce the impact of the pinch-off effect of the body region of the field effect transistor and the on-resistance, a large number of trench gate MOSFETs are used in an ultra-wide voltage application range, including but not limited to ordinary trench MOSFET, shielded gate MOSFET, super junction MOSFET and silicon carbide MOSFET.

[0003] In the related art, the avalanche withstand capability (Single Pulse Avalanche Energy, Eas) of conventional trench gate MOSFET is also greatly limited by the opening of parasitic transistors in the body region, resulting in low avalanche withstand capability, a wide damage range of the corresponding trench gate MOSFET, and a small application range.

[0004] Therefore, how to provide a trench field effect transistor with strong avalanche tolerance is a problem that needs to be solved urgently. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the present invention provides a novel trench field effect transistor to solve at least one of the above-mentioned technical problems.

[0006] In order to achieve the above-mentioned purpose and other related purposes, the technical solution provided by this application is as follows.

[0007] In a first aspect, the present application provides a trench field effect transistor, comprising:

[0008] A drain metal layer and a substrate stacked on the drain metal layer;

[0009] A second conductive type drift region is arranged on a side of the substrate away from the drain metal layer, and a source trench structure and a gate trench structure are arranged on the side of the second conductive type drift region away from the substrate;

[0010] A first conductive type body region, which is disposed on a side of the second conductive type drift region away from the substrate;

[0011] A second conductive type source region is disposed on a side of the first conductive type body region away from the second conductive type drift region;

[0012] A first conductive type ohmic contact region, which is arranged on a side of the first conductive type body region away from the second conductive type drift region;

[0013] An insulating dielectric layer, which is arranged on a side of the gate trench structure away from the second conductive type drift region, and the insulating dielectric layer covers a portion of the gate trench structure and the second conductive type source region;

[0014] a source metal layer, which is disposed on a side of the insulating dielectric layer away from the second conductive type drift region, and the source metal layer covers the insulating dielectric layer, a portion of the second conductive type source region, the first conductive type ohmic contact region and the source trench structure;

[0015] The first conductive type body region, the second conductive type source region, and the first conductive type ohmic contact region are located between the source trench structure and the gate trench structure.

[0016] In one embodiment of the present invention, a source polycrystalline electrode is disposed in the source trench structure, a gate polycrystalline electrode is disposed in the gate trench structure, and the source polycrystalline electrode and the gate polycrystalline electrode are isolated from the second conductivity type drift region by an oxide layer.

[0017] In one embodiment of the present invention, an oxide layer is disposed in the source trench structure, a gate polycrystalline electrode is disposed in the gate trench structure, and the gate polycrystalline electrode is isolated from the second conductivity type drift region by the oxide layer.

[0018] In an embodiment of the present invention, the bottom of the first conductivity type body region is higher than the bottom of the source trench structure.

[0019] In one embodiment of the present invention, one side of the second conductivity type source region is in contact with the first conductivity type ohmic contact region, and the side of the second conductivity type source region is away from the first conductivity type ohmic contact region and is isolated from the gate polycrystalline electrode by the oxide layer; the side of the first conductivity type ohmic contact region is away from the second conductivity type source region and is isolated from the source polycrystalline electrode by the oxide layer and the source metal layer.

[0020] In one embodiment of the present invention, the first conductivity type is P type, and the second conductivity type is N type; or, the first conductivity type is N type, and the second conductivity type is P type.

[0021] In a second aspect, the present application also provides a method for manufacturing a trench field effect transistor, comprising:

[0022] Providing a substrate, the substrate comprising a front side and a back side arranged opposite to each other, and generating a second conductive type drift region on the front side of the substrate;

[0023] Forming a first groove and a second groove on a side of the second conductive type drift region away from the substrate, and growing an oxide layer and a source polycrystalline electrode in the first groove to form a source trench structure, and growing the oxide layer and a gate polycrystalline electrode in the second groove to form a gate trench structure;

[0024] Perform multiple ion implantations and push junctions in the second conductive type drift region located between the source trench structure and the gate trench structure to form a first conductive type body region and a second conductive type source region;

[0025] Oxidation and passivation are performed on a side of the gate polycrystalline electrode away from the second conductive type drift region to form an insulating dielectric layer, wherein the insulating dielectric layer covers the source trench structure, the gate trench structure and the second conductive type source region;

[0026] Performing window processing on the insulating dielectric layer to form a window, wherein the window covers a portion of the second conductive type source region and the source trench structure;

[0027] Performing ion implantation and push-junction on a side of the second conductive type source region away from the gate trench structure to form the first conductive type ohmic contact region;

[0028] Depositing metal on a side of the insulating dielectric layer away from the second conductive type drift region to form a source metal layer, wherein the source metal layer covers the insulating dielectric layer, a portion of the second conductive type source region, the first conductive type ohmic contact region, and the source trench structure;

[0029] Depositing metal on the back side of the substrate to form a drain metal layer;

[0030] When a breakdown avalanche effect occurs in the field effect transistor, a path for the breakdown current to flow from the bottom of the source trench structure to the first conductive type ohmic contact region is increased.

[0031] In one embodiment of the present invention, a first groove and a second groove are formed on the side of the second conductive type drift region away from the substrate, and an oxide layer and a source polycrystalline electrode are grown in the first groove to form a source trench structure, and the oxide layer and the gate polycrystalline electrode are grown in the second groove to form a gate trench structure, including: generating a mask layer on the second conductive type drift region; exposing and developing the mask layer to determine the positions of the first groove and the second groove; etching the developed second conductive type drift region to form the first groove and the second groove; growing the oxide layer and the source polycrystalline electrode in the first groove to form the source trench structure; growing the oxide layer and the gate polycrystalline electrode in the second groove to form the gate trench structure.

[0032] In one embodiment of the present invention, multiple ion implantations and junctions are performed in the second conductive type drift region located between the source trench structure and the gate trench structure to form a first conductive type body region and a second conductive type source region, including: performing ion implantation and junctions in the second conductive type drift region located between the source trench structure and the gate trench structure to form the first conductive type body region, wherein the bottom of the first conductive type body region is higher than the bottom of the source trench structure; performing ion implantation and junctions on the side of the first conductive type body region away from the first conductive type body region to form the second conductive type source region.

[0033] In one embodiment of the present invention, the insulating dielectric layer is subjected to a window opening process to form a window opening, including: providing a mask plate, and determining a window to be etched based on the mask plate; etching the insulating dielectric layer corresponding to the window to be etched, and etching a portion of the oxide layer that wraps the source polycrystalline electrode to form the window opening.

[0034] The present application provides a trench field effect transistor and a manufacturing method thereof, wherein the trench field effect transistor is provided with a gate trench structure and a source trench structure on a side of a second conductive type drift region away from a substrate, and a source trench structure is introduced below a source metal layer, a high electric field peak will exist at the bottom of the gate trench structure and the source trench structure at the same time, and an avalanche breakdown current generated at the bottom of the source trench structure directly flows along the source trench to a first conductive type ohmic contact region, so that without changing the channel density and the withstand voltage capability of the field effect transistor, the current proportion of the first conductive type body region located under the second conductive type source region is reduced, thereby improving the avalanche energy of the field effect transistor.

[0035] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0037] Figure 1 is a cross-sectional view of a conventional trench gate field effect transistor in the prior art;

[0038] Figure 2 A schematic diagram of an ohmic injection region and a high electric field of a conventional trench gate field effect transistor in the prior art;

[0039] Figure 3 This is a schematic diagram of the current flow during avalanche breakdown of a conventional trench gate field effect transistor in the prior art:

[0040] Figure 4 A schematic cross-sectional view of a trench field effect transistor according to an exemplary embodiment of the present invention;

[0041] Figure 5 A schematic diagram of an ohmic injection region and a high electric field of a field effect transistor according to an exemplary embodiment of the present invention;

[0042] Figure 6 A schematic diagram of current flow during avalanche breakdown of a trench field effect transistor according to an exemplary embodiment of the present invention;

[0043] Figure 7 A schematic cross-sectional view of a trench field effect transistor according to another exemplary embodiment of the present invention;

[0044] Figure 8 A schematic diagram of an ohmic injection region and a high electric field of a trench field effect transistor according to another exemplary embodiment of the present invention;

[0045] Fig. 9 A flow chart of a method for manufacturing a trench field effect transistor according to an exemplary embodiment of the present invention;

[0046] Figures 10 to 13 A schematic cross-sectional view of a method for manufacturing a trench field effect transistor according to an exemplary embodiment of the present invention;

[0047] Explanation of the figure numbers: 1-drain metal layer; 2-substrate; 3-second conductivity type drift region; 4-oxide layer; 51-gate polycrystalline electrode; 52-source polycrystalline electrode; 6-first conductivity type body region; 7-second conductivity type source region; 8-first conductivity type ohmic contact region; 9-insulating dielectric layer; 10-source metal layer. DETAILED DESCRIPTION

[0048] The following will describe the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, not for limiting the scope of protection of the present invention.

[0049] It should be noted that the illustrations provided in the following embodiments are only used to illustrate the basic concept of the present invention in a schematic manner, and thus the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0050] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0051] As described in the background art, Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is widely used in various power systems due to its advantages of fast switching speed, low power consumption, easy gate drive, low drive power, high input impedance and fast frequency response. In order to further reduce the impact of the pinch-off effect of the body region of the field effect transistor and the on-resistance, a large number of trench gate MOSFETs are used in an ultra-wide voltage application range, including but not limited to ordinary trench MOSFET, shielded gate MOSFET, super junction MOSFET and silicon carbide MOSFET.

[0052] In the related art, conventional trench gate field effect transistors such as Figure 1 As shown, the ohmic injection region and high electric field position of a conventional trench gate field effect transistor are as follows Figure 2 As shown in FIG. 1 , the bottom of the gate trench structure is a high electric field position; when a conventional trench field effect transistor undergoes avalanche breakdown, as shown in FIG. Figure 3 As shown, the path of avalanche current is: Therefore, the avalanche withstand capability (Single Pulse Avalanche Energy, Eas) of conventional trench gate field effect transistors is easily limited by the turn-on limit of the parasitic transistor in the body region.

[0053] First, as Figure 4 As shown, the present application provides a trench field effect transistor, comprising:

[0054] A drain metal layer 1 and a substrate 2 stacked on the drain metal layer 1;

[0055] A second conductive type drift region 3 is arranged on a side of the substrate 2 away from the drain metal layer 1, and a source trench structure and a gate trench structure are arranged on the side of the second conductive type drift region 3 away from the substrate;

[0056] A first conductive type body region 6, which is arranged on a side of the second conductive type drift region 3 facing away from the substrate 2;

[0057] A second conductive type source region 7, which is arranged on a side of the first conductive type body region 6 away from the second conductive type drift region 3;

[0058] A first conductive type ohmic contact region 8, which is arranged on a side of the first conductive type body region 6 away from the second conductive type drift region 3;

[0059] An insulating dielectric layer 9, which is disposed on a side of the gate trench structure away from the second conductive type drift region 3, and the insulating dielectric layer 9 covers the gate trench structure and a portion of the second conductive type source region 7;

[0060] A source metal layer 10, which is disposed on a side of the insulating dielectric layer 9 away from the second conductive type drift region 3, and the source metal layer 10 covers the insulating dielectric layer 9, a portion of the second conductive type source region 7, the first conductive type ohmic contact region 8 and the source trench structure;

[0061] The first conductive type body region 6 , the second conductive type source region 7 , and the first conductive type ohmic contact region 8 are provided with a source trench structure and a gate trench structure on the side facing away from the substrate.

[0062] It should be noted that the substrate can be a heavily doped second conductivity type drain region, the second conductivity type drift region 3 is lightly doped, the first conductivity type body region 6 is medium doped, the second conductivity type source region 7 is heavily doped, and the first conductivity type ohmic contact region is heavily doped; in the field effect transistor provided in the present application, the lightly doped impurity concentration magnitude is: ≤1e16cm-3, the medium doped impurity concentration magnitude is: (1e16cm-3,1e18cm-3], and the heavily doped impurity concentration magnitude is: >1e18cm-3.

[0063] Specifically, a source polycrystalline electrode 52 is disposed in the source trench structure, a gate polycrystalline electrode 51 is disposed in the gate trench structure, and the source polycrystalline electrode 52 and the gate polycrystalline electrode 51 are isolated from the second conductive type drift region 3 by the oxide layer 4. Specifically, as Figure 4 As shown, the source groove structure is a U-shaped first groove, the bottom and side walls of the first groove are provided with an oxide layer 4, and a source polycrystalline electrode 52 is provided on the oxide layer 4 in the first groove; the gate groove structure is a U-shaped second groove, the bottom and side walls of the second groove are provided with an oxide layer 4, and a gate polycrystalline electrode 51 is provided on the oxide layer 4 in the second groove.

[0064] In some usage scenarios, a smaller cell size structure is required. Therefore, when a source trench structure is introduced, the size of the source trench structure can be reduced to provide a field effect transistor with a smaller cell size.

[0065] Specifically, an oxide layer 4 is disposed in the source trench structure, a gate polycrystalline electrode 51 is disposed in the gate trench structure, and the gate polycrystalline electrode 51 is isolated from the second conductive type drift region 3 by the oxide layer 4. Specifically, as Figure 7 As shown, only an oxide layer 4 is arranged in the first groove, an oxide layer 4 is arranged on the bottom and sidewall of the second groove, and a gate polycrystalline electrode 51 is arranged on the oxide layer 4 in the second groove.

[0066] In detail, Figure 4 As shown, the bottom of the first conductivity type body region 6 is higher than the bottom of the source trench structure. That is, the bottom of the first conductivity type body region 6 is higher than the bottom of the oxide layer 4 in the source trench structure.

[0067] In more detail, one side of the second conductive type source region 7 is in contact with the first conductive type ohmic contact region 8, and the side of the second conductive type source region 7 facing away from the first conductive type ohmic contact region 8 is isolated from the gate polycrystalline electrode 51 by the oxide layer 4; the side of the first conductive type ohmic contact region 8 facing away from the second conductive type source region 7 is isolated from the source polycrystalline electrode 52 by the oxide layer 4 and the source metal layer 10. Specifically, as Figure 4 or Figure 7 As shown, in the horizontal direction parallel to the substrate 2, the second conductive type source region 7 and the first conductive type ohmic contact region 8 are located between the source trench structure and the gate trench structure, and one side wall of the second conductive type source region 7 is in contact with the first conductive type ohmic contact region 8 in the horizontal direction, the second conductive type source region 7 is close to the gate polycrystalline electrode 51 and is isolated by the oxide layer 4, and the first conductive type ohmic contact region 8 is close to the source polycrystalline electrode and is isolated from the source polycrystalline electrode 52 by the source metal layer 10 and the oxide layer 4.

[0068] In detail, the substrate 2 is one of silicon, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, gallium oxide and silicon germanium.

[0069] In detail, the first conductivity type is P type, and the second conductivity type is N type; or, the first conductivity type is N type, and the second conductivity type is P type. That is, the first conductivity type body region 6 and the first conductivity type ohmic contact region 8 are N type semiconductors, and the second conductivity type drift region 3 and the second conductivity type source region 7 are P type semiconductors; or, the first conductivity type body region 6 and the first conductivity type ohmic contact region 8 are P type semiconductors, and the second conductivity type drift region 3 and the second conductivity type source region 7 are N type semiconductors.

[0070] It should be noted that if Figure 4 As shown, in the trench field effect transistor, the width of the gate trench structure is W1, the window width of the source contact area under the source metal layer is W2, and the distance between the window boundary of the source contact area and the gate trench structure is W3; the width of the source trench structure is W4, and the cell size of the trench field effect transistor is determined according to the above multiple widths to be (W1+W2+2*W3).

[0071] Among them, Figure 4 As shown, the window width W2 of the source contact area needs to be larger than the width W4 of the source trench structure, so that the source contact area and the first conductive type ohmic contact area 8 completely cover the source trench structure, and in the horizontal direction, the first conductive type ohmic contact area 8 and the source polycrystalline electrode 52 are connected to the source metal layer 10.

[0072] The trench field effect transistor provided in the present application will not increase the width W1 of the gate trench structure, the window width W2 of the source contact region, the spacing W3 between the window boundary of the source contact region and the gate trench structure, and the width of the cell size, and therefore will not reduce the channel density of the device; Figure 5 As shown, a source trench structure is introduced below the source metal layer 10, and a high electric field peak will exist at the bottom of the source trench structure and the gate trench structure at the same time, such as Figure 6 As shown, the avalanche breakdown current generated at the bottom of the source trench of the field effect transistor flows directly along the source trench to the first conductive type ohmic contact region 8, reducing the current proportion of the first conductive type body region 6 located under the second conductive type source region 7, thereby enhancing the avalanche withstand capability of the field effect transistor.

[0073] It should be emphasized that the direction of the avalanche breakdown current of the field effect transistor provided by the structure in which only the oxide layer 4 is provided in the source trench structure is the same as that provided by the source polycrystalline electrode 52 in the source trench structure. Figure 8 As shown, in the trench field effect transistor in which the source trench structure is only provided with the oxide layer 4, the bottom of the source trench structure and the bottom of the gate trench structure are high electric field positions.

[0074] Second, as Fig. 9 As shown, the present application also provides a method for manufacturing a trench field effect transistor, comprising:

[0075] S910, providing a substrate 2, the substrate 2 including a front side and a back side arranged opposite to each other, and generating a second conductivity type drift region 3 on the front side of the substrate 2. Specifically, providing a heavily doped single crystal material substrate 2 having a second conductivity type, growing a single crystal material epitaxial layer on the front side of the substrate 2, and generating a second conductivity type drift region 3.

[0076] S920, forming a first groove and a second groove in the second conductive type drift region 3, and growing an oxide layer 4 and a source polycrystalline electrode 52 in the first groove to form a source trench structure, and growing an oxide layer 4 and a gate polycrystalline electrode 51 in the second groove to form a gate trench structure.

[0077] In detail, a first groove and a second groove are formed on the side of the second conductive type drift region 3 facing away from the substrate 2, and an oxide layer 4 and a source polycrystalline electrode 52 are grown in the first groove to form a source groove structure, and an oxide layer 4 and a gate polycrystalline electrode 51 are grown in the second groove to form a gate groove structure, including: generating a mask layer on the second conductive type drift region 3; exposing and developing the mask layer to determine the positions of the first groove and the second groove; etching the developed second conductive type drift region 3 to form the first groove and the second groove; growing an oxide layer 4 and a source polycrystalline electrode 52 in the first groove to form a source groove structure; growing an oxide layer 4 and a gate polycrystalline electrode 51 in the second groove to form a gate groove structure. Specifically, as Fig.10 As shown, a mask layer is grown on the second conductive type drift region 3, and the position of the first groove and the position of the second groove are determined through exposure and development processing, and then the developed second conductive type drift region 3 is etched to form a first groove and two second grooves in the second conductive type drift region 3, and an oxide layer 4 is grown at the bottom and side walls of the first groove, and a source polycrystalline electrode 52 is deposited on the oxide layer 4, and an oxide layer 4 is generated at the bottom and side walls of the second groove, and a gate polycrystalline electrode 51 is deposited on the oxide layer 4, and excess polycrystalline material is etched so that the top height of the gate polycrystalline electrode 51 and the top height of the source polycrystalline electrode are lower than the side wall height of the first groove, and then the excess oxide layer 4 is etched to form a source trench structure and a gate trench structure.

[0078] It should be emphasized that the positions of the first groove and the second groove can be determined by using a single mask, or by using two masks for independent exposure to determine the positions of the first groove and the second groove.

[0079] S930 , perform multiple ion implantations and push junctions in the second conductivity type drift region 3 between the source trench structure and the gate trench structure to form a first conductivity type body region 6 and a second conductivity type source region 7 .

[0080] In more detail, multiple ion implantation and push-junction are performed in the second conductive type drift region 3 between the source trench structure and the gate trench structure to form the first conductive type body region 6 and the second conductive type source region 7, including: ion implantation and push-junction are performed in the second conductive type drift region 3 between the source trench structure and the gate trench structure to form the first conductive type body region 6, wherein the bottom of the first conductive type body region 6 is higher than the bottom of the source trench structure; ion implantation and push-junction are performed in the first conductive type body region 6 to form the second conductive type source region 7. Specifically, ion implantation is performed between the second conductive type drift region 3 between the first groove and the second groove to form the first conductive type body region 6 in the horizontal direction between the first groove and the second groove, and ion implantation and push-junction are performed in the region of the first conductive type body region 6 to form the second conductive type source region 7 in the horizontal direction between the first groove and the second groove. Wherein, when performing ion implantation of the second conductive type source region 7, ions may be implanted only in the region where the second conductive type source region 7 is set, or ion implantation may be performed in both the region where the second conductive type source region 7 and the first conductive type ohmic contact region 8 are set.

[0081] S940 , oxidizing and passivating the side of the gate polycrystalline electrode 51 away from the second conductivity type drift region 3 to form an insulating dielectric layer 9 , wherein the insulating dielectric layer 9 covers the source trench structure, the gate trench structure and the second conductivity type source region 7 .

[0082] S950, performing window processing on the insulating dielectric layer 9 to form a window, and the window covers a portion of the second conductive type source region 7 and the source trench structure.

[0083] Specifically, the insulating dielectric layer 9 is opened to form an opening window, including: providing a mask, determining a window to be etched based on the mask; etching the insulating dielectric layer 9 corresponding to the window to be etched, and etching a portion of the oxide layer 4 wrapping the source polycrystalline electrode 52 to form an opening window. Specifically, Fig.11 As shown, a mask is set on the insulating dielectric layer, and the position and size of the window to be etched at the source contact are determined according to the mask, such as Fig.12 As shown, the insulating dielectric layer 7 under the mask is etched, and the oxide layer 4 wrapping the source polycrystalline electrode 52 is partially etched, so as to form an opening window of the source contact.

[0084] S960, ion implantation and junction pushing are performed on the side of the second conductive type source region 7 away from the gate trench structure to form a first conductive type ohmic contact region 8. Specifically, Fig.12As shown, ion implantation and push-junction are performed on the second conductivity type source region 7 or the first conductivity type body region 6 at both ends of the source trench structure to form a first conductivity type ohmic contact region 8 .

[0085] S970, such as Fig.13 As shown, metal is deposited on one side of the second conductivity type drift region 3 of the insulating dielectric layer to form a source metal layer 10, which covers the insulating dielectric layer 9, part of the second conductivity type source region 7, the first conductivity type ohmic contact region 8 and the source trench structure.

[0086] S980, depositing metal on the back side of the substrate 2 to form a drain metal layer 1. Specifically, metal is deposited on the back side of the substrate 2 to form a drain metal 1, thereby obtaining a trench field effect transistor.

[0087] It should be noted that when a breakdown avalanche effect occurs in the field effect transistor, the breakdown current at the bottom of the source trench structure flows from the first conductivity type body region 6 to the first conductivity type ohmic contact region 8, increasing the current flow path and reducing the current flowing through the first conductivity type body region 6.

[0088] The present application provides a trench field effect transistor and a manufacturing method thereof, wherein a gate trench structure and a source trench structure are arranged on a side of a second conductive type drift region away from a substrate, a gate polycrystalline electrode and an oxide layer or only an oxide layer are arranged in the gate trench structure, and a source polycrystalline electrode and an oxide layer are arranged in the source trench structure; a source trench structure is introduced below a source metal layer, a high electric field peak will exist at the bottom of the source trench structure and the gate trench structure at the same time, and an avalanche breakdown current generated by the source trench structure will flow directly along the source trench to the first conductive type ohmic contact region. The groove structure provided in the present application is directly set within the lithography range of the source contact area. There is no need to consider the process spacing between the source contact area and the gate groove, and the cell size and process difficulty of the device will not increase; the spacing of the gate grooves still maintains the conventional cell size, so the introduction of the source groove structure will not reduce the channel density and will not increase the conduction loss; in the trench-type cell structure, the high electric field and the breakdown position are usually located at the bottom of the groove. After the introduction of the additional source trench structure, the breakdown current path can be adjusted so that most of the breakdown current flows directly out of the source along the side of the additional source trench structure, thereby optimizing the avalanche tolerance of the device.

[0089] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A trench field effect transistor, characterized in that: include: A drain metal layer and a substrate stacked on the drain metal layer; A second conductive type drift region is arranged on a side of the substrate away from the drain metal layer, and a source trench structure and a gate trench structure are arranged on the side of the second conductive type drift region away from the substrate; A first conductive type body region, which is arranged on a side of the second conductive type drift region away from the substrate; A second conductive type source region is disposed on a side of the first conductive type body region away from the second conductive type drift region; A first conductive type ohmic contact region, which is arranged on a side of the first conductive type body region away from the second conductive type drift region; An insulating dielectric layer, which is arranged on a side of the gate trench structure away from the second conductive type drift region, and the insulating dielectric layer covers the gate trench structure and a portion of the second conductive type source region; a source metal layer, which is disposed on a side of the insulating dielectric layer away from the second conductive type drift region, and the source metal layer covers the insulating dielectric layer, a portion of the second conductive type source region, the first conductive type ohmic contact region, and the source trench structure; The first conductive type body region, the second conductive type source region, and the first conductive type ohmic contact region are located between the source trench structure and the gate trench structure.

2. The trench field effect transistor according to claim 1, characterized in that: A source polycrystalline electrode is disposed in the source trench structure, a gate polycrystalline electrode is disposed in the gate trench structure, and the source polycrystalline electrode and the gate polycrystalline electrode are isolated from the second conductive type drift region by an oxide layer.

3. The trench field effect transistor according to claim 1, characterized in that: An oxide layer is disposed in the source trench structure, a gate polycrystalline electrode is disposed in the gate trench structure, and the gate polycrystalline electrode is isolated from the second conductive type drift region by the oxide layer.

4. The trench field effect transistor according to claim 2 or 3, characterized in that: The bottom of the first conductive type body region is higher than the bottom of the source trench structure.

5. The trench field effect transistor according to claim 4, characterized in that: One side of the second conductive type source region is in contact with the first conductive type ohmic contact region, and the second conductive type source region is away from the first conductive type ohmic contact region and is isolated from the gate polycrystalline electrode by the oxide layer; The first conductive type ohmic contact region is located away from a side of the second conductive type source region and is isolated from the source polycrystalline electrode by the oxide layer and the source metal layer.

6. The trench field effect transistor according to any one of claims 1 to 5, characterized in that: The first conductivity type is P type, and the second conductivity type is N type; or, the first conductivity type is N type, and the second conductivity type is P type.

7. A method for manufacturing a trench field effect transistor, characterized in that: include: Providing a substrate, the substrate comprising a front side and a back side arranged opposite to each other, and generating a second conductive type drift region on the front side of the substrate; Forming a first groove and a second groove on a side of the second conductive type drift region away from the substrate, and growing an oxide layer and a source polycrystalline electrode in the first groove to form a source trench structure, and growing the oxide layer and a gate polycrystalline electrode in the second groove to form a gate trench structure; Perform multiple ion implantations and push junctions in the second conductive type drift region located between the source trench structure and the gate trench structure to form a first conductive type body region and a second conductive type source region; Oxidation and passivation are performed on a side of the gate polycrystalline electrode away from the second conductive type drift region to form an insulating dielectric layer, wherein the insulating dielectric layer covers the source trench structure, the gate trench structure and the second conductive type source region; Performing window processing on the insulating dielectric layer to form a window, wherein the window covers a portion of the second conductive type source region and the source trench structure; Performing ion implantation and push-junction on a side of the second conductive type source region away from the gate trench structure to form the first conductive type ohmic contact region; Depositing metal on a side of the insulating dielectric layer away from the second conductive type drift region to form a source metal layer, wherein the source metal layer covers the insulating dielectric layer, a portion of the second conductive type source region, the first conductive type ohmic contact region, and the source trench structure; Depositing metal on the back side of the substrate to form a drain metal layer; When a breakdown avalanche effect occurs in the field effect transistor, a path for the breakdown current to flow from the bottom of the source trench structure to the first conductive type ohmic contact region is increased.

8. The method for manufacturing a trench field effect transistor according to claim 7, characterized in that: A first groove and a second groove are formed on a side of the second conductive type drift region away from the substrate, and an oxide layer and a source polycrystalline electrode are grown in the first groove to form a source trench structure, and the oxide layer and a gate polycrystalline electrode are grown in the second groove to form a gate trench structure, including: generating a mask layer on the second conductive type drift region; Exposing and developing the mask layer to determine the positions of the first groove and the second groove; Etching the developed second conductive type drift region to form the first groove and the second groove; The oxide layer and the source polycrystalline electrode are grown in the first groove to form the source trench structure; the oxide layer and the gate polycrystalline electrode are grown in the second groove to form the gate trench structure.

9. The method for manufacturing a trench field effect transistor according to claim 8, characterized in that: Performing multiple ion implantations and pushing junctions in the second conductive type drift region between the source trench structure and the gate trench structure to form a first conductive type body region and a second conductive type source region, including: Performing ion implantation and junction pushing in the second conductive type drift region between the source trench structure and the gate trench structure to form the first conductive type body region, wherein the bottom of the first conductive type body region is higher than the bottom of the source trench structure; Ion implantation and junction extension are performed on a side of the first conductive type body region away from the first conductive type body region to form a second conductive type source region.

10. The method for manufacturing a trench field effect transistor according to claim 7, wherein: Performing window processing on the insulating dielectric layer to form a window, including: Providing a mask, and determining a window to be etched based on the mask; The insulating dielectric layer corresponding to the window to be etched is etched, and the oxide layer wrapping the source polycrystalline electrode is partially etched to form the window.

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