Patterned substrate extended wavelength InGaAs focal plane detector and preparation method thereof

Abstract

The present invention discloses a patterned substrate extended wavelength InGaAs focal plane detector and its preparation method. The period of the patterned substrate is the same as the center distance of the focal plane detector pixels, and the size of the patterned substrate grooves and ridges is the same as the pixel-to-pixel spacing or the pixel spacing and pixel size. The extended wavelength InGaAs detector material structure on the patterned substrate is only available in the absence of SiN. x A semiconductor single crystal material is epitaxially formed on the dielectric layer, corresponding to the focal plane detector chip pixel region. Subsequently, an InGaAs focal plane detector is fabricated through processes such as passivation, metal deposition, and flip-flop soldering. This method allows dislocations in lattice-mismatched materials to terminate at the pattern edge rather than extending upward, reducing the dislocation density of the absorber layer material. The period and size of the patterned substrate align with the focal plane chip pixel region, reducing process complexity and making it suitable for large-scale deployment. This method can also be extended to the fabrication of focal plane detectors using other lattice-mismatched material systems, demonstrating its high versatility.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor optoelectronic devices, and in particular relates to a patterned substrate extended wavelength InGaAs focal plane detector and a preparation method thereof. Background Art

[0002] InGaAs semiconductor materials possess a direct bandgap, high electron mobility, high absorption coefficient, and excellent radiation resistance. Element and focal plane array detectors using InGaAs as the absorption layer have broad applications in a wide range of fields, including optical communications, imaging surveillance, and spectral analysis. When the In component of the InGaAs layer is 0.53, lattice-matched to the InP substrate, the room-temperature bandgap is approximately 0.74 eV, corresponding to a detector cutoff wavelength of approximately 1.7 microns, which precisely covers the wavelength band required for optical communications. Consequently, driven by optical communications applications, this material has experienced rapid growth. Furthermore, detectors with cutoff wavelengths greater than 1.7 microns are also required in many fields, including remote sensing, sensing, and spectral analysis. Because many ground objects exhibit spectral characteristics near the 2-micron wavelength band, and because characteristic absorption peaks of many gases also occur in this band, spectral analysis and remote sensing in this band have a wider range of applications, with important applications in mineral resources, meteorology, the environment, and resources.

[0003] By increasing the In element content in the InGaAs absorption layer material, the band gap of the InGaAs material can be reduced, thereby extending the cutoff wavelength of the InGaAs detector to a longer wavelength. For example, when x = 0.7, the cutoff wavelength of the InGaAs detector can reach about 2.1 microns; when x = 0.8, the cutoff wavelength of the InGaAs detector can reach about 2.4 microns. However, the increase in the In component in the InGaAs absorption layer will cause the InGaAs material and the InP substrate to no longer be lattice matched, thereby generating dislocation defects in the material and causing a significant deterioration in the material quality. These dislocation defects form dark current channels in the detector, greatly degrading the device performance. By inserting an InAlAs or InAsP buffer layer between the InP substrate and the InGaAs absorption layer, the dislocations can be mainly confined to the buffer layer, greatly reducing the dislocations in the InGaAs absorption layer, thereby reducing the performance degradation of the extended wavelength InGaAs detector to a certain extent. Currently, through the optimization of the buffer layer structure and material growth process, the threading dislocation density in the InGaAs absorption layer can be reduced to a minimum of about 10 5 -10 6 / cm 2 , which is still several orders of magnitude higher than that of lattice-matched material systems.

[0004] Patterned substrates are a major method for heterogeneous material growth in the semiconductor materials field, particularly in heteroepitaxial growth of III-V materials on silicon. Using patterned Si(001) substrates can overcome the polarity mismatch in epitaxial growth of III-V materials on Si(001) substrates, preventing the generation of antiphase domain defects. Studies have also reported reducing dislocation density in epitaxial materials through epitaxy on patterned substrates, as dislocations that reach the side of the material during extension will no longer extend upward. However, forming smooth thin films on patterned substrates generally requires a pattern period of no more than a few hundred nanometers, and the fabrication of patterns with such periodicity requires high process requirements.

[0005] For extended-wavelength InGaAs focal plane detectors (FPAs) based on lattice-mismatched materials, material quality degradation caused by material mismatch and device process peculiarities are bottlenecks limiting device performance. There is an urgent need to design innovative structures and process methods to specifically improve extended-wavelength InGaAs FPAs. This patent describes an innovative structure and fabrication process for an extended-wavelength InGaAs FPA combined with a patterned substrate. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a high-quality extended-wavelength InGaAs focal plane detector.

[0007] In order to solve the above problems, the present invention discloses a patterned substrate extended wavelength InGaAs focal plane detector, which comprises a patterned substrate 1, a SiN x Dielectric layer 1 2. Semiconductor single crystal material 3. Semiconductor polycrystalline or amorphous material 4. SiN x Dielectric layer 2 5, contact electrode 1 6, contact electrode 2 7, interconnect metal 8, Si readout circuit 9, see attached Figure 1 and attached Figure 2 .

[0008] The period of the patterned substrate is the same as the center distance of the focal plane detector pixels. The patterned substrate contains two structures. One is that the groove size is the same as the pixel size, and the corresponding ridge size is the same as the pixel spacing size. See the attached Figure 1 The other is that the groove size is the same as the pixel spacing size, and the corresponding ridge size is the same as the pixel size, see the attached Figure 2 .

[0009] The material of the patterned substrate is InP, and the doping type is N-type or P-type doping. The period of the patterned substrate is the same as the center distance of the focal plane detector pixel, which is 5-33μm; the focal plane detector pixel size is 4-30μm, and the pixel spacing size is 1-3μm. For the case where the groove position of the patterned substrate corresponds to the detector pixel, the groove and ridge sizes of the patterned substrate are 4-30μm and 1-3μm respectively; for the case where the ridge position of the patterned substrate corresponds to the detector pixel, the groove and ridge sizes of the patterned substrate are 1-3μm and 4-30μm respectively. The groove depth of the patterned substrate is 2-4μm. The SiN x Dielectric layer 1 and the SiN x The thickness of the second dielectric layer is 0.1-0.3 μm.

[0010] The semiconductor single crystal material and the semiconductor polycrystalline or amorphous material include an N-type or P-type heavily doped InAlAs or InAsP buffer layer with the same doping type as the patterned substrate and a thickness of 1-3 μm, an N-type lightly doped InGaAs absorption layer with a thickness of 1-3 μm, and a P-type or N-type heavily doped InAlAs or InAsP contact layer with a thickness of 0.4-1 μm. The thickness of the semiconductor single crystal material is equal to that of the semiconductor polycrystalline or amorphous material, which is 2.4-7 μm.

[0011] The present invention also discloses a method for preparing an extended wavelength InGaAs focal plane detector based on a patterned substrate, comprising the following steps:

[0012] (1) Preparing a patterned substrate on an InP substrate through photolithography, etching and other process steps;

[0013] (2) Retain or grow SiN in the pixel spacing area x The dielectric layer 1 serves as an epitaxial growth mask;

[0014] (3) Epitaxial growth of extended wavelength InGaAs detector material structure, including InAlAs or InAsP buffer layer, InGaAs absorption layer, InAlAs or InAsP cap layer. x The semiconductor single crystal material is formed on the dielectric layer, and on the SiN x The dielectric layer 1 is formed with semiconductor polycrystalline or amorphous material;

[0015] (4) Deposition of SiN x The second dielectric layer is used to passivate and protect the exposed area on the surface of the semiconductor single crystal material;

[0016] (5) combining etching, photolithography, development, stripping and other processes, using sputtering or evaporation process to prepare contact electrode 1 and contact electrode 2 on the semiconductor single crystal material and the patterned substrate respectively;

[0017] (6) preparing interconnecting metals such as indium or copper on the first contact electrode and the second contact electrode;

[0018] (7) The prepared extended wavelength InGaAs detector chip is soldered to the Si readout circuit to complete the preparation of the extended wavelength InGaAs focal plane detector.

[0019] Beneficial effects

[0020] The present invention provides an extended wavelength InGaAs focal plane detector based on a patterned substrate and a method for preparing the same. The patterned substrate period of InP is consistent with the pixel period of the focal plane chip, and the groove or ridge size of the patterned substrate is consistent with the pixel size. The patterned substrate can be used to allow the dislocation of the lattice mismatch material to terminate at the edge of the pattern instead of extending upward, thereby reducing the dislocation density in the absorption layer material. The present invention also greatly reduces the difficulty of preparing the patterned substrate and the complexity of the process, making it suitable for large-scale promotion. The semiconductor single crystal material in the pixel area of ​​the detector chip can also be SiN x The semiconductor polycrystalline or amorphous material formed on the dielectric layer forms a natural passivation effect, which is conducive to obtaining better device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of the structure of the extended wavelength InGaAs focal plane detector with a patterned substrate according to the present invention, with the groove positions corresponding to the detector pixels.

[0022] 1—Graphical substrate

[0023] 2—SiN x Dielectric layer 1

[0024] 3—Semiconductor single crystal materials

[0025] 4—Semiconductor polycrystalline or amorphous materials

[0026] 5—SiN x Dielectric layer 2

[0027] 6—Contact electrode 1

[0028] 7—Contact electrode 2

[0029] 8—Interconnected Metal

[0030] 9—Si readout circuit

[0031] Figure 2 This is a schematic diagram of the structure of the patterned substrate extended wavelength InGaAs focal plane detector of the present invention, with the ridge positions corresponding to the detector pixels.

[0032] 1—Graphical substrate

[0033] 2—SiN x Dielectric layer 1

[0034] 3—Semiconductor single crystal materials

[0035] 4—Semiconductor polycrystalline or amorphous materials

[0036] 5—SiN x Dielectric layer 2

[0037] 6—Contact electrode 1

[0038] 7—Contact electrode 2

[0039] 8—Interconnected Metal

[0040] 9—Si readout circuit

[0041] Figure 3 This is a schematic diagram of the preparation process of the patterned substrate extended wavelength InGaAs focal plane detector of the present invention, where the groove positions correspond to the detector pixels;

[0042] S11—Take a clean InP substrate with single-side polishing

[0043] S12—Growing SiN x Dielectric layer 1

[0044] S13—Prepare a patterned substrate through photolithography, etching and other process steps, and retain SiN in the pixel spacing area. x Dielectric layer 1 as epitaxial growth mask

[0045] S14—Epitaxial growth of extended wavelength InGaAs detector material structure, including InAlAs or InAsP buffer layer, InGaAs absorption layer, InAlAs or InAsP cap layer. x The semiconductor single crystal material is formed on the dielectric layer, and on the SiN x The dielectric layer is formed on the semiconductor polycrystalline or amorphous material

[0046] S15—Deposition of SiN x The dielectric layer 2 is used to passivate and protect the exposed area on the surface of the semiconductor single crystal material. In combination with etching, photolithography, development, stripping and other processes, sputtering or evaporation processes are used to prepare contact electrode 1 and contact electrode 2 on the semiconductor single crystal material and the patterned substrate respectively, and interconnect metals such as indium or copper are prepared on the contact electrode 1 and contact electrode 2.

[0047] S16—The prepared extended wavelength InGaAs detector chip is soldered to the Si readout circuit to complete the preparation of the extended wavelength InGaAs focal plane detector.

[0048] Figure 4 This is a schematic diagram of the preparation process of the patterned substrate extended wavelength InGaAs focal plane detector of the present invention, where the ridge positions correspond to the detector pixels;

[0049] S11—Take a clean InP substrate with single-side polishing

[0050] S22—Prepare patterned substrate through photolithography, etching and other process steps

[0051] S23—Growing SiN in the groove x Dielectric layer 1

[0052] S14—Epitaxial growth of extended wavelength InGaAs detector material structure, including InAlAs or InAsP buffer layer, InGaAs absorption layer, InAlAs or InAsP cap layer. x The semiconductor single crystal material is formed on the dielectric layer, and on the SiN x The dielectric layer is formed on the semiconductor polycrystalline or amorphous material

[0053] S15—Deposition of SiN x The dielectric layer 2 is used to passivate and protect the exposed area on the surface of the semiconductor single crystal material. In combination with etching, photolithography, development, stripping and other processes, sputtering or evaporation processes are used to prepare contact electrode 1 and contact electrode 2 on the semiconductor single crystal material and the patterned substrate respectively, and interconnect metals such as indium or copper are prepared on the contact electrode 1 and contact electrode 2.

[0054] S16—The prepared extended wavelength InGaAs detector chip is soldered to the Si readout circuit to complete the preparation of the extended wavelength InGaAs focal plane detector. DETAILED DESCRIPTION

[0055] Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiments are only used to illustrate the present invention and are not used in limiting the scope of the present invention.In addition, should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall equally within the scope limited by the appended claims of the application.

[0056] Example 1

[0057] This embodiment 1 illustrates the present invention's method of preparing a 640×512 scale InGaN detector based on a patterned substrate with the groove area corresponding to the detector pixel. 0.7 Ga 0.3 As the focal plane detector method, the specific steps are as follows:

[0058] (1) On an N-type InP substrate (doped with S, electron concentration 4×10 18 cm-3 ) is fabricated on a patterned substrate through film growth, photolithography, etching, and resin deposition. The pattern size on a single chip is 640×512, with grooves measuring 4μm×4μm, ridges between adjacent grooves measuring 1μm, and groove depths of 2μm. Adjacent 640×512 cells are spaced 1mm apart.

[0059] (2) Retaining SiN on the ridges after pattern etching of the InP substrate x Dielectric layer 1, thickness 200 nm;

[0060] (3) Using molecular beam epitaxy to grow extended wavelength In on the above substrate 0.7 Ga 0.3 As detector material structure, including thickness 1.5μm, electron concentration 2×10 18 cm -3 N-type heavily doped InAlAs buffer layer (In composition changes from 0.52 to 0.7), thickness 1.5μm, electron concentration 5×10 15 cm -3 N-type lightly doped In 0.7 Ga 0.3 As absorption layer, thickness 0.5 μm, hole concentration 2×10 18 cm -3 P-type heavily doped In 0.7 Al 0.3 As contact layer. x The semiconductor single crystal material is formed on the dielectric layer, and on the SiN x The semiconductor polycrystalline or amorphous material is formed on the dielectric layer. In the semiconductor single crystal material, the dislocation caused by lattice mismatch extends to the edge of the pattern in the InAlAs buffer layer and stops, and no longer extends upward, thereby reducing the InAlAs 0.7 Ga 0.3 Dislocation density in the As absorber layer material;

[0061] (4) Deposit SiN on the exposed area of ​​the semiconductor single crystal surface through processes such as photolithography, development, PECVD, and floating glue x The second dielectric layer is passivated for protection;

[0062] (5) Through processes such as photolithography, development, and etching, windows are opened in the areas where P-type and N-type contact metals need to be deposited; Ti / Pt / Au metal is deposited as the P-type contact metal at the location of contact electrode 1 by electron beam evaporation, and Cr / Au metal is prepared as the N-type contact metal at the location of contact electrode 2 by magnetron sputtering;

[0063] (6) using photolithography, thermal evaporation, and lift-off techniques to prepare copper pillars for interconnection;

[0064] (7) Prepare the extended wavelength In 0.7 Ga 0.3 The As detector chip is soldered to the Si readout circuit with copper pillars, and the detector is packaged to complete the extended wavelength In 0.7 Ga 0.3 As focal plane detector preparation.

[0065] Example 2

[0066] This embodiment 2 illustrates the present invention's method of preparing a 640×512 scale InGaN detector based on a patterned substrate with the ridge region corresponding to the detector pixel. 0.7 Ga 0.3 As the focal plane detector method, the specific steps are as follows:

[0067] (1) On an N-type InP substrate (doped with S, electron concentration 3×10 18 cm -3 ) is patterned using photolithography and etching processes. The pattern size on a single chip is 640×512, with a ridge terrace width of 13μm×13μm, a groove width of 2μm between adjacent ridge terraces, and a groove depth of 3μm. The spacing between adjacent 640×512 cells is 1mm.

[0068] (2) After the pattern preparation of the InP substrate is completed, SiN is deposited in the groove position using photolithography, PECVD, and floating glue processes. x Dielectric layer 1, thickness 200 nm;

[0069] (3) Using molecular beam epitaxy to grow extended wavelength In on the above substrate 0.7 Ga 0.3 As detector material structure, including thickness 1.5μm, electron concentration 2×10 18 cm -3 N-type heavily doped InAlAs buffer layer (In composition changes from 0.52 to 0.7), thickness 1.5μm, electron concentration 5×10 15 cm -3 N-type lightly doped In 0.7 Ga 0.3 As absorption layer, thickness 0.5 μm, hole concentration 2×10 18 cm -3 P-type heavily doped In 0.7 Al 0.3 As contact layer. x The semiconductor single crystal material is formed on the dielectric layer, and on the SiN xThe semiconductor polycrystalline or amorphous material is formed on the dielectric layer. In the semiconductor single crystal material, the dislocation caused by lattice mismatch extends to the edge of the pattern in the InAlAs buffer layer and stops, and no longer extends upward, thereby reducing the InAlAs 0.7 Ga 0.3 Dislocation density in the As absorber layer material;

[0070] (4) Deposit SiN on the exposed area of ​​the semiconductor single crystal surface through processes such as photolithography, development, PECVD, and floating glue x The second dielectric layer is passivated for protection;

[0071] (5) Opening windows in the areas where P-type and N-type contact metals need to be deposited by photolithography, development, etching, and other processes; using magnetron sputtering to prepare Cr / Au metals as P-type and N-type contact metals at the positions of contact electrode 1 and contact electrode 2, respectively;

[0072] (6) Using photolithography, thermal evaporation, and lift-off processes to prepare indium pillars for interconnection;

[0073] (7) Prepare the extended wavelength In 0.7 Ga 0.3 The As detector chip is connected to the Si readout circuit with the indium column prepared by reverse soldering, and the detector is packaged to complete the extended wavelength In 0.7 Ga 0.3 As focal plane detector preparation.

[0074] Example 3

[0075] This embodiment 3 illustrates the preparation of a 320×256 scale In CMOS process based on a patterned substrate according to the present invention. 0.8 Ga 0.2 As the focal plane detector method, the specific steps are as follows:

[0076] (1) On a P-type InP substrate (doped with Zn, electron concentration 5×10 18 cm -3 A patterned substrate is fabricated on a chip through film growth, photolithography, etching, and resin deposition. The pattern size on a single chip is 320×256 pixels, with a pixel center-to-center distance of 33μm. The grooves designed into the patterned substrate correspond to the detector pixels. The groove width of the pattern is 30μm×30μm, the ridge width between adjacent grooves is 3μm, and the groove depth is 4μm. The spacing between adjacent 320×256 pixels is 500μm.

[0077] (2) Retaining SiN on the ridges after pattern etching of the InP substrate x Dielectric layer 1, thickness 300 nm;

[0078] (3) Using molecular beam epitaxy to grow extended wavelength In on the above substrate 0.8 Ga 0.2 As detector material structure, including thickness 1.8μm, electron concentration 5×10 18 cm -3 The P-type heavily doped InAsP buffer layer (As composition increased from 0 to 0.57), with a thickness of 2μm and an electron concentration of 1×10 16 cm -3 N-type lightly doped In 0.8 Ga 0.2 As absorption layer, thickness 0.5 μm, hole concentration 3×10 18 cm -3 N-type heavily doped InAs 0.57 P 0.43 Contact layer. x The semiconductor single crystal material is formed on the dielectric layer, and on the SiN x The semiconductor polycrystalline or amorphous material is formed on the dielectric layer. In the semiconductor single crystal material, the dislocation caused by lattice mismatch extends to the edge of the pattern in the InAsP buffer layer and stops, and no longer extends upward, thereby reducing the InAsP 0.8 Ga 0.2 Dislocation density in the As absorber layer material;

[0079] (4) Deposit SiN on the exposed area of ​​the semiconductor single crystal surface through processes such as photolithography, development, PECVD, and floating glue x The second dielectric layer is passivated for protection;

[0080] (5) Through processes such as photolithography, development, and etching, windows are opened in the areas where N-type and P-type contact metals need to be deposited; Au / Ge / Ni metal prepared by electron beam evaporation is used as the N-type contact metal at the position of contact electrode 1, and Ti / Pt / Au metal is prepared by electron beam evaporation as the P-type contact metal at the position of contact electrode 2;

[0081] (6) using photolithography, electroplating, and stripping processes to prepare copper metal pillars for interconnection;

[0082] (7) Prepare the extended wavelength In 0.8 Ga 0.2 The As detector chip is soldered to the Si readout circuit with the copper metal column prepared, and the detector is packaged to complete the extended wavelength In 0.8 Ga 0.2 As focal plane detector preparation.

Claims

1. Patterned substrate extended wavelength InGaAs focal plane detector, the structure of which is from top to bottom including patterned substrate (1), SiN x Dielectric layer 1 (2), semiconductor single crystal material (3), semiconductor polycrystalline or amorphous material (4), SiN x The second dielectric layer (5), the first contact electrode (6), the second contact electrode (7), the interconnecting metal (8), and the Si readout circuit (9) are characterized by: The material of the patterned substrate (1) is InP, and the doping type is N-type or P-type doping. The period of the patterned substrate (1) is the same as the center distance of the focal plane detector pixel, and the period is 5-33 μm. The patterned substrate (1) includes two structures, one is that the groove size is the same as the pixel size, and the corresponding ridge size is the same as the pixel spacing size, and the other is that the ridge size is the same as the pixel size, and the corresponding groove size is the same as the pixel spacing size, wherein the pixel size is 4-30 μm, the pixel spacing size is 1-3 μm, and the groove depth is 2-4 μm.

2. A method for preparing a patterned substrate extended wavelength InGaAs focal plane detector, characterized in that The following steps are involved: 1) preparing a patterned substrate (1) on an InP substrate through photolithography, etching and other process steps; 2) Retain or grow SiN in the pixel spacer x The dielectric layer 1 (2) serves as an epitaxial growth mask; 3) Epitaxial growth of extended wavelength InGaAs detector material structure, including InAlAs or InAsP buffer layer, InGaAs absorption layer, InAlAs or InAsP contact layer; wherein no SiN x The semiconductor single crystal material (3) is epitaxially formed on the dielectric layer (2), and the semiconductor single crystal material (3) is epitaxially formed on the SiN x A semiconductor polycrystalline or amorphous material (4) is formed on the dielectric layer (2); 4) Deposition of SiN x The second dielectric layer (5) is used to passivate and protect the exposed area on the surface of the semiconductor single crystal material (3); 5) combining etching, photolithography, development, stripping and other processes, and using sputtering or evaporation process to prepare contact electrode 1 (6) and contact electrode 2 (7) on the semiconductor single crystal material (3) and the patterned substrate (1); 6) preparing interconnecting metal (8) such as indium or copper on the first contact electrode (6) and the second contact electrode (7); 7) The prepared extended wavelength InGaAs detector chip is interconnected with the Si readout circuit (9) by reverse soldering, thereby completing the preparation of the patterned substrate extended wavelength InGaAs focal plane detector.

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