Pulse voltage regulation circuit and DC-DC chip

Abstract

This invention provides a pulse voltage regulation circuit, comprising: a pulse control module and a reference voltage regulation module; the pulse control module is used to generate a set of M switching control signals according to the number of continuously input pulse signals; the reference voltage regulation module is connected to the output terminal of the pulse control module and is used to select a resistor voltage division ratio according to the M switching control signals, and to divide the bandgap voltage according to the selected resistor voltage division ratio to generate a reference voltage output; wherein, M = 2 N N is an integer greater than or equal to 1. The pulse voltage regulation circuit provided by this invention solves the problem of existing voltage regulation schemes adjusting the output voltage by changing the resistance value of external resistors.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a pulse voltage regulation circuit and a DC-DC chip. Background Technology

[0002] In existing DC-DC chips, a feedback pin FB is typically included. The output voltage VOUT is divided by external resistors and then fed into the feedback pin FB, allowing the output voltage VOUT to be adjusted by changing the resistance value of the external resistors. Therefore, proposing a new voltage regulation scheme that achieves adjustable output voltage without changing the external resistors is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a pulse voltage regulation circuit and a DC-DC chip to solve the problem that existing voltage regulation schemes adjust the output voltage by changing the resistance value of the external resistor.

[0004] To achieve the above and other related objectives, the present invention provides a pulse voltage regulation circuit, which includes: a pulse control module and a reference voltage regulation module;

[0005] The pulse control module is used to generate a set of M switch control signals based on the number of continuously input pulse signals;

[0006] The reference voltage regulation module is connected to the output terminal of the pulse control module and is used to select the resistor voltage division ratio according to the M switch control signals, and to divide the bandgap voltage according to the selected resistor voltage division ratio to generate a reference voltage output.

[0007] Where M = 2 N N is an integer greater than or equal to 1.

[0008] Optionally, the pulse control module includes: a counting control unit and a switch generation unit;

[0009] The counting control unit is used to count the number of continuously input pulse signals to generate an N-bit count result, and to generate a lock signal when the high-level duration of the pulse signal is greater than a high-dimensional set value, and to clear the N-bit count result when the low-level duration of the pulse signal is greater than a low-dimensional set value.

[0010] The switch generation unit is connected to the output terminal of the counting control unit and is used to generate the M switch control signals based on the N-bit counting result, and to lock the switches based on the locking signal.

[0011] Optionally, the counting control unit includes: a pulse input section, a first control section, a second control section, and a counting generation section;

[0012] The pulse input section is used to input the pulse signal;

[0013] The first control section is connected to the output terminal of the pulse input section and is used to generate a working enable signal according to the pulse signal after power-on startup, and to generate a clear signal when the low level duration of the pulse signal is greater than the low dimension set value.

[0014] The second control section is connected to the output terminal of the pulse input section and is used to generate a counting clock on the falling edge of the pulse signal and to generate the lock signal when the high level duration of the pulse signal is greater than the high-dimensional set value.

[0015] The counting generation section is connected to the output terminals of the first control section and the second control section. It is used to generate the N-bit count result by counting the number of pulses according to the counting clock when the working enable signal is valid, and to clear the N-bit count result when the lock signal or the clear signal is valid.

[0016] Optionally, the pulse input section includes: a first NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first resistor, a second resistor, a first inverter, and a second inverter; the gate of the first NMOS transistor is connected to the gate of the first PMOS transistor and connected to the pulse signal, the source is grounded, and the drain is connected to the drain of the first PMOS transistor and the input terminal of the first inverter; the source of the first PMOS transistor is connected to the power supply voltage via the first resistor and the second resistor; the output terminal of the first inverter is connected to the gate of the second PMOS transistor and the input terminal of the second inverter; the source of the second PMOS transistor is connected to the power supply voltage, and the drain is connected to the connection node of the first resistor and the second resistor; the output terminal of the second inverter serves as the output terminal of the pulse input section.

[0017] Optionally, the first control section includes: a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a third inverter, and a reset delay; the first input terminal of the first NAND gate is connected to the output terminal of the pulse input section, the second input terminal is connected to the output terminal of the second NAND gate, and the output terminal is connected to the first input terminal of the second NAND gate and the first input terminal of the third NAND gate; the second input terminal of the second NAND gate is connected to a power-on start signal; the second input terminal of the third NAND gate is connected to the output terminal of the pulse input section via the reset delay and the third inverter, the third input terminal is connected to the output terminal of the fourth NAND gate, and the output terminal is connected to the first input terminal of the fourth NAND gate; the second input terminal of the fourth NAND gate is connected to the output terminal of the pulse input section, and the output terminal generates the working enable signal; wherein, the reset delay is used to perform a low-dimensional set value delay at the falling edge of the pulse to generate the reset signal.

[0018] Optionally, the second control section includes: a fourth inverter, a fifth inverter, a first delay unit, and a lock delay unit; the input terminal of the fourth inverter is connected to the output terminal of the pulse input section, and the output terminal is connected to the input terminals of the first delay unit and the lock delay unit; the output terminal of the first delay unit is connected to the input terminal of the fifth inverter; the output terminal of the fifth inverter generates the counting clock; the output terminal of the lock delay unit generates the lock signal; wherein, the lock delay unit is used to perform a high-dimensional set value delay at the rising edge of the pulse to generate the lock signal.

[0019] Optionally, the counting generation section includes: a fifth NAND gate, a sixth NAND gate, a second delay, a third delay, a sixth inverter, a seventh inverter, an eighth inverter, and an N-bit counter; the first input of the fifth NAND gate is connected to a power-on start signal, the second input is connected to the reset signal, the third input is connected to the working enable signal via the second delay, and the output is connected to the first input of the sixth NAND gate via the sixth inverter; the second input of the sixth NAND gate is connected to the lock signal via the seventh inverter and the third delay, and the output is connected to the set input of the N-bit counter via the eighth inverter; the clock input of the N-bit counter is connected to the counting clock, and the output generates the N-bit counting result.

[0020] Optionally, the counting control unit further includes: a debouncing section connected between the pulse input section and the second control section for signal debouncing; wherein the debouncing section includes: a ninth inverter, a second NMOS transistor, a third PMOS transistor, a third resistor, a first capacitor, and a Schmitt trigger; the input terminal of the ninth inverter is connected to the output terminal of the pulse input section, and the output terminal is connected to the gates of the second NMOS transistor and the third PMOS transistor; the source of the second NMOS transistor is grounded, and the drain is connected to the drain of the third PMOS transistor and the first terminal of the third resistor; the source of the third PMOS transistor is connected to the power supply voltage; the second terminal of the third resistor is grounded via the first capacitor and connected to the input terminal of the Schmitt trigger; the output terminal of the Schmitt trigger is connected to the input terminal of the second control section;

[0021] At this time, the second control section is replaced by: a fifth inverter, a first delay unit, and a lock delay unit; the input terminal of the first delay unit is connected to the output terminal of the debouncing section, and the output terminal is connected to the input terminal of the fifth inverter; the output terminal of the fifth inverter generates the counting clock; the input terminal of the lock delay unit is connected to the output terminal of the debouncing section, and the output terminal generates the lock signal; wherein, the lock delay unit is used to perform a high-dimensional set value delay on the rising edge of the pulse to generate the lock signal.

[0022] Optionally, the switch generation unit includes: a complementary signal section and a switch decoding section;

[0023] The complementary signal portion is connected to the output terminal of the counting control unit, and is used to generate N sets of complementary signals based on the N-bit counting result, and to lock the output when the locking signal is valid.

[0024] The switch decoding section is connected to the output of the complementary signal section and is used to generate the M switch control signals based on the N sets of complementary signals.

[0025] Optionally, the complementary signal section includes N sets of signal latch structures, wherein the N sets of signal latch structures are identical and include: a latch and a tenth inverter; the set terminal of the latch is connected to the lock signal, the input terminal is connected to one bit of the N-bit counting result, and the output terminal generates a set of complementary signals via the tenth inverter.

[0026] Optionally, the switch decoding section includes M sets of switch decoding structures, wherein the M sets of switch decoding structures are identical, including: a seventh NAND gate and an eleventh inverter; the N input terminals of the seventh NAND gate are respectively connected to one of the complementary signals in each set, and the output terminal generates a switch control signal via the eleventh inverter.

[0027] Optionally, the reference voltage regulation module includes: a voltage generator, M switches, and at least (M+1) fourth resistors; the voltage generator is controlled by a power-on start signal and a working enable signal to generate the bandgap voltage; the (M+1) fourth resistors are connected in series between the output terminal of the voltage generator and ground to form M connection nodes; the first terminals of the M switches are correspondingly connected to the M connection nodes, the second terminals are connected to each other to generate the reference voltage, and the control terminals are correspondingly connected to the control signals of the M switches.

[0028] The present invention also provides a DC-DC chip, the DC-DC chip comprising: the pulse voltage regulation circuit and the error amplifier circuit as described above; the first input terminal of the error amplifier circuit is connected to the output terminal of the pulse voltage regulation circuit to connect to the reference voltage, the second input terminal is connected to the feedback voltage, and the output terminal generates an error voltage.

[0029] As described above, the pulse voltage regulation circuit and DC-DC chip of the present invention, based on the design of a pulse control module and a reference voltage regulation module, select the magnitude of the reference voltage by controlling the number of continuously input pulse signals, thereby realizing the output of different reference voltages and thus achieving adjustable output voltage; the circuit structure of the present invention is simple and can be implemented using ordinary MOS devices. Attached Figure Description

[0030] Figure 1 The diagram shown is a schematic diagram of the pulse voltage regulation circuit in Embodiment 1 of the present invention.

[0031] Figure 2 The diagram shown is a structural schematic of the pulse control module in Embodiment 1 of the present invention.

[0032] Figure 3 The diagram shown is a circuit diagram of a pulse control module in Embodiment 1 of the present invention.

[0033] Figure 4 This is another circuit diagram of the pulse control module in Embodiment 1 of the present invention.

[0034] Figure 5 The diagram shown is a circuit diagram of the complementary signal section in Embodiment 1 of the present invention.

[0035] Figure 6 The diagram shown is a circuit diagram of the latch for the complementary signal section in Embodiment 1 of the present invention.

[0036] Figure 7 The diagram shown is a circuit diagram of the switch decoding part in Embodiment 1 of the present invention.

[0037] Figure 8 The diagram shown is a circuit diagram of the reference voltage regulation module in Embodiment 1 of the present invention.

[0038] Figure 9This diagram illustrates the relationship between the number of input pulse signals and the output voltage of the pulse voltage regulation circuit in Embodiment 1 of the present invention.

[0039] Figure 10 The diagram shown is a timing diagram of the pulse voltage regulation circuit in Embodiment 1 of the present invention.

[0040] Figure 11 The diagram shown is a schematic diagram of the DC-DC chip in Embodiment 2 of the present invention. Detailed Implementation

[0041] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] Please see Figures 1 to 11 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0043] Example 1

[0044] like Figure 1 As shown, this embodiment provides a pulse voltage regulation circuit 10, which includes a pulse control module 100 and a reference voltage regulation module 200. Wherein,

[0045] The pulse control module 100 is used to generate a set of M switch control signals based on the number of continuously input pulse signals; where M = 2. N N is an integer greater than or equal to 1. It should be noted that a group of M switch control signals means that a group of signals contains M switch control signals, such as a group of signals containing 16 switch control signals KEY0-KEY15.

[0046] Specifically, such as Figure 2 As shown, the pulse control module 100 includes a counting control unit 110 and a switch generation unit 120.

[0047] in,

[0048] The counting control unit 110 is used to count the number of continuously input pulse signals to generate an N-bit count result, and to generate a lock signal when the high-level duration of the pulse signal is greater than the high-dimensional set value, and to clear the N-bit count result when the low-level duration of the pulse signal is greater than the low-dimensional set value.

[0049] More specifically, such as Figure 3 As shown, the counting control unit 110 includes: a pulse input section 111, a first control section 112, a second control section 113, and a counting generation section 114; further, it also includes: a debouncing section 115. Wherein,

[0050] The pulse input section 111 is used to input pulse signals.

[0051] As an example, such as Figure 3 As shown, the pulse input section 111 includes: a first NMOS transistor MN1, a first PMOS transistor MP1, a second PMOS transistor MP2, a first resistor R1, a second resistor R2, a first inverter INV1, and a second inverter INV2; the gate of the first NMOS transistor MN1 is connected to the gate of the first PMOS transistor MP1 and connected to the pulse signal, the source is grounded, and the drain is connected to the drain of the first PMOS transistor MP1 and the input terminal of the first inverter INV1; the source of the first PMOS transistor MP1 is connected to the power supply voltage via the first resistor R1 and the second resistor R2; the output terminal of the first inverter INV1 is connected to the gate of the second PMOS transistor MP2 and the input terminal of the second inverter INV2; the source of the second PMOS transistor MP2 is connected to the power supply voltage, and the drain is connected to the connection node J1 of the first resistor R1 and the second resistor R2; the output terminal of the second inverter INV2 serves as the output terminal of the pulse input section 111.

[0052] In this example, the first NMOS transistor MN1 and the first PMOS transistor MP1 constitute an inverting logic gate. When the input pulse signal is high, the first NMOS transistor MN1 is turned on, the first PMOS transistor MP1 is turned off, the inverting logic gate outputs a low level, which is then output as a high level after passing through the first inverter INV1, and then as a low level after passing through the second inverter INV2. At this time, the second PMOS transistor MP2 is turned off. When the input pulse signal is low, the first NMOS transistor MN1 is turned off, the first PMOS transistor MP1 is turned on, the inverting logic gate outputs a high level, which is then output as a low level after passing through the first inverter INV1, and then as a high level after passing through the second inverter INV2. At this time, the second PMOS transistor MP2 is turned on.

[0053] This example utilizes the voltage division of the first resistor R1 and the second resistor R2 to reduce the source voltage of the first PMOS transistor MP1. This allows the first PMOS transistor MP1 to conduct at a lower gate voltage, thus reducing the turn-on voltage of the first PMOS transistor MP1. Then, the second resistor R2 is shielded by the conducting second PMOS transistor MP2 to increase the source voltage of the first PMOS transistor MP1, thereby raising the turn-off voltage of the first PMOS transistor MP1.

[0054] The first control section 112 is connected to the output terminal of the pulse input section 111. It is used to generate a working enable signal CE_H based on the pulse signal after power-on startup, and to generate a clear signal DELAY_SHUT when the low level duration of the pulse signal is greater than the low-dimensional set value (e.g., 3ms).

[0055] As an example, such as Figure 3 As shown, the first control section 112 includes: a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a fourth NAND gate NAND4, a third inverter INV3, and a reset delay DL_SHUT; the first input terminal of the first NAND gate NAND1 is connected to the output terminal of the pulse input section 111, the second input terminal is connected to the output terminal of the second NAND gate NAND2, and the output terminal is connected to the first input terminal of the second NAND gate NAND2 and the first input terminal of the third NAND gate NAND3; the second input terminal of the second NAND gate NAND2 is connected to the power-on start signal SYSOK_H; the third NAND gate NAND3's first input terminal is connected to the first input terminal of the third NAND gate NAND3. The two input terminals are connected to the output of the pulse input section 111 via the clear delay timer DL_SHUT and the third inverter INV3. The third input terminal is connected to the output of the fourth NAND gate NAND4, and the output terminal is connected to the first input of the fourth NAND gate NAND4. The second input terminal of the fourth NAND gate NAND4 is connected to the output of the pulse input section 111, and the output terminal generates the working enable signal CE_H. The clear delay timer DL_SHUT is used to delay a low-dimensional setpoint value at the falling edge of the pulse to generate the clear signal DELAY_SHUT. No delay is performed at other times besides the falling edge of the pulse, and at these times, its input and output are in phase. In this example, the first NAND gate NAND1, the second NAND gate NAND2, and the fourth NAND gate NAND4 are two-input NAND gates, and the third NAND gate NAND3 is a three-input NAND gate. The first NAND gate NAND1 and the second NAND gate NAND2 constitute an RS latch, and the third NAND gate NAND3 and the fourth NAND gate NAND4 constitute an RS latch.

[0056] Before power-on, the power-on signal SYSOK_H is low. If there is no valid input, the input remains low, and the output of the pulse input section 111 remains high. At this time, the RS latch composed of the first NAND gate NAND1 and the second NAND gate NAND2 outputs a low level, and the RS latch composed of the third NAND gate NAND3 and the fourth NAND gate NAND4 outputs a low level (the work enable signal CE_H is low). Thus, before power-on, the power-on signal SYSOK_H directly determines that the work enable signal CE_H is invalid, and the clear delay DL_SHUT is disabled, preventing the clear delay DL_SHUT from still operating. After power-on, the power-on signal SYSOK_H is high.

[0057] When the input pulse signal is high, the pulse input section 111 outputs a low level; at this time, the RS latch composed of the first NAND gate NAND1 and the second NAND gate NAND2 outputs a high level, and the RS latch composed of the third NAND gate NAND3 and the fourth NAND gate NAND4 outputs a high level (the working enable signal CE_H is high), that is, the working enable signal CE_H is valid.

[0058] When the input pulse signal is low, the pulse input section 111 outputs a high level. At this time, the RS latch composed of the first NAND gate NAND1 and the second NAND gate NAND2 maintains the previous state, which is high. The clear delay DL_SHUT outputs a high level because it delays the low-dimensional set value on the falling edge of the pulse. The RS latch composed of the third NAND gate NAND3 and the fourth NAND gate NAND4 maintains the previous state, which is high. Thus, the work enable signal CE_H is valid.

[0059] During this process, if the input pulse signal changes from high level to low level and the low level duration is longer than the low-dimensional set value, the clear delay DL_SHUT outputs a low level, that is, the clear signal DELAY_SHUT is valid. At this time, the RS latch composed of the third NAND gate NAND3 and the fourth NAND gate NAND4 outputs a low level, and the work enable signal CE_H is invalid; otherwise, the clear delay DL_SHUT outputs a high level, that is, the clear signal DELAY_SHUT is invalid.

[0060] In practical applications, to enhance the signal's driving capability and add a certain delay, two inverters connected in series can be placed at corresponding positions in the first control section 112. The positions can be designed according to specific requirements. For example, the first control section 112 also includes: a twelfth inverter INV12, a thirteenth inverter INV13, a fourteenth inverter INV14, a fifteenth inverter INV5, a sixteenth inverter INV16, a seventeenth inverter INV17, an eighteenth inverter INV18, a nineteenth inverter INV19, a twentieth inverter INV20, and a twenty-first inverter INV21; wherein, the twelfth inverter INV12 and the thirteenth inverter INV13 are located between the output of the pulse input section 111 and the connection node J2, and the fourteenth inverter INV14... Inverters 14 and 15 (INV15) are located between the connection node J2 and the first input terminal of the first NAND gate NAND1. Inverters 16 and 17 (INV17) are located between the output terminal of the first NAND gate NAND1 and the first input terminal of the third NAND gate NAND3. Inverters 18 and 19 (INV19) are located between the connection node J2 and the second input terminal of the fourth NAND gate NAND4. Inverters 20 and 21 (INV21) are located at the output terminal of the fourth NAND gate NAND4.

[0061] The second control section 113 is connected to the output of the pulse input section 111 and is used to generate a counting clock EN_CLK on the falling edge of the pulse signal, and to generate a lock signal Latch_Lock when the high level duration of the pulse signal is greater than the high-dimensional set value (e.g., 1ms).

[0062] As an example, such as Figure 3 As shown, the second control section 113 includes: a fourth inverter INV4, a fifth inverter INV5, a first delay DL1, and a lock delay DL_Lock; the input terminal of the fourth inverter INV4 is connected to the output terminal of the pulse input section 111, and the output terminal is connected to the input terminals of the first delay DL1 and the lock delay DL_Lock; the output terminal of the first delay DL1 is connected to the input terminal of the fifth inverter INV5; the output terminal of the fifth inverter INV5 generates the counting clock EN_CLK; the output terminal of the lock delay DL_Lock generates the lock signal Latch_Lock; wherein, the lock delay DL_Lock is used to perform a high-dimensional set value delay at the rising edge of the pulse to generate the lock signal Latch_Lock, and no delay is performed at other times except the rising edge of the pulse. At this time, its input and output are in phase. It should be noted that the first delay unit DL1 delays the input by a first set value (such as 10μs), which includes both the rising edge and the falling edge of the pulse. Due to the short delay time, its input and output are in phase.

[0063] In this example, when the input pulse signal is high, the pulse input section 111 outputs a low level. At this time, the low level passes through the fourth inverter INV4 and outputs a high level, then passes through the first delay unit DL1 and the fifth inverter INV5 and outputs a low level again. That is, the counting clock EN_CLK is invalid. When the input pulse signal is low, the pulse input section 111 outputs a high level. At this time, the high level passes through the fourth inverter INV4 and outputs a low level, then passes through the first delay unit DL1 and the fifth inverter INV5 and outputs a high level again. That is, the counting clock EN_CLK is valid. In this way, the counting clock EN_CLK is generated on the falling edge of the pulse signal.

[0064] During this process, if the input pulse signal changes from low level to high level and the high level is maintained for a longer time than the high-dimensional setting value, the DL_Lock timer outputs a high level, that is, the Latch_Lock signal is valid; otherwise, the DL_Lock timer outputs a low level, that is, the Latch_Lock signal is invalid.

[0065] The counting generation section 114 is connected to the output terminals of the first control section 112 and the second control section 113. It is used to generate an N-bit count result by counting the number of pulses according to the counting clock EN_CLK when the working enable signal CE_H is valid, and to clear the N-bit count result when the lock signal Latch_Lock or the clear signal DELAY_SHUT is valid.

[0066] As an example, such as Figure 3 As shown, the counting generation section 114 includes: a fifth NAND gate NAND5, a sixth NAND gate NAND6, a second delay DL2, a third delay DL3, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, and an N-bit counter; the first input of the fifth NAND gate NAND5 is connected to the power-on start signal SYSOK_H, the second input is connected to the clear signal DELAY_SHUT, the third input is connected to the work enable signal CE_H via the second delay DL2, and the output is connected to the first input of the sixth NAND gate NAND6 via the sixth inverter INV6; the second input of the sixth NAND gate NAND6 is connected to the lock signal Latch_Lock via the seventh inverter INV7 and the third delay DL3, and the output is connected to the set input of the N-bit counter via the eighth inverter INV8; the clock input of the N-bit counter is connected to the counting clock EN_CLK, and the output generates an N-bit counting result.

[0067] It should be noted that the fifth NAND gate (NAND5) is a three-input NAND gate; the sixth NAND gate (NAND6) is a two-input NAND gate; the second delay unit (DL2) delays the input by a second set value (e.g., 10μs), including both the rising and falling edges of the pulse. Due to the short delay time, its input and output are in phase; the third delay unit (DL3) delays the input by a third set value (e.g., 100ns), including both the rising and falling edges of the pulse. Due to the short delay time, its input and output are in phase; the N-bit counter is an upward counting counter composed of N cascaded flip-flops. Optionally, N=4, in which case a four-bit counting result is generated, such as COUNT1-COUNT4.

[0068] In this example, after power-on startup, the power-on signal SYSOK_H remains high. When a continuous pulse signal is input, the enable signal CE_H is active (CE_H is high), the clear signal DELAY_SHUT is inactive (DELAY_SHUT is high), and the latch signal Latch_Lock is inactive (Latch_Lock is low). The enable signal CE_H remains high after passing through the second delay DL2. At this time, the fifth NAND gate NAND5 outputs a low level, which then outputs a high level after passing through the sixth inverter INV6. The latch signal Latch_Lock remains low after passing through the third delay DL3, which then outputs a high level after passing through the seventh inverter INV7. At this time, the sixth NAND gate NAND6 outputs a low level, which then outputs a high level after passing through the eighth inverter INV8. Thus, the N-bit counter can count the number of pulses according to the counting clock EN_CLK and generate an N-bit count result.

[0069] During this process, when the clear signal DELAY_SHUT is valid, that is, when the clear signal DELAY_SHUT is low, the fifth NAND gate NAND5 outputs a high level, and then outputs a low level after passing through the sixth inverter INV6. The sixth NAND gate NAND6 outputs a high level, and then outputs a low level after passing through the eighth inverter INV8. In this way, the N-bit counter is cleared, that is, the N-bit count result is cleared.

[0070] During this process, when the Latch_Lock signal is valid, that is, when the Latch_Lock signal is high, the Latch_Lock signal remains high after passing through the third delay DL3, and then outputs a low level after passing through the seventh inverter INV7. The sixth NAND gate NAND6 outputs a high level, and then outputs a low level after passing through the eighth inverter INV8. In this way, the N-bit counter is cleared, that is, the N-bit count result is cleared.

[0071] In practical applications, to enhance the signal's driving capability and add a certain delay, two inverters connected in series can be placed at corresponding positions in the counting generation section 114. The positions can be designed according to specific requirements. For example, the counting generation section 114 also includes a twenty-second inverter INV22 and a twenty-third inverter INV23, located at the second input terminal of the fifth NAND gate NAND5. In this case, the clear signal DELAY_SHUT is input to the second input terminal of the fifth NAND gate NAND5 via the twenty-second inverter INV22 and the twenty-third inverter INV23.

[0072] The debouncing section 115 is connected between the pulse input section 111 and the second control section 113, and is used to perform signal debouncing.

[0073] As an example, such as Figure 4 As shown, the debouncing section 115 includes: a ninth inverter INV9, a second NMOS transistor MN2, a third PMOS transistor MP3, a third resistor R3, a first capacitor C1, and a Schmitt trigger SMIT1; the input terminal of the ninth inverter INV9 is connected to the output terminal of the pulse input section 111, and the output terminal is connected to the gates of the second NMOS transistor MN2 and the third PMOS transistor MP3; the source of the second NMOS transistor MN2 is grounded, and its drain is connected to the drain of the third PMOS transistor MP3 and the first terminal of the third resistor R3; the source of the third PMOS transistor MP3 is connected to the power supply voltage; the second terminal of the third resistor R3 is grounded via the first capacitor C1 and connected to the input terminal of the Schmitt trigger SMIT1; the output terminal of the Schmitt trigger SMIT1 is connected to the input terminal of the second control section 113. At this time,

[0074] The second control section 113 no longer includes the fourth inverter INV4; that is, the output of the Schmitt trigger SMIT1 is connected to the input of the first delay DL1 and the lock delay DL_Lock. The second control section 113 is replaced by: a fifth inverter INV5, a first delay DL1, and a lock delay DL_Lock. The input of the first delay DL1 is connected to the output of the debouncing section 115, and its output is connected to the input of the fifth inverter INV5. The output of the fifth inverter INV5 generates the counting clock EN_CLK. The input of the lock delay DL_Lock is connected to the output of the debouncing section 115, and its output generates the lock signal Latch_Lock. The lock delay DL_Lock is used to delay at the rising edge of the pulse by a high-dimensional set value to generate the lock signal Latch_Lock. No delay is performed at other times besides the rising edge of the pulse; in this case, its input and output are in phase. It should be noted that the first delay unit DL1 delays the input by a first set value (such as 10μs), which includes both the rising edge and the falling edge of the pulse. Due to the short delay time, its input and output are in phase.

[0075] In this example, the second NMOS transistor MN2 and the third PMOS transistor MP3 constitute an inverting logic gate. The output of the pulse input section 111 is inverted by two stages, and then the waveform is shaped by the charging and discharging of the capacitor. Finally, the output is inverted by the Schmitt trigger. In this way, a 1μs delay between the rising and falling edges is generated, which achieves the purpose of eliminating jitter and filtering out glitches.

[0076] When the input pulse signal is high, the pulse input section 111 outputs a low level. At this time, the low level is debouncing and then outputs a high level after passing through the debouncing section 115. After passing through the first delay unit DL1 and the fifth inverter INV5, it outputs a low level again, meaning the counting clock EN_CLK is invalid. When the input pulse signal is low, the pulse input section 111 outputs a high level. At this time, the high level is debouncing and then outputs a low level after passing through the debouncing section 115. After passing through the first delay unit DL1 and the fifth inverter INV5, it outputs a high level again, meaning the counting clock EN_CLK is valid. In this way, the counting clock EN_CLK is generated on the falling edge of the pulse signal.

[0077] During this process, if the input pulse signal changes from low level to high level and the high level is maintained for a longer time than the high-dimensional setting value, the DL_Lock timer outputs a high level, that is, the Latch_Lock signal is valid; otherwise, the DL_Lock timer outputs a low level, that is, the Latch_Lock signal is invalid.

[0078] In practical applications, to enhance the signal's driving capability and perform waveform shaping, two inverters connected in series can be placed at corresponding positions in the debouncing section 115. The positions can be designed according to specific requirements. For example, the debouncing section 115 also includes a twenty-fourth inverter INV24 and a twenty-fifth inverter INV25, which are set at the output of Schmitt trigger SMIT1. In this case, the output of Schmitt trigger SMIT1 is connected to the input of the first delay DL1 and the lock delay DL_Lock via the twenty-fourth inverter INV24 and the twenty-fifth inverter INV25.

[0079] The switch generation unit 120 is connected to the output terminal of the counting control unit 110 and is used to generate M switch control signals (such as KEY0-KEY15) based on the N-bit counting results (such as COUNT1-COUNT4), and to lock the switches based on the lock signal Latch_Lock.

[0080] More specifically, such as Figures 5-7 As shown, the switch generation unit 120 includes a complementary signal section 121 and a switch decoding section 122. Wherein,

[0081] The complementary signal section 121 is connected to the output of the counting control unit 110 and is used to generate N sets of complementary signals (such as Q1 and Q1N-Q4 and Q4N) based on the N-bit counting results (such as COUNT1-COUNT4), and to lock the output when the lock signal Latch_Lock is valid.

[0082] As an example, such as Figure 5 As shown, the complementary signal section 121 includes N sets of signal latch structures 1211, wherein the N sets of signal latch structures 1211 are identical, including: a latch and a tenth inverter; the set terminal of the latch is connected to the lock signal Latch_Lock, the input terminal is connected to one bit of the N-bit counting result, and the output terminal generates a set of complementary signals via the tenth inverter.

[0083] Taking N=4 as an example, the complementary signal section 121 includes four sets of signal latch structures 1211; among which,

[0084] The first group of signal latch structure 1211 includes: latch LAT1 and tenth inverter INV10_1; the set terminal of latch LAT1 is connected to the lock signal Latch_Lock, the input terminal is connected to the counting result COUNT1, the output terminal is connected to the input terminal of the tenth inverter INV10_1 and generates signal Q1, and the output terminal of the tenth inverter INV10_1 generates signal Q1N.

[0085] The second group of signal latch structure 1211 includes: latch LAT2 and tenth inverter INV10_2; the set terminal of latch LAT2 is connected to the lock signal Latch_Lock, the input terminal is connected to the counting result COUNT2, the output terminal is connected to the input terminal of the tenth inverter INV10_2 and generates signal Q2, and the output terminal of the tenth inverter INV10_2 generates signal Q2N.

[0086] The third group of signal latch structure 1211 includes: latch LAT3 and tenth inverter INV10_3; the set terminal of latch LAT3 is connected to the lock signal Latch_Lock, the input terminal is connected to the counting result COUNT3, the output terminal is connected to the input terminal of the tenth inverter INV10_3 and generates signal Q3, and the output terminal of the tenth inverter INV10_3 generates signal Q3N.

[0087] The fourth group of signal latch structure 1211 includes: latch LAT4 and tenth inverter INV10_4; the set terminal of latch LAT4 is connected to the lock signal Latch_Lock, the input terminal is connected to the counting result COUNT4, the output terminal is connected to the input terminal of the tenth inverter INV10_4 and generates signal Q4, and the output terminal of the tenth inverter INV10_4 generates signal Q4N.

[0088] In practical applications, to enhance the signal's driving capability and add a certain delay, two inverters connected in series can be placed at corresponding positions in the signal latch structure 1211. The positions can be designed according to specific requirements. For example, the signal latch structure 1211 also includes a 26th inverter and a 27th inverter, located at the input of the latch. In this case, the corresponding counting result is input to the latch via the 26th and 27th inverters. Taking four sets of signal latch structures 1211 as an example, the 26th inverter INV26_1 and the 27th inverter INV27_1 are located at the input of latch LAT1, the 26th inverter INV26_2 and the 27th inverter INV27_2 are located at the input of latch LAT2, the 26th inverter INV26_3 and the 27th inverter INV27_3 are located at the input of latch LAT3, and the 26th inverter INV26_4 and the 27th inverter INV27_4 are located at the input of latch LAT4.

[0089] Among them, such as Figure 6 As shown, the four latches LAT1-LAT4 are identical, including: NAND8 (eighth NAND gate), NAND9 (ninth NAND gate), INV28 (twenty-eighth inverter), INV29 (twenty-ninth inverter), and INV30 (thirtieth inverter). The input of INV28 serves as the input of the latch, and its output is connected to the first input of NAND8. The second input of NAND8 is connected to the output of NAND9, and its output is connected to the first input of NAND9 and the input of INV29. The second input of NAND9 serves as the set input of the latch. The output of INV29 is connected to the input of INV30. The output of INV30 serves as the output of the latch.

[0090] In this example, when the latch signal Latch_Lock is invalid (i.e., the latch signal Latch_Lock is low), the output signals Q1-Q4 of the signal latch structure 1211 are in phase with the input count results COUNT1-COUNT4, and the output signals Q1N-Q4N are out of phase with the input count results COUNT1-COUNT4. When the latch signal Latch_Lock is valid (i.e., the latch signal Latch_Lock is high), the signals Q1-Q4 and Q1N-Q4N remain in the previous state, thus achieving output latching.

[0091] The switch decoding section 122 is connected to the output of the complementary signal section 121 and is used to generate M switch control signals (such as KEY0-KEY15) based on N sets of complementary signals (such as Q1 and Q1N-Q4 and Q4N).

[0092] As an example, such as Figure 7 As shown, the switch decoding section 122 includes M sets of switch decoding structures 1221, wherein the M sets of switch decoding structures 1221 are identical, including: a seventh NAND gate and an eleventh inverter; the N input terminals of the seventh NAND gate are respectively connected to one of the complementary signals in each group, and the output terminal generates a switch control signal via the eleventh inverter.

[0093] With N=4 and M=2 4 Taking 16 as an example, the switch decoding section 122 includes 16 sets of switch decoding structures 1221; among which,

[0094] The first set of switch decoding structure 1221 includes: a seventh NAND gate NAND7_1 and an eleventh inverter INV11_1; the first input terminal of the seventh NAND gate NAND7_1 is connected to signal Q1N, the second input terminal is connected to signal Q2N, the third input terminal is connected to signal Q3N, the fourth input terminal is connected to signal Q4N, and the output terminal generates a switch control signal KEY0 via the eleventh inverter INV11_1.

[0095] The second set of switch decoding structure 1221 includes: a seventh NAND gate NAND7_2 and an eleventh inverter INV11_2; the first input terminal of the seventh NAND gate NAND7_2 is connected to signal Q1, the second input terminal is connected to signal Q2N, the third input terminal is connected to signal Q3N, the fourth input terminal is connected to signal Q4N, and the output terminal generates a switch control signal KEY1 via the eleventh inverter INV11_2.

[0096] The third set of switch decoding structure 1221 includes: a seventh NAND gate NAND7_3 and an eleventh inverter INV11_3; the first input terminal of the seventh NAND gate NAND7_3 is connected to signal Q1N, the second input terminal is connected to signal Q2, the third input terminal is connected to signal Q3N, the fourth input terminal is connected to signal Q4N, and the output terminal generates a switch control signal KEY2 via the eleventh inverter INV11_3.

[0097] The fourth set of switch decoding structure 1221 includes: a seventh NAND gate NAND7_4 and an eleventh inverter INV11_4; the first input terminal of the seventh NAND gate NAND7_4 is connected to signal Q1, the second input terminal is connected to signal Q2, the third input terminal is connected to signal Q3N, the fourth input terminal is connected to signal Q4N, and the output terminal generates a switch control signal KEY3 via the eleventh inverter INV11_4.

[0098] The fifth set of switch decoding structure 1221 includes: a seventh NAND gate NAND7_5 and an eleventh inverter INV11_5; the first input terminal of the seventh NAND gate NAND7_5 is connected to signal Q1N, the second input terminal is connected to signal Q2N, the third input terminal is connected to signal Q3, the fourth input terminal is connected to signal Q4N, and the output terminal generates a switch control signal KEY4 via the eleventh inverter INV11_5.

[0099] The sixth set of switch decoding structure 1221 includes: a seventh NAND gate NAND7_6 and an eleventh inverter INV11_6; the first input terminal of the seventh NAND gate NAND7_6 is connected to signal Q1, the second input terminal is connected to signal Q2N, the third input terminal is connected to signal Q3, the fourth input terminal is connected to signal Q4N, and the output terminal generates a switch control signal KEY5 via the eleventh inverter INV11_6.

[0100] The seventh switch decoding structure 1221 includes: a seventh NAND gate NAND7_7 and an eleventh inverter INV11_7; the first input terminal of the seventh NAND gate NAND7_7 is connected to signal Q1N, the second input terminal is connected to signal Q2, the third input terminal is connected to signal Q3, the fourth input terminal is connected to signal Q4N, and the output terminal generates a switch control signal KEY6 via the eleventh inverter INV11_7.

[0101] The eighth switch decoding structure 1221 includes: a seventh NAND gate NAND7_8 and an eleventh inverter INV11_8; the first input terminal of the seventh NAND gate NAND7_8 is connected to signal Q1, the second input terminal is connected to signal Q2, the third input terminal is connected to signal Q3, the fourth input terminal is connected to signal Q4N, and the output terminal generates a switch control signal KEY7 via the eleventh inverter INV11_8.

[0102] The ninth switch decoding structure 1221 includes: a seventh NAND gate NAND7_9 and an eleventh inverter INV11_9; the first input terminal of the seventh NAND gate NAND7_9 is connected to signal Q1N, the second input terminal is connected to signal Q2N, the third input terminal is connected to signal Q3N, the fourth input terminal is connected to signal Q4, and the output terminal generates a switch control signal KEY8 via the eleventh inverter INV11_9.

[0103] The tenth switch decoding structure 1221 includes: a seventh NAND gate NAND7_10 and an eleventh inverter INV11_10; the first input terminal of the seventh NAND gate NAND7_10 is connected to signal Q1, the second input terminal is connected to signal Q2N, the third input terminal is connected to signal Q3N, the fourth input terminal is connected to signal Q4, and the output terminal generates a switch control signal KEY9 via the eleventh inverter INV11_10.

[0104] The eleventh switch decoding structure 1221 includes: a seventh NAND gate NAND7_11 and an eleventh inverter INV11_11; the first input terminal of the seventh NAND gate NAND7_11 is connected to signal Q1N, the second input terminal is connected to signal Q2, the third input terminal is connected to signal Q3N, the fourth input terminal is connected to signal Q4, and the output terminal generates a switch control signal KEY10 via the eleventh inverter INV11_11.

[0105] The twelfth switch decoding structure 1221 includes: a seventh NAND gate NAND7_12 and an eleventh inverter INV11_12; the first input terminal of the seventh NAND gate NAND7_12 is connected to signal Q1, the second input terminal is connected to signal Q2, the third input terminal is connected to signal Q3N, the fourth input terminal is connected to signal Q4, and the output terminal generates a switch control signal KEY11 via the eleventh inverter INV11_12.

[0106] The thirteenth switch decoding structure 1221 includes: a seventh NAND gate NAND7_13 and an eleventh inverter INV11_13; the first input terminal of the seventh NAND gate NAND7_13 is connected to signal Q1N, the second input terminal is connected to signal Q2N, the third input terminal is connected to signal Q3, the fourth input terminal is connected to signal Q4, and the output terminal generates a switch control signal KEY12 via the eleventh inverter INV11_13.

[0107] The fourteenth switch decoding structure 1221 includes: a seventh NAND gate NAND7_14 and an eleventh inverter INV11_14; the first input terminal of the seventh NAND gate NAND7_14 is connected to signal Q1, the second input terminal is connected to signal Q2N, the third input terminal is connected to signal Q3, the fourth input terminal is connected to signal Q4, and the output terminal generates a switch control signal KEY13 via the eleventh inverter INV11_14.

[0108] The fifteenth switch decoding structure 1221 includes: a seventh NAND gate NAND7_15 and an eleventh inverter INV11_15; the first input terminal of the seventh NAND gate NAND7_15 is connected to signal Q1N, the second input terminal is connected to signal Q2, the third input terminal is connected to signal Q3, the fourth input terminal is connected to signal Q4, and the output terminal generates a switch control signal KEY14 via the eleventh inverter INV11_15.

[0109] The sixteenth switch decoding structure 1221 includes: a seventh NAND gate NAND7_16 and an eleventh inverter INV11_16; the first input terminal of the seventh NAND gate NAND7_16 is connected to signal Q1, the second input terminal is connected to signal Q2, the third input terminal is connected to signal Q3, the fourth input terminal is connected to signal Q4, and the output terminal generates a switch control signal KEY15 via the eleventh inverter INV11_16.

[0110] In this example, the sixteen-group switch decoding structure 1221 implements sixteen-level decoding. By arranging and combining four groups of complementary signals (such as Q1 and Q1N-Q4 and Q4N), 16 switch control signals KEY0-KEY15 are generated. In this way, after each pulse, one of the 16 switch control signals KEY0-KEY15 will become high, thereby turning on the corresponding switch in the subsequent reference voltage regulation module 200, so that the reference voltage VREF corresponds to the selected voltage.

[0111] The reference voltage regulation module 200 is connected to the output terminal of the pulse control module 100. It is used to select the resistor voltage division ratio according to M switch control signals (such as KEY0-KEY15), and to divide the bandgap voltage VBGR according to the selected resistor voltage division ratio to generate the reference voltage VREF output.

[0112] Specifically, such as Figure 8 As shown, the reference voltage regulation module 200 includes: a voltage generator 210, M switches, and at least (M+1) fourth resistors; the voltage generator 210 is controlled by a power-on start signal SYSOK_H and a working enable signal CE_H to generate a bandgap voltage VBGR; the (M+1) fourth resistors are connected in series between the output terminal of the voltage generator 210 and ground to form M connection nodes; the first terminals of the M switches are connected to the M connection nodes, the second terminals are connected to each other to generate a reference voltage VREF, and the control terminals are connected to the control signals of the M switches.

[0113] With N=4 and M=2 4 For example, the reference voltage regulation module 200 in this example includes: a voltage generator 210, 16 switches S1_1-S1_16 and 18 fourth resistors R4_1-R4_18, wherein the 16 switches S1_1-S1_16 are controlled by 16 switch control signals KEY0-KEY15.

[0114] In this example, the voltage generator 210 is a bandgap reference circuit with load-carrying capability, which can be implemented using existing known circuit structures. It generates a bandgap voltage VBGR output when both the power-on start signal SYSOK_H and the operation enable signal CE_H are high. Through appropriate resistor voltage division, the bandgap voltage VBGR can be divided into the desired voltage values, such as 1.2V, 1.15V, 1.1V, 1.05V, 1V, 0.95V, 0.9V, 0.86V, 0.82V, 0.78V, 0.74V, 0.7V, 0.65V, 0.6V, 0.55V, and 0.5V. Then, by selecting any one of the 16 switch control signals KEY0-KEY15, the reference voltage VREF is made equal to the selected voltage.

[0115] Please refer to the following: Figures 4-8See Figure 9 and Figure 10 The operation of the pulse voltage regulation circuit in this embodiment will be explained; wherein, N=4 and M=2 4 =16. For example, the period of the pulse signal is no more than 1ms, the high-dimensional setting value is 1ms, and the low-dimensional setting value is 3ms.

[0116] The pulse voltage regulation circuit in this embodiment uses 16 pulse signals as one cycle. Internally, a four-bit counter counts the falling edge of each pulse signal to achieve dynamic adjustment of the output voltage VOUT. Specifically, as follows... Figure 9 and Figure 10 As shown.

[0117] Depend on Figure 10 As can be seen, the first high-level input triggers the voltage regulation circuit and sets the output voltage VOUT to 5V. As the number of input pulse signals increases, the output voltage VOUT gradually rises. After the output voltage VOUT is configured, the input must remain high for at least 1ms (generally 2ms) to lock the output; specifically as follows:

[0118] When the input transitions to a high level, the circuit starts, and the output voltage VOUT is initially 5V. On the first falling edge, the switch control signal KEY1 goes high, making the output voltage VOUT 5.5V. On the second falling edge, the switch control signal KEY2 goes high, making the output voltage VOUT 6V. On the third falling edge, the switch control signal KEY3 goes high, making the output voltage VOUT 6.5V, and so on. On the fifteenth falling edge, the switch control signal KEY15 goes high, making the output voltage VOUT 12V. If the input remains high for more than 1ms, the output voltage VOUT is locked. If the input transitions from high to low, the number of pulse signals is considered 1, and the output voltage VOUT will return to 5.5V from the locked voltage. If the input remains low for more than 3ms, the output voltage function is disabled, and the output voltage VOUT is 0V.

[0119] If the required output voltage VOUT is 9V, the output will be locked after the circuit is powered on by providing 9 falling edges and maintaining a high level for more than 1ms. If you want to change from 9V to 12V, the output will be locked after providing 15 falling edges and maintaining a high level for more than 1ms. If you want to restart the circuit to 12V, the output will be locked after providing a low level for more than 3ms to clear the entire circuit, and then providing 15 falling edges and maintaining a high level for more than 1ms.

[0120] Example 2

[0121] like Figure 11 As shown, this embodiment provides a DC-DC chip, which includes a pulse voltage regulation circuit 10 and an error amplifier circuit 20 as described in Embodiment 1; wherein, the first input terminal of the error amplifier circuit 20 is connected to the output terminal of the pulse voltage regulation circuit 10 to be connected to the reference voltage VREF, the second input terminal is connected to the feedback voltage VFB, and the output terminal generates an error voltage VCOMP.

[0122] Furthermore, the DC-DC chip also includes a PWM modulation circuit and a power switch (not shown in the figure), used to perform PWM modulation on the power switch according to the error voltage VCOMP. The PWM modulation circuit can employ existing circuit structures to implement known PWM modulation methods.

[0123] In this embodiment, the error amplifier circuit 20 is implemented using an error amplifier. The non-inverting input of the error amplifier is connected to the reference voltage VREF, and the inverting input is connected to the feedback voltage VFB. The feedback voltage VFB is obtained by dividing the output voltage VOUT by the fifth resistor R5 and the sixth resistor R6.

[0124] In practical applications, any port of the DC-DC chip can be used as the input port of the pulse voltage regulation circuit 10. For example, the enable port (EN port) of the DC-DC chip can be used as the input port of the pulse voltage regulation circuit 10.

[0125] In summary, the pulse voltage regulation circuit and DC-DC chip of this invention, based on the design of a pulse control module and a reference voltage regulation module, selects the magnitude of the reference voltage by controlling the number of continuously input pulse signals, thereby achieving different reference voltage outputs and thus realizing adjustable output voltage. The circuit structure of this invention is simple and can be implemented using ordinary MOS devices. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0126] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A pulse voltage regulating circuit, characterized by comprising: The pulse voltage regulation circuit comprises a pulse control module and a reference voltage regulation module. The pulse control module is configured to generate a group of M switch control signals according to the number of continuously input pulse signals. The reference voltage regulation module is connected to the output of the pulse control module, configured to select a resistance voltage division ratio according to the M switch control signals, and generate a reference voltage output by dividing the bandgap voltage according to the selected resistance voltage division ratio. where M = 2 N N is an integer greater than or equal to 1.

2. The pulse regulation circuit of claim 1, wherein, The pulse control module comprises a count control unit and a switch generation unit. The count control unit is configured to count the number of continuously input pulse signals to generate an N-bit count result, and generate a lock signal when the high level maintenance time of the pulse signal is greater than a high level setting value, and clear the N-bit count result when the low level maintenance time of the pulse signal is greater than a low level setting value. The switch generation unit is connected to the output of the count control unit, configured to generate the M switch control signals according to the N-bit count result, and switch lock according to the lock signal.

3. The pulse regulation circuit of claim 2, wherein, The count control unit comprises a pulse input part, a first control part, a second control part and a count generation part. The pulse input part is configured to input the pulse signal. The first control part is connected to the output of the pulse input part, configured to generate a work enable signal according to the pulse signal after power-on, and generate a clear signal when the low level maintenance time of the pulse signal is greater than a low level setting value. The second control part is connected to the output of the pulse input part, configured to generate a count clock at the falling edge of the pulse signal, and generate the lock signal when the high level maintenance time of the pulse signal is greater than a high level setting value. The count generation part is connected to the outputs of the first control part and the second control part, configured to count the number of pulses to generate the N-bit count result according to the count clock when the work enable signal is valid, and clear the N-bit count result when the lock signal or the clear signal is valid.

4. The pulse regulation circuit of claim 3, wherein, The pulse input part comprises a first NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first resistor, a second resistor, a first inverter and a second inverter; the gate of the first NMOS transistor is connected to the gate of the first PMOS transistor and the pulse signal, the source is grounded, and the drain is connected to the drain of the first PMOS transistor and the input of the first inverter; the source of the first PMOS transistor is connected to the power voltage via the first resistor and the second resistor; the output of the first inverter is connected to the gate of the second PMOS transistor and the input of the second inverter; the source of the second PMOS transistor is connected to the power voltage, and the drain is connected to the connection node of the first resistor and the second resistor; the output of the second inverter serves as the output of the pulse input part.

5. The pulse regulation circuit of claim 3, wherein, The first control part comprises a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a third inverter and a clear delay timer; the first input end of the first NAND gate is connected with the output end of the pulse input part, the second input end is connected with the output end of the second NAND gate, and the output end is connected with the first input end of the second NAND gate and the first input end of the third NAND gate; the second input end of the second NAND gate is connected with the power-on start signal; the second input end of the third NAND gate is connected with the output end of the pulse input part through the clear delay timer and the third inverter, the third input end is connected with the output end of the fourth NAND gate, and the output end is connected with the first input end of the fourth NAND gate; the second input end of the fourth NAND gate is connected with the output end of the pulse input part, and the output end generates the work enable signal; wherein the clear delay timer is used for delaying the low setting value at the pulse falling edge to generate the clear signal.

6. The pulse regulation circuit of claim 3, wherein, The second control part comprises a fourth inverter, a fifth inverter, a first delay timer and a lock delay timer; the input end of the fourth inverter is connected with the output end of the pulse input part, and the output end is connected with the input end of the first delay timer and the lock delay timer; the output end of the first delay timer is connected with the input end of the fifth inverter; the output end of the fifth inverter generates the count clock; the output end of the lock delay timer generates the lock signal; wherein the lock delay timer is used for delaying the high setting value at the pulse rising edge to generate the lock signal.

7. The pulse regulation circuit of claim 3, wherein, The count generation part comprises a fifth NAND gate, a sixth NAND gate, a second delay timer, a third delay timer, a sixth inverter, a seventh inverter, an eighth inverter and an N-bit counter; the first input end of the fifth NAND gate is connected with the power-on start signal, the second input end is connected with the clear signal, the third input end is connected with the work enable signal through the second delay timer, and the output end is connected with the first input end of the sixth NAND gate through the sixth inverter; the second input end of the sixth NAND gate is connected with the lock signal through the seventh inverter and the third delay timer, and the output end is connected with the set end of the N-bit counter through the eighth inverter; the clock end of the N-bit counter is connected with the count clock, and the output end generates the N-bit count result.

8. The pulse regulation circuit according to any one of claims 3 to 7, characterized in that The count control unit further comprises a jitter elimination part connected between the pulse input part and the second control part, for performing signal jitter elimination; wherein the jitter elimination part comprises a ninth inverter, a second NMOS transistor, a third PMOS transistor, a third resistor, a first capacitor and a Schmitt trigger; the input end of the ninth inverter is connected to the output end of the pulse input part, and the output end is connected to the gate of the second NMOS transistor and the third PMOS transistor; the source of the second NMOS transistor is grounded, and the drain is connected to the drain of the third PMOS transistor and the first end of the third resistor; the source of the third PMOS transistor is connected to a power supply voltage; the second end of the third resistor is grounded through the first capacitor and connected to the input end of the Schmitt trigger; the output end of the Schmitt trigger is connected to the input end of the second control part; At this time, the second control part is replaced by a fifth inverter, a first delay and a lock delay; the input end of the first delay is connected to the output end of the jitter elimination part, and the output end is connected to the input end of the fifth inverter; the output end of the fifth inverter generates the count clock; the input end of the lock delay is connected to the output end of the jitter elimination part, and the output end generates the lock signal; wherein the lock delay is used to delay the high set value at the pulse rising edge to generate the lock signal.

9. The pulse regulation circuit of claim 2, wherein, The switch generation unit comprises a complementary signal part and a switch decoding part; The complementary signal part is connected to the output end of the count control unit, for generating N groups of complementary signals according to the N-bit count result, and performing output locking when the lock signal is valid; The switch decoding part is connected to the output end of the complementary signal part, for generating the M switch control signals according to the N groups of complementary signals.

10. The pulse regulation circuit of claim 9, wherein, The complementary signal part comprises N groups of signal latch structures, wherein the N groups of signal latch structures are the same and comprise a latch and a tenth inverter; the set end of the latch is connected to the lock signal, the input end is connected to one bit of the N-bit count result, and the output end generates one group of complementary signals through the tenth inverter.

11. The pulse regulation circuit of claim 9, wherein, The switch decoding part comprises M groups of switch decoding structures, wherein the M groups of switch decoding structures are the same and comprise a seventh NAND gate and an eleventh inverter; the N input ends of the seventh NAND gate are respectively connected to one of each group of complementary signals, and the output end generates one switch control signal through the eleventh inverter.

12. The pulse regulation circuit of claim 5, wherein, The reference voltage regulation module comprises a voltage generator, M switches and at least M+1 fourth resistors; the voltage generator generates the bandgap voltage under the control of a power-on start signal and a working enable signal; M+1 fourth resistors are connected in series between the output end of the voltage generator and the ground and form M connection nodes; the first ends of the M switches are connected to the M connection nodes, the second ends are connected to each other to generate the reference voltage, and the control ends are connected to the M switch control signals.

13. A DC-DC chip, characterized by, The DC-DC chip comprises the pulse voltage regulating circuit and the error amplifier circuit as claimed in any one of claims 1-12; the first input end of the error amplifier circuit is connected with the output end of the pulse voltage regulating circuit to connect the reference voltage, the second input end is connected with the feedback voltage, and the output end generates the error voltage.

Images