Latch device and method of operating the same

Abstract

A latch device includes a differential pair, a differential circuit, and a clock gate circuit. The differential pair receives a differential input signal, and the differential circuit performs a logical operation on the differential input signal. The clock gate circuit is configured to supply a supply voltage from a power supply node to a first connection node according to a clock signal. The clock gate circuit includes an independent reference circuit and a dependent reference circuit. The independent reference circuit is configured to control a first power path between the power supply node and the first connection node according to the clock signal. The dependent reference circuit is configured to control a second power path between the power supply node and the first connection node according to the clock signal and a first control signal, where the first control signal is determined according to a voltage level of one of the differential input signals.

Description

Technical Field

[0001] This disclosure relates to a latch device, and more particularly to an operating method and latch device that operate over a relatively wide common-mode range of differential input signals. Background Technology

[0002] Latch devices (e.g., differential cascode voltage switch (DCVS) latches) are commonly used in systems due to their high speed, low power consumption, and noise immunity. In some systems, the common-mode input voltage supplied to the DCVS latch can be adjusted within a relatively wide percentage range of the supply voltage, resulting in a relatively wide variation in the voltage margin between the source and gate of the differential pair transistors available in the DCVS latch. This relatively wide voltage margin, resulting from the relatively wide common-mode input voltage range, can cause numerous problems related to the overall size, power consumption, and performance of the DCVS latch.

[0003] Because latch devices in different systems can operate within different common-mode input voltage ranges, it is expected that latch devices can operate over a relatively wide common-mode input voltage range. The content herein should not be construed as an admission of prior art knowledge in any part of this disclosure. Summary of the Invention

[0004] This disclosure describes an operating method and latch device that can reliably operate over a relatively wide common-mode range of differential input signals.

[0005] In some embodiments, the latch device includes a differential pair, a differential circuit, and a clock gate. The differential pair is configured to receive differential input signals. The differential circuit includes a pair of cross-coupled inverters and is configured to perform a logic operation on the differential input signals. The clock gate is coupled between a power supply node and a first connection node and is configured to provide a supply voltage from the power supply node to the first connection node according to a clock signal. The clock gate includes an independent reference circuit and a dependent reference circuit, wherein the independent reference circuit is configured to control a first power path between the power supply node and the first connection node according to the clock signal. The dependent reference circuit is configured to control a second power path between the power supply node and the first connection node according to the clock signal and a first control signal, wherein the first control signal is determined based on the voltage level of one of the differential input signals.

[0006] In some embodiments, the latch device includes a differential pair, a differential circuit, and an offset cancellation circuit unit. The differential pair is configured to receive a differential input signal. The differential circuit includes a pair of cross-coupled inverters and is configured to perform a logic operation on the differential input signal. The offset cancellation circuit unit includes at least one first offset cancellation circuit and at least one second offset cancellation circuit. The at least one first offset cancellation circuit is coupled between a first connection node and a second connection node, and the at least one second offset cancellation circuit is coupled between the first connection node and a third connection node. Each of the at least one first offset cancellation circuit and the at least one second offset cancellation circuit includes an independent reference circuit and a dependent reference circuit. The independent reference circuit is configured to control a first power path between the first connection node and one of the second and third connection nodes according to an offset control bit. The dependent reference circuit is configured to control a second power path between the first connection node and one of the second and third connection nodes according to the offset control bit and a first control signal, wherein the first control signal is determined based on the voltage level of one of the differential input signals.

[0007] In some embodiments, the operation of the latch device includes the following steps: receiving a differential input signal by a differential pair of the latch device; controlling a first power path between a power supply node and a first connection node according to a clock signal by a first independent reference circuit included in the clock gate circuit of the latch device; and controlling a second power path between the power supply node and the first connection node according to the clock signal and a first control signal by a first dependent reference circuit included in the clock gate circuit of the latch device, wherein the first control signal is determined based on the voltage level of one of the differential input signals.

[0008] According to embodiments of this disclosure, since each of the clock gate circuit and the offset cancellation circuit unit may include an independent reference circuit and a dependent reference circuit, the effective conduction width of the clock gate circuit and the offset cancellation circuit unit can be adjusted according to the voltage level of at least one of the differential input signals INP and INN. In this way, the latch device 100 can operate over a wide common-mode range of the differential input signals. Attached Figure Description

[0009] Figure 1 This illustration shows a latch device according to some embodiments;

[0010] Figure 2 A schematic diagram illustrating the clock gate circuit of a latch device according to some embodiments;

[0011] Figure 3A schematic diagram illustrating the differential pair and offset cancellation circuit unit of a latch device according to some embodiments;

[0012] Figure 4 A flowchart illustrating the operation method of a latch device according to some embodiments.

[0013] [Explanation of Symbols]

[0014] 100: Latch device

[0015] 110: Clock gate circuit

[0016] 112: Independent Reference Circuit

[0017] 114, 1232: Dependent Reference Circuits

[0018] 120: Offset Cancellation (OC) Circuit Unit / Offset Cancellation Circuit

[0019] 121, 122, MN1, MN3, MN4, MN5, MN6, MN7, MP1, MP2, T1, T2, T3, T4, T5, T21, T22, T23, T2 4. T25, T41, T42, T43, T44, T45, T51, T52, T53, T54, T55, T61, T62, T63, T64, T65: transistor

[0020] 123, 124: OC circuit / dependent reference circuit

[0021] 125, 126: OC circuits

[0022] 130: Differential circuit

[0023] 140: Reset Circuit

[0024] 150: Difference pairs

[0025] 410, 420, 430: Boxes

[0026] 1231: Independent Reference Circuit

[0027] CKF: Clock signal

[0028] GND: Grounding node

[0029] INN: Differential Input Signal / Reference Signal

[0030] INP: Differential Input Signal

[0031] N0: Power supply node

[0032] N1, N2, N3, N4, N5: Connection nodes

[0033] S1, S2, S3, S4: Control signals

[0034] SL <0> SL <1> Offset control bit

[0035] OUT, OUTF: Output signals

[0036] VDD: Power supply voltage Detailed Implementation

[0037] Examples of the present disclosure will now be described in detail with reference to preferred embodiments thereof, with the accompanying drawings. The same reference numerals are used as far as possible in the drawings and description to refer to the same or similar parts.

[0038] Figure 1 This illustration shows a latch device 100 according to some embodiments. The latch device 100 may include a clock gate circuit 110, an offset cancellation (OC) circuit unit 120, a differential circuit 130, a reset circuit 140, and a differential pair 150. Furthermore, the latch device 100 may include a power supply node N0 and a plurality of connection nodes N1 to N5. The power supply node N0 receives a power supply voltage VDD; connection nodes N1 are coupled to the clock gate circuit 110, the OC circuit unit 120, and the differential pair 150; connection nodes N2 and N3 are coupled to the OC circuit unit 120, the differential pair 150, and the differential circuit 130. In some embodiments, the differential pair 150 includes transistors 121 and 122, wherein the control terminals of transistors 121 and 122 receive input signals INP and INN, respectively. Note that this disclosure is not intended to limit the types of input signals INP and INN. For example, in an embodiment, the input signals INP and INN are differential input signals. In an alternative embodiment, one of the input signals INP or INN is a differential input signal, and the other of the input signals INP or INN is a reference signal. For simplicity, regardless of the types of input signals INP and INN, the input signal INN will be referred to as the reference signal. It should be noted that various modifications and changes can be made within the scope of this disclosure. For example, this disclosure is not limited to the case where VDD is the power supply for clock gate 110. The overall structure of latch device 100 can be reversed, where the connection to VDD becomes a connection to GND, and vice versa. If the circuit is reversed, the control polarity will also be reversed.

[0039] Clock gate circuit 110 may include independent reference circuit 112 and dependent reference circuit 124. Independent reference circuit 112 and dependent reference circuit 124 are configured to control the formation of power paths between power supply node N0 and connection node N1 to achieve the conductivity width of clock gate circuit 110. When there are more power paths formed between power supply node N0 and connection node N1, the effective conductivity width of clock gate circuit 110 increases; and when there are fewer power paths formed between power supply node N0 and connection node N1, the effective conductivity width of clock gate circuit 110 decreases. In some embodiments, independent reference circuit 112 is configured to control the formation of power paths between power supply node N0 and connection node N1 independently of the voltage level of reference signal INN; and dependent reference circuit 114 is configured to control the formation of power paths between power supply node N0 and connection node N1 based on the voltage level of reference signal INN. For example, the independent reference circuit 112 can control the formation of the power path between the power supply node N0 and the connection node N1 based on a clock signal CKF, which is independent of the voltage level of the reference signal INN. The dependent reference circuit 114 can control the formation of the power path between the power supply node N0 and the connection node N1 based on both the clock signal CKF and a control signal, wherein the value of the control signal is determined according to the voltage level of the reference signal INN. Figure 2 The detailed structure of clock gate circuit 110 according to some embodiments is described below.

[0040] refer to Figure 2 Independent reference circuit 112 includes transistor T1 coupled between power supply node N0 and connection node N1, wherein transistor T1 is controlled by clock signal CKF. Dependent reference circuit 114 includes transistors T2 and T3, which are coupled in series between power supply node N0 and connection node N1. Transistor T2 is controlled by clock signal CKF and control signal S1. In some embodiments, clock signal CKF is independent of the voltage level of reference signal INN, and control signal S1 depends on the voltage level of reference signal INN. In this way, dependent reference circuit 114 can control the formation of the power path between power supply node N0 and connection node N1 based on the voltage level of reference signal INN.

[0041] The dependent reference circuit 114 may further include transistors T4 and T5, which are series-coupled between power supply node N0 and connection node N1. Transistor T4 is controlled by a clock signal CKF, and transistor T5 is controlled by a control signal S2, which is determined based on the voltage level of reference signal INN. Since control signals S1 and S2 are determined based on the voltage level of reference signal INN, the dependent reference circuit 114 can control the formation of the power path between power supply node N0 and connection node N1 based on the voltage level of reference signal INN. Note that this disclosure is not intended to limit the number of power paths or the number of transistors included in the dependent reference circuit 114.

[0042] In some embodiments, the values ​​of control signals S1 and S2 are determined based on a comparison of the voltage level of the reference signal INN with a threshold. For example, the value of control signal S1 can be determined by comparing the voltage level of the reference signal INN with a first threshold. When the voltage level of the reference signal INN is higher than the first threshold, control signal S1 can be set to a first logic state (i.e., logic state "0"); and when the voltage level of the reference signal INN is lower than the first threshold, control signal S1 can be set to a second logic state (i.e., logic state "1"). The logic value of control signal S2 can be determined by comparing the voltage level of the reference signal INN with a second threshold, where the second threshold is greater than the first threshold. When the voltage level of the reference signal INN is higher than the second threshold, control signal S2 can be set to a first logic state (i.e., logic state "0"); and when the voltage level of the reference signal INN is lower than the second threshold, control signal S2 is in a second logic state (i.e., logic state "1").

[0043] In some embodiments, the voltage margin (i.e., gate-source voltage) of transistors 121 and 122 in differential pair 150 is inversely proportional to the voltage levels of input signals INP and INN. For example, when the voltage level of reference signal INN is low, the voltage margin of differential pair 150 is high, and vice versa. In some embodiments, when the voltage level of reference signal INN is relatively low and the voltage margin of the transistors in the differential pair is relatively high, clock gate circuit 110 uses control signals S1 and S2 to control dependent reference circuit 114 to form fewer power paths between power supply node N0 and connection node N1. For example, when the voltage level of reference signal INN is below a first threshold voltage, both control signals S1 and S2 are in logic state "1", and dependent reference circuit 114 does not form a power path between power supply node N0 and connection node N1. In another example, when the voltage level of the reference signal INN is higher than a first threshold but lower than a second threshold, control signal S1 has a logic state "0" and control signal S2 has a logic state "1", and the dependent reference circuit 114 forms a power path between power supply node N0 and connection node N1 via transistors T2 and T3. Thus, when the voltage level of the reference signal INN is relatively low, the effective conduction width of the clock gate circuit 110 decreases, the power supplied to the latch device 100 decreases, and the latch device 100 is not over-powered. Furthermore, when the clock gate circuit 110 controls the dependent reference circuit 114 to form fewer power paths between power supply node N0 and connection node N1, the dependent reference offset decreases. When the differential pair 150 has a relatively high voltage margin and is over-powered by the clock gate circuit 110, it will cause a dependent reference offset.

[0044] When the voltage level of the reference signal INN is relatively high and the voltage margin of the differential pair is relatively low, the clock gate circuit 110 uses control signals S1 and S2 to control the dependent reference circuit 114 to form more power paths between the power supply node N0 and the connection node N1. For example, when the voltage level of the reference signal INN is higher than both the first threshold and the second threshold, both control signals S1 and S2 are in the logic state "0", and the dependent reference circuit 114 forms power paths between the power supply node N0 and the connection node N1 via transistors T2 and T3 and transistors T4 and T5. Thus, the effective conduction width of the clock gate circuit 110 is increased, and more power is supplied to the latch device 100 to offset the loss of voltage margin. Therefore, the latch device 100 can operate reliably over a relatively wide common-mode range of the input signal, and the performance of the latch device 100 is improved.

[0045] It should be understood that this disclosure is not intended to limit the number of transistors, the number of control signals, the number of power paths, or the type of transistors in clock gate 110. The first and second thresholds may be predetermined values ​​pre-stored in a register, which may be included in or located outside the latch device 100. Additionally, control signals S1 and S2 may be generated by a controller (not shown) located inside or outside the latch device 100.

[0046] return Figure 1 In some embodiments, the OC circuit unit 120 may include left OC circuits 123 and 125 and right OC circuits 124 and 126, wherein the left OC circuits 123 and 125 are coupled between a first connection node N1 and a second connection node N2, and the right OC circuits 124 and 126 are coupled between a first connection node N1 and a third connection node N3. In some embodiments, the OC circuit unit 120 is coupled to the differential pair 150 and configured to eliminate offsets caused by the differential pair 150. These offsets may be caused by various factors, such as mismatches between transistors 121 and 122, mismatches in electronic components included in the latch device 100, or variations during the manufacture of the differential pair 150. The OC circuit unit 120 may selectively control the left OC circuits 123 and 125 and the right OC circuits 124 and 126 to eliminate offsets.

[0047] In some embodiments, each of the left-side OC circuits 123 and 125 and the right-side OC circuits 124 and 126 includes an independent reference circuit and a dependent reference circuit. The independent reference circuit can operate independently of the voltage level of the reference signal INN, while the operation of the dependent reference circuit is determined according to the voltage level of the reference signal INN. For example, OC circuit 123 includes an independent reference circuit 1231 and a dependent reference circuit 1232, wherein the independent reference circuit 1231 operates independently of the voltage level of the reference signal INN and the operation of the dependent reference circuit 1232 is determined according to the voltage level of the reference signal INN. Figure 3 The detailed structure of the OC circuit unit 120 according to some embodiments is described below.

[0048] refer to Figure 3The independent reference circuit 1231 may include a transistor T21, which is coupled between connection node N1 and connection node N2 and controlled by an offset control bit SL. <0> Control, where the offset control bit SL <0> The voltage level is independent of the reference signal INN. The dependent reference circuit 1232 may include transistors T22 and T23, which are series-coupled between connection node N1 and connection node N2. Transistor T22 is controlled by offset bit SL. <0> Control; and transistor T23 is controlled by control signal S3, which is determined according to the voltage level of reference signal INN. The dependent reference circuit 1232 can form a power path between connection node N1 and connection node N2 based on clock signal CKF and control signal S1.

[0049] The dependent reference circuit 1232 may further include transistors T24 and T25, which are series-coupled between connection node N1 and connection node N2. Transistor T24 is controlled by offset control bit SL. <0> The transistor T25 is controlled by a control signal S4, which is determined by the voltage level of the reference signal INN. In this way, the dependent reference circuit 1232 can be based on the offset control bit SL. <0> Control signals S3 and S4 control the formation of the power path between power supply node N0 and connection node N1. This disclosure is not intended to limit the number of power paths or the number of transistors included in the dependent reference circuit 1232 of the OC circuit 123.

[0050] OC circuits 124, 125, and 126 may have a circuit structure similar to that of OC circuit 123; therefore, detailed descriptions of the circuit structures of OC circuits 124, 125, and 126 will be omitted below. The difference between OC circuit 123 and OC circuits 124, 125, and 126 lies in the control signals, which are set to the control terminals of the transistors in each of the OC circuits. In OC circuit 125, transistors T51, T52, and T54 are controlled by the offset control bit SL. <1> Control; and transistors T53 and T55 of OC circuit 125 are controlled by control signals S3 and S4 respectively. In OC circuit 124, transistors T41, T42, and T44 of OC circuit 125 are controlled by offset control bit SR. <0> Control; and transistors T43 and T45 of OC circuit 124 are controlled by control signals S3 and S4 respectively. In OC circuit 126, transistors T61, T62, and T64 are controlled by offset control bit SR. <1> Control; and transistors T63 and T65 of the OC circuit 126 are controlled by control signals S3 and S4, respectively. In some embodiments, the offset control bit SL <0> and SL <1> These are two bits in a digital signal whose voltage level is independent of the reference signal INN; and the offset control bit SR <0> and SR <1> These are two bits in a digital signal whose voltage level is independent of the reference signal INN. The OC circuits 123, 124, and 125 may also differ in the size of the transistors chosen to achieve the electrical connection. For example, the transistor in OC circuit 123 may have the same size as the transistor in OC circuit 124; and the transistor in OC circuit 125 may have the same size as the transistor in OC circuit 126. The sizes of the transistors in OC circuits 123 and 124 may differ from the sizes of the transistors in OC circuits 125 and 126. The transistor sizes can be set using binary weighting, equal weighting, or any other weighting method between OC circuits 123, 124 and OC circuits 125, 126.

[0051] In some embodiments, the values ​​of control signals S3 and S4 are determined by comparing the voltage level of the reference signal INN with a threshold. For example, the value of control signal S3 is determined by comparing the voltage level of the reference signal INN with a third threshold. When the voltage level of the reference signal INN is lower than the third threshold, control signal S3 can be set to a first logic state (i.e., logic state "0"); and when the voltage level of the reference signal INN is higher than the third threshold, control signal S3 is set to a second logic state (i.e., logic state "1"). Similarly, the logic value of control signal S4 is determined by comparing the voltage level of the reference signal INN with a fourth threshold, which is higher than the third threshold. When the voltage level of the reference signal INN is lower than the fourth threshold, control signal S4 can be set to a first logic state (i.e., logic state "0"); and when the voltage level of the reference signal INN is higher than the fourth threshold, control signal S4 is set to a second logic state (i.e., logic state "1"). In some embodiments, the third threshold is the same as the first threshold and the second threshold is the same as the fourth threshold, but this disclosure is not limited thereto. In these embodiments, control signals S3 and S4 are the inverted signals of control signals S1 and S2, respectively.

[0052] In some embodiments, when the voltage level of the reference signal INN is relatively low and the voltage margin of the transistors in the differential pair is relatively high, the OC circuit unit 120 uses control signals S3 and S4 to control the dependent reference circuit 1232 to form more power paths between connection node N1 and connection node N2. For example, when the voltage level of the reference signal INN is below a third threshold voltage, both control signals S3 and S4 are in the logic state "0", and the dependent reference circuit 1232 forms power paths between connection node N1 and connection node N2 via transistors T22 and T23 and transistors T24 and T25. Therefore, the effective conduction width of the OC circuit 123 is increased, and the OC circuit unit 120 can reliably perform offset cancellation operation when the voltage level of the reference signal INN is relatively low.

[0053] When the voltage level of the reference signal INN is relatively high and the voltage margin of the differential pair is relatively low, the OC circuit unit 120 uses control signals S3 and S4 to control the dependent reference circuit 1232 to form fewer power paths between connection nodes N1 and N2. For example, when the voltage level of the reference signal INN is higher than both the third threshold voltage and the fourth threshold voltage, both control signals S3 and S4 are in logic state "1", and the dependent reference circuit 1232 does not form a power path between connection nodes N1 and N2. Thus, when the voltage level of the reference signal INN is relatively high, due to the loss of voltage margin, the effective conductivity width of the dependent reference circuit 1232 is reduced to correspond to the continuously decreasing conductivity of the differential pair 150. Therefore, the OC circuit unit 120 can operate well over a relatively wide common-mode range of the input signal.

[0054] It can be inferred that the operation of OC circuits 124, 125, and 126 is similar to that of OC circuit 123 described above; therefore, the operation of OC circuits 124, 125, and 126 will be omitted hereafter. It should be understood that this disclosure is not intended to limit the number of transistors, the number of control signals, the number of power paths, or the type of transistors in the OC circuit unit 120. Furthermore, control signals S3 and S4 can be generated by a controller (not shown) located inside or outside the latch device 100.

[0055] return Figure 1 The differential circuit 130 may include a cross-coupled inverter formed by transistors MP1, MP2, MN1, and MN2. Transistors MP1 and MP2 form one of the cross-coupled inverters, and transistors MP1 and MP2 form the other cross-coupled inverter. The differential circuit 130 may also include connection nodes N4 and N5, which serve as output terminals of the latch device 100. Connection node N4 is coupled between transistors MP1 and MN1, and connection node N5 is coupled between transistors MP2 and MN2.

[0056] In some embodiments, differential circuit 130 is coupled to differential pair 150 via connection nodes N2 and N3 to receive signals output from differential pair 150. Differential circuit 130 is configured to perform logical operations on the signals output from differential pair 150 to generate output signals OUT and OUTF at connection nodes N4 and N5, respectively. Output signals OUT and OUTF from connection nodes N4 and N5 are output signals of latch device 100. In some embodiments, when input signals INP and INN are differential signals, output signals OUT and OUTF are also differential signals. It should be understood that the types of input signals INP and INN and the types of output signals OUT and OUTF are not limited to this disclosure. Even Figure 1The text explains that transistors MP1 and MP2 are p-type transistors and Figure 1 The present disclosure describes transistors MN1 and MN2 as n-type transistors, but this disclosure is not intended to limit the types of transistors MP1, MP2, MN1 and MN2.

[0057] In some embodiments, the reset circuit 154 includes a plurality of transistors MN3 to MN7 coupled to connection nodes N2 to N5. The reset circuit 140 is configured to reset connection nodes N2 to N5 to a reference voltage level (i.e., ground level) in a preset phase of the latch device 100. Specifically, transistors MN3 and MN4 are coupled to connection nodes N2 and N3, respectively, and are configured to reset connection nodes N2 and N3 to the reference voltage level according to a clock signal CKF. Transistors MN6 and MN7 are coupled to connection nodes N4 and N5, respectively, and are configured to reset connection nodes N4 and N5 to the reference voltage level according to the clock signal CKF. Transistor MN5 is coupled between connection nodes N4 and N5 and is configured to electrically connect connection nodes N4 and N5 according to the clock signal CKF.

[0058] In some embodiments, the latch device 100 can operate in a preset phase and a set phase. During the preset phase, the clock signal CKF is in a high logic state (i.e., logic state "1"), and transistors MN3 to MN7 in the reset circuit 140 are turned on to reset the connection nodes N2 to N5 to a reference voltage level. Simultaneously, the clock gate circuit 110 is configured to electrically isolate the power supply node N0 from the connection node N1.

[0059] During the phase setting, with the clock signal CKF in a low logic state (i.e., logic state "0"), transistors MN3 to MN7 in the reset circuit 140 are turned off to isolate connection nodes N2 to N5 from the ground node GND. Simultaneously, clock gate circuit 110 is configured to electrically connect power supply node N0 to connection node N1. (Reference) Figure 1 and Figure 2Clock gate circuit 110 controls the formation of the power path between power supply node N0 and connection node N1 according to clock signal CKF and control signals S1 and S2. Since control signals S1 and S2 are determined based on the voltage level of reference signal INN, the effective conduction width of clock gate circuit 110 is adjusted according to the voltage level of reference signal INN. When input signals INP and INN are set to transistors 121 and 122 of differential pair 150, current can flow from power supply node N0 to connection node N1 and then through differential pair 150 to connection nodes N2 and N3. The difference between input signals INP and INN causes connection nodes N2 and N3 to charge at different rates. When the current difference at connection nodes N2 and N3 is sufficiently large, differential circuit 130 performs a latching operation to drive output signals OUT and OUTF to the output terminals of latch device 100.

[0060] Figure 4 Description of latch devices according to some embodiments (i.e., Figure 1 A flowchart illustrating the operation method of the latch device 100. (See reference...) Figure 1 , Figure 2 and Figure 4 In block 410, differential input signals INP and INN are received by the differential pair 150 of latch device 100. In block 420, the first independent reference circuit 112 of clock gate circuit 110 is configured to control the first power path between power supply node N0 and first connection node N1 according to clock signal CKF. In block 430, the dependent reference circuit 114 in clock gate circuit 110 is configured to control the power path between power supply node N0 and first connection node N1 according to clock signal CKF and a first control signal S1, wherein the first control signal S1 is determined based on the voltage level of one of the differential input signals.

[0061] In the above embodiments, since each of the clock gate circuit 110 and the offset cancellation circuit 120 includes an independent reference circuit and a dependent reference circuit, the effective conduction width of the clock gate circuit 110 and the offset cancellation circuit 120 can be adjusted according to the voltage level of at least one of the input signals INP or INN. In this way, the latch device 100 can operate over a relatively wide common-mode range of the input signals INP and INN. The input signals INP and INN can be differential input signals or may include a differential input signal and a reference signal. Therefore, the latch device 100 can be applied to a wide variety of applications. For example, the latch device 100 can be used in applications such as Double Data Rate (DDR) memory systems, where the common-mode voltage of the differential input signals can vary significantly. The latch device 100 can also be used as a single-ended receiver that receives a single-ended input signal and a reference signal as input signals. In some embodiments, the latch device 100 is a differential cascaded (cascode) voltage switch (DCVS) latch.

[0062] Although embodiments of the present disclosure have been described in detail, the present disclosure is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the present disclosure as disclosed in the claims.

Claims

1. A latching device, comprising: A differential pair receives differential input signals and is connected to the first connection node; A differential circuit includes a pair of cross-coupled inverters that perform logic operations on the differential input signals; as well as A clock gate circuit, coupled between the power supply node and the first connection node, supplies a supply voltage from the power supply node to the first connection node according to a clock signal, wherein the clock gate circuit includes: A first independent reference circuit controls a first power path between the power supply node and the first connection node according to the clock signal; as well as A first dependent reference circuit controls a second power path between the power supply node and the first connection node based on the clock signal and a first control signal, wherein the first control signal is determined based on the voltage level of one of the differential input signals. The first independent reference circuit and the first dependent reference circuit simultaneously provide the first power path and the second power path.

2. The latch device according to claim 1, wherein The first independent reference circuit includes a first transistor coupled between the power supply node and the first connection node, wherein the first transistor is controlled by the clock signal, and The first dependent reference circuit includes a second transistor and a third transistor, which are coupled in series between the power supply node and the first connection node, wherein the second transistor is controlled by the clock signal and the third transistor is controlled by the first control signal.

3. The latch device according to claim 2, wherein... The first dependent reference circuit is further configured to control a third power path between the power supply node and the first connection node according to the clock signal and a second control signal, wherein the second control signal is determined based on the voltage level of one of the differential input signals, and The first dependent reference circuit further includes a fourth transistor and a fifth transistor, which are coupled in series between the power supply node and the first connection node, wherein the fourth transistor is controlled by the clock signal and the fifth transistor is controlled by the second control signal.

4. The latch device according to claim 3, wherein The first control signal is configured to turn on the third transistor of the first dependent reference circuit when the voltage level of one of the differential input signals is higher than a first threshold. The second control signal is configured to turn on the fifth transistor of the first dependent reference circuit when the voltage level of one of the differential input signals is higher than a second threshold, wherein the second threshold is greater than the first threshold.

5. A latching device, comprising: A differential pair receives differential input signals and is connected to the first connection node; A differential circuit includes a pair of cross-coupled inverters that perform logic operations on the differential input signals; as well as The offset cancellation circuit unit includes at least one first offset cancellation circuit and at least one second offset cancellation circuit, wherein the at least one first offset cancellation circuit is coupled between the first connection node and the second connection node, and the at least one second offset cancellation circuit is coupled between the first connection node and the third connection node. Each of the at least one first offset cancellation circuit and the at least one second offset cancellation circuit includes: A first independent reference circuit controls a first power path between the first connection node and one of the second and third connection nodes according to an offset control bit. as well as A first dependent reference circuit controls a second power path between the first connection node and one of the second and third connection nodes based on the offset control bit and a first control signal, wherein the first control signal is determined based on the voltage level of one of the differential input signals. The first independent reference circuit and the first dependent reference circuit simultaneously provide the first power path and the second power path.

6. The latch device according to claim 5, wherein The first independent reference circuit includes a first transistor coupled between the first connection node and one of the second and third connection nodes, wherein the first transistor is controlled by the offset control bit, and The first dependent reference circuit includes a second transistor and a third transistor, which are coupled in series between the first connection node and one of the second and third connection nodes, wherein the second transistor is controlled by the offset control bit and the third transistor is controlled by the first control signal.

7. The latch device according to claim 6, wherein The first control signal is configured to turn on the third transistor when the voltage level of one of the differential input signals is lower than a first threshold.

8. The latch device according to claim 7, wherein The first dependent reference circuit is further configured to control a third power path between the first connection node and one of the second and third connection nodes according to the offset control bit and a second control signal, wherein the second control signal is determined according to the voltage level of one of the differential input signals.

9. The latch device according to claim 8, wherein The first dependent reference circuit further includes a fourth transistor and a fifth transistor, which are coupled in series between the first connection node and one of the second and third connection nodes, wherein the fourth transistor is controlled by the offset control bit and the fifth transistor is controlled by the second control signal.

10. The latch device according to claim 9, wherein The second control signal is configured to turn on the fifth transistor when the voltage level of one of the differential input signals is lower than a second threshold.

11. The latch device according to claim 5, further comprising: A clock gate circuit, coupled between the power supply node and the first connection node, supplies a supply voltage from the power supply node to the first connection node according to a clock signal, wherein the clock gate circuit includes: A second independent reference circuit controls a third power path between the power supply node and the first connection node according to the clock signal; and The second dependent reference circuit controls the fourth power path between the power supply node and the first connection node according to the clock signal and the third control signal, wherein the third control signal is determined according to the voltage level of one of the differential input signals.

12. The latch device according to claim 11, wherein... The second independent reference circuit includes a sixth transistor coupled between the power supply node and the first connection node, wherein the sixth transistor is controlled by the clock signal, and The second dependent reference circuit includes a seventh transistor and an eighth transistor, which are coupled in series between the power supply node and the first connection node, wherein the seventh transistor is controlled by the clock signal and the eighth transistor is controlled by the third control signal.

13. The latch device according to claim 11, wherein The second independent reference circuit of the clock gate circuit is further configured to control a fifth power path between the power supply node and the first connection node according to the clock signal and a fourth control signal, wherein the fourth control signal is determined according to the voltage level of one of the differential input signals.

14. The latch device of claim 13, wherein the second dependent reference circuit of the clock gate further comprises a ninth transistor and a tenth transistor, the ninth transistor and the tenth transistor being coupled in series between the power supply node and the first connection node, wherein the ninth transistor is controlled by the clock signal and the tenth transistor is controlled by the fourth control signal.

15. The latch device according to claim 13, wherein The first control signal is the inverted signal of the third control signal, and The second control signal is the inverted signal of the fourth control signal.

16. The latch device according to claim 13, wherein The third control signal is configured to turn on the eighth transistor of the second dependent reference circuit when the voltage level of one of the differential input signals is higher than the first threshold. The fourth control signal is configured to turn on the tenth transistor of the second dependent reference circuit when the voltage level of one of the differential input signals is higher than the second threshold, wherein the second threshold is greater than the first threshold.

17. A method of operating a latch device, comprising: The differential input signal is received by the differential pair of the latch device, so that the differential pair is connected to the first connection node; The first independent reference circuit included in the clock gate circuit of the latch device controls the first power path between the power supply node and the first connection node according to the clock signal; and The first dependent reference circuit included in the clock gate circuit of the latch device controls the second power path between the power supply node and the first connection node according to the clock signal and a first control signal, wherein the first control signal is determined based on the voltage level of one of the differential input signals. The first power path and the second power path are provided simultaneously.

18. The operating method according to claim 17, further comprising: The third power path between the first connection node and the second connection node is controlled by the second independent reference circuit included in the offset elimination circuit of the latch device according to the clock signal; as well as The second dependent reference circuit included in the offset cancellation circuit of the latch device controls the third power path between the first connection node and the second connection node according to the clock signal and the second control signal, wherein the second control signal is determined according to the voltage level of one of the differential input signals.

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