A low phase noise fast frequency hopping source

Abstract

The application discloses a low phase noise fast frequency hopping source, and belongs to the technical field of microwave frequency sources, which is composed of four single phase-locked loop units, a one-to-four power divider and three single-pole double-throw absorption type radio frequency switches. The single phase-locked loop unit is composed of an analog frequency mixer, a loop filter, a voltage-controlled oscillator, a frequency multiplier, a direct digital frequency synthesizer and a band pass filter, wherein the analog frequency mixer replaces a traditional frequency discriminator and phase discriminator plus a charge pump part, the direct digital frequency synthesizer replaces a traditional Sigma-Delta fractional modulator, and the single-pole double-throw absorption type radio frequency switches are connected in series in combination with the overall link "two-in-one" architecture. The application simultaneously has the characteristics of low phase noise and stray level, fast frequency hopping time, fine frequency stepping and high isolation degree and the like.

Description

Technical Field

[0001] This invention relates to the field of microwave frequency source technology, and more specifically, to a low phase noise fast-hopping frequency source. Background Technology

[0002] In microwave radio frequency communication, the performance of the frequency source is crucial, especially in radar applications. It provides the carrier frequency for transmitting modulated information. The frequency band distribution, frequency hopping time, phase noise and spurious performance, and frequency hopping combination of this carrier frequency determine its immunity to interference, agility, and resistance to spurious signals and interception in the physical transmission medium. Furthermore, if the frequency source is poorly designed to lock onto the target frequency in a timely manner, or if the phase noise and spurious levels at the target frequency are too high, it can significantly degrade the constellation diagram and even cause failures such as the inability to demodulate the transmitted modulated signal. Therefore, frequency source technology has always been a key research focus. A high-performance frequency source can greatly reduce the requirements and difficulty of digital demodulation algorithms, making the transmitted signal stable, less prone to distortion, and more resistant to interference.

[0003] In frequency source performance metrics, low phase noise and fast frequency hopping time have always been mutually restrictive and contradictory. For traditional designs, achieving lower phase noise or spurious levels typically involves selecting a narrower loop bandwidth, but a narrower loop bandwidth results in a longer lock-in time at the target frequency. Conversely, achieving a faster frequency hopping time generally involves selecting a wider loop bandwidth. While this significantly reduces the lock-in time, a wider loop bandwidth means that the filtering effect on phase noise and spurious signals is not as good as a narrower bandwidth, leading to a deterioration in phase noise performance. Therefore, designing a frequency source that simultaneously achieves both low phase noise and fast frequency hopping time is quite challenging.

[0004] The above describes the difficulties in design theory, but the engineering design phase is equally challenging. Since the frequency source needs to be installed within the overall equipment for collaborative operation, its size and volume must conform to the overall structural plan, leaving limited space for the frequency source. Its reference frequency signal is usually derived from the entire equipment and cannot be flexibly selected. Furthermore, many flexible imported phase-locked loop (PLL) chips are unusable, and there are very few stable domestically produced chips available. Frequency source design typically faces challenges such as low-frequency input reference signals (e.g., 10MHz), limited size constraints, and the lack of reference frequency multiplication functionality in selected domestic PLL chips. Ensuring both low phase noise and fast hopping becomes even more difficult under these conditions. A low reference frequency without the ability to multiply means a low phase detection frequency, resulting in a limited loop bandwidth and inevitably a slower locking time. Simultaneously, the low phase detection frequency leads to higher Sigma-Delta spurious emissions near the loop bandwidth, increasing both total phase noise and spurious emission levels. Summary of the Invention

[0005] To address the problems existing in the aforementioned background technology, this invention proposes a low phase noise fast hopping frequency source. Especially under conditions of low reference frequency, compact size, and inability of the phase detector to perform frequency doubling reference, it still exhibits characteristics such as low phase noise and spurious levels, fast frequency hopping time, fine frequency stepping, and high isolation.

[0006] The technical solution of this invention is implemented as follows:

[0007] A low phase noise fast-hopping frequency source is characterized by comprising a multi-channel two-in-one topology consisting of four single phase-locked loop units, a one-to-four power divider, and three single-pole double-throw absorptive RF switches.

[0008] An external low-frequency reference clock is input and output through a 1-to-4 power divider. The four outputs are respectively connected to the input ports of the corresponding single phase-locked loop units.

[0009] The four outputs of the four single phase-locked loop units are grouped in pairs. The RF output of single phase-locked loop unit one and the RF output of single phase-locked loop unit two are both connected to the two inputs of the first single-pole double-throw absorptive RF switch.

[0010] The RF output terminals of both the third and fourth single-pole double-throw (SPLL) units are connected to the two input terminals of the second single-pole double-throw (SPLL) absorbing RF switch. The two output terminals of the first and second SPLL absorbing RF switches are connected to the two input terminals of the third SPLL absorbing RF switch. The output terminal of the third SPLL absorbing RF switch serves as the final RF signal output port.

[0011] Furthermore, the single phase-locked loop unit includes an analog mixer, a loop filter, a voltage-controlled oscillator, a frequency multiplier, a direct digital frequency synthesizer, and a bandpass filter;

[0012] The low-frequency reference clock is input to the RF input port of the analog mixer. The output of the analog mixer is connected to the input port of the loop filter. The output port of the loop filter is connected to the input of the voltage-controlled oscillator (VCO). The fundamental output of the VCO is connected to the input of the frequency multiplier. The other output of the VCO can output both the fundamental signal and the frequency divider signal, which can be directly used as the output RF signal of the single phase-locked loop (PLL) unit. The frequency multiplier input comes from the fundamental output of the VCO, and its output is connected to the input of the direct digital frequency synthesizer (DDS). The output of the DDS is connected to the input of the bandpass filter, and the output of the bandpass filter needs to be connected to the local oscillator input port of the mixer.

[0013] Furthermore, each single phase-locked loop unit operates in turn in sequence, and is combined with the temporary power-off function of the single-pole double-throw absorptive RF switch and the voltage-controlled oscillator output buffer to achieve the characteristics of low phase noise and fast frequency hopping time of this frequency source.

[0014] This invention, through the unique internal circuit architecture of the aforementioned single phase-locked loop (PLL) unit, enables the output RF signal to maintain low phase noise or spurious levels and fine frequency steps while being compatible with low input reference clock and low phase detection frequency. At low phase detection frequencies, the loop bandwidth cannot be wide, thus the locking time of the PLL unit is not very fast. However, this invention, through a multi-channel, two-in-one "two-in-one" topology, allows different PLL units to work in turn, avoiding the disadvantage of the single PLL unit's locking time. Combined with a single-pole double-throw absorptive RF switch and a voltage-controlled oscillator output buffer for temporary power-off, a novel frequency-hopping source with high isolation and sufficiently short frequency-hopping time is successfully achieved. Attached Figure Description

[0015] Figure 1 A schematic diagram of the internal circuit of the single phase-locked loop unit of the present invention;

[0016] Figure 2 Overall circuit diagram of the present invention;

[0017] Figure 3 The control timing diagram of the present invention. Detailed Implementation

[0018] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0019] A low phase noise fast-hopping frequency source is characterized by comprising a multi-channel two-in-one topology consisting of four single phase-locked loop units, a one-to-four power divider, and three single-pole double-throw absorptive RF switches.

[0020] An external low-frequency reference clock is input and output through a 1-to-4 power divider. The four outputs are respectively connected to the input ports of the corresponding single phase-locked loop units.

[0021] The four outputs of the four single phase-locked loop units are grouped in pairs. The RF output of single phase-locked loop unit one and the RF output of single phase-locked loop unit two are both connected to the two inputs of the first single-pole double-throw absorptive RF switch.

[0022] The RF output terminals of both the third and fourth single-pole double-throw (SPLL) units are connected to the two input terminals of the second single-pole double-throw (SPLL) absorbing RF switch. The two output terminals of the first and second SPLL absorbing RF switches are connected to the two input terminals of the third SPLL absorbing RF switch. The output terminal of the third SPLL absorbing RF switch serves as the final RF signal output port.

[0023] Furthermore, the single phase-locked loop unit includes an analog mixer, a loop filter, a voltage-controlled oscillator, a frequency multiplier, a direct digital frequency synthesizer, and a bandpass filter;

[0024] The low-frequency reference clock is input to the RF input port of the analog mixer. The output of the analog mixer is connected to the input port of the loop filter. The output port of the loop filter is connected to the input of the voltage-controlled oscillator (VCO). The fundamental output of the VCO is connected to the input of the frequency multiplier. The other output of the VCO can output both the fundamental signal and the frequency divider signal, which can be directly used as the output RF signal of the single phase-locked loop (PLL) unit. The frequency multiplier input comes from the fundamental output of the VCO, and its output is connected to the input of the direct digital frequency synthesizer (DDS). The output of the DDS is connected to the input of the bandpass filter, and the output of the bandpass filter needs to be connected to the local oscillator input port of the mixer.

[0025] Furthermore, each single phase-locked loop unit operates in turn in sequence, and is combined with the temporary power-off function of the single-pole double-throw absorptive RF switch and the voltage-controlled oscillator output buffer to achieve the characteristics of low phase noise and fast frequency hopping time of this frequency source.

[0026] The following is a more specific example:

[0027] Reference Figures 1 to 3 In a single phase-locked loop (PLL) unit, a low-frequency reference clock, typically as low as 10MHz, is directly input to the RF input port of the analog mixer. The local oscillator input port of the analog mixer receives the signal from the feedback loop. The output of the analog mixer is connected to the input of either a loop filter or a low-pass filter. Here, the analog mixer acts as an analog phase detector, replacing the phase detector (phase detector plus charge pump circuit) typically found in charge-pump PLLs. This avoids the linearity problem caused by charge pump current mismatch in traditional digital phase detectors, thus significantly reducing spurious levels at phase leakage points. Whether a loop filter or a low-pass filter follows depends on the type of analog mixer and the output signal selected.

[0028] The loop filter output is fed to the voltage control terminal of the voltage-controlled oscillator (VCO), controlling the frequency of the RF signal generated by the VCO. The fundamental output of the VCO is connected to a direct digital frequency synthesizer (DDS) via a frequency multiplier. The DDS output signal has many spurious signals. After being filtered by the bandpass filter connected to it, a relatively clean feedback signal is obtained, which is compared with the low-frequency reference input signal in the analog mixer. Here, the DDS is introduced to replace the Sigma-Delta fractional divider in the traditional charge-pump phase-locked loop (PLL). This is mainly because the fractional spurious signal level is high at the low phase detection frequency, resulting in high total phase noise. Due to its unique frequency division characteristics, the DDS not only avoids introducing complex fractional spurious signals that increase phase noise, but also improves the phase noise of the output feedback signal. Compared to some schemes that use a mixer to replace the fractional modulator, the mixer introduces phase noise from the local oscillator signal into the PLL, which is not a good choice for low phase noise.

[0029] Considering that the output frequency of a direct digital frequency synthesizer (DFD) is relatively low compared to its input frequency, a frequency multiplier is added to extend the minimum output frequency of the single phase-locked loop (PLL) unit, which can be as low as one time the input frequency while maintaining compatibility with the voltage-controlled oscillator (VCO) band. The frequency multiplier does not need to be too high; a maximum of four times is sufficient. Some high-bit DFDs can achieve extremely fine frequency steps, so this PLL unit, in addition to the aforementioned low phase noise and low spurious levels, also possesses fine frequency steps. Due to the extremely short response time of the DFD, the lock time of this PLL unit is not long, but due to the low phase detection frequency, its lock time is not short enough.

[0030] In the overall architecture of the novel frequency hopping source described in this invention, the external low-frequency reference clock input is output as four paths by a one-to-four power divider and connected to the reference input terminals of four identical single-phase-locked loop (SPL) units. The four outputs of the four SPL units are grouped in pairs and connected in series in a "two-in-one" structure. The RF output terminals of SPL unit one and SPL unit two are respectively connected to the two input terminals of the same single-pole double-throw (SPD) absorptive RF switch. The RF output terminals of SPL unit three and SPL unit four are respectively connected to the two input terminals of another SPD absorptive RF switch. The two output terminals of the two SPD absorptive RF switches are respectively connected to the two input terminals of a third SPD absorptive RF switch. The output terminal of the third SPD absorptive RF switch directly serves as the final RF signal output port of the entire novel frequency hopping source.

[0031] Four single-phase-locked loop (SPL) units operate alternately in a sequence of "1→3→2→4" to ensure that at any given moment, one SPL unit is in a stable locked state. Assuming that the sum of the time it takes for the SPL unit to write the configuration word and the time it takes for the SPL to stabilize at the target frequency under a certain control mode is t, then the novel frequency hopping source described in this invention can shorten the frequency hopping time, or the shortest operating time at the frequency point, to (t / 3). The locking time of the SPL unit itself, combined with the optimized selection of the multi-path topology, will significantly reduce the locking time. The reason for choosing the "1→3→2→4" timing sequence to work alternately is to fully utilize the isolation effect of the two series-connected single-pole double-throw switches on the link. The single-pole double-throw switches themselves are absorptive and their isolation is not low. When one of the four channels is working, the other single-pole double-throw switch on channels 3 and 4 needs to be turned off. The third single-pole double-throw switch is switched to the corresponding channel 1 and 2, and the first single-pole double-throw switch is switched to turn off channels 1 and 2. The voltage-controlled oscillator output buffers of channels 2, 3, and 4 need to be turned off so that the single-phase-locked loop unit is isolated and in a silent state. This silent state does not affect the operation of the single-phase-locked loop unit itself, but only shuts off the external output path, which can provide at least 30dB of isolation. Combined with the isolation of the series-connected single-pole double-throw absorptive RF switches, the isolation of channel 2 is at least 60dB, and the isolation of channels 3 and 4 is at least 90dB. In addition, this symmetrical circuit topology is very suitable for applications with strict requirements for the amplitude and phase consistency of the local oscillator signal, such as radar, and all RF switches are used, so there is no need to add additional dedicated switches to improve isolation, saving board space.

Claims

1. A low phase noise fast-hopping frequency source, characterized in that, It includes a multi-channel, two-in-one topology consisting of four single phase-locked loop units, a one-to-four power divider, and three single-pole double-throw absorptive RF switches. An external low-frequency reference clock is input and output through a 1-to-4 power divider. The four outputs are respectively connected to the input ports of the corresponding single phase-locked loop units. The four outputs of the four single phase-locked loop units are grouped in pairs. The RF output of single phase-locked loop unit one and the RF output of single phase-locked loop unit two are both connected to the two inputs of the first single-pole double-throw absorptive RF switch. The RF output terminals of both single-phase-locked loop (PLL) unit three and single-phase-locked loop (PLL) unit four are connected to the two input terminals of the second single-pole double-throw (SPD) absorptive RF switch. The two output terminals of the first and second SPD absorptive RF switches are connected to the two input terminals of the third SPD absorptive RF switch. The output terminal of the third SPD absorptive RF switch serves as the final RF signal output port. The single phase-locked loop unit includes an analog mixer, a loop filter, a voltage-controlled oscillator, a frequency multiplier, a direct digital frequency synthesizer, and a bandpass filter; The low-frequency reference clock is input to the RF input port of the analog mixer. The output of the analog mixer is connected to the input port of the loop filter. The output port of the loop filter is connected to the input of the voltage-controlled oscillator (VCO). The fundamental output of the VCO is connected to the input of the frequency multiplier. The other output of the VCO can output both the fundamental signal and the divided frequency signal, which can be directly used as the output RF signal of the single phase-locked loop (PLL) unit. The frequency multiplier input comes from the fundamental output of the VCO, and its output is connected to the input of the direct digital frequency synthesizer (DDS). The output of the DDS is connected to the input of the bandpass filter, and the output of the bandpass filter needs to be connected to the local oscillator input port of the mixer. Each single phase-locked loop unit operates in turn in sequence, and is combined with a single-pole double-throw absorptive RF switch and a voltage-controlled oscillator output buffer to temporarily de-energize the frequency source, thereby achieving the characteristics of low phase noise and fast frequency hopping time.

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