Injection-Locked Multi-Phase Clock Filter, Analog-to-Digital / Digital-to-Analog Conversion System

Abstract

The present application discloses a multi-phase clock filter and an analog-to-digital / digital-to-analog conversion system based on injection locking. The filter includes: 2n paths and a ring oscillator. Each path includes an input buffer and an output buffer. The output end of each input buffer is connected to the input end of the corresponding output buffer at a node. The input ends of the input buffers respectively receive clock signals with different phases. The ring oscillator includes 2n delay units forming a loop. Among the 1st, 3rd, ……, (2n - 1)th paths, n delay units are sequentially connected between adjacent nodes, and the output end of the last delay unit is connected to the node of the 2nd path. Among the 2nd, 4th, ……, 2nth paths, n delay units are sequentially connected between adjacent nodes, and the output end of the last delay unit is connected to the node of the 1st path. The present application improves phase noise, reduces jitter, averages the offsets accumulated on the entire clock path, and reduces the burden of calibration and temperature drift.

Description

Technical Field

[0001] The present invention generally relates to the field of integrated circuit technology, and particularly relates to a multi-phase clock filter based on injection locking and an analog-to-digital / digital-to-analog conversion system. Background Art

[0002] With the development of communication technology, the amount of data generated per unit time is increasing, and the required communication speed is also increasing. Therefore, high-speed analog-to-digital converters (ADCs) have become increasingly important. For sampling rates of 32 GS / S or 64 GS / S, the clock-interleaved analog-to-digital converter is a relatively conventional architecture. For a clock-interleaved circuit, a complex clock generation circuit is required to create the interleaving of multiple-phase clocks. For the clock generation circuit, functionally, the relative order of phases must be satisfied. In addition, low power consumption and low clock jitter are both essential performances.

[0003] For modern wired and optical communications, the AD / DA sampling rate is getting faster and faster, and the requirement for time-domain accuracy is also getting higher and higher. However, limited by the transistor background noise and more complex clock schemes, it is more difficult to achieve low jitter and skew. Since jitter and offset accumulate along the entire clock path, we need to find a way to filter out jitter as much as possible at a later stage. Summary of the Invention

[0004] The purpose of the present invention is to provide a multi-phase clock filter based on injection locking, which can improve phase noise, reduce jitter, average the offset accumulated on the entire clock path, and reduce the burden of calibration and temperature drift.

[0005] The present application discloses a multi-phase clock filter based on injection locking, including:

[0006] 2n paths, each path includes an input buffer and an output buffer, the output end of each input buffer is connected to the input end of the corresponding output buffer at a node, and the input ends of the multiple input buffers respectively receive clock signals of different phases;

[0007] A ring oscillator, the ring oscillator includes 2n delay units forming a ring, wherein n delay units are sequentially connected between adjacent nodes in the 1st, 3rd, ……, 2n-1st paths and the output end of the last delay unit is connected to the node of the 2nd path, wherein n delay units are sequentially connected between adjacent nodes in the 2nd, 4th, ……, 2nth paths and the output end of the last delay unit is connected to the node of the 1st path, where n is greater than or equal to 2.

[0008] In a preferred example, a startup circuit is further included. The startup circuit includes a pull-down circuit and a pull-up circuit. The pull-up circuit is connected to the output terminal of a delay unit between the nodes of the (2k - 1)-th and (2k + 1)-th paths and is used to pull up the output signal of the delay unit. The pull-down circuit is connected to the output terminal of a delay unit between the nodes of the 2k-th and (2k + 2)-th paths and is used to pull down the output signal of the delay unit, where k ≤ n.

[0009] In a preferred example, the pull-up circuit includes a pull-up transistor and a first turn-off transistor. The gate of the pull-up transistor is connected to a pull-up startup signal. The source of the pull-up transistor is connected to a voltage source. The drain of the pull-up transistor is connected to the output terminal of the delay unit. The gate of the first turn-off transistor is connected to the pull-up startup signal. The source of the first turn-off transistor is connected to a ground terminal. The drain of the first turn-off transistor is connected to the delay unit.

[0010] In a preferred example, the pull-down circuit includes a pull-down transistor and a second turn-off transistor. The gate of the pull-down transistor is connected to a pull-down startup signal. The source of the pull-down transistor is connected to a ground terminal. The drain of the pull-down transistor is connected to the output terminal of the delay unit. The gate of the second turn-off transistor is connected to the pull-down startup signal. The source of the second turn-off transistor is connected to a power supply terminal. The drain of the second turn-off transistor is connected to the delay unit.

[0011] In a preferred example, the clock signals received by the input buffers of each path increase by π*(n + 1) / n in sequence along the loop direction of the 2n delay units.

[0012] In a preferred example, the multi-phase clock filter includes 8 paths. Among them, the phase of the node of the first path is 45°, the phase of the node of the second path is 225°, the phase of the node of the third path is 270°, the phase of the node of the fourth path is 90°, the phase of the node of the fifth path is 135°, the phase of the node of the sixth path is 315°, the phase of the node of the seventh path is 0°, and the phase of the node of the eighth path is 180°.

[0013] In a preferred example, two inverters are connected between the (2k - 1)-th path and the 2k-th path, and the connection directions of the two inverters are opposite, where k is greater than or equal to 1 and less than or equal to n.

[0014] This application also discloses an analog-to-digital / digital-to-analog conversion system, including:

[0015] A multi-phase input clock, used to generate a multi-phase clock signal;

[0016] The multi-phase clock filter as described above, used to receive the multi-phase clock signal and perform filtering;

[0017] Multiple sub - analog - to - digital / digital - to - analog conversion units, configured to receive the filtered multi - phase clock signal and perform analog - to - digital / digital - to - analog conversion;

[0018] A pseudo - multi - phase clock filter having the same structure as the multi - phase clock filter, the pseudo - multi - phase clock filter receiving a common - mode signal and outputting a multi - phase clock signal;

[0019] A selector, with two input terminals of the selector respectively receiving the filtered multi - phase clock signal of the multi - phase clock filter and the multi - phase clock signal of the pseudo - multi - phase clock filter;

[0020] A digital calibration circuit, the digital calibration circuit receiving the output of the selector and providing a calibration signal to the multi - phase clock filter.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] With the help of the multi - phase injection - locked clock filter, the AD / DA conversion system of the present application can improve phase noise and reduce jitter. In addition, it can also average the offsets accumulated along the entire clock path and reduce the burden of calibration and temperature drift.

[0023] A large number of technical features are recorded in this specification, distributed in various technical solutions. If all possible combinations of technical features (i.e., technical solutions) of the present application are listed, the specification will be too long. To avoid this problem, each technical feature disclosed in the above - mentioned invention content of this specification, each technical feature disclosed in the following embodiments and examples, and each technical feature disclosed in the drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, features A + B + C are disclosed, and in another example, features A + B + D + E are disclosed. Features C and D are equivalent technical means that play the same role, and only one of them can be used technically and it is impossible to use both at the same time. Feature E can be combined with feature C technically. Then, the solution of A + B + C + D should not be regarded as having been recorded because it is technically infeasible, while the solution of A + B + C + E should be regarded as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Shows a schematic diagram of an injection - locked multi - phase clock filter in an embodiment of the present application.

[0025] Figure 2 Shows a schematic diagram of the DC balance initial state of the multi - phase clock filter in an embodiment of the present application.

[0026] Figure 3 Shows a schematic diagram of the initial state of the multi-phase clock filter with a startup circuit in an embodiment of the present application.

[0027] Figure 4 Shows a schematic diagram of the topology of the delay unit in an embodiment of the present application.

[0028] Figure 5 Shows a schematic diagram of the ultra-high speed AD / DA conversion system in an embodiment of the present application.

[0029] Figure 6 Shows a schematic diagram of the ultra-high speed AD / DA conversion system with calibration in an embodiment of the present application.

[0030] Description of reference numerals:

[0031] 101.1 to 101.8: Path

[0032] 102: Ring oscillator

[0033] 103: Input buffer

[0034] 104: Output buffer

[0035] 105: Delay unit

[0036] 106, 107: Cross-coupled inverters

[0037] P1: Pull-up transistor

[0038] N1: First turn-off transistor

[0039] N2: Pull-down transistor

[0040] P2: Second turn-off transistor

[0041] 601: Multi-phase input clock

[0042] 602: Injection-locked multi-phase clock filter

[0043] 603: Sub ADC / DAC unit

[0044] 604: Pseudo multi-phase clock filter

[0045] 605: Strobe

[0046] 606: Digital calibration circuit Detailed implementation manners

[0047] In the following description, many technical details are provided to help the reader better understand the present application. However, those of ordinary skill in the art can understand that the claimed technical solution of the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0048] To make the objectives, technical solutions, and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0049] One embodiment of the present application discloses a multi-phase clock filter based on an injection-locked oscillator (ILO), and its structure is shown in Figure 1 as follows, including: 2n paths 101 and a loop oscillator 102. Each path 101 includes an input buffer 103 and an output buffer 104. The output end of each input buffer 103 on each path 101 is connected to the input end of the corresponding output buffer 104 at a node. The input ends of the input buffers 103 on each path 101 receive clock signals with different phases. Among them, n can be set to 4, 8, 12, 16, etc. As Figure 1 shown, taking eight paths (for example, n = 4) 101.1, 101.2,..., 101.8 from left to right as an example for illustration. The output end of each input buffer 103 is connected to the input end of the corresponding output buffer 104 at a node. For example, the output end of the input buffer 103 of the first path 101.1 is connected to the input end of the corresponding output buffer 104 at node n1, the output end of the input buffer 103 of the second path 101.1 is connected to the input end of the corresponding output buffer 104 at node n5,..., and the output end of the input buffer 103 of the eighth path 101.1 is connected to the input end of the corresponding output buffer 104 at node n8.

[0050] The loop oscillator 102 includes 2n delay units 105 forming a loop. Among them, n delay units are sequentially connected between adjacent nodes in the 1st, 3rd,..., 2n - 1st paths, and the output end of the last delay unit is connected to the node of the 2nd path. Among them, n delay units are sequentially connected between adjacent nodes in the 2nd, 4th,..., 2nth paths, and the output end of the last delay unit is connected to the node of the 1st path, where n is greater than or equal to 2. Taking Figure 1Taking the eight paths in [reference] as an example for illustration, a delay unit is connected between node n1 and node n6, between node n6 and node n3, and between node n3 and node n8 respectively. The output end of the delay unit with its input end connected to node n8 is connected to node n5. A delay unit is connected between node n5 and node n2, between node n2 and node n7, and between node n7 and node n4 respectively. The output end of the delay unit with its input end connected to node n4 is connected to node n1.

[0051] In one embodiment, the clock signals respectively received by the input buffers 103 of each path increase by π*(n + 1) / n in sequence along the loop direction of the 2n delay units. As Figure 1 shown in [reference], the multi-phase clock filter includes 8 paths. The clock signals respectively received by the input buffers 103 of each path increase by 5π / 4 in sequence along the loop direction of the 8 delay units, that is, along the direction of node n1, node n6, node n3, node n8, node n5, node n2, node n7, node n4, the clock signals respectively received by the input buffers 103 increase by 225° in sequence. In one embodiment, the phase of node n1 of the first path is 45°, the phase of node n5 of the second path is 225°, the phase of node n6 of the third path is 270°, the phase of node n2 of the fourth path is 90°, the phase of node n3 of the fifth path is 135°, the phase of node n7 of the sixth path is 315°, the phase of node n8 of the seventh path is 0°, and the phase of node n4 of the eighth path is 180°. It should be understood that in other embodiments of the present application, the phases of the nodes of each path may also be other phase values, as long as it is ensured that the phases of each path increase by 225° in sequence along the loop direction.

[0052] In one embodiment, two inverters are connected between the (2k - 1)-th path and the 2k-th path, and the connection directions of the two inverters are opposite, that is, two cross-coupled inverters, where k is greater than or equal to 1 and less than or equal to n. For example, between the first path and the second path, there are two inverters 106 and 107. The input end of inverter 106 is connected to node n1, the output end of inverter 106 is connected to node n5, the input end of inverter 107 is connected to node n5, and the output end of inverter 106 is connected to node n1. It should be understood that cross-coupled inverters are coupled between the first path and the second path, between the third path and the fourth path, ……, between the (2n - 1)-th path and the 2n-th path.

[0053] Figure 1 The loop oscillator shown in [reference] is an oscillator with an even number of stages, which means there is an obvious DC steady state. Figure 2Shows the DC steady state of an 8-phase loop oscillator, where nodes n1 - n8 have DC static voltages 01010101 (as shown in Table 1 below), forming a loop and preventing the loop oscillator. The reason is that we use pseudo-differential CMOS delay cells instead of fully differential circuits to avoid CMOS-CML conversion. To make the differential gain stronger, we can increase the size of the cross-coupled inverters. However, doing so, the parasitic resistance will prevent us from achieving high-frequency operation. Therefore, this method is not advisable in ultra-high-speed designs.

[0054] Next value of n6 n6 n3 n8 n5 n2 n7 n4 n1 1 1 0 1 0 1 0 1 0

[0055] Table 1 Initial DC Balanced State

[0056] To solve this problem, our solution is to give some unbalanced initial states to get rid of the DC balanced state. Specifically, the multi-phase clock filter further includes a startup circuit, the startup circuit includes a pull-down circuit and a pull-up circuit, the pull-up circuit is connected to the output end of the delay cell between the nodes of the (2k - 1)-th and (2k + 1)-th paths and is used to pull up the output signal of the delay cell, the pull-down circuit is connected to the output end of the delay cell between the nodes of the 2k-th and (2k + 2)-th paths and is used to pull down the output signal of the delay cell, where k ≤ n. The pull-up circuit includes a pull-up transistor and a first turn-off transistor, the gate of the pull-up transistor is connected to the pull-up startup signal, the source is connected to the voltage source, the drain is connected to the output end of the delay cell, the gate of the first turn-off transistor is connected to the pull-up startup signal, the source is connected to the ground terminal, and the drain is connected to the delay cell. The pull-down circuit includes a pull-down transistor and a second turn-off transistor, the gate of the pull-down transistor is connected to the pull-down startup signal, the source is connected to the ground terminal, the drain is connected to the output end of the delay cell, the gate of the second turn-off transistor is connected to the pull-down startup signal, the source is connected to the power supply terminal, and the drain is connected to the delay cell.

[0057] Reference Figure 3As shown, a pull-up transistor P1 and a first turn-off transistor N1 are connected to the output terminal of the delay unit between the node n1 of the first path and the node n6 of the third path. The gate of the pull-up transistor P1 is connected to the pull-up start signal, the source is connected to the power supply terminal, and the drain is connected to the output terminal of the delay unit (for example, node n6). The gate of the first turn-off transistor N1 is connected to the pull-up start signal, the source is connected to the ground terminal, and the drain is connected to the delay unit. When the pull-up start signal is enabled low, the pull-up transistor P1 is turned on, and the first turn-off transistor N1 is turned off, so that the corresponding delay unit is turned off, and the signal of the corresponding node (for example, node n6) is pulled high. A pull-down transistor N2 and the second turn-off transistor P2 are connected to the output terminal of the delay unit between the node n5 of the second path and the node n4 of the fourth path. The gate of the pull-down transistor N2 is connected to the pull-up start signal, the source is connected to the ground terminal, and the drain is connected to the output terminal of the delay unit (for example, node n2). The gate of the second turn-off transistor P2 is connected to the pull-down start signal, the source is connected to the power supply terminal, and the drain is connected to the delay unit. When the pull-down start signal is enabled high, the pull-down transistor N2 is turned on, and the second turn-off transistor N2 is turned off, so that the corresponding delay unit is turned off, and the signal of the corresponding node (for example, node n2) is pulled low.

[0058] When both the pull-up start signal and the pull-down start signal are enabled, the pull-up transistor P1 pulls the signal of node n6 high, the turn-off transistor N1 turns off the delay unit between node n1 and node n6, the pull-down transistor N1 pulls the signal of node n2 low, and the turn-off transistor P2 turns off the delay unit between node n5 and node n2. This loop is broken by tristating the delay unit between node n1 and node n6 and the delay unit between node n5 and node n2. Forcing node n6 to be 1, then nodes n3, n8, and n5 will be automatically set to 010. Since we disconnect the delay unit after node n5, nodes n2, n7, and n4 will initially be set to 010. When the start signal arrives, node n2 will be switched to 1 and this state will be passed to node n7. On the other hand, node n6 will be switched to 0 and the state will be passed to node n3. Since there are 3 delay units before the state of node n6 reaches node n5, there will be no signal conflict on node n2. The signals of nodes n1 - n8 are shown in Table 2 below.

[0059] Next value of n6 n6 n3 n8 n5 Next value of n2 n2 n7 n4 n1 0 1 0 1 0 1 0 1 0 1

[0060] Table 2 Initial State with Startup Circuit

[0061] Figure 4 shows Figure 1 the topology of the delay unit in

[0062] Figure 5 It shows how to use a clock filter based on multi-phase injection locking in an ultra-high speed AD / DA conversion system. We receive an N-phase clock from the PLL and clock distribution, pass it through the multi-phase injection-locked clock filter as described above, and then distribute the clock to each sub-AD / DA. The output clock can be M-phase, which is different from the number of phases of the input clock. Figure 5 In the main path, an 8-phase high-speed clock is sent from the top in the figure to the injection-locked multi-phase clock filter. In the injection-locked multi-phase clock filter, a loop oscillator can be driven by a buffer with adjustable strength. This tunable buffer can adjust the strength to trade off between the locking range and the filtering coefficient. The tunable delay units between nodes n1 and n8 form the loop oscillator circuit. The main path and the loop oscillator are added at n1 to n8. In addition, this loop can be closed to achieve the functions of power saving and low-speed operation.

[0063] Another embodiment of the present application discloses an analog-to-digital / digital-to-analog (AD / DA) conversion system, the structure of which is referred to Figure 6 as shown. The analog-to-digital / digital-to-analog conversion system includes: a multi-phase input clock 601, a multi-phase clock filter 602 as described above, a plurality of sub-analog-to-digital / digital-to-analog conversion units 603, a pseudo multi-phase clock filter 604 having the same structure as the multi-phase clock filter 602, a selector 605, and a digital calibration circuit 606. The multi-phase input clock 601 is used to generate a multi-phase clock signal. The multi-phase clock filter 602 is used to receive the multi-phase clock signal and perform filtering. The plurality of sub-analog-to-digital / digital-to-analog conversion units 603 are used to receive the filtered multi-phase clock signal and perform analog-to-digital / digital-to-analog conversion. The pseudo multi-phase clock filter 604 receives the common-mode signal VCM and outputs a multi-phase clock signal. The two input terminals of the selector 605 respectively receive the filtered multi-phase clock signal (or divided-frequency clock) of the multi-phase clock filter and the multi-phase clock signal (or divided-frequency clock) of the pseudo multi-phase clock filter. The digital calibration circuit 606 receives the output of the selector 605 and calibrates the multi-phase clock filter according to the filtered multi-phase clock signal of the multi-phase clock filter and the multi-phase clock signal of the pseudo multi-phase clock filter.

[0064] Figure 5 Calibration is required when using an ILO-based clock filter in the ultra-high speed AD / DA conversion system as shown to ensure the best performance in terms of locking conditions, noise filtering, phase shift, etc. Figure 6 It shows the calibration scheme. The frequency of the ILO can be calibrated using the frequency of the main clock or the replicated clock.

[0065] With the help of a clock filter based on multiphase injection locking, the present application can be improved in terms of phase noise and the jitter is reduced. Another advantage of this filter is that it can also average the offsets accumulated along the entire clock path, reducing the burden of calibration and temperature drift.

[0066] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one" does not exclude the presence of additional identical elements in the process, method, article or device comprising the element. In the application documents of this patent, if it is mentioned that an act is performed according to an element, it means that the act is performed at least according to the element, including two cases: the act is performed only according to the element, and the act is performed according to the element and other elements. Expressions such as multiple, multiple times, multiple types include 2, 2 times, 2 types, and more than 2, more than 2 times, more than 2 types.

[0067] The term "coupled to" and its derivatives may be used herein. "Coupling" may mean that two or more elements are in direct physical or electrical contact. However, "coupling" may also mean that two or more elements are in contact with each other indirectly, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.

[0068] This specification includes combinations of various embodiments described herein. Separate references to embodiments (e.g., "an embodiment" or "some embodiments" or "preferred embodiments") are not necessarily to the same embodiment; however, unless indicated as being mutually exclusive or clearly mutually exclusive to those skilled in the art, these embodiments are not mutually exclusive. It should be noted that the term "or" is used in a non-exclusive sense in this specification unless the context clearly dictates otherwise or requires otherwise.

[0069] All documents mentioned in this specification are considered to be incorporated herein by reference in their entirety so that they can be used as a basis for modification if necessary. In addition, it should be understood that the above description is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of this specification shall be included within the scope of protection of one or more embodiments of this specification.

Claims

1. A multi-phase clock filter based on injection locking, characterized in that, comprising: 2n paths, each path including an input buffer and an output buffer, the output end of each input buffer is connected to the input end of the corresponding output buffer at a node, and the input ends of the input buffers on each path respectively receive clock signals of different phases; A loop oscillator, the loop oscillator includes 2n delay units forming a loop, wherein n delay units are sequentially connected between adjacent nodes in the 1st, 3rd,..., 2n - 1st paths and the output end of the last delay unit is connected to the node of the 2nd path, wherein n delay units are sequentially connected between adjacent nodes in the 2nd, 4th,..., 2nth paths and the output end of the last delay unit is connected to the node of the 1st path, where n is greater than or equal to 2; and A startup circuit, the startup circuit includes a pull-down circuit and a pull-up circuit, the pull-up circuit is connected to the output end of the delay unit between the nodes of the 2k - 1st and 2k + 1st paths and is used to pull up the output signal of the delay unit, the pull-down circuit is connected to the output end of the delay unit between the nodes of the 2kth and 2k + 2nd paths and is used to pull down the output signal of the delay unit, where k ≤ n.

2. The multi-phase clock filter based on injection locking according to claim 1, characterized in that, the pull-up circuit includes a pull-up transistor and a first turn-off transistor, the gate of the pull-up transistor is connected to a pull-up startup signal, the source of the pull-up transistor is connected to a voltage source, the drain of the pull-up transistor is connected to the output end of the delay unit, the gate of the first turn-off transistor is connected to the pull-up startup signal, the source of the first turn-off transistor is connected to the ground terminal, and the drain of the first turn-off transistor is connected to the delay unit.

3. The multi-phase clock filter based on injection locking according to claim 1, characterized in that, the pull-down circuit includes a pull-down transistor and a second turn-off transistor, the gate of the pull-down transistor is connected to a pull-down startup signal, the source of the pull-down transistor is connected to the ground terminal, the drain of the pull-down transistor is connected to the output end of the delay unit, the gate of the second turn-off transistor is connected to the pull-down startup signal, the source of the second turn-off transistor is connected to the power supply terminal, and the drain of the second turn-off transistor is connected to the delay unit.

4. The multi-phase clock filter based on injection locking according to claim 1, characterized in that, the clock signals respectively received by the input buffers of each path increase by π*(n + 1) / n in sequence along the loop direction of the 2n delay units.

5. The multi-phase clock filter based on injection locking according to claim 1, characterized in that, The multi-phase clock filter includes 8 paths. Among them, the phase of the node of the first path is 45°, the phase of the node of the second path is 225°, the phase of the node of the third path is 270°, the phase of the node of the fourth path is 90°, the phase of the node of the fifth path is 135°, the phase of the node of the sixth path is 315°, the phase of the node of the seventh path is 0°, and the phase of the node of the eighth path is 180°.

6. The injection-locked multi-phase clock filter according to claim 1, characterized in that, Two inverters are connected between the (2k - 1)-th path and the 2k-th path, and the connection directions of the two inverters are opposite, where k is greater than or equal to 1 and less than or equal to n.

7. An analog-to-digital / digital-to-analog conversion system, characterized in that, comprising: A multi-phase input clock for generating a multi-phase clock signal; The multi-phase clock filter according to any one of claims 1 - 6, for receiving the multi-phase clock signal and performing filtering; Multiple sub-analog-to-digital / digital-to-analog conversion units for receiving the filtered multi-phase clock signal and performing analog-to-digital / digital-to-analog conversion; A pseudo multi-phase clock filter having the same structure as the multi-phase clock filter, the pseudo multi-phase clock filter receiving a common-mode signal and outputting a multi-phase clock signal; A selector, the two input ends of the selector respectively receiving the filtered multi-phase clock signal of the multi-phase clock filter and the multi-phase clock signal of the pseudo multi-phase clock filter; A digital calibration circuit, the digital calibration circuit receiving the output of the selector and providing a calibration signal to the multi-phase clock filter.

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