Control instruction synchronization circuit and distributed camera system

Abstract

The application provides a control instruction synchronization circuit and a distributed camera system, which are arranged in the interior of each camera of the distributed camera system. When a first control signal is received, a synchronization instruction signal transmission module transmits a synchronization instruction signal input by an input interface module to an output interface module. When the input interface module is not connected to a synchronization line, an instruction module receives a control instruction signal from a previous camera. Based on the corresponding synchronization instruction signal, the instruction module executes the control instruction signal and sends the control instruction signal to a subsequent camera. When a second control signal is received, the synchronization instruction signal transmission module transmits a synchronization instruction signal generated by a master control chip module to the output interface module. When the input interface module is not connected to the synchronization line, the instruction module generates a control instruction signal. Based on the corresponding synchronization instruction signal, the instruction module executes the control instruction signal and sends the control instruction signal to the subsequent camera.

Description

Technical Field

[0001] This invention relates to the field of camera circuits, and in particular to a control command synchronization circuit and a distributed camera system. Background Technology

[0002] In conventional distributed camera systems, cameras execute tasks based on control commands. However, since each camera operates independently, there is a delay in the execution of control commands, preventing them from executing synchronously. Therefore, existing distributed camera systems suffer from poor synchronization of control command execution among cameras.

[0003] Therefore, it is necessary to provide a control command synchronization circuit and a distributed camera system to solve the above-mentioned technical problems. Summary of the Invention

[0004] This invention provides a control command synchronization circuit and a distributed camera system, which effectively solves the technical problem of poor synchronization effect of each camera executing control commands in existing distributed camera systems.

[0005] This invention provides a control command synchronization circuit for a distributed camera system, which is installed inside each camera of the distributed camera system and includes:

[0006] The input interface module is used to input synchronization command signals;

[0007] The detection and control module is used to output a first control signal to the synchronization command signal transmission module when the input interface module is connected to the synchronization line; and to output a detection signal to the main control chip module and a second control signal to the synchronization command signal transmission module when the input interface module is not connected to the synchronization line.

[0008] The main control chip module is used to output the synchronization command signal to the synchronization command signal transmission module when the detection signal is received;

[0009] The synchronization command signal transmission module is used to transmit the synchronization command signal input by the input interface module to the output interface module when a first control signal is received; the synchronization command signal transmission module is used to transmit the synchronization command signal generated by the main control chip module to the output interface module when a second control signal is received; the output interface module is used to output the synchronization command signal to the next camera.

[0010] The instruction module is used to generate the control instruction signal and execute the control instruction signal; wherein the control instruction signal corresponds to the synchronization instruction signal;

[0011] An information transmission module is connected between the input interface module and the output interface module of two adjacent cameras, and the information transmission module is used to transmit the control command signal;

[0012] When the input interface module is connected to the synchronization line, the instruction module receives control instruction signals from the previous camera through the information transmission module, executes the control instruction signals based on the corresponding synchronization instruction signals, and sends the control instruction signals to the next camera through the information transmission module.

[0013] When the input interface module is not connected to the synchronization line, the instruction module generates the control instruction signal, executes the control instruction signal based on the corresponding synchronization instruction signal, and sends the control instruction signal to the next camera through the information transmission module.

[0014] In the control command synchronization circuit described in this invention, when the input interface module is connected to the synchronization line, the detection control module outputs a high-level detection signal, and the main control chip module identifies the camera's working mode as slave mode; when the input interface module is not connected to the synchronization line, the detection control module outputs a low-level detection signal, and the main control chip module identifies the camera's working mode as master mode.

[0015] In the control command synchronization circuit of the present invention, the detection control module includes a first MOS transistor and a second MOS transistor. The gate of the first MOS transistor is connected to the input interface module and the power supply. The drain of the first MOS transistor is connected to the gate of the second MOS transistor. The source of the first MOS transistor is grounded. The source of the second MOS transistor is connected to the gate. The source of the second MOS transistor is also connected to the power supply. The drain of the first MOS transistor is also used to output the detection signal and the first control signal. The drain of the second MOS transistor is used to output the second control signal.

[0016] In the control command synchronization circuit of the present invention, the synchronization command signal transmission module includes a synchronization command signal transmission chip, the synchronization command signal transmission chip includes a first control pin and a second control pin, the first control pin is connected to the drain of a first MOS transistor and is used to receive the first control signal, the second control pin is connected to the drain of a second MOS transistor and is used to receive the second control signal;

[0017] The synchronization command signal transmission chip further includes a first input pin, a second input pin, and a first output pin. The first input pin is connected to the input interface module and is used to receive the synchronization command signal input by the input interface module. The second input pin is connected to the main control chip module and is used to input the synchronization command signal generated by the main control chip module. The first output pin is connected to the output interface module and is used to output the synchronization command signal.

[0018] In the control command synchronization circuit of the present invention, the control command synchronization circuit further includes a master clock signal transmission module and a frame synchronization signal transmission module, and the input interface module is also used to input the master clock signal or the frame synchronization signal.

[0019] The detection and control module is also used to output a first control signal to the master clock signal transmission module and the frame synchronization signal transmission module when the input interface module is connected to the synchronization line; and to output a detection signal to the master control chip module and a second control signal to the master clock signal transmission module and the frame synchronization signal transmission module when the input interface module is not connected to the synchronization line.

[0020] The main control chip module is used to output the main clock signal to the main clock signal transmission module and output the frame synchronization signal to the frame synchronization signal transmission module when the detection signal is received.

[0021] The master clock signal transmission module is used to transmit the master clock signal input by the input interface module to the output interface module when a first control signal is received; and to transmit the master clock signal generated by the master control chip module to the output interface module when a second control signal is received.

[0022] The frame synchronization signal transmission module is used to transmit the frame synchronization signal input by the input interface module to the output interface module when a first control signal is received; and to transmit the frame synchronization signal generated by the main control chip module to the output interface module when a second control signal is received.

[0023] The camera module is used to capture images based on the frame synchronization signal and the master clock signal;

[0024] The output interface module is used to output the master clock signal or the frame synchronization signal.

[0025] In the control command synchronization circuit of the present invention, the master clock signal transmission module includes a master clock signal transmission chip, the master clock signal transmission chip includes a third control pin and a fourth control pin, the third control pin is connected to the drain of the first MOS transistor, the third control pin is used to receive the first control signal, and the fourth control pin is connected to the drain of the second MOS transistor, the fourth control pin is used to receive the second control signal;

[0026] The master clock signal transmission chip further includes a third input pin, a fourth input pin, and a second output pin. The third input pin is connected to the input interface module and is used to receive the master clock signal input by the input interface module. The fourth input pin is connected to the master control chip module and is used to input the master clock signal generated by the master control chip module. The second output pin is connected to the output interface module and is used to output the master clock signal.

[0027] In the control command synchronization circuit of the present invention, the frame synchronization signal transmission module includes a frame synchronization signal transmission chip, the frame synchronization signal transmission chip includes a fifth control pin and a sixth control pin, the third control pin is connected to the drain of the first MOS transistor, the fifth control pin is used to receive the first control signal, the fourth control pin is connected to the drain of the second MOS transistor, and the sixth control pin is used to receive the second control signal.

[0028] The frame synchronization signal transmission chip further includes a fifth input pin, a sixth input pin, and a third output pin. The fifth input pin is connected to the input interface module and is used to receive the frame synchronization signal input by the input interface module. The sixth input pin is connected to the main control chip module and is used to input the frame synchronization signal generated by the main control chip module. The third output pin is connected to the output interface module and is used to output the frame synchronization signal.

[0029] In the control command synchronization circuit described in this invention, the master clock signal transmission chip is a fast logic chip, and the model of the master clock signal transmission chip is SN74lVC2G126; the frame synchronization signal transmission chip is a fast logic chip, and the model of the frame synchronization signal transmission chip is SN74lVC2G126.

[0030] In the control command synchronization circuit described in this invention, the synchronization command transmission chip is a fast logic chip, and the model of the synchronization command transmission chip is SN74lVC2G126.

[0031] A distributed camera system comprising:

[0032] Multiple cameras, each of which has a corresponding control command synchronization circuit as described above, wherein one of the cameras is a master camera and the rest are slave cameras. The master camera operates in master mode and the slave cameras operate in slave mode.

[0033] A synchronization line, one end of which is connected to the output interface module of the host camera and the other end of which is connected to the input interface module of the slave camera, or connected between the input interface modules and output interface modules of two adjacent slave cameras, is used to transmit control command signals, synchronization command signals, master clock signals and / or frame synchronization signals;

[0034] Each camera generates an image based on the master clock signal and the frame synchronization signal for subsequent synchronized display; each camera performs synchronized control of all cameras based on the control command signal and the synchronization command signal.

[0035] Compared to existing technologies, the advantages of this invention are as follows: This invention provides a control command synchronization circuit, which includes an input interface module, a main control chip module, a synchronization command signal transmission module, an output interface module, a command module, and an information transmission module. When the input interface module is connected to a synchronization line, the synchronization command signal transmission module can receive synchronization command signals from the input interface module. Furthermore, the command module receives control command signals from the preceding camera through the information transmission module. Because the control command signals correspond to the synchronization command signals, the command module can execute control command signals based on the corresponding synchronization command signals. Moreover, the command module sends the control command signals to the following camera through the information transmission module, and the synchronization command signal transmission module can transmit the synchronization command signals to the output interface module.

[0036] When the input interface module is not connected to the synchronization line, the main control chip module generates a synchronization command signal. Furthermore, the command module can generate control command signals. Because the control command signals correspond to the synchronization command signals, the command module executes the control command signals based on the corresponding synchronization command signals. Additionally, the command module can send the control command signals to the next camera via the information transmission module, and the synchronization command signal transmission module can transmit the synchronization command signals to the output interface module.

[0037] Therefore, multiple cameras equipped with this control command synchronization circuit can form a distributed camera system, where all synchronization command signals within the cameras are generated by the host camera. Furthermore, because the control command signal corresponds to the synchronization command signal, the host camera can control all cameras to simultaneously trigger and execute the control command signal. Consequently, there is no delay in the execution of control commands by each camera, allowing all cameras to execute control commands synchronously. This effectively solves the technical problem of poor synchronization in the execution of control commands by each camera in existing distributed camera systems. Moreover, in this distributed camera system, the synchronization of control signals executed by all cameras can reach a very high standard. Since there is no delay in the execution of control commands by each camera, the operating efficiency of this distributed camera system is high. Attached Figure Description

[0038] Figure 1 This is a block diagram of a first embodiment of the control command synchronization circuit of the present invention.

[0039] Figure 2 This is a circuit diagram of the input interface module of the first embodiment of the control command synchronization circuit of the present invention.

[0040] Figure 3 This is a circuit diagram of the detection control module of a second embodiment of the control command synchronization circuit of the present invention.

[0041] Figure 4 This is a circuit diagram of the output interface module of a second embodiment of the control command synchronization circuit of the present invention.

[0042] Figure 5 This is a circuit diagram of the information transmission module of the control command synchronization circuit of the present invention.

[0043] Figure 6 This is a circuit diagram of the synchronization command signal transmission module of the control command synchronization circuit of the present invention.

[0044] Figure 7 This is a block diagram of a second embodiment of the control command synchronization circuit of the present invention.

[0045] Figure 8 This is a circuit diagram of the master clock signal transmission module of a second embodiment of the control command synchronization circuit of the present invention.

[0046] Figure 9 This is a circuit diagram of the frame synchronization signal transmission module of a second embodiment of the control command synchronization circuit of the present invention.

[0047] Figure 10 This is a schematic diagram of the synchronization circuit of the distributed camera system of the present invention.

[0048] In the diagram, 10 is the control command synchronization circuit; 11 is the input interface module; 12 is the detection and control module; 13 is the main control chip module; 14 is the synchronization command signal transmission module; 15 is the main clock signal transmission module; 16 is the frame synchronization signal transmission module; 17 is the output interface module; 18 is the information transmission module; 181 is the command module; 19 is the power supply; and 1A is the camera module. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] The directional terms mentioned in this invention, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", "top" and "bottom", are only for reference to the orientation of the accompanying drawings. The directional terms used are for the purpose of explaining and understanding this invention, and are not intended to limit this invention.

[0051] The terms "first" and "second" used in the terminology of this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance, nor as limiting the order of events.

[0052] In the diagram, units with similar structures are represented by the same labels.

[0053] Please refer to Figure 1 , Figure 2 and Figure 3 The following is a detailed description of the first embodiment of the present invention:

[0054] This invention provides a control command synchronization circuit 10, which is disposed inside a camera. The control command synchronization circuit 10 includes an input interface module 11, a detection control module 12, a main control chip module 13, a synchronization command signal transmission module 14, an output interface module 17, an information transmission module 18, and a command module 181. The input interface module 11 is used to input a synchronization command signal, which comes from the previous camera. The detection control module 12 can output a first control signal OE1 and a second control signal OE2. When the input interface module 11 is connected to a synchronization line, the detection control module 12 outputs the first control signal OE1 to the synchronization command signal transmission module 14. When the input interface module 11 is not connected to a synchronization line, the detection control module 12 outputs a low-level detection signal to the main control chip module 13 and outputs the second control signal OE2 to the synchronization command signal transmission module 14. Thus, the main control chip module 13 can generate a synchronization command signal based on the detection signal.

[0055] Please refer to Figure 1 , Figure 2 and Figure 3 When the first control signal OE1 is received, the synchronization command signal transmission module 14 can transmit the synchronization command signal input from the input interface module 11 to the output interface module 17. When the second control signal OE2 is received, the synchronization command signal transmission module 14 transmits the synchronization command signal generated by the main control chip module 13 to the output interface module 17. The command module 181 can be used to generate and execute control command signals. The information transmission module 18 is connected between the input interface module 11 and the output interface module 17 of two adjacent cameras, and is used to transmit control command signals. When the input interface module 11 is connected to the synchronization line, i.e., the camera is in slave mode, the command module 181 receives the control command signal from the previous camera through the information transmission module 18. Since the control command signal corresponds to the synchronization command signal, the command module 181 can execute the control command signal based on the synchronization command signal. Subsequently, the command module 181 sends the control command signal to the next camera through the information transmission module 18. When the input interface module is not connected to the synchronization line, i.e., the camera is in master mode, the command module 181 can generate control command signals. Since the control command signal corresponds to the synchronization command signal, the command module 181 can execute the control command signal based on the synchronization command signal. Subsequently, the command module 181 sends the control command signal to the next camera through the information transmission module 18.

[0056] Please refer to Figure 2 and Figure 3The input interface module 11 includes a DET pin, and the detection and control module 12 includes a first MOSFET Q1 and a second MOSFET Q2. The gate of the first MOSFET Q1 is connected to the DET pin of the input interface module 11 and the power supply VCC, and the drain of the first MOSFET Q1 is connected to the gate of the second MOSFET Q2. The source of the first MOSFET Q1 is grounded, and the source of the second MOSFET Q2 is connected to its gate. The source of the second MOSFET Q2 is also connected to the power supply 19. The gate of the drain of the first MOSFET Q1 is also used to output a detection signal and a first control signal OE1, and the drain of the second MOSFET Q2 is used to output a second control signal OE2.

[0057] Please refer to Figure 3 and Figure 4 The detection control module 12 also includes a first resistor R1, a second resistor R2, and a third resistor R3. One end of the first resistor R1 is connected to the gate of the first MOSFET Q1, and the other end is connected to the power supply VCC. The resistance of the first resistor R1 is 100KΩ. One end of the second resistor R2 is connected to the source of the second MOSFET Q2, and the other end is connected to the gate of the second MOSFET Q2. The resistance of the second resistor R2 is 10KΩ. One end of the third resistor R3 is connected to the drain of the second MOSFET Q2, and the other end is grounded. The resistance of the third resistor R3 is 10KΩ. The output interface module 17 includes a PULL_DOWN pin and a fourth resistor R4. One end of the fourth resistor R4 is connected to the PULL_DOWN pin. The fourth resistor R4 is a pull-down resistor. Therefore, after the input interface modules 11 and output interface modules 17 of two adjacent cameras are connected through a synchronization line, the DET pin of the input interface module 11 of the previous camera can be pulled down to a low level by the fourth resistor R4 of the output interface module 17 of the next camera.

[0058] Each camera can function as both a master and slave device. The connection method of the synchronization line determines whether the camera is currently operating in master or slave mode. The camera has an internal master control chip module 13, which can identify the camera's operating mode as master or slave based on detection signals. When the input interface module 11 is connected to the synchronization line, the detection control module 12 outputs a high-level detection signal, and the master control chip module 13 identifies the camera's operating mode as slave mode. When the input interface module 11 is not connected to the synchronization line, the detection control module 12 outputs a low-level detection signal, and the master control chip module 13 identifies the camera's operating mode as master mode.

[0059] Please refer to Figure 2 , Figure 3 and Figure 4If the camera's input interface module 11 is not connected to the synchronization line, the first resistor R1 can pull up to the power supply, and the gate of the first MOSFET Q1 receives a high-level signal (the first MOSFET Q1 is turned on). Therefore, the drain of the first MOSFET Q1 outputs a low-level detection signal. Based on this low-level detection signal, the main control chip module 13 can identify the camera's operating mode as master mode. If the camera's input interface module 11 is connected to the synchronization line, it can be connected to the output interface module 17 of another camera via the synchronization line. In this case, the DET pin of the input interface module 11 is connected to the PULL_DOWN pin of the other camera's output interface module 17. Therefore, the DET pin of the input interface module 11 is pulled down to a low level by the fourth resistor R4 of the other camera via the synchronization line. Consequently, the gate of the first MOSFET Q1 receives a low-level signal. Furthermore, the drain of the first MOSFET Q1 can output a high-level detection signal (the first MOSFET Q1 is turned off). Based on this high-level detection signal, the main control chip module 13 can identify the camera's operating mode as slave mode. When a low-level detection signal is received, the main control chip module 13 outputs a synchronization command signal to the synchronization command signal transmission module 14.

[0060] Please refer to Figure 2 , Figure 4 and Figure 5 The information transmission module 18 includes a fifth resistor R10, a sixth resistor R11, a seventh resistor R12, and an eighth resistor R13. The input interface module 11 includes UART0_TX, UART0_RX, UART1_TX, and UART1_RX pins, and the output interface module 17 includes UART0_TX_OUT, UART0_RX_IN, UART1_TX_OUT, and UART1_RX_IN pins. One end of the fifth resistor R10 is connected to the UART0_TX pin, and the other end is connected to the UART0_TX_OUT pin. One end of the sixth resistor R11 is connected to the UART0_RX pin, and the other end is connected to the UART0_RX_IN pin. One end of the seventh resistor R12 is connected to the UART1_TX pin, and the other end is connected to the UART1_RX_IN pin. One end of the eighth resistor R13 is connected to the UART0_TX pin, and the other end is connected to the UART1_RX_IN pin.

[0061] The control command signal can be numbering information. When the camera is in master mode, the command module of the master mode camera performs a numbering operation on the camera. Furthermore, the command module of the master mode camera can also generate numbering information and transmit it to the next camera. When the camera is in slave mode, the camera receives the numbering information generated by the previous camera through the information transmission module 18, and the camera's command module can perform a numbering operation on the camera based on the numbering information. Furthermore, the camera's command module can generate numbering information and transmit it to the next camera.

[0062] For example, network cameras can be automatically numbered sequentially. The master mode camera is numbered 0 and sends number 1 to the adjacent slave mode camera through the information transmission module 18; the adjacent master mode camera is numbered 1 and sends number 2 to the next adjacent slave mode camera through the information transmission module 18; the next adjacent slave mode camera is numbered 2, and so on. This automatic sequential numbering simplifies system maintenance.

[0063] Please refer to Figure 1 and Figure 3 The control command synchronization circuit also includes a synchronization command signal transmission module 14. The input interface module 11 is used to input the synchronization command signal. When a detection signal is received, the main control chip module 13 outputs a synchronization command signal to the synchronization command signal transmission module 14. The control command signal corresponds to the synchronization command signal. Therefore, based on this synchronization command signal, all cameras can execute the control command signal simultaneously. Thus, even if multiple cameras need to execute the control command signal, there will be no delay.

[0064] Please refer to Figure 1 and Figure 3 The synchronization command signal transmission module 14 includes a synchronization command signal transmission chip, which is a fast logic chip and its model number is SN741VC2G126. There are two synchronization command signal transmission chips: a first synchronization command signal transmission chip U1 and a second synchronization command signal transmission chip U2, wherein the first synchronization command signal transmission chip U1 and the second synchronization command signal transmission chip U2 are two identical chips.

[0065] Please refer to Figure 2 , Figure 3 and Figure 6The input interface module 11 includes an IO_IN pin, which is used to input synchronization command signals from adjacent cameras. The synchronization command signal transmission chip U1 includes a first control pin U11 and a second control pin U12, and the synchronization command signal transmission chip U2 includes a first control pin U21 and a second control pin U22. Both the first control pin U11 and the first control pin U21 are connected to the drain of the second MOSFET Q2. The first control pins U11 and U21 are used to receive the second control signal OE2, and the second control pins U12 and U22 are connected to the drain of the first MOSFET Q1, and are used to receive the first control signal OE1.

[0066] Please refer to Figure 2 and Figure 6 The synchronization command signal transmission chip U1 further includes a first input pin U14, a second input pin U13, and a first output pin U15. The synchronization command signal transmission chip U2 further includes a first input pin U24, a second input pin U23, and a first output pin U25. The input interface module 11 includes an IO_IN pin. The first input pins U14 and U24 are both connected to the IO_IN pin of the input interface module 11. The first input pins U14 and U24 are used to receive the synchronization command signal input from the input interface module 11. The second input pins U13 and U23 are both connected to the main control chip module 13. The second input pins U13 and U23 are used to input the synchronization command signal generated by the main control chip module 13. The first output pins U15 and U25 are connected to the output interface module 17. The first output pins U15 and U25 are used to output the synchronization command signal. This synchronization command signal transmission chip includes a VCC pin and a GND pin. The VCC pin is connected to the power supply 19, and the GND pin is grounded.

[0067] exist Figure 1 and Figure 2 Based on this, please combine Figure 3 and Figure 6When the camera operates in master mode, the first control pins U11 and U21 receive the second control signal OE2. Specifically, the first control pins U11 and U21 receive a high-level signal. At this time, the second input pins U13 and U23 can input the synchronization command signal generated by the master control chip module 13. Furthermore, since the control command signal corresponds to the synchronization command signal, the camera can execute the control command signal based on the synchronization command signal. Subsequently, the first output pins U15 and U25 can output the synchronization command signal to the output interface module 17. When the camera operates in slave mode, the second control pins U21 and U22 receive the first control signal OE1. Specifically, the second control pins U11 and U12 receive a high-level signal. At this time, the first input pins U14 and U24 are used to receive the synchronization command signal input from the input interface module 11. Moreover, since the control command signal corresponds to the synchronization command signal, the camera can execute the control command signal based on the synchronization command signal. Subsequently, the first output pins U15 and U25 can output the synchronization command signal to the output interface module 17. The output interface module 17 includes an IO_OUT pin, which is connected to the first output pin and is used to output the synchronization command signal to an adjacent external camera. Therefore, this control command synchronization circuit 10 can achieve rapid synchronization of synchronization command signal transmission between multiple cameras.

[0068] The control command signal can be a shutter speed signal. Executing the control command signal based on this synchronization command signal achieves shutter speed synchronization. For the shutter speed signal, the master mode camera calculates the shutter speed and then transmits it to all slave mode cameras via its information transmission module 18. Therefore, all slave mode cameras share the same shutter speed with the master mode cameras. That is, the master sends its own shutter speed to the slave cameras in real time, and the slave cameras send the shutter speed parameters received from the master to their own image sensors, so the entire system can always use the same shutter speed. The control command signal can also be a time signal. Executing the control command signal based on this synchronization command signal achieves time synchronization. That is, the master mode camera sends its system time to the slave mode cameras, so the entire system can always use the same system time. The control command signal can also be a task signal. Executing the control command signal based on this synchronization command signal achieves task synchronization. For example, the master mode camera sends a task signal to the slave mode cameras, allowing all cameras in the system to start or stop recording simultaneously. Automatic numbering can take effect in real time, while shutter speed signals, time signals, and task signals can be sent as control commands first, and then the camera in host mode can control all cameras to trigger and execute simultaneously.

[0069] Based on the first embodiment, the control command synchronization circuit 10 of this embodiment further includes a master clock signal transmission module 15, a frame synchronization signal transmission module 16, and a camera module 1A. The input interface module 11 also includes a VD_IN pin and an MCLK_IN pin. The VD_IN pin is used to input the frame synchronization signal from the previous camera and output it to the frame synchronization signal transmission module 16. The MCLK_IN pin is used to input the master clock signal from the previous camera and output it to the master clock signal transmission module 15. When the master control chip module 13 receives a detection signal, it can output a master clock signal to the master clock signal transmission module 15. Furthermore, the master control chip module 13 outputs a frame synchronization signal to the frame synchronization signal transmission module 16. Moreover, the camera module 1A performs image acquisition operations based on the master clock signal output by the master clock signal transmission module 15 and the frame synchronization signal output by the frame synchronization signal transmission module 16.

[0070] Please refer to Figure 7 and Figure 8 The master clock signal transmission module 15 includes a master clock signal transmission chip. This master clock signal transmission chip is a fast logic chip, model number SN741VC2G126. There are two master clock signal transmission chips: a first master clock signal transmission chip U5 and a second master clock signal transmission chip U6. Both chips are identical. When the first control signal OE1 is received, the master clock signal transmission module 15 transmits the master clock signal input from the input interface module 11 to the output interface module 17. When the second control signal OE2 is received, the master clock signal transmission module 15 transmits the master clock signal generated by the master control chip module 13 to the output interface module 17.

[0071] Please refer to Figure 7 and Figure 8 The main clock signal transmission chip U5 includes a third control pin U51 and a fourth control pin U52, and the main clock signal transmission chip U6 includes a third control pin U61 and a fourth control pin U62. The third control pins U51 and U61 are connected to the drain of the second MOSFET Q2 and are used to receive the second control signal OE2. The fourth control pins U52 and U62 are connected to the drain of the first MOSFET Q1 and are used to receive the first control signal OE1.

[0072] Please refer to Figure 7 and Figure 8The master clock signal transmission chip U5 also includes a third input pin U54, a fourth input pin U53, and a second output pin U55. The master clock signal transmission chip U6 also includes a third input pin U64, a fourth input pin U63, and a second output pin U65. The third input pins U54 and U64 are connected to the MCLK_IN pin of the input interface module 11 and are used to receive the master clock signal input from the input interface module 11. The fourth input pins U53 and U63 are connected to the main control chip module 13 and are used to input the master clock signal generated by the main control chip module 13. The second output pins U55 and U65 are connected to the output interface module 17 and are used to output the master clock signal. This master clock signal transmission chip includes a VCC pin and a GND pin. The VCC pin is connected to the power supply 19, and the GND pin is grounded.

[0073] Please refer to Figure 7 and Figure 9 The frame synchronization signal transmission module 16 includes a frame synchronization signal transmission chip, which is a fast logic chip, model number SN741VC2G126. There are two frame synchronization signal transmission chips: a first frame synchronization signal transmission chip U3 and a second frame synchronization signal transmission chip U4. The first frame synchronization signal transmission chip U3 and the second frame synchronization signal transmission chip U4 are two identical chips. When the first control signal OE1 is received, the frame synchronization signal transmission module 16 transmits the frame synchronization signal input from the input interface module 11 to the output interface module 17. When the second control signal OE2 is received, the frame synchronization signal transmission module 16 transmits the frame synchronization signal generated by the main control chip module 13 to the output interface module 17.

[0074] Please refer to Figure 7 and Figure 9 The frame synchronization signal transmission chip U3 includes a fifth control pin U31 and a sixth control pin U32, and the frame synchronization signal transmission chip U4 includes a fifth control pin U41 and a sixth control pin U42. The fifth control pins U31 and U41 are connected to the drain of the second MOSFET Q2 and are used to receive the second control signal OE2. The sixth control pins U32 and U42 are connected to the drain of the first MOSFET Q1 and are used to receive the first control signal OE1.

[0075] Please refer to Figure 7 and Figure 9The frame synchronization signal transmission chip U3 also includes a fifth input pin U34, a sixth input pin U33, and a third output pin U35. The frame synchronization signal transmission chip U4 also includes a fifth input pin U44, a sixth input pin U43, and a third output pin U45. The fifth input pins U34 and U44 are both connected to the VD_IN pin of the input interface module 11, and are used to receive the frame synchronization signal input from the input interface module 11. The sixth input pins U33 and U43 are both connected to the main control chip module 13, and are used to input the frame synchronization signal generated by the main control chip module 13. The third output pins U35 and U45 are both connected to the output interface module 17, and are used to output the frame synchronization signal. This frame synchronization signal transmission chip includes a VCC pin and a GND pin. The VCC pin is connected to the power supply 19, and the GND pin is grounded.

[0076] Please refer to Figure 7 and Figure 8 When the camera is operating in master mode, the third control pins U51 and U61 receive the second control signal OE2. Specifically, the third control pins U51 and U61 receive a high-level signal. At this time, the fourth input pins U53 and U63 can input the master clock signal generated by the master control chip module 13. Furthermore, the second output pins U55 and U65 can output the master clock signal to the output interface module 17. When the camera is operating in slave mode, the fourth control pins U52 and U62 receive the first control signal OE1. Specifically, the fourth control pins U52 and U62 receive a high-level signal. At this time, the third input pins U54 and U64 are used to receive the master clock signal input from the input interface module 11. Furthermore, the second output pins U55 and U65 can output the master clock signal to the output interface module 17. Therefore, this control command synchronization circuit 10 can achieve rapid synchronization of master clock signal transmission between multiple cameras.

[0077] Please refer to Figure 7 and Figure 9When the camera is operating in master mode, the fifth control pins U31 and U41 receive the second control signal OE2. Specifically, the fifth control pins U31 and U41 receive a high-level signal. At this time, the sixth input pins U33 and U43 can input the frame synchronization signal generated by the master control chip module 13. Furthermore, the third output pins U35 and U45 can output the frame synchronization signal to the output interface module 17. When the camera is operating in slave mode, the sixth control pin receives the first control signal OE1. Specifically, the sixth control pins U32 and U42 receive a high-level signal. At this time, the fifth input pins U34 and U44 are used to receive the frame synchronization signal input from the input interface module 11. Furthermore, the third output pins U35 and U45 can output the frame synchronization signal to the output interface module 17. Therefore, this control command synchronization circuit 10 can achieve rapid synchronization of frame synchronization signal transmission between multiple cameras. By selecting a fast logic chip, the control command synchronization circuit 10 can achieve extremely low-latency frame synchronization between two adjacent cameras. This circuit uses the SN741VC2G126 logic chip, thus enabling the control command synchronization circuit 10 to achieve frame synchronization within 8ns between two adjacent camera modules 1A.

[0078] Please refer to Figure 6 The output interface module 17 is used to output the master clock signal or frame synchronization signal to the next camera. The output interface module 17 includes a VD_OUT pin and an MCLK_OUT pin. The MCLK_OUT pin is connected to the second output pin, and the VD_OUT pin is connected to the third output pin. The MCLK_OUT pin is used to output the master clock signal to the next camera, and the VD_OUT pin is used to output the frame synchronization signal to the next camera. Multiple cameras equipped with this control command synchronization circuit can form a distributed camera system. The master clock signal and frame synchronization signal of the image sensor of all cameras' camera modules 1A are generated by the master camera, thus achieving a very high standard of frame synchronization for all cameras, and ensuring that the number of image frames output by all cameras is strictly the same. In a distributed system consisting of 100 digital cameras, the time difference between image frames can be within 0.8µs. Furthermore, using a standard USB 3.0 Type-C to Type-C cable for synchronization reduces the cost of the synchronization cable and simplifies the complexity of distributed networking of multiple cameras.

[0079] This embodiment provides a control command synchronization circuit 10, which is installed inside each camera of a distributed camera system. When the input interface module 11 is connected to the synchronization line, the detection control module 12 outputs a first control signal OE1 to the synchronization command signal transmission module 14. Upon receiving the first control signal OE1, the synchronization command signal transmission module 14 transmits the synchronization command signal received by the input interface module 11. Simultaneously, the command module 181 receives the control command signal from the previous camera through the information transmission module 18. Since the control command signal corresponds to the synchronization command signal, the command module 181 can execute the control command signal based on the synchronization command signal. Subsequently, the command module 181 can also send the control command signal to the next camera through the information transmission module 18. Furthermore, the synchronization command signal transmission module 14 can transmit the synchronization command signal to the output interface module 17 based on the first control signal OE1.

[0080] When the input interface module 11 is not connected to the synchronization line, the detection control module 12 outputs a low-level detection signal to the main control chip module 13, and outputs a second control signal OE2 to the synchronization command signal transmission module 14. When a low-level detection signal is received, the main control chip module 13 outputs a synchronization command signal to the synchronization command signal transmission module 14. Simultaneously, the command module 181 generates a control command signal. Since the control command signal corresponds to the synchronization command signal, the command module 181 can execute the control command signal based on the synchronization command signal. Subsequently, the command module 181 sends the control command signal to the next camera through the information transmission module 18. Furthermore, the synchronization command signal transmission module 14 can transmit the synchronization command signal generated by the main control chip module 13 to the output interface module 17 based on the second control signal OE2.

[0081] Furthermore, when the input interface module 11 is connected to the synchronization line, the camera is in slave mode. The detection control module 12 outputs a first control signal OE1 to the master clock signal transmission module 15 and the frame synchronization signal transmission module 16. When the input interface module 11 is not connected to the synchronization line, the camera is in master mode. The detection control module 12 outputs a low-level detection signal to the master control chip module 13. Additionally, the detection control module 12 outputs a second control signal OE2 to the master clock signal transmission module 15 and the frame synchronization signal transmission module 16.

[0082] When the first control signal OE1 is received, the master clock signal transmission module 15 transmits the master clock signal input from the input interface module 11 to the output interface module 17, and the frame synchronization signal transmission module 16 transmits the frame synchronization signal input from the input interface module 11 to the output interface module 17. When the second control signal OE2 is received, the master clock signal transmission module 15 transmits the master clock signal generated by the main control chip module 13 to the output interface module 17, and the frame synchronization signal transmission module 16 transmits the frame synchronization signal generated by the main control chip module 13 to the output interface module 17. Furthermore, the output interface module 17 can output either the master clock signal or the frame synchronization signal.

[0083] Each camera generates an image based on the master clock signal and frame synchronization signal, and subsequent images can be displayed synchronously. Therefore, the master clock signal and frame synchronization signal correspond, achieving a very high standard of frame synchronization for all images generated by all cameras. Furthermore, each camera synchronously controls all other cameras based on control command signals and synchronization command signals. Based on the synchronization command signal, the camera in master mode can control all cameras to simultaneously trigger and execute control command signals. Consequently, there is no delay when any camera performs the master's tasks.

[0084] This invention also includes a distributed camera system comprising multiple cameras and a synchronization line. Each camera internally has a corresponding control command synchronization circuit, with one camera serving as the master camera and the others as slave cameras. The master camera operates in master mode, and the slave cameras operate in slave mode. One end of the synchronization line is connected to the output interface module of the master camera, and the other end is connected to the input interface module of the slave camera. Alternatively, the synchronization line can be connected between the input and output interface modules of two adjacent slave cameras. The synchronization line can be used to transmit control command signals, synchronization command signals, master clock signals, or frame synchronization signals. Each camera generates an image based on the master clock signal and frame synchronization signal for subsequent synchronized image display, and each camera performs synchronized control of all cameras based on the control command signals and synchronization command signals. Specifically... Figure 10 As shown, the synchronization signals include synchronization command signals, master clock signals, and frame synchronization signals, and the command signals include control command signals.

[0085] The working principle of this invention is as follows: When the input interface module 11 is not connected to the synchronization line, the detection control module 12 outputs a low-level detection signal. Then, the main control chip module 13 can identify the camera's working mode as host mode. Subsequently, the detection control module 12 outputs a second control signal OE2. Moreover, the instruction module 181 generates a control instruction signal. At the same time, both the first control pin U11 and the first control pin U21 receive the second control signal OE2. Based on the second control signal OE2, the second input pin U13 and the second input pin U23 can input the synchronization instruction signal generated by the main control chip module 13. Furthermore, this control instruction signal corresponds to the synchronization instruction signal. Therefore, the camera can execute the control instruction signal based on the synchronization instruction signal. Subsequently, the instruction module 181 sends the control instruction signal to the next camera through the information transmission module 18. Furthermore, the first output pin U15 and the first output pin U25 can output the synchronization instruction signal to the output interface module 17.

[0086] Furthermore, the third control pins U51 and U61 receive the second control signal OE2. Based on the second control signal OE2, the fourth input pins U53 and U63 can input the master clock signal generated by the main control chip module 13. The second output pins U55 and U65 can output the master clock signal to the output interface module 17. Moreover, the fifth control pins U31 and U41 of the frame synchronization signal transmission chip can receive the second control signal OE2. Based on the second control signal OE2, the sixth input pins U34 and U44 can input the frame synchronization signal generated by the main control chip module 13. The third output pins U35 and U45 can output the frame synchronization signal to the output interface module 17. Since the output interface module 17 is connected to the next camera via a synchronization line, it can output either the master clock signal or the frame synchronization signal to the next camera.

[0087] When the input interface module 11 is connected to the synchronization line, the detection control module 12 can output a high-level detection signal. Then, the main control chip module 13 can identify the camera's operating mode as slave mode. Subsequently, the detection control module 12 outputs a first control signal OE1. Moreover, the instruction module 181 receives and executes the control instruction signal from the previous camera through the information transmission module 18. At the same time, the second control pin U21 and the second control pin U22 receive the first control signal OE1. Based on the first control signal OE1, the first input pin U14 and the first input pin U24 can input the synchronization instruction signal from the input interface module 11. Furthermore, this control instruction signal corresponds to the synchronization instruction signal. Therefore, the camera can execute the control instruction signal based on the synchronization instruction signal. Subsequently, the instruction module 181 can also send the control instruction signal to the next camera through the information transmission module 18. Furthermore, the first output pin U15 and the first output pin U25 can output the synchronization instruction signal to the output interface module 17.

[0088] Based on the synchronization line connected to the input interface module 11, the input interface module 11 can input the master clock signal or frame synchronization signal from the previous camera. Furthermore, both the fourth control pin U52 and the fourth control pin U62 receive the first control signal OE1. Based on the first control signal OE1, the third input pins U54 and U64 can input the master clock signal from the input interface module 11. Furthermore, the second output pins U55 and U65 can output the master clock signal to the output interface module 17. Moreover, the sixth control pins U32 and U42 can receive the first control signal OE1. Based on the first control signal OE1, the fifth input pins U34 and U44 can input the frame synchronization signal from the input interface module 11. Furthermore, the third output pins U35 and U45 can output the frame synchronization signal to the output interface module 17. Since the output interface module 17 is connected to the next camera via the synchronization line, the output interface module 17 can output the master clock signal or frame synchronization signal to the next camera.

[0089] This invention provides a control command synchronization circuit, which includes an input interface module, a main control chip module, a synchronization command signal transmission module, an output interface module, a command module, and an information transmission module. When the input interface module is connected to a synchronization line, the synchronization command signal transmission module can receive synchronization command signals from the input interface module. Furthermore, the command module receives control command signals from the preceding camera via the information transmission module. Because the control command signals correspond to the synchronization command signals, the command module can execute control command signals based on the corresponding synchronization command signals. The command module then sends the control command signals to the following camera via the information transmission module, and the synchronization command signal transmission module can transmit the synchronization command signals to the output interface module.

[0090] When the input interface module is not connected to the synchronization line, the main control chip module generates a synchronization command signal. Furthermore, the command module can generate control command signals. Because the control command signals correspond to the synchronization command signals, the command module executes the control command signals based on the corresponding synchronization command signals. Additionally, the command module can send the control command signals to the next camera via the information transmission module, and the synchronization command signal transmission module can transmit the synchronization command signals to the output interface module.

[0091] Therefore, multiple cameras equipped with this control command synchronization circuit can form a distributed camera system, where all synchronization command signals within the cameras are generated by the host camera. Furthermore, because the control command signal corresponds to the synchronization command signal, the host camera can control all cameras to simultaneously trigger and execute the control command signal. Consequently, there is no delay in the execution of control commands by each camera, allowing all cameras to execute control commands synchronously. This effectively solves the technical problem of poor synchronization in the execution of control commands by each camera in existing distributed camera systems. Moreover, in this distributed camera system, the synchronization of control signals executed by all cameras can reach a very high standard. Since there is no delay in the execution of control commands by each camera, the operating efficiency of this distributed camera system is high.

[0092] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A control command synchronization circuit, disposed inside each camera of a distributed camera system, characterized in that, It includes: The input interface module is used to input synchronization command signals; The detection and control module is used to output a first control signal to the synchronization command signal transmission module when the input interface module is connected to the synchronization line; and to output a detection signal to the main control chip module and a second control signal to the synchronization command signal transmission module when the input interface module is not connected to the synchronization line. The main control chip module is used to output the synchronization command signal to the synchronization command signal transmission module when the detection signal is received; The synchronization command signal transmission module is used to transmit the synchronization command signal input by the input interface module to the output interface module when the first control signal is received. The synchronization command signal transmission module is used to transmit the synchronization command signal generated by the main control chip module to the output interface module when the second control signal is received; The output interface module is used to output the synchronization command signal to the next camera; The instruction module is used to generate control instruction signals and execute the control instruction signals; wherein the control instruction signals correspond to the synchronization instruction signals; An information transmission module is connected between the input interface module and the output interface module of two adjacent cameras, and the information transmission module is used to transmit the control command signal; When the input interface module is connected to the synchronization line, the instruction module receives the control instruction signal from the previous camera through the information transmission module, executes the control instruction signal based on the corresponding synchronization instruction signal, and sends the control instruction signal to the next camera through the information transmission module. When the input interface module is not connected to the synchronization line, the instruction module generates the control instruction signal, executes the control instruction signal based on the corresponding synchronization instruction signal, and sends the control instruction signal to the next camera through the information transmission module; The detection and control module includes a first MOS transistor and a second MOS transistor. The gate of the first MOS transistor is connected to the input interface module and the power supply. The drain of the first MOS transistor is connected to the gate of the second MOS transistor. The source of the first MOS transistor is grounded. The source of the second MOS transistor is connected to the gate. The source of the second MOS transistor is also connected to the power supply. The drain of the first MOS transistor is also used to output the detection signal and the first control signal. The drain of the second MOS transistor is used to output the second control signal.

2. The control command synchronization circuit according to claim 1, characterized in that, When the input interface module is connected to the synchronization line, the detection control module outputs a high-level detection signal, and the main control chip module identifies the camera's operating mode as slave mode; when the input interface module is not connected to the synchronization line, the detection control module outputs a low-level detection signal, and the main control chip module identifies the camera's operating mode as master mode.

3. The control command synchronization circuit according to claim 2, characterized in that, The synchronization command signal transmission module includes a synchronization command signal transmission chip. The synchronization command signal transmission chip includes a first control pin and a second control pin. The first control pin is connected to the drain of a second MOS transistor and is used to receive the second control signal. The second control pin is connected to the drain of a first MOS transistor and is used to receive the first control signal. The synchronization command signal transmission chip further includes a first input pin, a second input pin, and a first output pin. The first input pin is connected to the input interface module and is used to receive the synchronization command signal input by the input interface module. The second input pin is connected to the main control chip module and is used to input the synchronization command signal generated by the main control chip module. The first output pin is connected to the output interface module and is used to output the synchronization command signal.

4. The control command synchronization circuit according to claim 1, characterized in that, The control command synchronization circuit also includes a master clock signal transmission module and a frame synchronization signal transmission module. The input interface module is also used to input the master clock signal or the frame synchronization signal. The detection and control module is also used to output a first control signal to the master clock signal transmission module and the frame synchronization signal transmission module when the input interface module is connected to the synchronization line; and to output a detection signal to the master control chip module and a second control signal to the master clock signal transmission module and the frame synchronization signal transmission module when the input interface module is not connected to the synchronization line. The main control chip module is used to output the main clock signal to the main clock signal transmission module and output the frame synchronization signal to the frame synchronization signal transmission module when the detection signal is received. The master clock signal transmission module is used to transmit the master clock signal input by the input interface module to the output interface module when the first control signal is received. When the second control signal is received, the main clock signal generated by the main control chip module is transmitted to the output interface module; The frame synchronization signal transmission module is used to transmit the frame synchronization signal input by the input interface module to the output interface module when the first control signal is received. When the second control signal is received, the frame synchronization signal generated by the main control chip module is transmitted to the output interface module; The camera module is used to capture images based on the frame synchronization signal and the master clock signal; The output interface module is used to output the master clock signal or the frame synchronization signal; The master clock signal transmission module includes a master clock signal transmission chip, which includes a third control pin and a fourth control pin. The third control pin is connected to the drain of a second MOS transistor and is used to receive the second control signal. The fourth control pin is connected to the drain of a first MOS transistor and is used to receive the first control signal. The master clock signal transmission chip further includes a third input pin, a fourth input pin, and a second output pin. The third input pin is connected to the input interface module and is used to receive the master clock signal input by the input interface module. The fourth input pin is connected to the master control chip module and is used to input the master clock signal generated by the master control chip module. The second output pin is connected to the output interface module and is used to output the master clock signal.

5. The control command synchronization circuit according to claim 4, characterized in that, The frame synchronization signal transmission module includes a frame synchronization signal transmission chip, which includes a fifth control pin and a sixth control pin. The fifth control pin is connected to the drain of a second MOS transistor and is used to receive the second control signal. The sixth control pin is connected to the drain of a first MOS transistor and is used to receive the first control signal. The frame synchronization signal transmission chip further includes a fifth input pin, a sixth input pin, and a third output pin. The fifth input pin is connected to the input interface module and is used to receive the frame synchronization signal input by the input interface module. The sixth input pin is connected to the main control chip module and is used to input the frame synchronization signal generated by the main control chip module. The third output pin is connected to the output interface module and is used to output the frame synchronization signal.

6. The control command synchronization circuit according to claim 5, characterized in that, The master clock signal transmission chip is a fast logic chip, and the model number of the master clock signal transmission chip is SN74lVC2G126; the frame synchronization signal transmission chip is a fast logic chip, and the model number of the frame synchronization signal transmission chip is SN74lVC2G126.

7. The control command synchronization circuit according to claim 3, characterized in that, The synchronous command transmission chip is a fast logic chip, and the model of the synchronous command transmission chip is SN74lVC2G126.

8. A distributed camera system, characterized in that, It includes: Multiple cameras, each camera having a corresponding control command synchronization circuit as described in any one of claims 1-7, wherein one of the cameras is a master camera and the rest are slave cameras, the master camera operates in master mode and the slave cameras operate in slave mode; A synchronization line, one end of which is connected to the output interface module of the host camera and the other end of which is connected to the input interface module of the slave camera, or connected between the input interface modules and output interface modules of two adjacent slave cameras, is used to transmit control command signals, synchronization command signals, master clock signals and / or frame synchronization signals; Each camera generates an image based on the master clock signal and the frame synchronization signal for subsequent synchronized display; each camera performs synchronized control of all cameras based on the control command signal and the synchronization command signal.

Images