Adjustable Fluid Coupling in a Data Center Cooling System

Abstract

An adjustable fluid coupling in a data center cooling system is disclosed, and a system and method for cooling a data center are also disclosed. In at least one embodiment, a flow controller adapter of a cooling manifold interchangeably receives a flow controller among a plurality of flow controllers, wherein the flow controller adapter is associated with a rack-side flow controller and a pipe therebetween, and is configured to be movable within the cooling manifold to allow different positions for mating the flow controller with a server-side flow controller of a server tray or enclosure.

Description

Technical Field

[0001] At least one embodiment relates to cooling systems, including systems and methods for operating such cooling systems. In at least one embodiment, such a cooling system can be utilized in a data center that includes one or more racks or computing servers. Background Art

[0002] Data center cooling systems use fans to circulate air through server components. Certain supercomputers or other high-capacity computers can use water or other cooling systems instead of air-cooling systems to draw heat from server components or racks in the data center to an area outside the data center. The cooling system can include a chiller within the data center area, and the data center area can include an area outside the data center itself. Further, the area outside the data center can include a cooling tower or other external heat exchanger that receives heated coolant from the data center and dissipates the heat to the environment (or external cooling medium) through forced air or other means. The cooled coolant is recirculated back into the data center. The chiller and the cooling tower together form a cooling facility. Brief Description of the Drawings

[0003] Figure 1 An exemplary data center cooling system that is subject to the improvements described in at least one embodiment is shown;

[0004] Figure 2 Server-level features associated with an adjustable fluid coupling for a data center cooling system according to at least one embodiment are shown;

[0005] Figure 3 Rack-level features associated with an adjustable fluid coupling for a data center cooling system according to at least one embodiment are shown;

[0006] Figure 4 Data center-level features associated with an adjustable fluid coupling for a data center cooling system according to at least one embodiment are shown;

[0007] Figure 5 Shows according to at least one embodiment the Figures 2 to 4 associated with a data center cooling system;

[0008] Fig. 6A Inference and / or training logic according to at least one embodiment is shown;

[0009] Figure 6B Inference and / or training logic according to at least one embodiment is shown;

[0010] Figure 7Shows the training and deployment of a neural network according to at least one embodiment;

[0011] Figure 8 Shows an example data center system according to at least one embodiment;

[0012] Fig. 9 Is a block diagram showing a computer system according to at least one embodiment;

[0013] Fig.10 Is a block diagram showing a computer system according to at least one embodiment;

[0014] Fig.11 Shows a computer system according to at least one embodiment;

[0015] Fig.12 Shows a computer system according to at least one embodiment;

[0016] Fig.13A Shows a computer system according to at least one embodiment;

[0017] Fig. 13B Shows a computer system according to at least one embodiment;

[0018] Fig. 13C Shows a computer system according to at least one embodiment;

[0019] Fig.13D Shows a computer system according to at least one embodiment;

[0020] Fig.13E and Fig.13F Shows a shared programming model according to at least one embodiment;

[0021] Fig.14 Shows an exemplary integrated circuit and associated graphics processor according to at least one embodiment;

[0022] Fig.15A 、 Fig. 15B Shows an exemplary integrated circuit and associated graphics processor according to at least one embodiment;

[0023] Fig.16A 、 Fig. 16B Shows additional exemplary graphics processor logic according to at least one embodiment;

[0024] Fig.17 Shows a computer system according to at least one embodiment;

[0025] Fig.18A Shows a parallel processor according to at least one embodiment;

[0026] Fig.18B Shows a partitioning unit according to at least one embodiment;

[0027] Fig. 18C Shows a processing cluster according to at least one embodiment;

[0028] Fig.18D Shows a graphics multiprocessor according to at least one embodiment;

[0029] Fig.19 Shows a multi-graphics processing unit (GPU) system according to at least one embodiment;

[0030] Fig. 20 Shows a graphics processor according to at least one embodiment;

[0031] Fig.21 Is a block diagram showing a processor microarchitecture for a processor according to at least one embodiment;

[0032] Fig. 22 Shows a deep learning application processor according to at least one embodiment;

[0033] Fig.23 Is a block diagram showing an example neuromorphic processor according to at least one embodiment;

[0034] Fig.24 Shows at least a portion of a graphics processor according to one or more embodiments;

[0035] Fig.25 Shows at least a portion of a graphics processor according to one or more embodiments;

[0036] Fig.26 Shows at least a portion of a graphics processor according to one or more embodiments;

[0037] Fig. 27 Is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0038] Fig.28 Is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0039] Fig.29A 、 Fig.29B Shows thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core.

[0040] Fig.30 Shows a parallel processing unit (“PPU”) according to at least one embodiment;

[0041] Fig.31illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0042] Fig.32 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0043] Fig.33 A streaming multiprocessor is shown according to at least one embodiment;

[0044] Fig.34 is an example data flow diagram of a high-level computing pipeline according to at least one embodiment;

[0045] Fig.35 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline in accordance with at least one embodiment;

[0046] Fig.36A A data flow diagram illustrating a process for training a machine learning model according to at least one embodiment; and

[0047] Fig.36B is an example illustration of a client-server architecture for enhancing an annotation tool using a pre-trained annotation model in accordance with at least one embodiment. DETAILED DESCRIPTION

[0048] In at least one embodiment, the following can be used: Figure 1 An exemplary data center 100 is shown, which has a cooling system that is subjected to the improvements described herein. In at least one embodiment, many specific details are set forth to provide a thorough understanding, but the concepts herein can be practiced without one or more of these specific details. In at least one embodiment, a data center cooling system can respond to sudden high thermal demands caused by changing computing loads in today's computing components. In at least one embodiment, since these demands experience changes from minimum to maximum values ​​of different cooling demands or tend to change from minimum to maximum values, appropriate cooling systems must be used to meet these demands in an economical manner. In at least one embodiment, a liquid cooling system can be used for medium to high cooling demands. In at least one embodiment, high cooling demands are economically met by local immersion cooling. In at least one embodiment, these different cooling demands also reflect different thermal characteristics of the data center. In at least one embodiment, the heat generated from these components, servers, and racks is cumulatively referred to as thermal characteristics or cooling requirements because the cooling requirements must fully address the thermal characteristics.

[0049] In at least one embodiment, a data center liquid cooling system is disclosed. In at least one embodiment, the data center cooling system addresses thermal characteristics in associated computing or data center equipment, such as in a graphics processing unit (GPU), in a switch, in a dual in-line memory module (DIMM), or in a central processing unit (CPU). In at least one embodiment, these components may herein be referred to as high heat density computing components. Additionally, in at least one embodiment, the associated computing or data center equipment may be a processing card having one or more GPUs, switches, or CPUs thereon. In at least one embodiment, each of the GPU, switch, and CPU may be a heat generating characteristic of the computing device. In at least one embodiment, the GPU, CPU, or switch may have one or more cores, and each core may be a heat generating characteristic.

[0050] In at least one embodiment, an adjustable fluid coupling in a data center cooling system is disclosed. In at least one embodiment, a flow controller adapter movable within a cooling manifold is provided. In at least one embodiment, such a flow controller adapter can receive one of a plurality of first flow controllers in an interchangeable manner. In at least one embodiment, such a flow controller adapter can be associated with a rack-side flow controller and piping therebetween such that fluid can flow through the rack-side flow controller, through the flow controller adapter, through the interchangeable first flow controller associated with the flow controller adapter, and through a server-side flow controller to enter a server tray or enclosure.

[0051] Thus, in at least one embodiment, on one side, different orifice sizes and different coupling characteristics are enabled for each interchangeable first flow controller, and on the other side, standard orifice sizes and standard coupling characteristics are enabled for each such interchangeable first flow controller. In at least one embodiment, this enables a matching interchangeable first flow controller to be coupled to the flow controller adapter, regardless of the type (such as orifice size or coupling characteristics) of the server-side flow controller, and subsequently the server-side flow controller can be coupled to the flow controller adapter such that coolant can flow into the server tray or enclosure.

[0052] In at least one embodiment, further, such a flow controller adapter can be associated with the rack-side flow controller to receive coolant from a rack manifold through piping between such a flow controller adapter and the rack-side flow controller. In at least one embodiment, the flow controller adapter is also movable within the cooling manifold such that it can be positioned to mate with a corresponding server-side flow controller, regardless of the positioning (which may be a fixed position) of such a server-side flow controller of the server tray or enclosure.

[0053] In at least one embodiment, such adjustable fluid couplings in a data center cooling system can address the following issues: Server trays and enclosures include certain fixed orifice sizes and / or certain fixed coupling features, such as 9 mm couplers, 6 mm couplers, or couplers with different coupling features, such as threads, press - fits, J - slot connections, or spring - release features. In at least one embodiment, such orifice sizes and / or coupling features require similar types of matching couplers from the rack side. In at least one embodiment, the adjustable fluid couplings in a data center cooling system can address the following further issue: Server trays and enclosures include fixed positions or orientations at the areas of such server trays or enclosures for such fixed orifice sizes and / or such fixed coupling features to couple to a rack - side rack cooling manifold.

[0054] In at least one embodiment, the adjustable fluid couplings in a data center cooling system enable or provide a flow - controller adapter that can move within a rack cooling manifold to receive interchangeable flow controllers that have different orifice sizes and / or different coupling features on one side and standard orifice sizes and standard coupling features on the other side. In at least one embodiment, such interchangeable flow controllers with different orifice sizes and / or different coupling features can be selected to couple with corresponding server - side flow controllers of a server tray or enclosure. In at least one embodiment, this movable flow - controller adapter can also be adjusted to a position on the rack manifold or bracket to match the fixed position of the corresponding server - side flow controller of the server tray or enclosure.

[0055] In at least one embodiment, such adjustable fluid couplings in a data center cooling system can also address the issue where delivering liquid from a rack cooling manifold to a server tray or enclosure for liquid - cooling purposes requires certain determinations (e.g., the number of liquid - line connections, the locations of such liquid - line connections, and the size / style of the flow controller). In at least one embodiment, the size and style of the flow controller can be referenced to the orifice size and coupling feature, such as a quick - disconnect flow controller or a threaded flow controller that can be used in a server tray or enclosure. In at least one embodiment, the rack - side flow controller must match such server - side requirements. In at least one embodiment, these requirements can be the case for servers with direct - to - chip liquid cooling and servers with high - heat - density racks, in at least one embodiment.

[0056] In at least one embodiment, the flow controller adapter herein is capable of connecting a liquid line from a rack cooling manifold to various flow controller locations of a server tray or a rack by allowing such a flow controller adapter to be movable to abut against a server-side flow controller and receiving a flow controller having a matching orifice size or coupling feature as the server-side flow controller. In at least one embodiment, this eliminates any requirement for a substantial amount of downtime when the entire cooling feature of the rack has to be replaced.

[0057] In at least one embodiment, an adjustable fluid coupling in a data center cooling system enables a universal, adjustable, and intelligent system including a flow controller adapter. In at least one embodiment, the system is a single design of a rack cooling manifold or bracket associated with a rack for distributing fluid, such as coolant for a server tray or enclosure for liquid-to-liquid cooling, the server tray or enclosure having a single pair or multiple pairs of flow controllers at any location on any boundary of the server tray or enclosure. In at least one embodiment, the ability to adjust the position, orifice size, or coupling feature of the flow controller associated with the rack cooling manifold or bracket and then intelligently control such a flow controller through the flow controller adapter enables fluid distribution to any server tray or enclosure, regardless of any specific requirements on the server-side flow controller associated therewith.

[0058] In at least one embodiment, it is possible to utilize as Figure 1The exemplary data center 100 shown has a cooling system that undergoes the improvements described herein. In at least one embodiment, the data center 100 can be one or more rooms 102 with racks 110 and auxiliary equipment to house one or more servers on one or more server trays. In at least one embodiment, the data center 100 is supported by a cooling tower 104 located outside the data center 100. In at least one embodiment, the cooling tower 104 dissipates heat from within the data center 100 by acting on the main cooling loop 106. In at least one embodiment, a cooling distribution unit (CDU) 112 is used between the main cooling loop 106 and the second or auxiliary cooling loop 108 to enable heat extraction from the second or auxiliary cooling loop 108 to the main cooling loop 106. In at least one embodiment, in one aspect, the auxiliary cooling loop 108 can access different plumbing devices leading into the server trays as needed. In at least one embodiment, the loops 106, 108 are shown as line diagrams, but one of ordinary skill in the art will recognize that one or more plumbing device features can be used. In at least one embodiment, flexible polyvinyl chloride (PVC) tubing can be used with the associated plumbing devices to move fluid along each provided loop 106; 108. In at least one embodiment, one or more coolant pumps can be used to maintain a pressure differential within the coolant loops 106, 108 such that the coolant can move in accordance with temperature sensors in different locations, including within the room, within one or more racks 110, and / or within server enclosures or server trays within one or more racks 110.

[0059] In at least one embodiment, the coolant in the main cooling loop 106 and the auxiliary cooling loop 108 can be at least water and an additive. In at least one embodiment, the additive can be ethylene glycol or propylene glycol. In operation, in at least one embodiment, each of the main cooling loop and the auxiliary cooling loop can have its own coolant. In at least one embodiment, the coolant in the auxiliary cooling loop can be dedicated to the requirements of components in the server trays or the associated racks 110. In at least one embodiment, the CDU 112 is capable of complex control of the coolant within the provided coolant loops 106, 108 independently or simultaneously. In at least one embodiment, the CDU is adapted to control the flow rate of the coolant such that the coolant is appropriately distributed to extract heat generated within the associated racks 110. In at least one embodiment, more flexible plumbing 114 is provided from the auxiliary cooling loop 108 to enter each server tray to provide coolant to the electrical and / or computing components therein.

[0060] In at least one embodiment, the pipe fitting 118 that forms part of the auxiliary cooling circuit 108 may be referred to as a chamber manifold. Separately, in at least one embodiment, the additional pipe fitting 116 may extend from the row manifold pipe fitting 118 and may also be part of the auxiliary cooling circuit 108, but may be referred to as a row manifold. In at least one embodiment, the coolant pipe fitting 114 enters the rack as part of the auxiliary cooling circuit 108, but may be referred to as a rack cooling manifold within one or more racks. In at least one embodiment, the row manifold 116 extends along the rows in the data center 100 to all the racks. In at least one embodiment, the plumbing of the auxiliary cooling circuit 108 including the coolant manifolds 118, 116, and 114 may be improved by at least one embodiment herein. In at least one embodiment, a cooler 120 may be provided in the primary cooling circuit within the data center 102 to support cooling prior to the cooling tower. In at least one embodiment, for the present disclosure, an additional cooling circuit that may be present in the primary control circuit and that provides cooling external to the racks and external to the auxiliary cooling circuit may be separate from the primary cooling circuit and different from the auxiliary cooling circuit.

[0061] In at least one embodiment, in operation, the heat generated within the server trays of the provided racks 110 may be transferred via the flexible pipe fittings of the row manifold 114 of the second cooling circuit 108 to the coolant exiting one or more of the racks 110. In at least one embodiment, the second coolant (in the second cooling circuit 108) from the CDU 112 for cooling the provided racks 110 moves via the provided pipe fittings toward one or more of the racks 110. In at least one embodiment, the second coolant from the CDU 112 is transferred from one side of the chamber manifold having the pipe fitting 118 via the row manifold 116 to one side of the rack 110 and passes through one side of the server tray via a different pipe fitting 114. In at least one embodiment, the used or returned second coolant (or the exiting second coolant carrying heat from the computing components) exits from the other side of the server tray (such as entering the left side of the rack for the server tray and exiting the right side of the rack for the server tray after circulating through the server tray or through the components on the server tray). In at least one embodiment, the used second coolant exiting the server tray or the rack 110 exits from a different side (such as the exit side) of the pipe fitting 114 and moves to the parallel but also exiting side of the row manifold 116. In at least one embodiment, the used second coolant moves in the parallel portion of the chamber manifold 118 from the row manifold 116 and travels toward the CDU 112 in a direction opposite to the entering second coolant (which may also be a fresher second coolant).

[0062] In at least one embodiment, the used secondary coolant exchanges its heat with the primary coolant in the primary cooling loop 106 via the CDU 112. In at least one embodiment, the used secondary coolant can be refreshed (such as relatively cooled when compared to the temperature of the used secondary coolant stage) and be ready to cycle back to one or more computing components via the secondary cooling loop 108. In at least one embodiment, the various flow and temperature control features in the CDU 112 can control the heat exchanged from the used secondary coolant or the flow of the secondary coolant into and out of the CDU 112. In at least one embodiment, the CDU 112 can also control the flow of the primary coolant in the primary cooling loop 106.

[0063] In at least one embodiment, as Figure 2 shown, the server-level feature 200 can be associated with an adjustable fluid coupling of the data center cooling system. In at least one embodiment, the server-level feature 200 includes a server tray or enclosure 202. In at least one embodiment, the server tray or enclosure 202 includes a server manifold 204 that is inter-coupled between the provided cold plates 210A-D of the server tray or enclosure 202 and the rack manifold of the rack that houses the server tray or enclosure 202. In at least one embodiment, the server tray or enclosure 202 includes one or more cold plates 210A-D associated with one or more computing or data center components or devices 220A-D. In at least one embodiment, one or more of the cold plates 210A-D can be a cold plate having the ability to support two different types of coolants via provisions such as a first tube 270B or using fins or a second tube 270A, where such a feature allows different coolant flows without mixing the different coolants.

[0064] In at least one embodiment, one or more server-level cooling loops 214A, 214B can be provided between the server manifold 204 and one or more of the cold plates 210A-D for dual-coolant cold plates. In at least one embodiment, each server-level cooling loop 214A, 214B includes an inlet line 210 and an outlet line 212. In at least one embodiment, when there are cold plates 210A, 210B in a series configuration, an intermediate line 216 can be provided. In at least one embodiment, for the data center cooling system, different paths can be established via the provided lines 276A, B between the channels (illustrated as dashed lines) within the dual-coolant manifold 204, the dual-coolant manifold 204 being adapted to pass a first coolant through different provided lines 206A, B and a second coolant through the provided lines 208A, B associated with these provided channels.

[0065] In at least one embodiment, one or more cold plates 210A-D can support only a single coolant and can use a single feature of fins or tubes to allow the coolant to flow therethrough. In at least one embodiment, when applicable to dual coolants, one or more cold plates 210A-D can support different ports and channels for an auxiliary coolant for an auxiliary cooling loop associated with the CDU and a local coolant circulated from a local coolant source. In at least one embodiment, a fluid for cooling (such as a second coolant) can be provided to the server manifold 204 via provided inlets and outlets 206A, 206B. In at least one embodiment, a local coolant for cooling can be provided to the server manifold 204 via the provided inlets and outlets 208A, 208B. In at least one embodiment, all such manifolds, pipelines, or loops can be terminated using a server-side flow controller having mechanical coupling and electrical coupling features. In at least one embodiment, the electrical coupling feature enables at least one processor to control aspects of the adjustable fluid coupling, including one or more flow controllers associated therewith. In at least one embodiment, such manifolds, pipelines, or loops within the server tray or enclosure 202 terminate at one or more server-side flow controllers that will be coupled to an adjustable fluid coupling in a data center cooling system.

[0066] In at least one embodiment, the server tray 202 is an immersion-cooled server tray that can be fluidly submerged. In at least one embodiment, the fluid for the immersion-cooled server tray can be a dielectric engineered fluid capable of being used in an immersion-cooled server. In at least one embodiment, an auxiliary coolant or a local coolant can be used to cool the engineered fluid. In at least one embodiment, the local coolant can be used to cool the engineered fluid when the primary cooling loop associated with the auxiliary cooling loop circulating the auxiliary coolant has failed or is failing. In at least one embodiment, at least one cold plate thus has a port for the auxiliary cooling loop of the adjustable fluid coupling and can support the local coolant that is activated in the event of a failure of the primary cooling loop. In at least one embodiment, the adjustable fluid coupling for the data center cooling system can be mounted in a rack as a bracket or a cooling manifold.

[0067] In at least one embodiment, at least one dual-cooling cold plate 210B; 250 can be configured to work beside conventional cold plates 210A, C, D. In at least one embodiment, a three-dimensional (3D) exploded view (of cold plate 250) provides internal details of at least some features that may be included in a dual-cooling cold plate or a conventional cold plate. In at least one embodiment, a tear-away view of cold plate 250 shows microchannels 270, 270A. In at least one embodiment, different second sections can be provided side by side and have a set of pipe fittings 264. In at least one embodiment, a locally coolant-enabled cold plate can have a set of pipe fittings 264 and no microchannels 270, 270A therein, or can have only such microchannels 270, 270A and no pipe fittings 264 therein.

[0068] In at least one embodiment, the dual-cooling cold plate 250 has different paths 264, 270 for an auxiliary coolant for an auxiliary cooling loop and a local coolant from a local cooling source, both docked through an adjustable fluid coupling for a data center cooling system. In at least one embodiment, in the case of the use of an immersion-cooled server, a fluid that can be a dielectric engineered fluid can be applicable to both cold plate applications and immersion-cooled server tray applications. In at least one embodiment, some microchannels 270 are paths provided by fins 270A or other such aspects that are elevated internally and perpendicular to the base of the cold plate section and have a gap therebetween for coolant or fluid flow. In at least one embodiment, some microchannels 270, 270A are fluid passages in different cold plate sections of cold plate 250.

[0069] In at least one embodiment, a reference to a cold plate along with its dual-cooling feature can imply a reference to a cold plate that can support at least two types of cooling loops, unless otherwise stated. In at least one embodiment, two types of cold plates at least receive an auxiliary coolant for cooling, but one type can support both an auxiliary cooling loop or a local cooling loop, as well as an adjustable fluid coupler, thereby providing a plug-and-play mounting capability for a rack and thus supporting any type of server-side flow controller. In at least one embodiment, a standard coolant such as facility water can be used in the auxiliary cooling loop.

[0070] In at least one embodiment, a fluid (such as an auxiliary coolant or a local coolant) can only support the use of cold plates and is not available for immersion cooling. In at least one embodiment, each type of cold plate receives coolant through an adjustable fluid coupling for a data center cooling system, which may include a plurality of flow controller adapters for different auxiliary or local coolants from corresponding local cooling loops or other cooling loops interfacing with the main cooling loop. In at least one embodiment, in the case of using different fluids (such as auxiliary coolant and local coolant) in a data center cooling system, the auxiliary or local cooling loop can be adapted for dual-cooling cold plates and adjustable fluid couplings such that different channels can be used for each of the local coolants and for different auxiliary or local coolants.

[0071] In at least one embodiment, the dual-cooling cold plate 250 is adapted to receive two types of fluids (such as an auxiliary coolant and a local coolant) and keep the two types of fluids distinct from each other via their different ports 252, 272; 268, 262 and their different paths 264, 270, for example, by different sections separated by gaskets and plates (such as in a gasket-type cold plate). In at least one embodiment, the fluid lines 256, 258, 266, 274 are associated with such ports 225, 262, 268, 272 via respective flow controllers. In at least one embodiment, each different path is a cooling path. In at least one embodiment, fluids (such as local coolant) from a local coolant source and an auxiliary coolant can be provided simultaneously to address additional cooling requirements. In at least one embodiment, the different ports and paths can support different sources that can be provided to address higher cooling requirements from associated computing devices.

[0072] In at least one embodiment, the dual-cooling cold plate 250 includes ports 252, 272 to receive local coolant into the cold plate 250 such that this local coolant can pass through a set of tubes 264 and such that this local coolant can flow out of the cold plate 250. In at least one embodiment, the dual-cooling cold plate 250 includes ports 268, 262 to receive auxiliary coolant or local coolant into the cold plate 250 and let the local coolant or auxiliary coolant flow out of the cold plate 250. In at least one embodiment, the ports 252, 272 can have valve caps 254, 260, which can be oriented and pressure-controlled such that the local coolant or local coolant can flow through the cold plate 250.

[0073] In at least one embodiment, such valve covers can be controlled in a manner that allows coolant at a determined flow rate or flow volume to pass therethrough. In at least one embodiment, opening such a valve cover allows sufficient liquid to flow through the valve portion of the flow controller and into a set of tubes or microchannels of the cold plate. In at least one embodiment, the valve cover can be associated with all of the provided ports of the cold plate. In at least one embodiment, the provided valve covers 254, 260 are mechanical features of an associated flow controller or flow controller adapter, which may also have corresponding electronic features (such as at least one processor that executes instructions stored in an associated memory and controls the mechanical features for the associated flow controller or flow controller adapter).

[0074] In at least one embodiment, each valve can be actuated by the electronic features of an associated flow controller or flow controller adapter. In at least one embodiment, the electronic and mechanical features of the provided flow controller or flow controller adapter are integrated. In at least one embodiment, the electronic and mechanical features of the provided flow controller or flow controller adapter are physically distinct. In at least one embodiment, reference to a flow controller or flow controller adapter can be a reference to one or more of the provided electronic and mechanical features or a combination thereof, but at least a reference to features capable of controlling the flow of coolant or fluid through each cold plate or an immersion-cooled server tray or enclosure.

[0075] In at least one embodiment, the electronic features of the provided flow controller receive a control signal and assert control over the mechanical features. In at least one embodiment, the electronic features of the provided flow controller can be other electronic components such as an actuator or other similar electromechanical features. In at least one embodiment, a flow pump can be used as a flow controller. In at least one embodiment, an impeller, piston, or bellows can be mechanical features, and an electric motor and circuitry form the electronic features of the provided flow controller or flow controller adapter.

[0076] In at least one embodiment, the circuitry of the provided flow controller or flow controller adapter can include a processor, a memory, a switch, sensors, and other components that together form the electronic characteristics of the provided flow controller. In at least one embodiment, the provided ports 252, 262, 272, 268 of the provided flow controller are adapted to allow immersion fluid to enter or to allow immersion fluid to exit. In at least one embodiment, a flow controller 280 (capable of acting as an expansion valve) can be associated with fluid lines 276A, 276B (also 256, 274), which enable local coolant to enter and exit cold plates 210B and 210B. In at least one embodiment, other flow controllers can be similarly associated with coolant lines 210, 216, 212 (also 266, 258) to enable auxiliary coolant to enter and exit cold plates 210B, 210D.

[0077] In at least one embodiment, local coolant enters the provided fluid lines 276A, B via dedicated inlet line 208A and outlet line 208B. In at least one embodiment, the server manifold 204 is adapted to the channels therein (shown by dash or dotted lines) to support different paths to different fluid lines 276A, 276B (also 256, 274) and to any remaining loops 214A, 214B associated with auxiliary coolant inlet and outlet lines 206A, 206B. In at least one embodiment, there can be multiple manifolds to differently support different local coolants and auxiliary coolants via different adjustable fluid couplings for a data center cooling system. In at least one embodiment, there can be multiple manifolds to differently support the inlets and outlets of each provided adjustable fluid coupling having support for local coolant or for auxiliary coolant. In at least one embodiment, such adjustable fluid couplings for a data center cooling system can be used alone with a local coolant source and without an auxiliary cooling loop or CDU.

[0078] In at least one embodiment, as Figure 3The rack-level feature 300 shown in [Figure] can be associated with an intelligent flow controller adapter and a cooling manifold of a data center cooling system. In at least one embodiment, the rack-level feature 300 includes a rack 302 having brackets 304, 306 to suspend the cooling manifolds 314A, 314B. In at least one embodiment, although the rack 330 is shown separately from the rack 302, the rack 330 can show a rear perspective view of the rack 302. In at least one embodiment, similarly, the brackets 334, 336 provided on the rack 330 are perspective views of the brackets 304, 306 provided on the rack 302. In at least one embodiment, the brackets 304, 306 provided for the rack are flat structures against the inner wall of the rack. In at least one embodiment, the brackets 304, 306 provided for the rack extend from the inner wall of the rack. In at least one embodiment, the brackets 304, 306 provided for the rack are attached to the inner wall of the rack and have a plurality of mounting points 348, 350 facing one or more directions (including inside the rack or towards the rear of the rack). In at least one embodiment, the cooling manifolds 314A, 314B can be provided to allow an auxiliary coolant or a local coolant to pass between the server-level feature 200 (and shown as the server tray or enclosure 308 in [Figure]) and the CDU of the auxiliary cooling circuit or the local cooling circuit of the data center cooling system (such as Figure 3 shown as the server tray or enclosure 308) and the CDU (such as Figure 4 the CDU 406) of the auxiliary cooling circuit or the local cooling circuit of the data center cooling system. In at least one embodiment, different CDUs can serve different racks. In at least one embodiment, different rack cooling manifolds can differently be part of the auxiliary cooling circuit and the local cooling circuit.

[0079] In at least one embodiment, the data center cooling system has interchangeable flow controller adapters 356A, 356B that can move within the cooling manifold or bracket 352A of the rack 302 (or the cooling manifold or bracket 352A of the rack 330). In at least one embodiment, the flow controller adapters 356A, 356B include grooves 356E to enable movement in at least one direction along a dimension relative to the cooling manifold 352B in the provided path. In at least one embodiment, tabs or other fixing features 340 can be provided to fix the cooling manifold 352B to the brackets 334, 336 of the rack. In at least one embodiment, the tabs or other fixing features 340 can be equipped with hinges to enable folding when not in use or to enable fixing the cooling manifold 352B in one or more different rotational orientations around the brackets 334, 336.

[0080] In at least one embodiment, the flow controller adapters 356A; 356B of the cooling manifold 352B interchangeably receive individual ones of several such first flow controllers 356C; 356D. In at least one embodiment, such first flow controllers 356C; 356D are interchangeable flow controllers 356C; 356D. In at least one embodiment, the flow controller adapters 356A, 356B may be associated with the rack side flow controllers 354A, 354B. In at least one embodiment, there may be tubes 358A; 358B therebetween to allow the flow controller adapters 356A; 356B to move within the cooling manifold 352B. In at least one embodiment, such a tube 358A may be a flexible tube. In at least one embodiment, the flow controller adapters 356A, 356B are configured to be movable within the cooling manifold to allow for different positions for mating an individual one of the provided interchangeable flow controllers 356C; 356D with a server side flow controller (such as, Figure 2 the flow controller 278 of the server tray or enclosure 202 in

[0081] In at least one embodiment, such server side flow controllers 278 project externally facing the rear of the rack 302 and allow the server tray or enclosure 308 to be pushed back into the rack 302. In at least one embodiment, this enables coupling between the server side flow controllers 278 and between such interchangeable flow controllers 356C, 356D with the brackets or cooling manifolds 352A; 352B, which may be on the outlet side and / or the inlet side of the server tray or enclosure 308. In at least one embodiment, the flow controller adapters 356A; 356B are associated with interchangeable flow controllers 356C; 356D of a determined type, based in part on the type of server side flow controller 278 available on the server tray or enclosure 308. In at least one embodiment, at least one type of interchangeable flow controller 356C (or 356D) may be associated with each of the flow controller adapters 356A, 356B.

[0082] Thus, in at least one embodiment, such interchangeable flow controllers 356C; 356D include at least different first orifice sizes and / or different first coupling features on at least a first side; and a determined second orifice size and a determined second coupling feature 356F on a second side. In at least one embodiment, the determined second orifice size and the determined second coupling feature 356F (the determined second orifice size and the determined second coupling feature) may be standard features that match the orifice size and the second coupling feature 356G of the flow controller adapters 356A; 356B. In at least one embodiment, the interchangeable flow controllers 356C; 356D may be press-fit or threaded to the flow controller adapters 356A; 356B.

[0083] In at least one embodiment, at least one processor may be associated with a first flow controller and a second flow controller among a plurality of interchangeable flow controllers 356C; 356D. In at least one embodiment, the first flow controller may be associated with a first rated flow rate metric of the coolant flow passing through it, and the second flow controller may be associated with a second rated flow rate metric of the coolant flow passing through it. In at least one embodiment, such a rated flow rate metric is the flow velocity or flow rate of the coolant flow that can be enabled by such interchangeable flow controllers. In at least one embodiment, at least one processor may achieve an expected flow velocity of the cold plate from the first flow controller or the second flow controller, at least in part based on information associated with the first rated flow rate metric and the second rated flow rate metric.

[0084] In at least one embodiment, the first rated flow rate metric of the first coolant for the first flow controller may be associated with the thermodynamic properties of such coolant. Thus, in at least one embodiment, the second rated flow rate metric of the second coolant for the second flow controller may be associated with the thermodynamic properties of the second coolant. Thus, in at least one embodiment, sensors, flow controller adapters are capable of determining the type of coolant and the type of flow controller associated therewith. In at least one embodiment, prior data of the flow controller and the coolant are stored in a memory location associated with at least one processor capable of controlling the flow controller adapter. In at least one embodiment, upon detection of a type of coolant associated with specific thermodynamic properties of a different type of coolant, the change in the thermodynamic properties may be registered by the processor. In at least one embodiment, the processor may then be capable of adjusting the flow controller adapter to provide a determined flow rate and pressure of the coolant to meet the cooling requirements. In at least one embodiment, a system having such interchangeable flow controllers may not be aware of the type of coolant.

[0085] In at least one embodiment, the previous flow rate and previous pressure of each flow controller associated with different cooling requirements, along with the thermodynamic properties of different coolants, can be stored in a memory as part of such previous data. Thus, in at least one embodiment, based in part on the type of coolant and in part on the type of flow controller associated with the flow controller adapter, it can be enabled to pass a coolant of a determined flow rate and flow from the flow controller adapter through the flow controller interchangeably associated with the flow controller adapter. In at least one embodiment, a pH sensor can be provided in the flow controller adapter. In at least one embodiment, the pH sensor can provide the sensed pH information to at least one processor to enable determination of the thermodynamic properties of the associated coolant.

[0086] In at least one embodiment, at least one processor can access the previous pH information and previous thermodynamic properties of the coolant. In at least one embodiment, at least one processor can include at least one logic unit that executes a trained neural network to infer the thermodynamic properties of the coolant in use from such sensed pH information. In at least one embodiment, at least one processor can cause at least one flow controller adapter or associated flow controller to adjust the flow rate and / or flow of the coolant within the ratings of the flow controller to address the cooling requirements.

[0087] In at least one embodiment, this enables, regardless of the orifice size of the interchangeable flow controllers 356C; 356D used, depending on the cooling requirements of the cold plate, a flow metric (such as flow rate and / or flow) to be enabled by at least one processor. In at least one embodiment, tagging can be enabled in at least one processor based in part on the identification of the type of interchangeable flow controllers 356C; 356D that can be associated with the flow controller adapters 356A, 356B. In at least one embodiment, information related to the rated flow metrics of different interchangeable flow controllers 356C; 356D is stored. In at least one embodiment, the identification of a particular interchangeable flow controller 356C; 356D can be implemented to enable specific control of the interchangeable flow controllers 356C; 356D based in part on such stored information.

[0088] In at least one embodiment, based in part on such information, the valves of the interchangeable flow controllers 356C; 356D can be controlled to open partially or fully to meet the expected flow rate metric for the cooling demand. In at least one embodiment, a partial opening is sufficient for the interchangeable flow controllers 356C; 356D with a larger orifice size, but the interchangeable flow controllers 356C; 356D with a smaller orifice size require a full opening. In at least one embodiment, based in part on such information, the pumps of the interchangeable flow controllers 356C; 356D can be controlled to apply a certain pressure to meet the expected flow rate metric for the cooling demand. However, in at least one embodiment, some of the interchangeable flow controllers 356C; 356D can have pump limitations, and thus such information enables unified and appropriate control over different types of interchangeable flow controllers 356C; 356D.

[0089] In at least one embodiment, such control depends on the flow controller adapters 356A, 356B such that the valves or pumps associated with the flow controller adapters 356A, 356B can be adjusted based in part on the associated flow controllers in the interchangeable flow controllers 356C; 356D. Therefore, in at least one embodiment, the interchangeable flow controllers 356C; 356D can be replaced without having to fully adapt the electrical couplers dedicated to this type of interchangeable flow controllers 356C; 356D. Instead, such electrical coupling can be provided at the flow controller adapter 356A. Thus, in at least one embodiment, at least one adapted processor can adjust the flow controller adapter to achieve the expected flow rate metric based in part on the proportional metric from the first rated flow rate metric and the second rated flow rate metric.

[0090] In at least one embodiment, the interchangeable flow controllers 356C; 356D can be associated with the rack-side flow controllers 354A; 354B and with the tubes 358A; 358B therebetween. In at least one embodiment, the tubes 358A; 358B provided for the flow controller adapters 356A; 356B are flexible tubes having a length sufficient to allow the flow controller adapters 356A; 356B to traverse via the groove 356E the tracks 362 formed on the top and bottom of the channel 360 of the cooling manifold 352B.

[0091] In at least one embodiment, the flow controller adapters 356A; 356B can move in at least one direction with respect to the dimensions of the cooling manifold 352B. In at least one embodiment, the flow controller adapters 356A; 356B can be positioned to mate the associated interchangeable flow controllers 356C; 356D (e.g., after moving to a position within the provided track 362) with the server-side flow controllers, which have matching orifice sizes and / or coupling features to enable such mating. In at least one embodiment, the mating is with respect to a server tray or enclosure that has its own corresponding flow controller (third flow controller). In at least one embodiment, at least one rack-side flow controller 354A; 354B for a fixed flow controller can mate with another corresponding flow controller 342; 346 of the rack manifolds 338; 344 (314A; 314B).

[0092] In at least one embodiment, at least one processor can be provided to enable fluid to flow through one or more of the following: flow controller adapters 356A; 356B and / or interchangeable flow controllers 356C; 356D. In at least one embodiment, all aspects of the mechanical or electrical features can be similar to the flow controller adapters 356A; 356B and the interchangeable flow controllers 356C; 356D. In at least one embodiment, the flow controller adapters 356A; 356B can include a groove 356E to be placed into the provided track 362 of the cooling manifold 352B and be movable within the track 362. In at least one embodiment, the flow controller adapters 356A; 356B can move in a provided path (e.g., track 362) in at least one direction within the cooling manifold. In at least one embodiment, a position lock 370 (e.g., a wing nut) can be associated with the provided path to lock the flow controller adapter in a determined position to align the multiple interchangeable flow controllers 356C; 356D with the multiple server-side flow controllers 278 of the server tray or enclosure 302, which can be in a fixed position for the server tray or enclosure.

[0093] In at least one embodiment, at least one processor may be provided to receive sensor inputs from sensors associated with flow controller adapters 356A; 356B and / or interchangeable flow controllers 356C; 356D. In at least one embodiment, the at least one processor may be capable of determining a first change in coolant state, at least in part based on the sensor inputs, and causing a stoppage or change of fluid flow through one or more of flow controller adapters 356A; 356B and / or interchangeable flow controllers 356C; 356D associated with coolant manifold 352B. In at least one embodiment, the sensors may be leak sensors, humidity sensors, temperature sensors, or other suitable sensor uses for determining whether coolant flow is effective, whether coolant flow is appropriate, and whether coolant flow remains unchanged from rack manifolds 338; 344 to coolant manifold 352B. In at least one embodiment, a single rack manifold may be used to circulate the coolant of the auxiliary coolant loop instead of the two rack manifolds shown in the figure.

[0094] In at least one embodiment, one or more neural networks may be adapted to receive sensor inputs from sensors and may be capable of reasoning about changes in coolant state. In at least one embodiment, using previous coolant states and previous sensor inputs, one or more neural networks may be trained to make such inferences such that when new sensor inputs are related to previous sensor inputs, the previous coolant state of the previous sensor inputs may be the coolant state of the received sensor inputs.

[0095] In at least one embodiment, a fast response time may be enabled for one or more of the plurality of flow controllers interchangeable with the flow controller adapter. In at least one embodiment, a fast response time may be enabled for the flow controller adapter. In at least one embodiment, the electronic and mechanical features, electric motor, and circuitry, which may include an impeller, piston, or bellows, also enable a solenoid valve to react to provide such a fast leak control. In at least one embodiment, the fast response is within 5 seconds, but may be within 10 seconds.

[0096] In at least one embodiment, at least one processor may be provided to effect an electrical disconnect of the cooling manifold 352B and to effect replacement of the cooling manifold 352B. In at least one embodiment, the cooling manifold or bracket 352B includes an electrical coupler 368 that may have a digital switch addressable by an input from the at least one processor. In at least one embodiment, a valve or other mechanical feature associated with the flow controller adapters 356A; 356B and / or the interchangeable flow controllers 356C; 356D may be activated or controlled via an input to an electrical feature such as an actuator 364 coupled to an arm 366, which may be adapted to operate the valve or other mechanical feature such as a pump. In at least one embodiment, the at least one processor may provide an input to an electrical feature of the flow controller adapter to cause the arm 366 to open, close, or throttle a valve within the flow controller adapters 356A; 356B and / or the interchangeable flow controllers 356C; 356D. In at least one embodiment, such features may also be present in the rack side flow controller 354A associated with the rack manifold. In at least one embodiment, all provided flow controllers are enabled for push coupling such that fluid flow may commence upon coupling. In at least one embodiment, a sensor may be provided to delay fluid flow until several seconds after coupling to ensure no leakage occurs upon push coupling.

[0097] In at least one embodiment, the flow controller adapters 356A; 356B and / or the interchangeable flow controllers 356C; 356D may be associated with the rack side flow controllers 354A; 354B via tubing 358A; 358B within the cooling manifold 352B. In at least one embodiment, the flexible tubing is adapted to extend as the flow controller adapter moves in at least one direction. In at least one embodiment, the flexible tubing enables fluid to flow from the rack side flow controller 354A to the flow controller adapters 356A; 356B and / or the interchangeable flow controllers 356C; 356D.

[0098] In at least one embodiment, two rack manifolds 338, 344 may be associated with the provided brackets 334, 336. In at least one embodiment, the two rack manifolds 338, 344 are associated with the provided brackets 334, 336 via tabs 340 to allow the flow controllers 342, 346 to face into the rack 330. In at least one embodiment, the tabs 340 are provided offset such that the brackets 334, 336 do not interfere with the coupling of the provided flow controllers 342, 346 of the rack manifolds. In at least one embodiment, the cooling manifold 352B may be prepared for push coupling by first adjusting its flow controller adapter to the position of the server tray or the rack. In at least one embodiment, the cooling manifold 352B may be push-coupled with the flow controllers 342, 346 of the provided rack manifolds 338, 344, and this push coupling may be sufficient to hold the cooling manifold against the rack manifold without additional securing means. In at least one embodiment, wing nuts or other position locks may be used with the flow controller adapter and may be used to associate the cooling manifold with the bracket.

[0099] In at least one embodiment, the cooling manifold 352B may be associated with one or more rack manifolds by a push coupling of a fixed flow controller with a corresponding flow controller of at least one of the one or more rack manifolds 338, 344. In at least one embodiment, the flow controller adapters 356A; 356B may be moved in at least one direction to a position in the cooling manifold 352B that aligns with the server tray flow controller of the server tray.

[0100] In at least one embodiment, in the event of a failure in the primary cooling loop, the secondary cooling loop, or the cooling facility, parameters such as flow rate, velocity, and the expected temperature of the local coolant (or secondary coolant) may be used to determine whether to allow the cooling manifold to be disconnected. In at least one embodiment, the SLA-specified downtime may be compensated for by parameters enabled for the local cooling loop such that sufficient redundant cooling may be provided by the local cooling loop until the failure of any one of the primary cooling loop, the secondary cooling loop, or the associated components can be repaired.

[0101] In at least one embodiment, in the event of a failure in the primary cooling loop, the secondary cooling loop, or the cooling facility, after the failure is determined, at least one processor may cause at least one of the flow controller adapters 356A; 356B and / or the interchangeable flow controllers 356C; 356D to engage the local cooling loop while closing the secondary cooling loop to at least one rack 302. In at least one embodiment, the flow controllers 310C, 312C may close the secondary cooling loop by diverting the secondary coolant flow via line 364 to a local cooling header different from the row header 350. In at least one embodiment, completely different lines 320, 354, 322 and the rack manifold may be used with the alternative cooling header.

[0102] In at least one embodiment, as Figure 4 shown, the data center-level feature 400 may be associated with an adjustable fluid coupling for a data center cooling system. In at least one embodiment, the data center-level feature 400, within the data center 402, may include: racks 404 for hosting one or more server trays or enclosures; one or more CDUs 406 for exchanging heat between the secondary cooling loop 412 and the primary cooling loop 422; one or more row headers 410 for distributing coolant from the CDU 406; and associated various flow controllers 424, as well as inlet and outlet lines 412, 414, 416, 418.

[0103] In at least one embodiment, an adjustable fluid coupling via a cooling manifold or bracket is provided for the back door of each rack 404. In at least one embodiment, the aisle behind the rack 404 is a hot aisle for exhausting heat from at least one computing device in at least one of the racks. In at least one embodiment, different row headers 410 may be associated with different racks 404. In at least one embodiment, different coolants may be chemically matched or mismatched relative to the local coolant. In at least one embodiment, depending on the chemical nature of the different secondary coolants used with each of the different CDUs provided, different fluid sources are provided as redundant features to the different CDUs.

[0104] In at least one embodiment, a processor having one or more circuits can be associated with all such flow controllers that form an adjustable fluid coupling in a data center cooling system. In at least one embodiment, the adjustable fluid coupling in the data center cooling system can be associated with a plurality of cooling manifolds or brackets, each of which has a flow controller adapter, a rack-side flow controller, an interchangeable flow controller, and a tube between each rack-side flow controller and the interchangeable flow controller. In at least one embodiment, the flow controller adapter can be moved within the cooling manifold such that it can be adjusted to couple with a server-side flow controller having a specific orifice size and specific coupling features provided with a server tray or enclosure. In at least one embodiment, the adjustable fluid coupling in the data center cooling system can be provided on both sides of the cooling manifold for further flexibility in coupling with a rack manifold on one side and a server tray or enclosure on the other side. In at least one embodiment, the space within the cooling manifold and the provided tracks protect the tubes disposed therein from additional exposure to elements of flexible tubes used in the absence of the cooling manifold.

[0105] In at least one embodiment, the flow controller adapter is movable in at least one direction with respect to the dimensions of the cooling manifold. In at least one embodiment, the flow controller adapter can be adapted to horizontal and vertical channels. In at least one embodiment, diagonal channels or spaces (and associated paths) can be provided in the cooling manifold or bracket to enable the flow controller adapter to move further in multiple directions. In at least one embodiment, one or more circuits of the processor can be adapted to cause the flow controller adapter to transfer fluid to the server tray or enclosure via a fixed flow controller and a tube. In at least one embodiment, this allows the flow controller adapter to block fluid from flowing therethrough while selecting an interchangeable flow controller and associating the interchangeable flow controller with the flow controller adapter. In at least one embodiment, the server tray or enclosure can then be associated with the data center cooling system regardless of a mismatch between the server-side flow controller and the flow controller of the rack manifold.

[0106] In at least one embodiment, a processor may include an output to provide a signal to one or more of a flow controller adapter or an interchangeable flow controller. In at least one embodiment, this may enable fluid in a cooling loop to flow from a rack manifold to a cooling manifold or bracket, to a server manifold, and to a cold plate associated with at least one computing device. In at least one embodiment, the processor may include an input to receive sensor input from sensors associated with one or more of the flow controller adapter or the interchangeable flow controller. In at least one embodiment, the sensors may be capable of sensing leaks, humidity, temperature, flow rate, flow volume, or other parameters as may be desired to direct coolant flow to the receiving cold plate.

[0107] In at least one embodiment, the processor may be adapted to determine that a change in coolant state may be determined, in part, based on sensor input from sensors capable of detecting one or more of the above parameters. In at least one embodiment, the reference to sensors may include sensor assemblies for sensing one or more of the above parameters, but different sensors may alternatively be used. In at least one embodiment, one or more circuits of the processor may be adapted to cause or allow one or more of the flow controller adapter or the interchangeable flow controller to stop or effect a change in fluid flow as a result of information determined using the provided sensor input.

[0108] In at least one embodiment, one or more neural networks may be provided in one or more circuits of the processor. In at least one embodiment, the one or more neural networks may be adapted to receive sensor input and infer a change in coolant state. In at least one embodiment, one or more neural networks of the processor may be adapted to infer a failure of an auxiliary cooling loop or a primary cooling loop. In at least one embodiment, one or more circuits of the processor may be adapted to cause one or more of the flow controller adapter or a fixed flow controller to prevent fluid from flowing therebetween.

[0109] In at least one embodiment, the processor has one or more circuits and may be associated with a flow controller adapter. In at least one embodiment, the flow controller adapter may further be associated with an interchangeable flow controller and a rack-side flow controller. In at least one embodiment, the flow controller adapter may be movable within the cooling manifold in at least one direction with respect to the dimensions of the cooling manifold. In at least one embodiment, one or more circuits of the processor may be adapted to train one or more neural networks to infer a change in coolant state from sensor inputs of one or more sensors associated with one or more of the flow controller adapter or the interchangeable flow controller. In at least one embodiment, the processor may be adapted to cause a stop or a change in the fluid flow through one or more of the flow controller adapter or the interchangeable flow controller. In at least one embodiment, this may be accomplished by sending a signal to an actuator, such as Figure 3 as described in

[0110] In at least one embodiment, an output of the processor may provide a signal to one or more of the flow controller adapter or the interchangeable flow controller within the cooling manifold. In at least one embodiment, this may effectuate the flow of fluid in a cooling loop from a rack manifold to the cooling manifold, through a server manifold, and through a cold plate. In at least one embodiment, the processor may be adapted to include one or more neural networks for receiving sensor inputs and may be trained to infer a change in coolant state as part of an analysis of previous sensor inputs and previous coolant states.

[0111] In at least one embodiment, the processor may include an output to provide a signal to one or more of the flow controller adapter or the interchangeable flow controller. In at least one embodiment, such a signal may effectuate engaging the cooling manifold based in part on a first threshold cooling requirement of at least one computing device and engaging an auxiliary cooling loop based in part on a second threshold cooling requirement of at least one computing device. In at least one embodiment, this enables the use of a local cooling loop with a cooling manifold differently than a second cooling loop.

[0112] In at least one embodiment, an input to a processor can be provided to enable receipt of sensor input in the processor. In at least one embodiment, the sensor input received in the processor can be associated with the temperature of a fluid from at least one computing device or from a cold plate that is to be passed or is passing through at least one computing device. In at least one embodiment, one or more neural networks can be trained to reason that a change in coolant state has occurred, based at least in part on the temperature and a previous temperature. In at least one embodiment, the temperature or the previous temperature can be associated with a particular coolant. In at least one embodiment, one or more circuits of the processor can be adapted to cause a stop or a change in the flow of fluid through one or more of a flow controller adapter or an interchangeable flow controller.

[0113] In at least one embodiment, a processor having one or more circuits can be associated with a flow controller adapter and an interchangeable flow controller. In at least one embodiment, the flow controller adapter can move within a cooling manifold in at least one direction, and one or more circuits of the processor can be adapted to include one or more neural networks. In at least one embodiment, one or more neural networks can reason that a change in coolant state has occurred from sensor input from one or more sensors associated with one or more of the flow controller adapter or a fixed flow controller. In at least one embodiment, the processor can be adapted to cause a stop or a change in the flow of fluid through one or more of the flow controller adapter to a fixed flow controller.

[0114] In at least one embodiment, throughout Figures 1 to 4Each of the at least one processors described has inference and / or training logic 615, which can include but is not limited to: code and / or data storage device 601 for storing forwarding and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the training logic 615 can include or be coupled to a code and / or data storage device 601 for storing graphical code or other software for controlling timing and / or sequence, where the weights and / or other parameter information can be loaded for configuring logic including integer and / or floating-point units (collectively arithmetic logic units (ALUs)). In at least one embodiment, code such as graphical code loads weight or other parameter information into the processor ALU based on the architecture of the neural network corresponding to such code. In at least one embodiment, the code and / or data storage device 601 stores weight parameters and / or input / output data for each layer of the neural network used or trained during training and / or inference during forward propagation of input / output data and / or weight parameters in conjunction with one or more embodiments. In at least one embodiment, any part of the code and / or data storage device 601 can be included with other on-chip or off-chip data storage devices, including the L1, L2, or L3 cache of the processor or system memory.

[0115] In at least one embodiment, the inference and / or training logic 615 of at least one processor can be part of a building management system (BMS) for controlling traffic controllers at one or more of the server level, rack level, and row level. In at least one embodiment, determination of engaging a flow controller associated with a local cooling loop, a smart flow controller adapter, and a cooling manifold, CDU, cold plate, or other cooling manifold can be provided to one or more neural networks of the inference and / or training logic 615 such that one or more neural networks infer at least which flow controller adapter or interchangeable flow controller engages or disengages appropriately for replacement of a server tray or enclosure or for coolant requirements of one or more cold plates, servers, or racks from an auxiliary cooling loop or local cooling loop. In at least one embodiment, an increase or decrease in fluid flow can be achieved by a flow controller adapter and / or interchangeable flow controller controlled by the inference and / or training logic 615 of at least one processor associated with control logic associated with the local cooling loop.

[0116] In at least one embodiment, at least one processor may be associated with a local cooling loop and with an auxiliary cooling loop. In at least one embodiment, at least one processor may be associated with a flow controller adapter and an interchangeable flow controller. In at least one embodiment, at least one processor includes control logic such as inference and / or training logic 615 and is associated with at least one of a flow controller adapter and an interchangeable flow controller. In at least one embodiment, at least one of the flow controller adapter and the interchangeable flow controller may have its own respective processor or microcontroller.

[0117] In at least one embodiment, a processor or microcontroller executes instructions sent to it from the control logic. In at least one embodiment, the control logic may be used to determine a change in coolant status, such as a fault in an auxiliary cooling loop (such as a CDU and a cooling manifold) or a primary cooling loop (such as a refrigeration facility, a cooling manifold, and also an associated CDU). In at least one embodiment, a fault may also occur for a cooling manifold that needs to be replaced. In at least one embodiment, the control logic may cause at least one flow controller to provide a coolant response, for example, by engaging a local cooling loop with a fluid source to provide local coolant or auxiliary coolant to at least one computing device.

[0118] In at least one embodiment, the control logic may cause a first signal to at least one flow controller to enable the stopping of auxiliary coolant from the auxiliary cooling loop as part of the coolant response. In at least one embodiment, the control logic may cause a second signal to at least one flow controller to enable the starting of local coolant from the local cooling loop as part of the coolant response. In at least one embodiment, signals are sent only to the flow controller adapter to enable temporarily stopping, enabling the removal of a server tray or enclosure, enabling the repositioning of the flow controller adapter, and enabling a push-coupling with a new server tray or enclosure that has a flow controller spaced differently from the server tray or enclosure it is replacing. In at least one embodiment, the control logic may receive sensor input from sensors associated with the auxiliary coolant, local coolant, and / or at least one computing device of the CDU. In at least one embodiment, at least one processor may determine a change in coolant status based in part on the sensor input. In at least one embodiment, one or more neural networks of the inference and / or training logic 615 may be adapted to receive the sensor input and infer a change in coolant status.

[0119] In at least one embodiment, at least one processor may include one or more circuits for one or more neural networks, such as inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 may be adapted to infer a change in coolant state from sensor inputs associated with at least one server or at least one rack, such as coolant from a CDU being ineffective or retaining too much heat when entering the rack. In at least one embodiment, one or more circuits may be adapted to cause at least one flow controller to provide a coolant response from a local cooling loop.

[0120] In at least one embodiment, control logic associated with one or more loops may cause a first signal (along with any associated signals) to at least one of a flow controller adapter and an interchangeable flow controller to enable a coolant response. In at least one embodiment, a second signal to at least one of a flow controller adapter and an interchangeable flow controller may also enable a coolant response. In at least one embodiment, one or more circuits of at least one processor enable a distributed or integrated architecture. In at least one embodiment, the distributed architecture may be supported by circuits located differently in one or more circuits. In at least one embodiment, at least one logic unit of a process may determine a change in coolant state based in part on a classification or clustering of sensor inputs relative to historical sensor inputs of a flow controller adapter and associated historical coolant states.

[0121] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 may be adapted to infer an increase or decrease in the cooling requirements of at least one computing component of at least one server. In at least one embodiment, one or more circuits may be adapted to cause a cooling loop to economically address a reduced cooling requirement or supplement an increased cooling requirement for at least one computing component. In at least one embodiment, enabling the cooling loop represents a coolant response from a local cooling loop that preempts a corresponding increase or corresponding decrease in the cooling requirements of at least one computing component of at least one server, based in part on the workload sent to at least one computing component.

[0122] In at least one embodiment, at least one processor includes one or more circuits (such as inference and / or training logic 615) that are configured to train one or more neural networks to make inferences based on the provided data. In at least one embodiment, the inference and / or training logic 615 may infer a change in coolant status from sensor inputs associated with at least one server or at least one rack. In at least one embodiment, inference may be used to enable one or more circuits to cause at least one of a flow controller adapter of a local cooling loop and an interchangeable flow controller to provide a coolant response. In at least one embodiment, the coolant response may cause a coolant response from the local cooling loop to absorb heat into the local coolant of the cooling manifold and exchange the absorbed heat to the environment, rather than having an auxiliary cooling loop with a CDU.

[0123] In at least one embodiment, one or more circuits may be adapted to train one or more neural networks to infer an increase or decrease in the cooling requirements of at least one computing component of at least one server. In at least one embodiment, one or more circuits may be adapted to train one or more neural networks to infer that an increase or decrease in the flow output from an auxiliary cooling loop associated with an increase or decrease in the power requirements of at least one computing component of at least one server due to a CDU failure or a corresponding increase or decrease is associated with an inappropriate flow of auxiliary coolant.

[0124] In at least one embodiment, one or more neural networks may be trained to make inferences based on previously associated thermal characteristics or cooling requirements from a computing device, server, or rack, and the cooling capacity or ability indicated by a fluid source of a local cooling loop. In at least one embodiment, previously satisfied cooling requirements of a local cooling loop may be used to enable one or more neural networks to make similar inferences in order to satisfy future similar cooling requirements (taking into account small changes thereto) by adjusting one or more flow controllers to engage the local cooling loop.

[0125] Figure 5 A method 500 associated with a Figures 2 to 4 data center cooling system according to at least one embodiment is shown. In at least one embodiment, method 500 herein includes providing (502) a flow controller adapter that is movable within a cooling manifold and adapted to interchangeably receive a flow controller from among a plurality of flow controllers. In at least one embodiment, method 500 herein includes determining (504) a flow controller from among the plurality of flow controllers for a server-side flow controller of a server tray or enclosure, based in part on a match of a determined orifice size and determined coupling characteristics of the server-side flow controller with such a flow controller from among the plurality of flow controllers that is interchangeable with the flow controller adapter.

[0126] In at least one embodiment, verification step 506 may be performed to confirm that the flow controller among the plurality of flow controllers has been determined by the matching performed in step 504. In at least one embodiment, step 504 may be repeated. In at least one embodiment, method 500 herein includes associating a flow controller adapter with the flow controller among the plurality of flow controllers (508). In at least one embodiment, the flow controller adapter is in one of different available positions to match such a flow controller with the server-side flow controller. In at least one embodiment, the server-side flow controller may be fixedly located on a server tray or enclosure provided by the manufacturer. In at least one embodiment, the flow controller adapter may be movable to allow alignment and mating of the flow controller with the server-side flow controller. In at least one embodiment, an inlet and an outlet flow controller may be present on the server side, and thus a plurality of flow controller adapters are provided, one for the inlet flow controller and another for the outlet flow controller. In at least one embodiment, another step in method 500 herein is for enabling (510) coolant to flow into the server tray or enclosure through the flow controller adapter, the flow controller among the plurality of flow controllers, and the server-side flow controller. In at least one embodiment, such enabling (510) may be an input from at least one processor to the flow controller or the flow controller adapter.

[0127] In at least one embodiment, at least one processor is used to determine the cooling requirement associated with at least one computing device. In at least one embodiment, method 500 herein includes further steps or sub-steps for flowing coolant through at least the flow controller adapter, the flow controller among the plurality of flow controllers, and the server-side flow controller, and for a cold plate associated with the cooling requirement.

[0128] In at least one embodiment, such method 500 herein includes another step or sub-step for determining the position of the flow controller adapter in different available positions in the cooling manifold. In at least one embodiment, method 500 herein includes further steps or sub-steps for enabling position locking using a position associated with a provided path in the cooling manifold. In at least one embodiment, such position locking may be used to lock the flow controller adapter in a position to align the flow controller among the plurality of flow controllers with the server-side flow controller of the server tray or enclosure.

[0129] In at least one embodiment, such a method 500 herein includes further steps or sub-steps for enabling a flow controller adapter to move in a provided path in at least one direction relative to the dimensions of a cooling manifold via a provided groove in the cooling manifold. In at least one embodiment, such a method 500 herein includes further steps or sub-steps for enabling a plurality of flow controllers to include at least different first orifice sizes and different first coupling features on at least a first side, and a determined second orifice size and a determined second coupling feature on a second side. In at least one embodiment, the determined second orifice size and the determined second coupling feature are provided to match the flow controller adapter. In at least one embodiment, similarly, a flow controller among the plurality of flow controllers may be determined to match a server-side flow controller and may then be associated with the flow controller adapter using the determined second orifice size and the determined second coupling feature to allow further matching with the server-side flow controller using its matching first orifice size and its matching first coupling feature with different first orifice sizes and different first coupling features.

[0130] Inference and training logic

[0131] Fig. 6A An inference and / or training logic 615 for performing inference and / or training operations associated with one or more embodiments is shown. Details regarding the inference and / or training logic 615 are provided below in conjunction with Fig. 6A and / or Figure 6B and provide details regarding the inference and / or training logic 615.

[0132] In at least one embodiment, the inference and / or training logic 615 can include, but is not limited to, code and / or data memory 601 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the training logic 615 can include or be coupled to the code and / or data memory 601 to store graphical code or other software for controlling timing and / or sequence, where weight and / or other parameter information will be loaded to configure the logic, including integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, the code (such as graphical code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network corresponding to this code. In at least one embodiment, the code and / or data memory 601 stores weight parameters and / or input / output data for each layer of the neural network, which is trained or used in combination with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using one or more embodiments. In at least one embodiment, any portion of the code and / or data memory 601 can be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0133] In at least one embodiment, any portion of the code and / or data memory 601 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data memory 601 can be cache memory, dynamic random-access memory (“DRAM”), static random-access memory (“SRAM”), non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the choice of whether the code and / or data memory 601 is internal or external to the processor, e.g., or includes DRAM, SRAM, flash memory, or some other storage type, can depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0134] In at least one embodiment, the inference and / or training logic 615 may include, but is not limited to: code and / or data memory 605 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network that is trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the code and / or data memory 605 stores weight parameters and / or input / output data for each layer of the neural network, which is combined with one or more embodiments during the backward propagation of input / output data and / or weight parameters during the training and / or inference using aspects of one or more embodiments. In at least one embodiment, the training logic 615 may include or be coupled to the code and / or data memory 605 to store graphical code or other software to control timing and / or sequencing, where weight and / or other parameter information will be loaded to configure the logic, including integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)).

[0135] In at least one embodiment, the code (such as graphical code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network corresponding to this code. In at least one embodiment, any portion of the code and / or data storage 605 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data memory 605 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data memory 605 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash), or other memory. In at least one embodiment, the choice of whether the code and / or data memory 605 is internal or external to the processor, e.g., or includes DRAM, SRAM, flash, or some other storage type, may depend on the available memory on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0136] In at least one embodiment, code and / or data memory 601 and code and / or data memory 605 may be separate storage structures. In at least one embodiment, code and / or data memory 601 and code and / or data memory 605 may be combined storage structures. In at least one embodiment, code and / or data memory 601 and code and / or data memory 605 may be partially combined and partially separate. In at least one embodiment, any portion of code and / or data memory 601 and code and / or data memory 605 may be included with other on-chip or off-chip data memories, including the L1, L2, or L3 cache of the processor or system memory.

[0137] In at least one embodiment, inference and / or training logic 615 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 610, including integer and / or floating point units, that perform logical and / or mathematical operations at least partially based on or indicative of, training and / or inference code (e.g., graphics code), the result of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in activation memory 620, the activations being a function of input / output and / or weight parameter data stored in code and / or data memory 601 and / or code and / or data memory 605. In at least one embodiment, the activations stored in activation memory 620 are generated according to linear algebra and / or matrix-based mathematical operations performed by one or more ALUs 610 in response to executing instructions or other code, where weight values stored in code and / or data memory 605 and / or code and / or data memory 601 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any one or all of which may be stored in code and / or data memory 605 or code and / or data memory 601 or another memory on-chip or off-chip.

[0138] In at least one embodiment, one or more ALUs 610 are included within one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 610 may be external to the processor or other hardware logic devices or circuits that use them (e.g., a coprocessor). In at least one embodiment, the ALU 610 may be included within the execution unit of the processor or otherwise included within a group of ALUs accessible by the execution unit of the processor, where the execution units of the processor are within the same processor or distributed among different types of different processors (e.g., a central processing unit, a graphics processing unit, a fixed function unit, etc.). In at least one embodiment, the code and / or data memories 601, the code and / or data memories 605, and the activation memory 620 may be shared on a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits, or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of the activation memory 620 may be included with other on-chip or off-chip data memories, where the other on-chip or off-chip data memories include the L1, L2, or L3 cache of the processor or system memory. Additionally, the inference and / or training code may be stored together with other code accessible by the processor or other hardware logic or circuit and fetched and / or processed using the fetch, decode, schedule, execute, retire, and / or other logic circuits of the processor.

[0139] In at least one embodiment, the activation memory 620 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the activation memory 620 may be entirely or partially within or outside of one or more processors or other logic circuits. In at least one embodiment, the selection of whether the activation memory 620 is internal or external to the processor, e.g., or includes DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0140] In at least one embodiment, Fig. 6A the inference and / or training logic 615 shown may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore, or the (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, Fig. 6AThe inference and / or training logic 615 shown in [Figure] can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate array (“FPGA”).

[0141] Figure 6B An inference and / or training logic 615 according to at least one embodiment is shown. In at least one embodiment, the inference and / or training logic 615 can include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise used in combination with weight values or other information corresponding to one or more neuron layers within a neural network. In at least one embodiment, Figure 6B the inference and / or training logic 615 shown in [Figure] can be used in conjunction with an application specific integrated circuit (ASIC), such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore, or the (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, Figure 6B the inference and / or training logic 615 shown in [Figure] can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as field programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 615 includes, but is not limited to, code and / or data memories 601 and 605, which can be used to store code (e.g., graphics code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In Figure 6B at least one embodiment shown in [Figure], each of the code and / or data memories 601 and 605 is respectively associated with dedicated computing resources such as computing hardware 602 and 606. In at least one embodiment, each of the computing hardware 602 and 606 includes one or more ALUs that respectively perform mathematical functions (such as linear algebra functions) only on the information stored in the code and / or data memories 601 and 605, and the results are stored in the activation memory 620.

[0142] In at least one embodiment, each of code and / or data memories 601 and 605 and corresponding computing hardware 602 and 606, respectively, corresponds to a different layer of a neural network such that the resulting activations from one “store / compute pair 601 / 602” of code and / or data memory 601 and computing hardware 602 are provided as input to the next store / compute pair 605 / 606 of code and / or data memory 605 and computing hardware 606 in order to reflect the conceptual organization of the neural network. In at least one embodiment, each of store / compute pairs 601 / 602 and 605 / 606 may correspond to more than one neural network layer. In at least one embodiment, additional memory / compute pairs (not shown) may be included in inference and / or training logic 615 subsequent to or in parallel with store compute pairs 601 / 602 and 605 / 606.

[0143] Neural Network Training and Deployment

[0144] Figure 7 Illustrated is the training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, an untrained neural network 706 is trained using a training data set 702. In at least one embodiment, the training framework 704 is the PyTorch framework, while in other embodiments, the training framework 704 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 704 trains the untrained neural network 706 and enables it to be trained using the processing resources described herein to generate a trained neural network 708. In at least one embodiment, the weights may be randomly selected or selected by pre-training using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0145] In at least one embodiment, a supervised learning is used to train an untrained neural network 706, where the training dataset 702 includes inputs paired with desired outputs for the inputs, or where the training dataset 702 includes inputs with known outputs and the outputs of the neural network 706 are manually graded. In at least one embodiment, the untrained neural network 706 is trained in a supervised manner, processes inputs from the training dataset 702, and compares the resulting outputs with a set of desired or wanted outputs. In at least one embodiment, the error is then backpropagated through the untrained neural network 706. In at least one embodiment, the training framework 704 adjusts the weights that control the untrained neural network 706. In at least one embodiment, the training framework 704 includes tools for monitoring the degree to which the untrained neural network 706 converges to a model (such as a trained neural network 708) suitable for generating correct answers (such as results 714) based on input data (such as a new dataset 712). In at least one embodiment, the training framework 704 repeatedly trains the untrained neural network 706 while adjusting the weights to refine the output of the untrained neural network 706 using a loss function and an adjustment algorithm (such as stochastic gradient descent). In at least one embodiment, the training framework 704 trains the untrained neural network 706 until the untrained neural network 706 reaches a desired accuracy. In at least one embodiment, the trained neural network 708 can then be deployed to perform any number of machine learning operations.

[0146] In at least one embodiment, an unsupervised learning is used to train an untrained neural network 706, where the untrained neural network 706 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 702 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 706 can learn groupings within the training dataset 702 and can determine how individual inputs relate to the untrained dataset 702. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in the trained neural network 708, which can perform operations useful for reducing the dimension of a new dataset 712. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identifying data points in the new dataset 712 that deviate from the normal pattern of the new dataset 712.

[0147] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled data and unlabeled data is included in the training dataset 702. In at least one embodiment, the training framework 704 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 708 to adapt to the new dataset 712 without forgetting the knowledge injected into the trained neural network 708 during the initial training.

[0148] In at least one embodiment, the training framework 704 is a framework that is processed in combination with a software development toolkit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit developed by Intel Corporation, Santa Clara, California, for example.

[0149] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (especially neural network applications) for various tasks and operations, such as human vision simulation, speech recognition, natural language processing, recommendation systems, and / or variants thereof. In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variants thereof.

[0150] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., of people and / or objects), monocular depth estimation, image inpainting, style transfer, action recognition, coloring, and / or variants thereof.

[0151] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also known as the Model Optimizer. In at least one embodiment, the Model Optimizer is a command-line tool that facilitates the conversion between the training and deployment of neural network models. In at least one embodiment, the Model Optimizer optimizes neural network models to execute on various devices and / or processing units such as GPUs, CPUs, PPUs, GPGPUs, and / or their variants. In at least one embodiment, the Model Optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the Model Optimizer reduces the number of layers of the model. In at least one embodiment, the Model Optimizer removes the layers of the model used for training. In at least one embodiment, the Model Optimizer performs various neural network operations such as modifying the input of the model (e.g., resizing the input of the model), modifying the size of the input of the model (e.g., modifying the batch size of the model), modifying the model structure (e.g., modifying the layers of the model), normalization, standardization, quantization (e.g., converting the weights of the model from a first representation such as floating point to a second representation such as integer), and / or their variants.

[0152] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also known as the Inference Engine. In at least one embodiment, the Inference Engine is a C++ library or any suitable programming language library. In at least one embodiment, the Inference Engine is used to infer input data. In at least one embodiment, the Inference Engine implements various classes to infer input data and generate one or more results. In at least one embodiment, the Inference Engine implements one or more API functions to process the intermediate representation, set the input and / or output format, and / or execute the model on one or more devices.

[0153] In at least one embodiment, OpenVINO provides various capabilities for the heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or parts of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., execute a first set of layers on a first device (e.g., GPU) and a second set of layers on a second device (e.g., CPU)).

[0154] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or their variants. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0155] Data center

[0156] Figure 8 An example data center 800 that can use at least one embodiment is shown. In at least one embodiment, data center 800 includes a data center infrastructure layer 810, a framework layer 820, a software layer 830, and an application layer 840.

[0157] In at least one embodiment, as Figure 8As shown, the data center infrastructure layer 810 may include a resource coordinator 812, grouped computing resources 814, and node computing resources ("node C.R.") 816(1)-816(N), where "N" represents a positive integer (which may be a different integer "N" from the integers used in other figures). In at least one embodiment, the node C.R. 816(1)-816(N) may include, but is not limited to, any number of central processing units ("CPU") or other processors (including accelerators, field programmable gate arrays (FPGA), graphics processors, etc.), memory storage devices 818(1)-818(N) (such as dynamic read-only memory, solid-state storage, or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VM"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node C.R. 816(1)-816(N) may be servers having one or more of the above computing resources.

[0158] In at least one embodiment, the grouped computing resources 814 may include separate groupings of node C.R. housed within one or more racks (not shown), or many racks housed within data centers (also not shown) at various geographical locations. In at least one embodiment, the separate groupings of node C.R. within the grouped computing resources 814 may include grouped computing, network, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R. including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0159] In at least one embodiment, the resource coordinator 812 may configure or otherwise control one or more of the node C.R. 816(1)-816(N) and / or the grouped computing resources 814. In at least one embodiment, the resource coordinator 812 may include a software design infrastructure ("SDI") management entity for the data center 800. In at least one embodiment, the resource coordinator 812 may include hardware, software, or some combination thereof.

[0160] In at least one embodiment, as Figure 8As shown, the framework layer 820 includes a job scheduler 822, a configuration manager 824, a resource manager 826, and a distributed file system 828. In at least one embodiment, the framework layer 820 may include a framework that supports software 832 of the software layer 830 and / or one or more applications 842 of the application layer 840. In at least one embodiment, the software 832 or the application 842 may respectively include web-based service software or applications, such as service software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 820 may be, but is not limited to, a type of free and open-source software web application framework, such as Apache Spark that can utilize the distributed file system 828 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 822 may include a Spark driver for facilitating the scheduling of workloads supported by the various layers of the data center 800. In at least one embodiment, the configuration manager 824 may be capable of configuring different layers, such as the software layer 830 and the framework layer 820 including Spark and the distributed file system 828 for supporting large-scale data processing. In at least one embodiment, the resource manager 826 may be capable of managing clustered or grouped computing resources mapped to or allocated for supporting the distributed file system 828 and the job scheduler 822. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 814 at the data center infrastructure layer 810. In at least one embodiment, the resource manager 826 may coordinate with the resource coordinator 812 to manage these mapped or allocated computing resources.

[0161] In at least one embodiment, the software 832 included in the software layer 830 may include software used by at least respective parts of the nodes C.R. 816(1)-816(N), the grouped computing resources 814, and / or the distributed file system 828 of the framework layer 820. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0162] In at least one embodiment, one or more applications 842 included in the application layer 840 may include one or more types of applications used by at least respective portions of nodes C.R. 816(1)-816(N), grouped computing resources 814, and / or the distributed file system 828 of the framework layer 820. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (such as PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0163] In at least one embodiment, any one of the configuration manager 824, the resource manager 826, and the resource coordinator 812 may implement any number and type of self-modifying actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modifying actions may relieve the data center operator of the data center 800 from making potentially bad configuration decisions and may avoid underutilization and / or poorly performing portions of the data center.

[0164] In at least one embodiment, the data center 800 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture by using the software and computing resources described above with respect to the data center 800. In at least one embodiment, by using the weight parameters calculated by one or more training techniques described herein, the resources described above with respect to the data center 800 may be used to infer or predict information using the trained machine learning model corresponding to one or more neural networks.

[0165] In at least one embodiment, the data center may use a CPU, an application-specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to perform training and / or inference using the above resources. In addition, one or more of the above software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0166] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in connection with Fig. 6A and / or Figure 6BProvide details regarding inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 may be used in a Figure 8 system to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0167] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 may be used in conjunction with a Figure 8 system and may be configured to receive sensor inputs from a plurality of sensors 372 (in Figure 3 ) and may be trained to infer the coolant state of a first coolant or a second coolant. In at least one embodiment, the inference and / or training logic 615 may include information of the type of interchangeable flow controllers such that the coolant state can be further differentiated with respect to the type of interchangeable flow controllers used with a flow controller adapter. In at least one embodiment, the inference and / or training logic 615 may infer a change in the coolant state of the coolant. In at least one embodiment, the sensor inputs may be associated with categories of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states may indicate the coolant state of the coolant or a change thereof.

[0168] Computer system

[0169] Fig. 9 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system having interconnected devices and components, a system-on-chip (SOC), or some combination thereof formed with a processor, which may include execution units for executing instructions. In at least one embodiment, according to the present disclosure, such as in the embodiments described herein, the computer system 900 may include, but is not limited to, components such as a processor 902 for executing algorithms for processing data using execution units (including logic). In at least one embodiment, the computer system 900 may include a processor such as those available from Intel Corporation of Santa Clara, California, processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TMA microprocessor, although other systems can also be used (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.). In at least one embodiment, the computer system 900 can execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces can also be used.

[0170] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application can include a microcontroller, a digital signal processor (“DSP”), a system-on-chip, a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0171] In at least one embodiment, the computer system 900 can include, but is not limited to, a processor 902, which can include, but is not limited to, one or more execution units 908 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 900 is a single-processor desktop or server system, but in another embodiment, the computer system 900 can be a multi-processor system. In at least one embodiment, the processor 902 can include, but is not limited to, for example, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 902 can be coupled to a processor bus 910, which can transmit data signals between the processor 902 and other components in the computer system 900.

[0172] In at least one embodiment, the processor 902 may include, but is not limited to, a level 1 (“L1”) internal cache memory (“cache”) 904. In at least one embodiment, the processor 902 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside external to the processor 902. Depending on the particular implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, the register file 906 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0173] In at least one embodiment, an execution unit 908, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 902. In at least one embodiment, the processor 902 may also include a microcode (“ucode”) read-only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, the execution unit 908 may include logic for processing a packed instruction set 909. In at least one embodiment, by including the packed instruction set 909 in the instruction set of a general-purpose processor and the associated circuitry to execute instructions, packed data in the processor 902 can be used to perform operations used by many multimedia applications. In at least one embodiment, operations on packed data can be performed more efficiently by using the full width of the processor's data bus, which can eliminate the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0174] In at least one embodiment, the execution unit 908 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, the computer system 900 may include, but is not limited to, a memory 920. In at least one embodiment, the memory 920 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory devices. In at least one embodiment, the memory 920 may store one or more instructions 919 and / or data 921 represented by data signals that can be executed by the processor 902.

[0175] In at least one embodiment, the system logic chip may be coupled to a processor bus 910 and a memory 920. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 916, and the processor 902 may communicate with the MCH 916 via the processor bus 910. In at least one embodiment, the MCH 916 may provide a high-bandwidth memory path 918 to the memory 920 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 916 may direct data signals among the processor 902, the memory 920, and other components in the computer system 900, and may bridge data signals among the processor bus 910, the memory 920, and the system I / O interface 922. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 916 may be coupled to the memory 920 via the high-bandwidth memory path 918, and the graphics / video card 912 may be coupled to the MCH 916 via an Accelerated Graphics Port (“AGP”) interconnect 914.

[0176] In at least one embodiment, the computer system 900 may use the system I / O interface 922 as a proprietary hub interface bus to couple the MCH 916 to an I / O controller hub (“ICH”) 930. In at least one embodiment, the ICH 930 may provide a direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 920, the chipset, and the processor 902. Examples may include, but are not limited to, an audio controller 929, a firmware hub (“Flash BIOS”) 928, a wireless transceiver 926, a data storage 924, a legacy I / O controller 923 including a user input and keyboard interface 925, a serial expansion port 927 (such as a Universal Serial Bus (“USB”) port), and a network controller 934. In at least one embodiment, the data storage 924 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash device, or other mass storage devices.

[0177] In at least one embodiment, Fig. 9 a system including interconnected hardware devices or “chips” is shown, while in other embodiments, Fig. 9 an exemplary SoC may be shown. In at least one embodiment, Fig. 9 the devices shown in may be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 900 use Compute Express Link (CXL) interconnects for interconnection.

[0178] The inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in conjunction with Fig. 6A and / or Figure 6B details regarding the inference and / or training logic 615 are provided. In at least one embodiment, the inference and / or training logic 615 may be used in a Fig. 9 system for performing inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0179] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 may be used in conjunction with Fig. 9 features and may be configured to receive sensor inputs from a plurality of sensors 372 (in Figure 3 ), and may be trained to infer the coolant state of a first coolant or a second coolant. In at least one embodiment, the inference and / or training logic 615 may include information of the type of interchangeable flow controllers such that the coolant state can be further differentiated relative to the type of interchangeable flow controllers used with a flow controller adapter. In at least one embodiment, the inference and / or training logic 615 may infer a change in the coolant state of the coolant. In at least one embodiment, the sensor inputs may be related to categories of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states may indicate the coolant state of the coolant or a change thereof.

[0180] Fig.10 is a block diagram illustrating an electronic device 1000 for utilizing a processor 1010 according to at least one embodiment. In at least one embodiment, the electronic device 1000 may be, for example but not limited to, a laptop computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0181] In at least one embodiment, the electronic device 1000 may include, but is not limited to, a processor 1010 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1010 is coupled using a bus or interface, such as I 2C bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Attachment (“SATA”) bus, Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.) or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Fig.10 A system is shown that includes interconnected hardware devices or “chips”, and in other embodiments, Fig.10 An exemplary SoC may be shown. In at least one embodiment, Fig.10 The devices shown in may be interconnected using a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Fig.10 One or more components of are interconnected using Compute Express Link (CXL) interconnects.

[0182] In at least one embodiment, Fig.10 May include a display 1024, a touch screen 1025, a touch pad 1030, a Near Field Communication unit (“NFC”) 1045, a sensor hub 1040, a thermal sensor 1046, an Embedded Controller (“EC”) 1035, a Trusted Platform Module (“TPM”) 1038, BIOS / Firmware / Flash (“BIOS, FW Flash”) 1022, a DSP 1060, a drive 1020 (such as a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”)), a Wireless Local Area Network unit (“WLAN”) 1050, a Bluetooth unit 1052, a Wireless Wide Area Network unit (“WWAN”) 1056, a Global Positioning System (GPS) unit 1055, a camera (“USB 3.0 camera”) 1054 (such as a USB 3.0 camera) and / or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1015 implemented, for example, to the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0183] In at least one embodiment, other components may be communicatively coupled to the processor 1010 via the components described herein. In at least one embodiment, the accelerometer 1041, the ambient light sensor (“ALS”) 1042, the compass 1043, and the gyroscope 1044 may be communicatively coupled to the sensor hub 1040. In at least one embodiment, the thermal sensor 1039, the fan 1037, the keyboard 1036, and the touchpad 1030 may be communicatively coupled to the EC 1035. In at least one embodiment, the speaker 1063, the headphones 1064, and the microphone (“mic”) 1065 may be communicatively coupled to the audio unit (“audio codec and class-D amplifier”) 1062, which may in turn be communicatively coupled to the DSP 1060. In at least one embodiment, the audio unit 1062 may include, for example but not limited to, an audio encoder / decoder (“codec”) and a class-D amplifier. In at least one embodiment, the SIM card (“SIM”) 1057 may be communicatively coupled to the WWAN unit 1056. In at least one embodiment, components such as the WLAN unit 1050, the Bluetooth unit 1052, and the WWAN unit 1056 may be implemented in a next-generation form factor (“NGFF”).

[0184] The inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Fig. 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided. In at least one embodiment, the inference and / or training logic 615 may be used in a Fig.10 system for performing inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0185] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 may be used in a Fig.10 system and may be configured to receive input from a plurality of sensors 372 (in Figure 3receives sensor inputs and can be trained to infer the coolant state of a first coolant or a second coolant. In at least one embodiment, the inference and / or training logic 615 can include information of the type of interchangeable flow controllers such that the coolant state can be further differentiated relative to the type of interchangeable flow controllers used with a flow controller adapter. In at least one embodiment, the inference and / or training logic 615 can infer a change in the coolant state of the coolant. In at least one embodiment, the sensor inputs can be associated with categories of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states can indicate the coolant state of the coolant or a change thereof.

[0186] Fig.11 FIG. shows a computer system 1100 according to at least one embodiment. In at least one embodiment, the computer system 1100 is configured to implement the various processes and methods described throughout this disclosure.

[0187] In at least one embodiment, the computer system 1100 includes, but is not limited to, at least one central processing unit (“CPU”) 1102, which is connected to a communication bus 1110 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1100 includes, but is not limited to, a main memory 1104 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in the main memory 1104 that can take the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1122 provides an interface to other computing devices and networks for receiving data from other systems and sending data to other systems using the computer system 1100.

[0188] In at least one embodiment, the computer system 1100 includes, but is not limited to, an input device 1108, a parallel processing system 1112, and a display device 1106 in at least one embodiment, which can be implemented using a conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light emitting diode (“LED”) display, plasma display, or other suitable display technology. In at least one embodiment, user input is received from the input device 1108 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each module described herein can be located on a single semiconductor platform to form a processing system.

[0189] The inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection with Fig. 6A and / or Figure 6B details regarding the inference and / or training logic 615 are provided. In at least one embodiment, the inference and / or training logic 615 may be used in a Fig.11 system to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0190] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 may be used in conjunction with Fig.11 features in Figure 3 and may be configured to receive sensor inputs from a plurality of sensors 372 (in

[0191] Fig.12 FIG. 12 shows a computer system 1200 according to at least one embodiment. In at least one embodiment, the computer system 1200 includes, but is not limited to, a computer 1210 and a USB drive 1220. In at least one embodiment, the computer 1210 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, the computer 1210 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0192] In at least one embodiment, the USB drive 1220 includes, but is not limited to, a processing unit 1230, a USB interface 1240, and a USB interface logic 1250. In at least one embodiment, the processing unit 1230 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1230 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1230 includes an application specific integrated circuit (“ASIC”) that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1230 is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1230 is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations.

[0193] In at least one embodiment, the USB interface 1240 can be any type of USB connector or USB socket. For example, in at least one embodiment, the USB interface 1240 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, the USB interface 1240 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1250 can include any number and type of logic that enables the processing unit 1230 to interface with a device (such as computer 1210) via the USB connector 1240.

[0194] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 615 are provided herein in conjunction with Fig. 6A and / or Figure 6B In at least one embodiment, inference and / or training logic 615 can be used in a Fig.12 system for performing inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0195] In at least one embodiment, one or more neural networks of inference and / or training logic 615 can be used in conjunction with Fig.12 features in Figure 3receives sensor inputs and can be trained to infer the coolant state of a first coolant or a second coolant. In at least one embodiment, the inference and / or training logic 615 can include information of the type of interchangeable flow controllers such that the coolant state can be further differentiated relative to the type of interchangeable flow controllers used with a flow controller adapter. In at least one embodiment, the inference and / or training logic 615 can infer a change in the coolant state of the coolant. In at least one embodiment, the sensor inputs can be associated with categories of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states can indicate the coolant state of the coolant or a change thereof.

[0196] Fig.13A shows an exemplary architecture in which a plurality of GPUs 1310(1)-1310(N) are communicatively coupled to a plurality of multi-core processors 1305(1)-1305(M) via high-speed links 1340(1)-1340(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed links 1340(1)-1340(N) support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. In at least one embodiment, various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, and their values can vary from figure to figure. In at least one embodiment, one or more of the plurality of GPUs 1310(1)-1310(N) include one or more graphics cores (also simply referred to as "cores") 1600 as disclosed in Fig.16A and Fig. 16B and. In at least one embodiment, one or more graphics cores 1600 can be referred to as a streaming multi-processor ("SM"), a stream processor ("SP"), a stream processing unit ("SPU"), a compute unit ("CU"), an execution unit ("EU"), and / or a slice, where, in this context, a slice can refer to a portion of the processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director or scheduler).

[0197] In addition, in at least one embodiment, two or more GPUs 1310 are interconnected by high-speed links 1329(1)-1329(2), which may be implemented using a protocol / link similar to or different from that used for high-speed links 1340(1)-1340(N). Similarly, two or more multi-core processors 1305 may be connected by a high-speed link 1328, which may be a symmetric multi-processor (SMP) bus operating at speeds of 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links (e.g., via a common interconnect structure) may be used to accomplish Fig.13A all communications between the various system components shown

[0198] In at least one embodiment, each multi-core processor 1305 is communicatively coupled to a processor memory 1301(1)-1301(M) via a memory interconnect 1326(1)-1326(M), respectively, and each GPU 1310(1)-1310(N) is communicatively coupled to a GPU memory 1320(1)-1320(N) via a GPU memory interconnect 1350(1)-1350(N), respectively. In at least one embodiment, the memory interconnects 1326 and 1350 may utilize similar or different memory access technologies. By way of example and not limitation, the processor memories 1301(1)-1301(M) and the GPU memory 1320 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In at least one embodiment, some portions of the processor memory 1301 may be volatile memory while another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0199] As described herein, although the respective multi-core processors 1305 and GPUs 1310 may be physically coupled to specific memories 1301, 1320, and / or a unified memory architecture may be implemented, in which the virtual system address space (also referred to as the "effective address" space) is distributed among the respective physical memories. For example, the processor memories 1301(1)-1301(M) may each include 64 GB of system memory address space, and the GPU memories 1320(1)-1320(N) may each include 32 GB of system memory address space, such that when M = 2 and N = 4, a total of 256 GB of addressable memory results. Other values of N and M are possible.

[0200] Fig. 13B Additional details of the interconnection between the multi-core processor 1307 and the graphics acceleration module 1346 according to an exemplary embodiment are shown. In at least one embodiment, the graphics acceleration module 1346 may include one or more GPU chips integrated on a line card, which is coupled to the processor 1307 via a high-speed link 1340 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1346 may alternatively be integrated on a package or chip having the processor 1307.

[0201] In at least one embodiment, the processor 1307 includes a plurality of cores 1360A - 1360D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 1361A - 1361D and one or more caches 1362A - 1362D. In at least one embodiment, the cores 1360A - 1360D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, the caches 1362A - 1362D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1356 may be included in the caches 1362A - 1362D and shared by groups of cores 1360A - 1360D. For example, one embodiment of the processor 1307 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1307 and the graphics acceleration module 1346 are connected to the system memory 1314, which may include Fig.13A processor memories 1301(1) - 1301(M).

[0202] In at least one embodiment, coherence is maintained for data and instructions stored in the respective caches 1362A - 1362D, 1356, and the system memory 1314 through an inter-core communication via the coherence bus 1364. In at least one embodiment, for example, each cache may have cache coherence logic / circuit associated therewith to communicate via the coherence bus 1364 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the coherence bus 1364 to snoop on cache accesses.

[0203] In at least one embodiment, the proxy circuit 1325 communicatively couples the graphics acceleration module 1346 to the coherence bus 1364, thereby allowing the graphics acceleration module 1346 to participate in the cache coherence protocol as a peer of the cores 1360A - 1360D. In particular, in at least one embodiment, the interface 1335 provides a connection to the proxy circuit 1325 via the high-speed link 1340, and the interface 1337 couples the graphics acceleration module 1346 to the high-speed link 1340.

[0204] In at least one embodiment, the accelerator integrated circuit 1336 provides cache management, memory access, context management, and interrupt management services on behalf of the plurality of graphics processing engines 1331(1)-1331(N) of the graphics acceleration module 1346. In at least one embodiment, the graphics processing engines 1331(1)-1331(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the plurality of graphics processing engines 1331(1)-1331(N) of the graphics acceleration module 1346 includes one or more graphics cores 1600 as discussed in connection with Fig.16A and 16B . In at least one embodiment, the graphics processing engines 1331(1)-1331(N) may alternatively include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1346 may be a GPU having a plurality of graphics processing engines 1331(1)-1331(N), or the graphics processing engines 1331(1)-1331(N) may be individual GPUs integrated on a common package, line card, or chip.

[0205] In at least one embodiment, accelerator integrated circuit 1336 includes a memory management unit (MMU) 1339 for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and also includes a memory access protocol for accessing system memory 1314. In at least one embodiment, MMU 1339 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, cache 1338 may store commands and data for efficient access by graphics processing engines 1331(1)-1331(N). In at least one embodiment, fetch unit 1344 may be used to keep the data stored in cache 1338 and graphics memories 1333(1)-1333(M) coherent with core caches 1362A-1362D, 1356, and system memory 1314. As previously described, this may be representative of cache 1338 and memories 1333(1)-1333(M) being implemented via proxy circuit 1325 (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1362A-1362D, 1356 to cache 1338 and receiving updates from cache 1338).

[0206] In at least one embodiment, a set of registers 1345 stores context data for threads executed by graphics processing engines 1331(1)-1331(N), and context management circuit 1348 manages thread contexts. For example, context management circuit 1348 may perform save and restore operations to save and restore the contexts of individual threads during a context switch (e.g., where the first thread is saved and the second thread is stored so that the second thread may be executed by the graphics processing engine). For example, context management circuit 1348 may store the current register values to a specified area in memory (e.g., identified by a context pointer) during a context switch. Then, the register values may be restored when returning to the context. In at least one embodiment, interrupt management circuit 1347 receives and processes interrupts received from system devices.

[0207] In at least one embodiment, the MMU 1339 converts virtual / valid addresses from the graphics processing engine 1331 into real / physical addresses in the system memory 1314. In at least one embodiment, the accelerator integrated circuit 1336 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1346 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1346 can be dedicated to a single application executing on the processor 1307 or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented where the resources of the graphics processing engines 1331(1)-1331(N) are shared among multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" based on the processing requirements and priorities associated with the VMs and / or applications, and these slices are allocated to different VMs and / or applications.

[0208] In at least one embodiment, the accelerator integrated circuit 1336 acts as a bridge for the system of the graphics accelerator modules 1346 and provides address translation and system memory cache services. Additionally, in at least one embodiment, the accelerator integrated circuit 1336 can provide virtualization facilities for the host processor to manage the virtualization, interrupts, and memory management of the graphics processing engines 1331(1)-1331(N).

[0209] In at least one embodiment, since the hardware resources of the graphics processing engines 1331(1)-1331(N) are explicitly mapped to the real address space seen by the host processor 1307, any host processor can directly address these resources using valid address values. In at least one embodiment, one function of the accelerator integrated circuit 1336 is the physical separation of the graphics processing engines 1331(1)-1331(N) such that they appear as independent units to the system.

[0210] In at least one embodiment, one or more graphics memories 1333(1)-1333(M) are coupled to each of the graphics processing engines 1331(1)-1331(N) respectively, and N = M. In at least one embodiment, the graphics memories 1333(1)-1333(M) store the instructions and data being processed by each of the graphics processing engines 1331(1)-1331(N). In at least one embodiment, the graphics memories 1333(1)-1333(M) can be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories such as 3D XPoint or Nano-Ram.

[0211] In at least one embodiment, to reduce data traffic on the high-speed link 1340, bias techniques can be used to ensure that the data stored in the graphics memories 1333(1)-1333(M) is the data most frequently used by the graphics processing engines 1331(1)-1331(N), and preferably is data not used (at least not frequently used) by the cores 1360A-1360D. Similarly, in at least one embodiment, the bias mechanism attempts to keep the data needed by the cores (and preferably not needed by the graphics processing engines 1331(1)-1331(N)) in the caches 1362A-1362D, 1356, and the system memory 1314.

[0212] Fig. 13C Another exemplary embodiment is shown where the accelerator integrated circuit 1336 is integrated within the processor 1307. In this embodiment, the graphics processing engines 1331(1)-1331(N) communicate directly with the accelerator integrated circuit 1336 via the interface 1337 and the interface 1335 (again, which can be any form of bus or interface protocol) over the high-speed link 1340. In at least one embodiment, the accelerator integrated circuit 1336 can perform operations similar to the operations described with respect to Fig. 13B but may have higher throughput due to its close proximity to the coherence bus 1364 and the caches 1362A-1362D, 1356. In at least one embodiment, the accelerator integrated circuit supports different programming models, which include a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), and the programming models can include a programming model controlled by the accelerator integrated circuit 1336 and a programming model controlled by the graphics acceleration module 1346.

[0213] In at least one embodiment, the graphics processing engines 1331(1)-1331(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to the graphics processing engines 1331(1)-1331(N), thereby providing virtualization within the VM / partition.

[0214] In at least one embodiment, the graphics processing engines 1331(1)-1331(N) can be shared by multiple VM / application partitions. In at least one embodiment, a shared model can use a hypervisor to virtualize the graphics processing engines 1331(1)-1331(N) to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns the graphics processing engines 1331(1)-1331(N). In at least one embodiment, the operating system can virtualize the graphics processing engines 1331(1)-1331(N) to provide access to each process or application.

[0215] In at least one embodiment, the graphics acceleration module 1346 or an individual graphics processing engine 1331(1)-1331(N) uses a process handle to select a process element. In at least one embodiment, the process element is stored in the system memory 1314 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engines 1331(1)-1331(N) (i.e., calling the system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0216] Fig.13D An exemplary accelerator integration slice 1390 is shown. In at least one embodiment, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 1336. In at least one embodiment, an application is an effective address space 1382 in the system memory 1314 that stores process elements 1383. In at least one embodiment, in response to a GPU call 1381 from an application 1380 executing on the processor 1307, the process element 1383 is stored. In at least one embodiment, the process element 1383 contains the process state of the corresponding application 1380. In at least one embodiment, the work descriptor (WD) 1384 contained in the process element 1383 can be a single job requested by the application or can contain a pointer to a job queue. In at least one embodiment, the WD 1384 is a pointer to a job request queue in the effective address space 1382 of the application.

[0217] In at least one embodiment, the graphics acceleration module 1346 and / or each of the graphics processing engines 1331(1)-1331(N) may be shared by all processes or a subset of processes in the system. In at least one embodiment, there may be included an infrastructure for setting the process state and sending the WD 1384 to the graphics acceleration module 1346 to start a job in a virtualized environment.

[0218] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1346 or an individual graphics processing engine 1331. In at least one embodiment, when the graphics acceleration module 1346 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 1336 for the owned partition, and when the graphics acceleration module 1346 is assigned, the operating system initializes the accelerator integrated circuit 1336 for the owned process.

[0219] In at least one embodiment, in operation, the WD fetch unit 1391 in the accelerator integrated slice 1390 fetches the next WD 1384, which includes an indication of work to be completed by one or more of the graphics processing engines of the graphics acceleration module 1346. In at least one embodiment, the data from the WD 1384 may be stored in the register 1345 and used by the MMU 1339, the interrupt management circuit 1347, and / or the context management circuit 1348, as shown. For example, one embodiment of the MMU 1339 includes a segment / page walk circuit for accessing the segment / page table 1386 within the OS virtual address space 1385. In at least one embodiment, the interrupt management circuit 1347 may process the interrupt event 1392 received from the graphics acceleration module 1346. In at least one embodiment, when performing a graphics operation, the effective address 1393 generated by the graphics processing engines 1331(1)-1331(N) is translated by the MMU 1339 into a real address.

[0220] In at least one embodiment, the register 1345 is replicated for each of the graphics processing engines 1331(1)-1331(N) and / or the graphics acceleration module 1346, and the register 1345 may be initialized by the hypervisor or the operating system. In at least one embodiment, each of these replicated registers may be included in the accelerator integrated slice 1390. Exemplary registers that may be initialized by the hypervisor are shown in Table 1.

[0221] Table 1 – Hypervisor-Initialized Registers

[0222]

[0223]

[0224] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0225] Table 2 – Registers Initialized by the Operating System

[0226]

[0227] In at least one embodiment, each WD 1384 is specific to a particular graphics acceleration module 1346 and / or graphics processing engine 1331(1)-1331(N). In at least one embodiment, it contains all the information required for the graphics processing engine 1331(1)-1331(N) to complete its work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0228] Fig.13E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1398 in which a list of process elements 1399 is stored. In at least one embodiment, the hypervisor real address space 1398 can be accessed via the hypervisor 1396, which virtualizes the graphics acceleration module engine for the operating system 1395.

[0229] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1346. In at least one embodiment, there are two programming models in which the graphics acceleration module 1346 is shared by multiple processes and partitions, namely time-slicing sharing and graphics-directed sharing.

[0230] In at least one embodiment, in this model, the system hypervisor 1396 owns the graphics acceleration module 1346 and makes its functions available to all operating systems 1395. In at least one embodiment, for the graphics acceleration module 1346 to support virtualization through the system hypervisor 1396, the graphics acceleration module 1346 may have to comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., do not require maintaining state between jobs), or the graphics acceleration module 1346 must provide a context save and restore mechanism, (2) the graphics acceleration module 1346 guarantees that the job requests of the application are completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1346 provides the ability to preempt job processing, and (3) when operating in a directed sharing programming model, it must be ensured that the graphics acceleration module 1346 is fair among processes.

[0231] In at least one embodiment, the application 1380 is required to use the graphics acceleration module type, work descriptor (WD), access mask register (AMR) value, and context save / restore area pointer (CSRP) for system calls to the operating system 1395. In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1346 and can take the form of a graphics acceleration module 1346 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure that describes the work to be done by the graphics acceleration module 1346.

[0232] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1336 (not shown) and the graphics acceleration module 1346 does not support the user access mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1396 can selectively apply the current access mask override register (AMOR) value before placing the AMR in the process element 1383. In at least one embodiment, the CSRP is one of the registers 1345 that contains the valid address of a region in the valid address space 1382 of the application for the graphics acceleration module 1346 to save and restore the context state. In at least one embodiment, this pointer is optional if there is no need to save state between jobs or when a job is preempted. In at least one embodiment, the context save / restore area can be a fixed system memory.

[0233] Upon receiving the system call, the operating system 1395 can verify that the application 1380 has been registered and granted permission to use the graphics acceleration module 1346. Then, in at least one embodiment, the operating system 1395 uses the information shown in Table 3 to call the hypervisor 1396.

[0234] Table 3 – Operating System to Hypervisor Call Parameters

[0235]

[0236] In at least one embodiment, upon receiving a hypervisor call, the hypervisor 1396 verifies that the operating system 1395 is registered and has been granted permission to use the graphics acceleration module 1346. Then, in at least one embodiment, the hypervisor 1396 places the process element 1383 into a process element linked list corresponding to the type of the graphics acceleration module 1346. In at least one embodiment, the process element may include the information shown in Table 4.

[0237] Table 4 – Process Element Information

[0238]

[0239] In at least one embodiment, the hypervisor initializes the registers 1345 of multiple accelerator integration slices 1390.

[0240] As Fig.13F shown, in at least one embodiment, a unified memory is used, and the unified memory can be addressed via a common virtual memory address space for accessing the physical processor memories 1301(1)-1301(N) and the GPU memories 1320(1)-1320(N). In this implementation, operations executed on the GPUs 1310(1)-1310(N) utilize the same virtual / effective memory address space to access the processor memories 1301(1)-1301(M), and vice versa, thus simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to the processor memory 1301(1), a second portion is allocated to the second processor memory 1301(N), a third portion is allocated to the GPU memory 1320(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of the processor memories 1301 and the GPU memories 1320, allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0241] In at least one embodiment, the bias / coherence management circuits 1394A-1394E within one or more MMUs 1339A-1339E ensure cache coherence between one or more host processors (e.g., 1305) and the caches of the GPUs 1310, and implement a bias technique for indicating the physical memory in which certain types of data should be stored. In at least one embodiment, although multiple instances of the bias / coherence management circuits 1394A-1394E are shown in Fig.13F , the bias / coherence circuits can be implemented within the MMUs of one or more host processors 1305 and / or within the accelerator integrated circuit 1336.

[0242] One embodiment allows the GPU memory 1320 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with full-system cache coherence. In at least one embodiment, the ability of the GPU memory 1320 to be accessed as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the software of the host processor 1305 to set operands and access computation results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access the GPU memory 1320 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in the case of a large amount of streaming write memory traffic, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 1310. In at least one embodiment, the efficiency of operand setting, result access, and GPU computation may play a role in determining the effectiveness of GPU offloading.

[0243] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page-granularity structure (e.g., controlled at the granularity of memory pages), and this page-granularity structure includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, with or without a bias cache in the GPU 1310 (e.g., for caching frequently / most recently used entries of the bias table), the bias table may be implemented in the stolen memory ranges of one or more GPU memories 1320. Alternatively, in at least one embodiment, the entire bias table may be maintained within the GPU.

[0244] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU attached memory 1320 is accessed, thereby causing the following operations. In at least one embodiment, local requests from the GPU 1310 that find their pages in the GPU bias are directly forwarded to the corresponding GPU memory 1320. In at least one embodiment, local requests from the GPU that find their pages in the host bias are forwarded to the processor 1305 (e.g., via the high-speed link described herein). In at least one embodiment, requests from the processor 1305 that find the requested page in the host processor bias complete requests similar to normal memory reads. Alternatively, requests pointing to GPU bias pages can be forwarded to the GPU 1310. In at least one embodiment, if the GPU is not currently using a page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed by a software-based mechanism, a software mechanism assisted by hardware, or in a limited set of cases by a purely hardware-based mechanism.

[0245] In at least one embodiment, a mechanism for changing the bias state employs an API call (such as OpenCL), which in turn calls the device driver of the GPU. The device driver in turn sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and perform a cache flush operation in the host in certain migrations. In at least one embodiment, the cache flush operation is used for migrations from the host processor 1305 bias to the GPU bias, but not for the reverse migration.

[0246] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that cannot be cached by the host processor 1305. In at least one embodiment, to access these pages, the processor 1305 can request access from the GPU 1310, and the GPU 1310 may or may not immediately grant access. Thus, in at least one embodiment, to reduce communication between the processor 1305 and the GPU 1310, it is beneficial to ensure that GPU bias pages are pages required by the GPU rather than the host processor 1305, and vice versa.

[0247] One or more hardware structures 615 are used to execute one or more embodiments. Details regarding one or more hardware structures 615 may be provided herein in conjunction with Fig. 6A and / or Figure 6B provide details about one or more hardware structures 615.

[0248] Fig.14An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrated, other logic and circuits may also be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0249] Fig.14 1400 is a block diagram illustrating an exemplary system on a chip integrated circuit 1400 that can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1400 includes one or more application processors 1405 (e.g., CPU), at least one graphics processor 1410, and may additionally include an image processor 1415 and / or a video processor 1420, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1400 includes peripheral or bus logic, which includes a USB controller 1425, a UART controller 1430, an SPI / SDIO controller 1435, and an I 2 S / I 2 C controller 1440. In at least one embodiment, the integrated circuit 1400 may include a display device 1445 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1450 and a mobile industry processor interface (MIPI) display interface 1455. In at least one embodiment, storage may be provided by a flash memory subsystem 1460, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1465 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1470.

[0250] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in integrated circuit 1400 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0251] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 may be combined with Fig.14 and can be configured to receive information from multiple sensors 372 (in Figure 3In at least one embodiment, the reasoning and / or training logic 615 may include information about the type of interchangeable flow controller so that the coolant state can be further distinguished relative to the type of interchangeable flow controller used with the flow controller adapter. In at least one embodiment, the reasoning and / or training logic 615 may infer changes in the coolant state of the coolant. In at least one embodiment, the sensor input may be associated with categories of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states may indicate the coolant state of the coolant or a change thereof.

[0252] Figures 15A-15B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general processor cores.

[0253] Figures 15A-15B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Fig.15A An exemplary graphics processor 1510 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Fig. 15B An additional exemplary graphics processor 1540 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, according to at least one embodiment. In at least one embodiment, Fig.15A The graphics processor 1510 is a low power graphics processor core. In at least one embodiment, Fig. 15B The graphics processor 1540 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1510, 1540 can be Fig.14 A variant of graphics processor 1410.

[0254] In at least one embodiment, the graphics processor 1510 includes a vertex processor 1505 and one or more fragment processors 1515A-1515N (e.g., 1515A, 1515B, 1515C, 1515D to 1515N-1 and 1515N). In at least one embodiment, the graphics processor 1510 can execute different shader programs via separate logic, so that the vertex processor 1505 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1515A-1515N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1505 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1515A-1515N use the primitives and vertex data generated by the vertex processor 1505 to generate a frame buffer displayed on a display device. In at least one embodiment, one or more fragment processors 1515A-1515N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0255] In at least one embodiment, graphics processor 1510 additionally includes one or more memory management units (MMUs) 1520A-1520B, one or more caches 1525A-1525B, and one or more circuit interconnects 1530A-1530B. In at least one embodiment, one or more MMUs 1520A-1520B provide virtual to physical address mapping for graphics processor 1510 (including for vertex processor 1505 and / or fragment processors 1515A-1515N), which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1525A-1525B. In at least one embodiment, one or more MMUs 1520A-1520B may synchronize with other MMUs within the system, including with Fig.14 One or more MMUs associated with one or more application processors 1405, image processor 1415, and / or video processor 1420 enable each processor 1405-1420 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1530A-1530B enable graphics processor 1510 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0256] In at least one embodiment, graphics processor 1540 includes: Fig. 15B One or more shader cores 1555A-1555N (e.g., 1555A, 1555B, 1555C, 1555D, 1555E, 1555F to 1555N-1 and 1555N) are shown, which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1540 includes an inter-core task manager 1545 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1555A-1555N and a tiling unit 1558 to accelerate tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0257] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 may be combined with Figures 15A-15B and can be configured to receive information from multiple sensors 372 (in Figure 3 In at least one embodiment, the inference and / or training logic 615 may include information about the type of interchangeable flow controller so that the coolant state can be further distinguished relative to the type of interchangeable flow controller used with the flow controller adapter. In at least one embodiment, the inference and / or training logic 615 may infer changes in the coolant state of the coolant. In at least one embodiment, the sensor input may be associated with categories of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states may indicate the coolant state of the coolant or a change thereof.

[0258] Figures 16A-16B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Fig.16A shows that it can be included in Fig.14 The graphics core 1600 within the graphics processor 1410 of FIG. 1400 and, in at least one embodiment, may be as follows Fig. 15B Unified shader cores 1555A-1555N are shown. Fig. 16B A highly parallel general purpose graphics processing unit ("GPGPU") 1630 suitable for deployment on a multi-chip module in at least one embodiment is shown.

[0259] In at least one embodiment, graphics core 1600 includes a shared instruction cache 1602, texture units 1618, and cache / shared memory 1620 (e.g., including L1, L2, L3, last level cache, or other caches) that are common to execution resources within graphics core 1600. In at least one embodiment, graphics core 1600 may include multiple slices 1601A-1601N or partitions of each core, and a graphics processor may include multiple instances of graphics core 1600. In at least one embodiment, each slice 1601A-1601N refers to graphics core 1600. In at least one embodiment, slices 1601A-1601N have sub-slices that are part of slices 1601A-1601N. In at least one embodiment, slices 1601A-1601N are independent of other slices or dependent on other slices. In at least one embodiment, the slices 1601A-1601N may include support logic including a local instruction cache 1604A-1604N, a thread scheduler (sequencer) 1606A-1606N, a thread dispatcher 1608A-1608N, and a set of registers 1610A-1610N. In at least one embodiment, the slices 1601A-1601N may include a set of additional function units (AFU 1612A-1612N), floating point units (FPU 1614A-1614N), integer arithmetic logic units (ALU 1616A-1616N), address calculation units (ACU 1613A-1613N), double precision floating point units (DPFPU 1615A-1615N), and matrix processing units (MPU 1617A-1617N).

[0260] In at least one embodiment, each slice 1601A-1601N includes one or more engines for floating point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning or large data set workloads. In at least one embodiment, one or more slices 1601A-1601N include one or more vector engines for calculating vectors (e.g., calculating mathematical operations of vectors). In at least one embodiment, the vector engine can calculate vector operations in 16-bit floating point (also known as "FP16"), 32-bit floating point (also known as "FP32"), or 64-bit floating point (also known as "FP64"). In at least one embodiment, one or more slices 1601A-1601N include 16 vector engines paired with 16 matrix math units to calculate matrix / tensor operations, wherein the vector engines and math units are shown by matrix expansion. In at least one embodiment, a specified portion of the processing resources of the processing unit (e.g., 16 cores and ray tracing units or 8 cores), a thread scheduler, a thread scheduler, and additional functional units of the processor are sliced. In at least one embodiment, graphics core 1600 includes one or more matrix engines for computing matrix operations, such as when computing tensor operations.

[0261] In at least one embodiment, one or more slices 1601A-1601N include one or more ray tracing units (e.g., 16 ray tracing units per slice slices 1601A-1601N) for computing ray tracing operations. In at least one embodiment, the ray tracing units compute ray traversals, triangle intersections, bounding box intersections, or other ray tracing operations.

[0262] In at least one embodiment, one or more slices 1601A-1601N include media slices that encode, decode, and / or transcode data; scale and / or format convert data; and / or perform video quality operations on video data.

[0263] In at least one embodiment, one or more slices 1601A - 1601N are linked to an L2 cache and a memory structure, a link connector, a high - bandwidth memory (HBM) (e.g., HBM2e, HBM3) stack, and a media engine. In at least one embodiment, one or more slices 1601A - 1601N include a plurality of cores (e.g., 16 cores) and a plurality of ray - tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 1601A - 1601N have one or more L1 caches. In at least one embodiment, one or more slices 1601A - 1601N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data corresponding to, for example, instructions; one or more samplers for sampling data; one or more ray - tracing units for performing ray - tracing operations; one or more geometries for performing operations in a geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for depicting an image in a vector - graphics format (e.g., a shape) and converting it into a raster image (e.g., a series of pixels, dots, or lines that, when displayed together, create an image represented by the shape); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel back - ends. In at least one embodiment, slices 1601A - 1601N include a memory structure, e.g., an L2 cache.

[0264] In at least one embodiment, FPUs 1614A - 1614N can perform single - precision (32 - bit) and half - precision (16 - bit) floating - point operations, while DPFPU 1615A - 1615N performs double - precision (64 - bit) floating - point operations. In at least one embodiment, ALUs 1616A - 1616N can perform variable - precision integer operations at 8 - bit, 16 - bit, and 32 - bit precisions and can be configured for mixed - precision operations. In at least one embodiment, MPUs 1617A - 1617N can also be configured for mixed - precision matrix operations, including half - precision floating - point operations and 8 - bit integer operations. In at least one embodiment, MPUs 1617A - 1617N can perform various matrix operations to accelerate machine - learning application frameworks, including enabling support for accelerated general matrix - to - matrix multiplication (GEMM). In at least one embodiment, AFUs 1612A - 1612N can perform additional logical operations not supported by a floating - point unit or an integer unit, including trigonometric operations (e.g., sine, cosine). Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Fig. 6A and / or Figure 6B Provide details regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 can be used in the graphics core 1600 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0265] In at least one embodiment, the graphics core 1600 includes an interconnect and link structure sublayer attached to a switch and a GPU-GPU bridge that enables multiple graphics processors 1600 (e.g., 8) to be interconnected with each other without bonding through load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 1600. In at least one embodiment, the interconnect includes a standardized interconnect (e.g., PCIe) or some combination thereof.

[0266] In at least one embodiment, the graphics core 1600 includes multiple tiles. In at least one embodiment, a tile is a separate die or one or more dies, where a separate die can be connected to the interconnect (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, the graphics core 1600 includes compute tiles, memory tiles (e.g., where the memory tiles can be exclusively accessed by different tiles or different chip sets such as Rambo tiles), substrate tiles, foundation tiles, HMB tiles, link tiles, and EMIB tiles, where all the tiles are encapsulated together in the graphics core 1600 as part of the GPU. In at least one embodiment, the graphics core 1600 can include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, a compute tile can have 8 graphics cores 1600, an L1 cache; and a foundation tile can have a host interface to PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with 8 links, and 8 ports with an embedded switch. In at least one embodiment, the tiles are connected by face-to-face (F2F) chip-on-chip bonding with fine-pitch 36-micron microbumps (e.g., copper pillars). In at least one embodiment, the graphics core 1600 includes a memory structure that includes memory and is a tile accessible by multiple tiles. In at least one embodiment, the graphics core 1600 stores, accesses, or loads its own hardware context into the memory, where the hardware context is a set of data loaded from registers before process restoration, and where the hardware context can indicate the state of the hardware (e.g., the state of the GPU).

[0267] In at least one embodiment, the graphics core 1600 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream into a parallel data stream, or a parallel data stream into a serial data stream.

[0268] In at least one embodiment, the graphics core 1600 includes a high-speed coherent unified fabric (GPU-to-GPU), load / store units, bulk data transfer and synchronization semantics, and GPUs connected by an embedded switch, where the GPU-GPU bridge is controlled by a controller.

[0269] In at least one embodiment, the graphics core 1600 executes an API, where the API abstracts the hardware of the graphics core 1600 and uses instructions to access libraries to perform mathematical operations (e.g., math kernel libraries), deep neural network operations (e.g., deep neural network libraries), vector operations, collective communications, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0270] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 can be used in conjunction with Fig.16A features in, and can be configured to receive sensor inputs from multiple sensors 372 (in Figure 3 ), and can be trained to infer the coolant state of a first coolant or a second coolant. In at least one embodiment, the inference and / or training logic 615 can include information of the type of interchangeable flow controllers such that the coolant state can be further differentiated with respect to the type of interchangeable flow controllers used with a flow controller adapter. In at least one embodiment, the inference and / or training logic 615 can infer a change in the coolant state of the coolant. In at least one embodiment, the sensor inputs can be associated with categories of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states can indicate the coolant state of the coolant or a change thereof.

[0271] Fig. 16BShows a general - purpose processing unit (GPGPU) 1630 in at least one embodiment, which can be configured to enable highly parallel computing operations to be performed by an array of graphics processing units. In at least one embodiment, GPGPU 1630 can be directly linked to other instances of GPGPU 1630 to create a multi - GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 1630 includes a host interface 1632 for enabling connection to a host processor. In at least one embodiment, host interface 1632 is a PCI Express interface. In at least one embodiment, host interface 1632 can be a vendor - specific communication interface or communication fabric. In at least one embodiment, GPGPU 1630 receives commands from the host processor and uses a global scheduler 1634 (which can be referred to as a thread sequencer and / or asynchronous computing engine) to assign execution threads associated with those commands to a set of compute clusters 1636A - 1636H. In at least one embodiment, compute clusters 1636A - 1636H share a cache memory 1638. In at least one embodiment, cache memory 1638 can be used as a higher - level cache for the cache memories within compute clusters 1636A - 1636H.

[0272] In at least one embodiment, GPGPU 1630 includes memories 1644A - 1644B, which are coupled to compute clusters 1636A - 1636H via a set of memory controllers 1642A - 1642B (e.g., one or more controllers for HBM2e). In at least one embodiment, memories 1644A - 1644B can include various types of memory devices, which include dynamic random - access memory (DRAM) or graphics random - access memory, such as synchronous graphics random - access memory (SGRAM), which includes graphics double - data rate (GDDR) memory.

[0273] In at least one embodiment, each of compute clusters 1636A - 1636H includes a set of graphics cores, such as Fig.16A the graphics core 1600, which can include multiple types of integer and floating - point logic units that can perform computing operations over a range of precisions suitable for machine - learning computations. For example, in at least one embodiment, at least a subset of the floating - point units in each of compute clusters 1636A - 1636H can be configured to perform 16 - bit or 32 - bit floating - point operations, while a different subset of floating - point units can be configured to perform 64 - bit floating - point operations.

[0274] In at least one embodiment, multiple instances of the GPGPU 1630 may be configured to operate as compute clusters. In at least one embodiment, the communication for synchronization and data exchange of the compute clusters 1636A - 1636H varies between embodiments. In at least one embodiment, multiple instances of the GPGPU 1630 communicate via the host interface 1632. In at least one embodiment, the GPGPU 1630 includes an I / O hub 1639 that couples the GPGPU 1630 to the GPU link 1640, which enables a direct connection to other instances of the GPGPU 1630. In at least one embodiment, the GPU link 1640 is coupled to a dedicated GPU - to - GPU bridge that enables communication and synchronization between multiple instances of the GPGPU 1630. In at least one embodiment, the GPU link 1640 is coupled to a high - speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of the GPGPU 1630 are located in separate data - processing systems and communicate via network devices accessible via the host interface 1632. In at least one embodiment, in addition to or as an alternative to the host interface 1632, the GPU link 1640 may also be configured to enable a connection to the host processor.

[0275] In at least one embodiment, the GPGPU 1630 may be configured to train neural networks. In at least one embodiment, the GPGPU 1630 may be used within an inference platform. In at least one embodiment, in the case of using the GPGPU 1630 for inference, the GPGPU 1630 may include fewer compute clusters 1636A - 1636H compared to when using the GPGPU 1630 to train neural networks. In at least one embodiment, the memory technology associated with the memories 1644A - 1644B may vary between the inference and training configurations, with higher - bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1630 may support inference - specific instructions. For example, in at least one embodiment, the inference configuration may provide support for one or more 8 - bit integer dot - product instructions that may be used during the inference operations of a deployed neural network.

[0276] The inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Fig. 6A and / or Figure 6BProvide details regarding inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 can be used in the GPGPU 1630 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0277] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 can be used in conjunction with Fig.16A features in, and can be configured to receive sensor inputs from a plurality of sensors 372 (in Figure 3 ), and can be trained to infer the coolant state of a first coolant or a second coolant. In at least one embodiment, the inference and / or training logic 615 can include information of the type of interchangeable flow controllers such that the coolant state can be further differentiated with respect to the type of interchangeable flow controllers used with a flow controller adapter. In at least one embodiment, the inference and / or training logic 615 can infer a change in the coolant state of the coolant. In at least one embodiment, the sensor inputs can be associated with categories of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states can indicate the coolant state of the coolant or a change thereof.

[0278] Fig.17 is a block diagram illustrating a computing system 1700 according to at least one embodiment. In at least one embodiment, the computing system 1700 includes a processing subsystem 1701 having one or more processors 1702 and a system memory 1704 communicating via an interconnect path that can include a memory hub 1705. In at least one embodiment, the memory hub 1705 can be a separate component within a chipset component or can be integrated within one or more processors 1702. In at least one embodiment, the memory hub 1705 is coupled to an I / O subsystem 1711 via a communication link 1706. In at least one embodiment, the I / O subsystem 1711 includes an I / O hub 1707 that can enable the computing system 1700 to receive inputs from one or more input devices 1708. In at least one embodiment, the I / O hub 1707 can enable a display controller, which can be included in one or more processors 1702, to provide outputs to one or more display devices 1710A. In at least one embodiment, one or more display devices 1710A coupled to the I / O hub 1707 can include local, internal, or embedded display devices.

[0279] In at least one embodiment, the processing subsystem 1701 includes one or more parallel processors 1712 coupled to the memory hub 1705 via a bus or other communication link 1713. In at least one embodiment, the communication link 1713 can use any number of standards based on communication link technologies or protocols (such as but not limited to PCI Express), or can be a vendor-specific communication interface or communication fabric. In at least one embodiment, the one or more parallel processors 1712 form a parallel or vector processing system in a computing concentration, which can include a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. In at least one embodiment, some or all of the one or more parallel processors 1712 form a graphics processing subsystem, which can output pixels to one of the one or more display devices 1710A coupled via the I / O hub 1707. In at least one embodiment, the one or more parallel processors 1712 can also include a display controller and a display interface (not shown) for implementing a direct connection to one or more display devices 1710B. In at least one embodiment, the parallel processor 1712 includes one or more cores, such as the graphics core 1600 discussed herein.

[0280] In at least one embodiment, the system storage unit 1714 can be connected to the I / O hub 1707 to provide a storage mechanism for the computing system 1700. In at least one embodiment, the I / O switch 1716 can be used to provide an interface mechanism for implementing connections between the I / O hub 1707 and other components, which other components can be, for example, a network adapter 1718 and / or a wireless network adapter 1719 integrated into the platform, and various other devices that can be added via one or more additional devices 1720. In at least one embodiment, the network adapter 1718 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1719 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0281] In at least one embodiment, the computing system 1700 can include other components not explicitly shown that can also be connected to the I / O hub 1707, the other components including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, any suitable protocol (such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (such as NV-Link high-speed interconnect or interconnect protocol)) can be used to implement the communication paths of the various components Fig.17 therein.

[0282] In at least one embodiment, one or more parallel processors 1712 include circuitry optimized for graphics and video processing, the circuitry including, for example, video output circuitry and constituting a graphics processing unit (GPU). For example, the parallel processor 1712 includes a graphics core 1600. In at least one embodiment, one or more parallel processors 1712 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of the computing system 1700 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1712, the memory hub 1705, one or more processors 1702, and the I / O hub 1707 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of the computing system 1700 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 1700 may be integrated into a multi-chip module (MCM), and the multi-chip module may be interconnected with other multi-chip modules into a modular computing system.

[0283] The inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 615 are provided herein in connection with Fig. 6A and / or Figure 6B In at least one embodiment, the inference and / or training logic 615 may be used in the Fig.17 system 1700 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0284] Processor

[0285] Fig.18A FIG. shows a parallel processor 1800 according to at least one embodiment. In at least one embodiment, the various components of the parallel processor 1800 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 1800 is a variant of the Fig.17 one or more parallel processors 1712 shown in accordance with an exemplary embodiment. In at least one embodiment, the parallel processor 1800 includes one or more graphics cores 1600.

[0286] In at least one embodiment, the parallel processor 1800 includes a parallel processing unit 1802. In at least one embodiment, the parallel processing unit 1802 includes an I / O unit 1804 that enables communication with other devices, including other instances of the parallel processing unit 1802. In at least one embodiment, the I / O unit 1804 can be directly connected to other devices. In at least one embodiment, the I / O unit 1804 is connected to other devices via a hub or switch interface (e.g., memory hub 1805). In at least one embodiment, the connection between the memory hub 1805 and the I / O unit 1804 forms a communication link 1813. In at least one embodiment, the I / O unit 1804 is connected to a host interface 1806 and a memory crossbar 1816, where the host interface 1806 receives commands for performing processing operations and the memory crossbar 1816 receives commands for performing memory operations.

[0287] In at least one embodiment, when the host interface 1806 receives a command buffer via the I / O unit 1804, the host interface 1806 can direct the work operations for executing those commands to the front end 1808. In at least one embodiment, the front end 1808 is coupled to a scheduler 1810 (which may be referred to as an orderer), and the scheduler 1810 is configured to allocate commands or other work items to an array of processing clusters 1812. In at least one embodiment, the scheduler 1810 ensures that the array of processing clusters 1812 is properly configured and in an active state before tasks are assigned to the clusters in the array of processing clusters 1812. In at least one embodiment, the scheduler 1810 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1810 can be configured to perform complex scheduling and work allocation operations at both coarse-grained and fine-grained levels, enabling fast preemption and context switching of threads executing on the array of processing clusters 1812. In at least one embodiment, the host software can attest to the workload for scheduling on the array of processing clusters 1812 via one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically allocated on the array of processing clusters 1812 by the scheduler 1810 logic within the microcontroller that includes the scheduler 1810.

[0288] In at least one embodiment, the processing cluster array 1812 may include up to "N" processing clusters (e.g., cluster 1814A, cluster 1814B to cluster 1814N), where "N" represents a positive integer (which may be a different integer "N" from the integers used in other figures). In at least one embodiment, each of the clusters 1814A - 1814N of the processing cluster array 1812 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 1810 may use various scheduling and / or work assignment algorithms to assign work to the clusters 1814A - 1814N in the processing cluster array 1812, and these algorithms may vary according to the workload generated for each type of program or computation. In at least one embodiment, the scheduling may be handled dynamically by the scheduler 1810, or may be assisted in part by compiler logic during the compilation of the program logic configured to be executed by the processing cluster array 1812. In at least one embodiment, different clusters 1814A - 1814N in the processing cluster array 1812 may be assigned to process different types of programs or to perform different types of computations.

[0289] In at least one embodiment, the processing cluster array 1812 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 1812 is configured to perform general - purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 1812 may include logic for performing processing tasks, which include filtering of video and / or audio data, performing modeling operations, including physical operations, and performing data transformation.

[0290] In at least one embodiment, the processing cluster array 1812 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 1812 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 1812 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 1802 may transfer data from the system memory via the I / O unit 1804 for processing. In at least one embodiment, during processing, the transferred data may be stored in on - chip memory (e.g., parallel processor memory 1822) during processing and then written back to the system memory.

[0291] In at least one embodiment, when the parallel processing unit 1802 is used to perform graphics processing, the scheduler 1810 can be configured to divide the processing workload into tasks of approximately equal size to better achieve the distribution of graphics processing operations to the multiple clusters 1814A - 1814N in the processing cluster array 1812. In at least one embodiment, portions of the processing cluster array 1812 can be configured to perform different types of processing. For example, in at least one embodiment, the first portion can be configured to perform vertex shading and topology generation, the second portion can be configured to perform tessellation and geometry shading, and the third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, the intermediate data generated by one or more of the clusters 1814A - 1814N can be stored in a buffer to allow the transfer of intermediate data between the clusters 1814A - 1814N for further processing.

[0292] In at least one embodiment, the processing cluster array 1812 can receive the processing tasks to be executed via the scheduler 1810, which receives commands defining the processing tasks from the front end 1808. In at least one embodiment, the processing tasks can include indices of the data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as status parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 1810 can be configured to obtain the index corresponding to the task or can receive the index from the front end 1808. In at least one embodiment, the front end 1808 can be configured to ensure that the processing cluster array 1812 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch - buffer, push buffer, etc.).

[0293] In at least one embodiment, each of one or more instances of parallel processing unit 1802 may be coupled to parallel processor memory 1822. In at least one embodiment, parallel processor memory 1822 may be accessed via memory crossbar 1816, which may receive memory requests from processing cluster array 1812 as well as I / O unit 1804. In at least one embodiment, memory crossbar 1816 may access parallel processor memory 1822 via memory interface 1818. In at least one embodiment, memory interface 1818 may include a plurality of partitioning units (e.g., partitioning unit 1820A, partitioning unit 1820B through partitioning unit 1820N), each of which may be coupled to a portion (e.g., a memory unit) of parallel processor memory 1822. In at least one embodiment, the number of partitioning units 1820A - 1820N is configured to be equal to the number of memory units such that first partitioning unit 1820A has a corresponding first memory unit 1824A, second partitioning unit 1820B has a corresponding second memory unit 1824B, and Nth partitioning unit 1820N has a corresponding Nth memory unit 1824N. In at least one embodiment, the number of partitioning units 1820A - 1820N may not be equal to the number of memory units.

[0294] In at least one embodiment, memory units 1824A - 1824N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1824A - 1824N may further include 3D stacked memory, including but not limited to high bandwidth memory (HBM, HBM2e, or HBM3). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 1824A - 1824N, allowing partitioning units 1820A - 1820N to write portions of each render target in parallel to efficiently utilize the available bandwidth of parallel processor memory 1822. In at least one embodiment, a local instance of parallel processor memory 1822 may be excluded in favor of a unified memory design that utilizes system memory as well as local cache memory.

[0295] In at least one embodiment, any one of clusters 1814A - 1814N in the processing cluster array 1812 can process data to be written into any of the memory cells 1824A - 1824N within the parallel processor memory 1822. In at least one embodiment, the memory crossbar 1816 can be configured to transfer the output of each of clusters 1814A - 1814N to any of the partition units 1820A - 1820N or to another cluster 1814A - 1814N, and the other cluster 1814A - 1814N can perform additional processing operations on the output. In at least one embodiment, each of clusters 1814A - 1814N can communicate with the memory interface 1818 via the memory crossbar 1816 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar 1816 has connections to the memory interface 1818 for communicating with the I / O unit 1804 and connections to local instances of the parallel processor memory 1822, which enable processing units within different processing clusters 1814A - 1814N to communicate with system memory or other memories that are not local to the parallel processing units 1802. In at least one embodiment, the memory crossbar 1816 can use virtual channels to separate the traffic flow between the clusters 1814A - 1814N and the partition units 1820A - 1820N.

[0296] In at least one embodiment, multiple instances of the parallel processing unit 1802 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of the parallel processing unit 1802 can be configured to operate with each other even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 1802 can include floating-point units with higher precision relative to other instances. In at least one embodiment, a system including one or more instances of the parallel processing unit 1802 or the parallel processor 1800 can be implemented in various configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0297] Fig.18B is a block diagram of a partition unit 1820 according to at least one embodiment. In at least one embodiment, the partition unit 1820 is Fig.18AAn example of one of the partition units 1820A - 1820N. In at least one embodiment, the partition unit 1820 includes an L2 cache 1821, a frame buffer interface 1825, and a ROP 1826 (raster operation unit). In at least one embodiment, the L2 cache 1821 is a read / write cache configured to perform load and store operations received from the memory crossbar 1816 and the ROP 1826. In at least one embodiment, the L2 cache 1821 outputs read misses and urgent write-back requests to the frame buffer interface 1825 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 1825 for processing. In at least one embodiment, the frame buffer interface 1825 interfaces with one of the memory units (such as Fig.18A the memory units 1824A - 1824N (e.g., within the parallel processor memory 1822)).

[0298] In at least one embodiment, the ROP 1826 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. In at least one embodiment, the ROP 1826 then outputs the processed graphics data stored in the graphics memory. In at least one embodiment, the ROP 1826 includes compression logic for compressing depth or color data written to the memory and decompressing depth or color data read from the memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by the ROP 1826 can be changed based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on depth and color data per tile.

[0299] In at least one embodiment, the ROP 1826 is included within each processing cluster (e.g., Fig.18A the clusters 1814A - 1814N), rather than within the partition unit 1820. In at least one embodiment, read and write requests for pixel data rather than pixel fragment data are transmitted through the memory crossbar 1816. In at least one embodiment, the processed graphics data can be displayed on a display device (such as Fig.17 one of the one or more display devices 1710), routed by the processor 1702 for further processing, or routed by Fig.18A one of the processing entities within the parallel processor 1800 for further processing.

[0300] Fig. 18C is a block diagram of a processing cluster 1814 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is Fig.18AAn instance of one of the processing clusters 1814A - 1814N. In at least one embodiment, the processing cluster 1814 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronous threads using a common instruction unit, which is configured to issue instructions to a set of processing engines within each processing cluster.

[0301] In at least one embodiment, the operation of the processing cluster 1814 can be controlled by a pipeline manager 1832 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 1832 receives instructions from Fig.18A the scheduler 1810 and manages the execution of these instructions via the graphics multiprocessor 1834 and / or the texture unit 1836. In at least one embodiment, the graphics multiprocessor 1834 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures can be included within the processing cluster 1814. In at least one embodiment, one or more instances of the graphics multiprocessor 1834 can be included within the processing cluster 1814. In at least one embodiment, the graphics multiprocessor 1834 can process data, and a data crossbar 1840 can be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 1832 can facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 1840.

[0302] In at least one embodiment, each graphics multiprocessor 1834 within the processing cluster 1814 can include the same set of functional execution logic (e.g., arithmetic logic units, load - store units, etc.). In at least one embodiment, the functional execution logic can be configured in a pipelined manner, where new instructions can be issued before the previous instructions are completed. In at least one embodiment, the functional execution logic supports various operations, including integer and floating - point arithmetic, comparison operations, boolean operations, bit shifting, and the calculation of various algebraic functions. In at least one embodiment, different operations can be executed using the same functional unit hardware, and any combination of functional units can exist.

[0303] In at least one embodiment, the instructions transmitted to processing cluster 1814 constitute threads. In at least one embodiment, a set of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 1834. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within graphics multiprocessor 1834. In at least one embodiment, when the number of threads included in a thread group is less than the number of processing engines, one or more processing engines can be idle during the cycle in which the thread group is being processed. In at least one embodiment, a thread group can also include more threads than the number of processing engines within graphics multiprocessor 1834. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor 1834, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor 1834.

[0304] In at least one embodiment, graphics multiprocessor 1834 includes an internal cache memory for performing load and store operations. In at least one embodiment, graphics multiprocessor 1834 can forgo the internal cache and use the cache memory (e.g., L1 cache 1848) within processing cluster 1814. In at least one embodiment, each graphics multiprocessor 1834 can also access the L2 cache within partition units (e.g., Fig.18A partition units 1820A - 1820N) of partition unit, which are shared among all processing clusters 1814 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1834 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 1802 can be used as global memory. In at least one embodiment, processing cluster 1814 includes multiple instances of graphics multiprocessor 1834, which can share common instructions and data that can be stored in L1 cache 1848.

[0305] In at least one embodiment, each processing cluster 1814 can include a memory management unit (“MMU”) 1845 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 1845 can reside in Fig.18Awithin the memory interface 1818. In at least one embodiment, the MMU 1845 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 1845 may include a translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 1834 or the L1 cache 1848 or the processing cluster 1814. In at least one embodiment, the physical address is processed to allocate surface data access locality for efficient request interleaving among partition units. In at least one embodiment, the cache line index may be used to determine whether a request to a cache line is a hit or a miss.

[0306] In at least one embodiment, the processing cluster 1814 may be configured such that each graphics multiprocessor 1834 is coupled to a texture unit 1836 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from the L1 cache within the graphics multiprocessor 1834 as needed, and texture data is fetched from the L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 1834 outputs the processed tasks to the data crossbar 1840 to provide the processed tasks to another processing cluster 1814 for further processing, or stores the processed tasks in the L2 cache, local parallel processor memory, or in the system memory via the memory crossbar 1816. In at least one embodiment, the preROP 1842 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 1834 and direct the data to the ROP unit, which may be located together with the partition units (e.g., Fig.18A the partition units 1820A - 1820N) described herein. In at least one embodiment, the PreROP 1842 unit may perform optimizations for color blending, organizing pixel color data, and performing address translation.

[0307] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 615 are provided in connection with Fig. 6A and / or Figure 6B In at least one embodiment, the inference and / or training logic 615 may be used within the graphics processing cluster 1814 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0308] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 may be combined with 18A to 18C features in and may be configured to receive sensor inputs from a plurality of sensors 372 (in Figure 3 ) and may be trained to infer the coolant state of a first coolant or a second coolant. In at least one embodiment, the inference and / or training logic 615 may include information of the type of interchangeable flow controllers such that the coolant state can be further differentiated relative to the type of interchangeable flow controllers used with a flow controller adapter. In at least one embodiment, the inference and / or training logic 615 may infer a change in the coolant state of the coolant. In at least one embodiment, the sensor inputs may be related to categories of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states may indicate the coolant state of the coolant or a change thereof.

[0309] Fig.18D FIG. shows a graphics multiprocessor 1834 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 1834 is coupled to a pipeline manager 1832 of a processing cluster 1814. In at least one embodiment, the graphics multiprocessor 1834 has an execution pipeline that includes, but is not limited to, an instruction cache 1852, an instruction unit 1854, an address mapping unit 1856, a register file 1858, one or more general-purpose graphics processing unit (GPGPU) cores 1862, and one or more load / store units 1866, where one or more load / store units 1866 may perform load / store operations to load / store instructions corresponding to execution operations. In at least one embodiment, the GPGPU cores 1862 and the load / store units 1866 are coupled to a cache memory 1872 and a shared memory 1870 via a memory and cache interconnect 1868.

[0310] In at least one embodiment, the instruction cache 1852 receives a stream of instructions to be executed from the pipeline manager 1832. In at least one embodiment, the instructions are cached in the instruction cache 1852 and dispatched for execution by the instruction unit 1854. In at least one embodiment, the instruction unit 1854 may dispatch instructions as thread groups (e.g., warps, wavefronts, waves), where each thread in a thread group is assigned to a different execution unit within a GPGPU core 1862. In at least one embodiment, instructions may access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, the address mapping unit 1856 may be used to convert an address in the unified address space into a different memory address that can be accessed by the load / store units 1866.

[0311] In at least one embodiment, register file 1858 provides a set of registers for the functional units of graphics multiprocessor 1834. In at least one embodiment, register file 1858 provides temporary storage for the operands of the data paths of the functional units (e.g., GPGPU cores 1862, load / store units 1866) connected to graphics multiprocessor 1834. In at least one embodiment, register file 1858 is partitioned among each of the functional units such that a dedicated portion of register file 1858 is allocated to each functional unit. In at least one embodiment, register file 1858 is partitioned among different warps (which may be referred to as wavefronts and / or waves) being executed by graphics multiprocessor 1834.

[0312] In at least one embodiment, each of GPGPU cores 1862 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing the instructions of graphics multiprocessor 1834. In at least one embodiment, the architectures of the respective GPGPU cores 1862 may be similar or may be different. In at least one embodiment, a first portion of GPGPU core 1862 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, graphics multiprocessor 1834 may additionally include one or more fixed-function or special-function units for performing specific functions such as copy rectangle or pixel blend operations. In at least one embodiment, one or more of GPGPU cores 1862 may also include fixed or special-function logic.

[0313] In at least one embodiment, GPGPU core 1862 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, GPGPU core 1862 may physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core may be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a single-program multiple-data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logic unit.

[0314] In at least one embodiment, the memory and cache interconnect 1868 is an interconnect network that connects each functional unit of the graphics multiprocessor 1834 to the register file 1858 and the shared memory 1870. In at least one embodiment, the memory and cache interconnect 1868 is a crossbar interconnect that allows the load / store unit 1866 to perform load and store operations between the shared memory 1870 and the register file 1858. In at least one embodiment, the register file 1858 can operate at the same frequency as the GPGPU core 1862, so that the latency of data transfer between the GPGPU core 1862 and the register file 1858 is very low. In at least one embodiment, the shared memory 1870 can be used to implement communication between threads executing on the functional units within the graphics multiprocessor 1834. In at least one embodiment, the cache memory 1872 can be used as, for example, a data cache for caching texture data communicated between the functional units and the texture unit 1836. In at least one embodiment, the shared memory 1870 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in the cache memory 1872, threads executing on the GPGPU core 1862 can also programmatically store data in the shared memory.

[0315] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated with the core on a package or chip and communicatively coupled to the core via an internal processor bus / interconnect within the package or chip. In at least one embodiment, regardless of how the GPU is connected, the processor core can allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0316] The inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection with Fig. 6A and / or Figure 6BProvide details regarding inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 can be used in the graphics multiprocessor 1834 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0317] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 can be used in conjunction with Fig.18D features in, and can be configured to receive sensor inputs from multiple sensors 372 (in Figure 3 ), and can be trained to infer the coolant state of a first coolant or a second coolant. In at least one embodiment, the inference and / or training logic 615 can include information of the type of interchangeable flow controllers such that the coolant state can be further differentiated relative to the type of interchangeable flow controllers used with a flow controller adapter. In at least one embodiment, the inference and / or training logic 615 can infer a change in the coolant state of the coolant. In at least one embodiment, the sensor inputs can be associated with categories of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states can indicate the coolant state of the coolant or a change thereof.

[0318] Fig.19FIG. 1900 shows a multi-GPU computing system 1900 according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 1900 may include a processor 1902 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 1906A-D via a host interface switch 1904. In at least one embodiment, the host interface switch 1904 is a PCI Express switch device that couples the processor 1902 to a PCI Express bus, and the processor 1902 may communicate with the GPGPUs 1906A-D via the PCI Express bus. In at least one embodiment, the GPGPUs 1906A-D may be interconnected via a set of high-speed P2P (peer-to-peer) GPU-to-GPU links 1916. In at least one embodiment, the GPU-to-GPU link 1916 is connected to each of the GPGPUs 1906A-D via a dedicated GPU link. In at least one embodiment, the P2P GPU link 1916 enables direct communication between each of the GPGPUs 1906A-D without communicating through the host interface bus 1904 to which the processor 1902 is connected. In at least one embodiment, when GPU-to-GPU traffic is directed to the P2P GPU link 1916, the host interface bus 1904 remains available for system memory access or communication with other instances of the multi-GPU computing system 1900 via, for example, one or more network devices. Although in at least one embodiment the GPGPUs 1906A-D are connected to the processor 1902 via the host interface switch 1904, in at least one embodiment the processor 1902 includes direct support for the P2P GPU link 1916 and may be directly connected to the GPGPUs 1906A-D.

[0319] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in connection with Fig. 6A and / or Figure 6B provides details regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 may be used in the multi-GPU computing system 1900 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0320] In at least one embodiment, the multi-GPU computing system 1900 includes one or more graphics cores 1600.

[0321] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 may be combined with Fig.19is used in the features and can be configured to receive sensor inputs from multiple sensors 372 (in Figure 3 ), and can be trained to infer the coolant state of the first coolant or the second coolant. In at least one embodiment, the inference and / or training logic 615 may include information of the type of interchangeable flow controllers such that the coolant state can be further differentiated relative to the type of interchangeable flow controllers used with the flow controller adapter. In at least one embodiment, the inference and / or training logic 615 can infer a change in the coolant state of the coolant. In at least one embodiment, the sensor inputs can be related to categories of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states can indicate the coolant state of the coolant or a change thereof.

[0322] Fig. 20 is a block diagram of a graphics processor 2000 according to at least one embodiment. In at least one embodiment, the graphics processor 2000 includes a ring interconnect 2002, a pipeline front end 2004, a media engine 2037, and graphics cores 2080A - 2080N. In at least one embodiment, the ring interconnect 2002 couples the graphics processor 2000 to other processing units, which include other graphics processors or one or more general - purpose processor cores. In at least one embodiment, the graphics processor 2000 is one of many processors integrated within a multi - core processing system. In at least one embodiment, the graphics processor 2000 includes a graphics core 1600.

[0323] In at least one embodiment, the graphics processor 2000 receives multiple batches of commands via the ring interconnect 2002. In at least one embodiment, the input commands are interpreted by a command streamer 2003 in the pipeline front end 2004. In at least one embodiment, the graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via the graphics cores 2080A - 2080N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2003 provides the commands to a geometry pipeline 2036. In at least one embodiment, for at least some media processing commands, the command streamer 2003 provides the commands to a video front end 2034, which is coupled to the media engine 2037. In at least one embodiment, the media engine 2037 includes a video quality engine (VQE) 2030 for video and image post - processing, and a multi - format encoding / decoding (MFX) 2033 engine for providing hardware - accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 2036 and the media engine 2037 each generate execution threads for thread execution resources provided by at least one graphics core 2080.

[0324] In at least one embodiment, the graphics processor 2000 includes scalable thread execution resources featuring graphics cores 2080A-2080N (which may be modular and sometimes referred to as core slices), each graphics core having a plurality of sub-cores 2050A-2050N, 2060A-2060N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2000 can have any number of graphics cores 2080A. In at least one embodiment, the graphics processor 2000 includes a graphics core 2080A having at least a first sub-core 2050A and a second sub-core 2060A. In at least one embodiment, the graphics processor 2000 is a low-power processor having a single sub-core (e.g., 2050A). In at least one embodiment, the graphics processor 2000 includes a plurality of graphics cores 2080A-2080N, each graphics core including a set of first sub-cores 2050A-2050N and a set of second sub-cores 2060A-2060N. In at least one embodiment, each of the first sub-cores 2050A-2050N includes at least a first set of execution units 2052A-2052N and media / texture samplers 2054A-2054N. In at least one embodiment, each of the second sub-cores 2060A-2060N includes at least a second set of execution units 2062A-2062N and samplers 2064A-2064N. In at least one embodiment, each sub-core 2050A-2050N, 2060A-2060N shares a set of shared resources 2070A-2070N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic. In at least one embodiment, the graphics processor 2000 includes load / store units in a pipeline front end 2004.

[0325] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Fig. 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided. In at least one embodiment, the inference and / or training logic 615 can be used in the graphics processor 2000 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0326] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 can be used in conjunction with Fig. 20 features in, and can be configured to receive data from a plurality of sensors 372 (in Figure 3receives sensor inputs and can be trained to infer the coolant state of a first coolant or a second coolant. In at least one embodiment, the inference and / or training logic 615 can include information of the type of interchangeable flow controllers such that the coolant state can be further differentiated relative to the type of interchangeable flow controllers used with a flow controller adapter. In at least one embodiment, the inference and / or training logic 615 can infer a change in the coolant state of the coolant. In at least one embodiment, the sensor inputs can be related to categories of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states can indicate the coolant state of the coolant or a change thereof.

[0327] Fig.21 is a block diagram showing a microarchitecture for a processor 2100 according to at least one embodiment, the processor 2100 can include logic circuitry for executing instructions. In at least one embodiment, the processor 2100 can execute instructions, including x86 instructions, ARM instructions, special instructions for application specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2100 can include registers for storing packed data, such as 64-bit wide MMX TM registers implemented in a microprocessor using the MMX technology of Intel Corporation in Santa Clara, California. In at least one embodiment, MMX registers available in both integer and floating-point forms can operate with packed data elements that accompany single instruction multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX or beyond (commonly referred to as “SSEx”) technologies can hold such packed data operands. In at least one embodiment, the processor 2100 can execute instructions to accelerate machine learning or deep learning algorithms, training or inference.

[0328] In at least one embodiment, the processor 2100 includes an in-order front end (“front end”) 2101 for fetching instructions to be executed and preparing the instructions for later use in the processor pipeline. In at least one embodiment, the front end 2101 may include a number of units. In at least one embodiment, the instruction prefetcher 2126 fetches instructions from memory and feeds the instructions to the instruction decoder 2128, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2128 decodes the received instructions into one or more operations of so-called “micro-operations” or “micro-instructions” (also referred to as “micro ops” or “uops” or “μ-ops”) that are machine-executable. In at least one embodiment, the instruction decoder 2128 parses the instruction into an opcode and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, the trace cache 2130 may assemble the decoded micro-operations into a program-ordered sequence or trace in the micro-operation queue 2134 for execution. In at least one embodiment, when the trace cache 2130 encounters a complex instruction, the microcode ROM 2132 provides the micro-operations required to complete the operation.

[0329] In at least one embodiment, some instructions may be converted into a single micro-operation, while other instructions require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-operations are required to complete an instruction, the instruction decoder 2128 may access the microcode ROM 2132 to execute the instruction. In at least one embodiment, instructions may be decoded into a small number of micro-operations for processing at the instruction decoder 2128. In at least one embodiment, if multiple micro-operations are required to complete the operation, the instruction may be stored in the microcode ROM 2132. In at least one embodiment, the trace cache 2130 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2132 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2132 finishes serializing the micro-operations for an instruction, the front end 2101 of the machine may resume fetching micro-operations from the trace cache 2130.

[0330] In at least one embodiment, an out-of-order execution engine (“out-of-order engine”) 2103 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction stream to optimize performance as the instruction stream proceeds down the pipeline and is scheduled for execution. In at least one embodiment, the out-of-order execution engine 2103 includes, but is not limited to, an allocator / register renamer 2140, a memory micro-operation queue 2142, an integer / floating-point micro-operation queue 2144, a memory scheduler 2146, a fast scheduler 2102, a slow / general floating-point scheduler (“slow / general FP scheduler”) 2104, and a simple floating-point scheduler (“simple FP scheduler”) 2106. In at least one embodiment, the fast scheduler 2102, the slow / general floating-point scheduler 2104, and the simple floating-point scheduler 2106 are also collectively referred to herein as “micro-operation schedulers 2102, 2104, 2106”. In at least one embodiment, the allocator / register renamer 2140 allocates the machine buffers and resources required for each micro-operation for execution. In at least one embodiment, the allocator / register renamer 2140 renames logical registers to entries in the register file. In at least one embodiment, the allocator / register renamer 2140 also allocates entries for each micro-operation in one of two micro-operation queues, the memory micro-operation queue 2142 for memory operations and the integer / floating-point micro-operation queue 2144 for non-memory operations, ahead of the memory scheduler 2146 and the micro-operation schedulers 2102, 2104, 2106. In at least one embodiment, the micro-operation schedulers 2102, 2104, 2106 determine when a micro-operation is ready for execution based on the readiness of its dependent input register operand sources and the availability of the execution resources required for the micro-operation to complete its operation. In at least one embodiment, the fast scheduler 2102 may be scheduled on each half of the main clock cycle, while the slow / general floating-point scheduler 2104 and the simple floating-point scheduler 2106 may be scheduled once per main processor clock cycle. In at least one embodiment, the micro-operation schedulers 2102, 2104, 2106 arbitrate dispatch ports to schedule micro-operations for execution.

[0331] In at least one embodiment, execution block 2111 includes, but is not limited to, integer register file / bypass network 2108, floating-point register file / bypass network (“FP register file / bypass network”) 2110, address generation units (“AGUs”) 2112 and 2114, fast arithmetic logic units (ALUs) (“fast ALUs”) 2116 and 2118, slow arithmetic logic unit (“slow ALU”) 2120, floating-point ALU (“FP”) 2122, and floating-point move unit (“FP move”) 2124. In at least one embodiment, integer register file / bypass network 2108 and floating-point register file / bypass network 2110 are also referred to herein as “register files 2108, 2110”. In at least one embodiment, AGUs 2112 and 2114, fast ALUs 2116 and 2118, slow ALU 2120, floating-point ALU 2122, and floating-point move unit 2124 are also referred to herein as “execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124”. In at least one embodiment, execution block 2111 may include, but is not limited to, any number (including zero) and type of register files, bypass networks, address generation units, and execution units in any combination.

[0332] In at least one embodiment, register networks 2108, 2110 may be arranged between micro-operation schedulers 2102, 2104, 2106 and execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124. In at least one embodiment, integer register file / bypass network 2108 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2110 performs floating-point operations. In at least one embodiment, each of register networks 2108, 2110 may include, but is not limited to, a bypass network that may bypass or forward to a new dependent micro-operation a just-completed result that has not yet been written to the register file. In at least one embodiment, register networks 2108, 2110 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2108 may include, but is not limited to, two separate register files, one for low-order 32-bit data and the other for high-order 32-bit data. In at least one embodiment, floating-point register file / bypass network 2110 may include, but is not limited to, 128-bit wide entries since floating-point instructions typically have operands with widths ranging from 64 bits to 128 bits.

[0333] In at least one embodiment, execution units 2112, 2114, 2116, 2118, 2120, 2122, 2124 may execute instructions. In at least one embodiment, register networks 2108, 2110 store integer and floating-point data operand values required for microinstructions to be executed. In at least one embodiment, processor 2100 may include, but is not limited to, any number of execution units 2112, 2114, 2116, 2118, 2120, 2122, 2124 and combinations thereof. In at least one embodiment, floating-point ALU 2122 and floating-point move unit 2124 may execute floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2122 may include, but is not limited to, a 64-bit by 64-bit floating-point divider for performing division, square root, and remainder micro-operations. In at least one embodiment, instructions involving floating-point values may be processed with floating-point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs 2116, 2118. In at least one embodiment, fast ALUs 2116, 2118 may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations enter slow ALU 2120 because slow ALU 2120 may include, but is not limited to, integer execution hardware for long-latency type operations such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations may be performed by AGUs 2112, 2114. In at least one embodiment, fast ALU 2116, fast ALU 2118, and slow ALU 2120 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2116, fast ALU 2118, and slow ALU 2120 may be implemented to support various data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, floating-point ALU 2122 and floating-point move unit 2124 may be implemented to support a range of operands with various widths of bits, such as supporting 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0334] In at least one embodiment, the micro - operation schedulers 2102, 2104, 2106 dispatch dependent operations before the parent load has completed execution. In at least one embodiment, since micro - operations can be speculatively scheduled and executed in the processor 2100, the processor 2100 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be dependent operations running in the pipeline, which leave the scheduler temporarily without the correct data. In at least one embodiment, a replay mechanism tracks and re - executes instructions that used incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and independent operations may be allowed to complete. In at least one embodiment, the scheduler and the replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text - string comparison operations.

[0335] In at least one embodiment, a "register" may refer to an on - board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from the programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuits within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32 - bit integer data. The register file of at least one embodiment also contains eight multimedia SIMD registers for packing data.

[0336] In at least one embodiment, the processor 2100 or each core of the processor 2100 includes one or more prefetchers, one or more fetchers, one or more pre - decoders, one or more decoders for decoding data (e.g., instructions), one or more instruction queues for processing instructions (e.g., corresponding to operations or API calls), one or more micro - operation (μOP) caches for storing μOPs, one or more micro - operation (μOP) queues, an in - order execution engine, one or more load buffers, one or more store buffers, one or more reorder buffers, one or more fill buffers, an out - of - order execution engine, one or more ports, one or more shift and / or shifter units, one or more fused multiply - add (FMA) units, one or more load and store units (“LSU”) for performing load operations corresponding to loading / storing data (e.g., instructions) to perform operations (e.g., execute an API, API call), one or more matrix multiply - accumulate (MMA) units, and / or one or more shuffle units, to perform any function further described herein with respect to the processor 2100. In at least one embodiment, the processor 2100 can access, use, execute, or perform instructions corresponding to calling an API.

[0337] In at least one embodiment, the processor 2100 includes one or more Ultra - Path Interconnects (UPI), e.g., the UPI is a point - to - point processor interconnect; one or more PCIe; one or more accelerators for accelerating computations or operations; and / or one or more memory controllers. In at least one embodiment, the processor 2100 includes a shared last - level cache (LLC) coupled to one or more memory controllers, which can enable shared memory access across processor cores.

[0338] In at least one embodiment, the processor 2100 or the core of the processor 2100 has a mesh architecture, where processor cores, on - chip caches, memory controllers, and I / O controllers are organized in rows and columns, and wires and switches connect them at each intersection to allow turns. In at least one embodiment, the processor 2100 has one or more higher memory bandwidths (HMB, e.g., HMBe) to store data or cache data, for example, in double - data - rate 5 synchronous dynamic random - access memory (DDR5 SDRAM). In at least one embodiment, one or more components of the processor 2100 are interconnected using Compute Express Link (CXL) interconnects. In at least one embodiment, the memory controller uses the “least recently used” (LRU) method to determine what is stored in the cache. In at least one embodiment, the processor 2100 includes one or more PCIe (e.g., PCIe 5.0).

[0339] The inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in connection with Fig. 6A and / or Figure 6B providing details regarding the inference and / or training logic 615. In at least one embodiment, part or all of the inference and / or training logic 615 may be incorporated into the execution block 2111 and other memories or registers, shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in the execution block 2111. Additionally, weight parameters may be stored in on-chip or off-chip memories and / or registers (shown or not shown), which configure the ALUs of the execution block 2111 to perform one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0340] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 may be used in conjunction with Fig.21 features in, and may be configured to receive sensor inputs from multiple sensors 372 (in Figure 3 ), and may be trained to infer the coolant state of a first coolant or a second coolant. In at least one embodiment, the inference and / or training logic 615 may include information of the type of interchangeable flow controllers such that the coolant state can be further differentiated with respect to the type of interchangeable flow controllers used with a flow controller adapter. In at least one embodiment, the inference and / or training logic 615 may infer a change in the coolant state of the coolant. In at least one embodiment, the sensor inputs may be associated with classes of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states may indicate the coolant state of the coolant or a change thereof.

[0341] Fig. 22The deep learning application processor 2200 according to at least one embodiment is shown. In at least one embodiment, the deep learning application processor 2200 uses instructions that, if executed by the deep learning application processor 2200, cause the deep learning application processor 2200 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2200 is an application specific integrated circuit (ASIC). In at least one embodiment, as a result of executing one or more instructions or both, the application processor 2200 performs matrix multiplication operations or is "hardwired" into the hardware. In at least one embodiment, the deep learning application processor 2200 includes, but is not limited to, processing clusters 2210(1)-2210(12), inter-chip links ("ICL") 2220(1)-2220(12), inter-chip controllers ("ICC") 2230(1)-2230(2), second generation high bandwidth memories ("HBM2") 2240(1)-2240(4), memory controllers ("Mem Ctrlr") 2242(1)-2242(4), high bandwidth memory physical layers ("HBM PHY") 2244(1)-2244(4), management controller central processing units ("management controller CPU") 2250, serial peripheral interfaces, internal integrated circuits and general purpose input / output blocks ("SPI, I 2 C, GPIO") 2260, peripheral component interconnect express controllers and direct memory access blocks ("PCIe controllers and DMA") 2270, and sixteen-lane peripheral component interconnect express ports ("PCI Express x16") 2280.

[0342] In at least one embodiment, the processing cluster 2210 can perform deep learning operations, including inference or prediction operations based on weight parameters calculated using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2210 can include, but is not limited to, any number and type of processors. In at least one embodiment, the deep learning application processor 2200 can include any number and type of processing clusters 2200. In at least one embodiment, the inter-chip link 2220 is bidirectional. In at least one embodiment, the inter-chip link 2220 and the inter-chip controller 2230 enable multiple deep learning application processors 2200 to exchange information, including activation information resulting from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2200 can include any number (including zero) and type of ICL 2220 and ICC 2230.

[0343] In at least one embodiment, the HBM2 2240 provides a total of 32 GB of memory. In at least one embodiment, the HBM2 2240 (i) is associated with both a memory controller 2242(i) and an HBM PHY 2244(i), where "i" is any integer. In at least one embodiment, any number of HBM2 2240s can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controllers 2242 and HBM PHYs 2244. In at least one embodiment, any number and type of blocks implementing any number and type of communication standards can replace SPI, I 2 C, GPIO 2260, PCIe controller, and DMA 2270 and / or PCIe 2280.

[0344] The inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 615 are provided herein in connection with Fig. 6A and / or Figure 6B In at least one embodiment, a deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the deep learning application processor 2200. In at least one embodiment, the deep learning application processor 2200 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2200. In at least one embodiment, the processor 2200 can be used to perform one or more of the neural network use cases described herein.

[0345] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 can be used in conjunction with Fig. 22 features in, and can be configured to receive sensor inputs from multiple sensors 372 (in Figure 3 ), and can be trained to infer the coolant state of a first coolant or a second coolant. In at least one embodiment, the inference and / or training logic 615 can include information of the type of interchangeable flow controllers such that the coolant state can be further differentiated with respect to the type of interchangeable flow controllers used with a flow controller adapter. In at least one embodiment, the inference and / or training logic 615 can infer a change in the coolant state of the coolant. In at least one embodiment, the sensor inputs can be associated with categories of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states can indicate the coolant state of the coolant or a change thereof.

[0346] Fig.23 is a block diagram of a neuromorphic processor 2300 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2300 may receive one or more inputs from a source external to the neuromorphic processor 2300. In at least one embodiment, these inputs may be transmitted to one or more neurons 2302 within the neuromorphic processor 2300. In at least one embodiment, the neurons 2302 and their components may be implemented using circuitry or logic that includes one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2300 may include, but is not limited to, thousands or millions of instances of neurons 2302, but any suitable number of neurons 2302 may be used. In at least one embodiment, each instance of the neurons 2302 may include a neuron input 2304 and a neuron output 2306. In at least one embodiment, the neurons 2302 may generate outputs that may be inputs to other instances of the neurons 2302. For example, in at least one embodiment, the neuron input 2304 and the neuron output 2306 may be interconnected via a synapse 2308.

[0347] In at least one embodiment, neurons 2302 and synapses 2308 may be interconnected such that neuromorphic processor 2300 operates to process or analyze information received by neuromorphic processor 2300. In at least one embodiment, when the input received via neuron input 2304 exceeds a threshold, neuron 2302 may send an output pulse (or “fire” or “spike”). In at least one embodiment, neuron 2302 may sum or integrate the signals received at neuron input 2304. For example, in at least one embodiment, neuron 2302 may be implemented as a leaky integrate-and-fire neuron, where if the sum (referred to as the “membrane potential”) exceeds a threshold, neuron 2302 may use a transfer function such as a sigmoid or threshold function to produce an output (or “fire”). In at least one embodiment, a leaky integrate-and-fire neuron may sum the signals received at neuron input 2304 into a membrane potential and may also apply a decay factor (or leak) to decrease the membrane potential. In at least one embodiment, if multiple input signals are received at neuron input 2304 fast enough to exceed the threshold (i.e., before the membrane potential decays too low to fire), then the leaky integrate-and-fire neuron may fire. In at least one embodiment, neuron 2302 may be implemented using circuitry or logic that receives inputs, integrates the inputs into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Additionally, in at least one embodiment, neuron 2302 may include, but is not limited to, comparator circuitry or logic that produces an output spike at neuron output 2306 when the result of applying a transfer function to neuron input 2304 exceeds a threshold. In at least one embodiment, once neuron 2302 fires, it may ignore previously received input information, for example, by resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2302 may resume normal operation after a suitable period of time (or refractory period).

[0348] In at least one embodiment, neurons 2302 may be interconnected by synapses 2308. In at least one embodiment, synapses 2308 may operate to send a signal of the output from a first neuron 2302 to the input of a second neuron 2302. In at least one embodiment, a neuron 2302 may convey information on more than one instance of a synapse 2308. In at least one embodiment, one or more instances of a neuron output 2306 may be connected to an instance of a neuron input 2304 in the same neuron 2302 via an instance of a synapse 2308. In at least one embodiment, with respect to an instance of a synapse 2308, the instance of the neuron 2302 that produces the output to be conveyed on that instance of the synapse 2308 may be referred to as a "presynaptic neuron". In at least one embodiment, with respect to an instance of a synapse 2308, the instance of the neuron 2302 that receives the input conveyed through that instance of the synapse 2308 may be referred to as a "postsynaptic neuron". In at least one embodiment, with respect to each instance of a synapse 2308, since an instance of a neuron 2302 may receive input from one or more instances of a synapse 2308 and may also convey output through one or more instances of a synapse 2308, a single instance of a neuron 2302 may be both a "presynaptic neuron" and a "postsynaptic neuron".

[0349] In at least one embodiment, the neurons 2302 may be organized into one or more layers. In at least one embodiment, each instance of the neurons 2302 may have a neuron output 2306 that may fan out through one or more synapses 2308 to one or more neuron inputs 2304. In at least one embodiment, the neuron outputs 2306 of the neurons 2302 in the first layer 2310 may be connected to the neuron inputs 2304 of the neurons 2302 in the second layer 2312. In at least one embodiment, the layer 2310 may be referred to as a "feed-forward layer". In at least one embodiment, each instance of the neurons 2302 in an instance of the first layer 2310 may fan out to each instance of the neurons 2302 in the second layer 2312. In at least one embodiment, the first layer 2310 may be referred to as a "fully connected feed-forward layer". In at least one embodiment, each instance of the neurons 2302 in an instance of the second layer 2312 may fan out to fewer than all instances of the neurons 2302 in the third layer 2314. In at least one embodiment, the second layer 2312 may be referred to as a "sparsely connected feed-forward layer". In at least one embodiment, the neurons 2302 in the second layer 2312 may fan out to the neurons 2302 in multiple other layers, including fanning out to the neurons 2302 that are also in the second layer 2312. In at least one embodiment, the second layer 2312 may be referred to as a "recurrent layer". In at least one embodiment, the neuromorphic processor 2300 may include any suitable combination of, but is not limited to, recurrent layers and feed-forward layers, including but not limited to sparsely connected feed-forward layers and fully connected feed-forward layers.

[0350] In at least one embodiment, the neuromorphic processor 2300 may include, but is not limited to, a reconfigurable interconnect architecture or dedicated hardwired interconnections for connecting the synapses 2308 to the neurons 2302. In at least one embodiment, the neuromorphic processor 2300 may include, but is not limited to, circuitry or logic that allows the assignment of synapses to different neurons 2302 as needed based on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, an interconnect structure such as a network-on-chip may be used or dedicated connections may be utilized to connect the synapses 2308 to the neurons 2302. In at least one embodiment, circuitry or logic may be used to implement the synapse interconnections and their components.

[0351] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 may be combined Fig.23 with the features in, and may be configured to be used for receiving data from multiple sensors 372 (in Figure 3receives sensor inputs and can be trained to infer the coolant state of a first coolant or a second coolant. In at least one embodiment, the inference and / or training logic 615 can include information of the type of interchangeable flow controllers such that the coolant state can be further differentiated relative to the type of interchangeable flow controllers used with a flow controller adapter. In at least one embodiment, the inference and / or training logic 615 can infer a change in the coolant state of the coolant. In at least one embodiment, the sensor inputs can be associated with categories of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states can indicate the coolant state of the coolant or a change thereof.

[0352] Fig.24 is a processing system according to at least one embodiment. In at least one embodiment, the system 2400 includes one or more processors 2402 and one or more graphics processors 2408, and can be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2402 or processor cores 2407. In at least one embodiment, the system 2400 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices. In at least one embodiment, one or more of the graphics processors 2408 include one or more graphics cores 1600.

[0353] In at least one embodiment, the system 2400 can be included in or incorporated with a server-based gaming platform, a gaming console including a game and media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In at least one embodiment, the system 2400 is a mobile phone, a smartphone, a tablet computing device, or a mobile Internet device. In at least one embodiment, the processing system 2400 can also be coupled to or integrated within a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2400 is a television or set-top box device having one or more processors 2402 and a graphical interface generated by one or more graphics processors 2408.

[0354] In at least one embodiment, each of one or more processors 2402 includes one or more processor cores 2407 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores 2407 is configured to process a particular instruction sequence 2409. In at least one embodiment, the instruction sequence 2409 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). In at least one embodiment, the processor cores 2407 can each process a different instruction sequence 2409, which can include instructions that help to emulate other instruction sequences. In at least one embodiment, the processor cores 2407 can also include other processing devices, such as digital signal processors (DSPs).

[0355] In at least one embodiment, the processor 2402 includes a cache memory 2404. In at least one embodiment, the processor 2402 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among the various components of the processor 2402. In at least one embodiment, the processor 2402 also uses an external cache (e.g., a level three (L3) cache or a last level cache (LLC)) (not shown), which can be shared among the processor cores 2407 using known cache coherence techniques. In at least one embodiment, the processor 2402 additionally includes a register file 2406, which can include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and instruction pointer registers). In at least one embodiment, the register file 2406 can include general purpose registers or other registers.

[0356] In at least one embodiment, one or more processors 2402 are coupled to one or more interface buses 2410 to transfer communication signals, such as address, data, or control signals, between the processors 2402 and other components in the system 2400. In at least one embodiment, the interface bus 2410 can be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 2410 is not limited to the DMI bus and can include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, one or more processors 2402 include an integrated memory controller 2416 and a Platform Controller Hub 2430. In at least one embodiment, the memory controller 2416 facilitates communication between the memory device and other components of the system 2400, while the Platform Controller Hub (PCH) 2430 provides connections to I / O devices via a local I / O bus.

[0357] In at least one embodiment, the memory device 2420 can be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, a Phase Change Memory device, or some other memory device with suitable performance to be used as processor memory. In at least one embodiment, the memory device 2420 can operate as the system memory of the system 2400 for storing data 2422 and instructions 2421 to be used when one or more processors 2402 execute an application or process. In at least one embodiment, the memory controller 2416 is also coupled to an optional external graphics processor 2412, which can communicate with one or more graphics processors 2408 in the processors 2402 to perform graphics and media operations. In at least one embodiment, a display device 2411 can be connected to one or more processors 2402. In at least one embodiment, the display device 2411 can include one or more of internal display devices, such as in a mobile electronic device or a laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 2411 can include a Head-Mounted Display (HMD), such as a stereoscopic display device for Virtual Reality (VR) applications or Augmented Reality (AR) applications.

[0358] In at least one embodiment, the platform controller hub 2430 enables peripheral devices to be connected to the memory device 2420 and the processor 2402 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2446, a network controller 2434, a firmware interface 2428, a wireless transceiver 2426, a touch sensor 2425, a data storage device 2424 (e.g., a hard disk drive, a flash memory, etc.). In at least one embodiment, the data storage device 2424 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2425 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2426 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2428 enables communication with the system firmware and can be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, the network controller 2434 can implement a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 2410. In at least one embodiment, the audio controller 2446 is a multi-channel high-definition audio controller. In at least one embodiment, the system 2400 includes an optional legacy I / O controller 2440 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system 2400. In at least one embodiment, the platform controller hub 2430 can also be connected to one or more Universal Serial Bus (USB) controllers 2442, which connect input devices, such as a keyboard and mouse 2443 combination, a camera 2444, or other USB input devices.

[0359] In at least one embodiment, instances of the memory controller 2416 and the platform controller hub 2430 can be integrated into a discrete external graphics processor, such as the external graphics processor 2412. In at least one embodiment, the platform controller hub 2430 and / or the memory controller 2416 can be external to one or more processors 2402. For example, in at least one embodiment, the system 2400 can include an external memory controller 2416 and a platform controller hub 2430, which can be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with one or more processors 2402.

[0360] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Fig. 6A and / or Figure 6BProvide details regarding inference and / or training logic 615. In at least one embodiment, part or all of the inference and / or training logic 615 may be incorporated into the graphics processor 2408. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in a 3D pipeline. Additionally, in at least one embodiment, the inference and / or training operations described herein may be completed using logic other than the Fig. 6A or Figure 6B shown logic. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the graphics processor 2408 to perform one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0361] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 may be combined Fig.24 with features in, and may be configured to receive sensor inputs from multiple sensors 372 (in Figure 3 ) and may be trained to infer the coolant state of a first coolant or a second coolant. In at least one embodiment, the inference and / or training logic 615 may include information of the type of interchangeable flow controllers such that the coolant state can be further differentiated with respect to the type of interchangeable flow controllers used with a flow controller adapter. In at least one embodiment, the inference and / or training logic 615 may infer a change in the coolant state of the coolant. In at least one embodiment, the sensor inputs may be related to classes of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states may indicate the coolant state of the coolant or a change thereof.

[0362] Fig.25 is a block diagram of a processor 2500 having one or more processor cores 2502A - 2502N, an integrated memory controller 2514, and an integrated graphics processor 2508 according to at least one embodiment. In at least one embodiment, the processor 2500 may include additional cores, up to and including the additional core 2502N represented by the dashed box. In at least one embodiment, each processor core 2502A - 2502N includes one or more internal cache units 2504A - 2504N. In at least one embodiment, each processor core may also access one or more shared cache units 2506. In at least one embodiment, the graphics processor 2508 includes one or more graphics cores 1600.

[0363] In at least one embodiment, the internal cache units 2504A - 2504N and the shared cache unit 2506 represent the cache memory hierarchy within the processor 2500. In at least one embodiment, the cache memory units 2504A - 2504N can include at least one level of instruction and data cache within each processor core and one or more levels of shared mid - level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest - level cache before the external memory is classified as the LLC. In at least one embodiment, cache coherence logic maintains coherence between the respective cache units 2506 and 2504A - 2504N.

[0364] In at least one embodiment, the processor 2500 may further include a group of one or more bus controller units 2516 and a system agent core 2510. In at least one embodiment, the bus controller units 2516 manage a group of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2510 provides management functions for the respective processor components. In at least one embodiment, the system agent core 2510 includes one or more integrated memory controllers 2514 for managing access to various external memory devices (not shown).

[0365] In at least one embodiment, one or more processor cores 2502A - 2502N include support for simultaneous multi - threading. In at least one embodiment, the system agent core 2510 includes components for coordinating and operating the cores 2502A - 2502N during multi - threading. In at least one embodiment, the system agent core 2510 may additionally include a power control unit (PCU) that includes logic and components for regulating one or more power states of the processor cores 2502A - 2502N and the graphics processor 2508.

[0366] In at least one embodiment, the processor 2500 further includes a graphics processor 2508 for performing graphics processing operations. In at least one embodiment, the graphics processor 2508 is coupled to the shared cache unit 2506 and the system agent core 2510 that includes one or more integrated memory controllers 2514. In at least one embodiment, the system agent core 2510 further includes a display controller 2511 for driving the output of the graphics processor to one or more coupled displays. In at least one embodiment, the display controller 2511 can also be an independent module coupled to the graphics processor 2508 via at least one interconnect, or can be integrated within the graphics processor 2508.

[0367] In at least one embodiment, a ring-based interconnect unit 2512 is used to couple internal components of the processor 2500. In at least one embodiment, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2508 is coupled to the ring interconnect 2512 via an I / O link 2513.

[0368] In at least one embodiment, the I / O link 2513 represents at least one of a variety of I / O interconnects, including a package I / O interconnect that facilitates communication between individual processor components and a high-performance embedded memory module 2518, such as an eDRAM module. In at least one embodiment, each of the processor cores 2502A - 2502N and the graphics processor 2508 uses the embedded memory module 2518 as a shared last-level cache.

[0369] In at least one embodiment, the processor cores 2502A - 2502N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2502A - 2502N are heterogeneous in terms of instruction set architecture (ISA), where one or more of the processor cores 2502A - 2502N execute a common instruction set, while one or more other cores among the processor cores 2502A - 2502N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, in terms of microarchitecture, the processor cores 2502A - 2502N are heterogeneous, where one or more cores with relatively high power consumption are coupled to one or more power cores with lower power consumption. In at least one embodiment, the processor 2500 may be implemented on one or more chips or as a SoC integrated circuit.

[0370] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 615 are provided herein in connection with Fig. 6A and / or Figure 6B In at least one embodiment, part or all of the inference and / or training logic 615 may be incorporated into the graphics processor 2508. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in Fig.25 the 3D pipeline, graphics core 2502, shared functional logic, or other logic in. Additionally, in at least one embodiment, the inference and / or training operations described herein may use other than Fig. 6A or Figure 6Bcompleted by logic other than the logic shown. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the processor 2500 to perform one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0371] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 may be combined Fig.25 with the features in and may be configured to receive sensor inputs from a plurality of sensors 372 (in Figure 3 ) and may be trained to infer the coolant state of a first coolant or a second coolant. In at least one embodiment, the inference and / or training logic 615 may include information of a type of interchangeable flow controller such that the coolant state can be further differentiated with respect to the type of interchangeable flow controller used with the flow controller adapter. In at least one embodiment, the inference and / or training logic 615 may infer a change in the coolant state of the coolant. In at least one embodiment, the sensor inputs may be associated with classes of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states may indicate the coolant state of the coolant or a change thereof.

[0372] Fig.26 is a block diagram of a graphics processor 2600, which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores. In at least one embodiment, the graphics processor 2600 communicates with registers on the graphics processor 2600 and commands placed in memory via a memory-mapped I / O interface. In at least one embodiment, the graphics processor 2600 includes a memory interface 2614 for accessing memory. In at least one embodiment, the memory interface 2614 is an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory. In at least one embodiment, the graphics processor 2600 includes a graphics core 1600.

[0373] In at least one embodiment, the graphics processor 2600 further includes a display controller 2602 for driving display output data to a display device 2620. In at least one embodiment, the display controller 2602 includes hardware for one or more overlay planes of the display device 2620 and a combination of multi-layer video or user interface elements. In at least one embodiment, the display device 2620 can be an internal or external display device. In at least one embodiment, the display device 2620 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In at least one embodiment, the graphics processor 2600 includes a video codec engine 2606 to encode, decode, or transcode media into one or more media coding formats, from one or more media coding formats, or between one or more media coding formats, the media coding formats including but not limited to Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1 and Joint Photographic Experts Group (JPEG) formats (such as JPEG) and Motion JPEG (MJPEG) formats.

[0374] In at least one embodiment, the graphics processor 2600 includes a block image transfer (BLIT) engine 2604 for performing two-dimensional (2D) rasterizer operations, including for example bit boundary block transfers. However, in at least one embodiment, one or more components of the graphics processing engine (GPE) 2610 are used to perform 2D graphics operations. In at least one embodiment, the GPE 2610 is a computing engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0375] In at least one embodiment, the GPE 2610 includes a 3D pipeline 2612 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). In at least one embodiment, the 3D pipeline 2612 includes programmable and fixed-function elements that perform various tasks and / or generate execution threads to the 3D / media subsystem 2615. Although the 3D pipeline 2612 can be used to perform media operations, in at least one embodiment, the GPE 2610 further includes a media pipeline 2616 for performing media operations, such as video post-processing and image enhancement.

[0376] In at least one embodiment, the media pipeline 2616 includes fixed-function or programmable logic units for performing one or more specialized media operations, such as video decode acceleration, video deinterlacing, and video encode acceleration, in place of or on behalf of the video codec engine 2606. In at least one embodiment, the media pipeline 2616 also includes a thread generation unit for generating threads to execute on the 3D / media subsystem 2615. In at least one embodiment, the generated threads execute computations for media operations on one or more graphics execution units included in the 3D / media subsystem 2615.

[0377] In at least one embodiment, the 3D / media subsystem 2615 includes logic for executing threads generated by the 3D pipeline 2612 and the media pipeline 2616. In at least one embodiment, the 3D pipeline 2612 and the media pipeline 2616 send thread execution requests to the 3D / media subsystem 2615, which includes thread dispatch logic for arbitrating various requests and dispatching them to available thread execution resources. In at least one embodiment, the execution resources include an array of graphics execution units for processing 3D and media threads. In at least one embodiment, the 3D / media subsystem 2615 includes one or more internal caches for thread instructions and data. In at least one embodiment, the subsystem 2615 also includes a shared memory that includes registers and addressable memory for sharing data between threads and storing output data.

[0378] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 615 are provided herein in connection with Fig. 6A and / or Figure 6B In at least one embodiment, portions or all of the inference and / or training logic 615 may be incorporated into the graphics processor 2600. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs included in the 3D pipeline 2612. Additionally, in at least one embodiment, the inference and / or training operations described herein may be performed using logic other than that shown in Fig. 6A or Figure 6B In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the graphics processor 2600 to perform one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0379] In at least one embodiment, one or more neural networks of the inference and / or training logic 615 may be used in conjunction with Fig.26 features in, and may be configured to receive input from, multiple sensors 372 (in Figure 3 receives sensor inputs and can be trained to infer the coolant state of a first coolant or a second coolant. In at least one embodiment, the inference and / or training logic 615 can include information about the type of interchangeable flow controllers such that the coolant state can be further differentiated relative to the type of interchangeable flow controllers used with a flow controller adapter. In at least one embodiment, the inference and / or training logic 615 can infer a change in the coolant state of the coolant. In at least one embodiment, the sensor inputs can be associated with categories of different coolant states for each type of coolant. In at least one embodiment, new sensor inputs classified within such different coolant states can indicate the coolant state of the coolant or a change thereof.

[0380] Fig. 27 is a block diagram of a graphics processing engine 2710 of a graphics processor according to at least one embodiment. In at least one embodiment, the graphics processing engine (GPE) 2710 is Fig.26 a version of the GPE 2610 as shown therein. In at least one embodiment, the media pipeline 2716 is optional and may not be explicitly included in the GPE 2710. In at least one embodiment, a separate media and / or image processor is coupled to the GPE 2710.

[0381] In at least one embodiment, the GPE 2710 is coupled to or includes a command stream converter 2703 that provides a command stream to the 3D pipeline 2712 and / or the media pipeline 2716. In at least one embodiment, the command stream converter 2703 is coupled to a memory, which can be a system memory or one or more of an internal cache memory and a shared cache memory. In at least one embodiment, the command stream converter 2703 receives commands from the memory and sends the commands to the 3D pipeline 2712 and / or the media pipeline 2716. In at least one embodiment, the commands are instructions, primitives, or micro-operations fetched from a ring buffer that stores commands for the 3D pipeline 2712 and the media pipeline 2716. In at least one embodiment, the ring buffer may further include a batch command buffer that stores batches of multiple commands. In at least one embodiment, the commands for the 3D pipeline 2712 may further include references to data stored in the memory, such as but not limited to vertex and geometry data for the 3D pipeline 2712 and / or image data and memory objects for the media pipeline 2716. In at least one embodiment, the 3D pipeline 2712 and the media pipeline 2716 process commands and data by performing operations or by dispatching one or more execution threads to the graphics core array 2714. In at least one embodiment, the graphics core array 2714 includes one or more graphics core blocks (e.g., one or more graphics cores 2715A, one or more graphics cores 2715B), each block including one or more graphics cores. In at least one embodiment, the graphics cores 2715A, 2715B may be referred to as execution units (“EUs”). In at least one embodiment, each graphics core includes a set of graphics execution resources, the graphics execution resources including general and graphics-specific execution logic for performing graphics and computing operations and fixed function texture processing and / or machine learning and artificial intelligence acceleration logic, which includes Fig. 6A and Figure 6B the inference and / or training logic 615 in

[0382] In at least one embodiment, the 3D pipeline 2712 includes fixed functionality and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2714. In at least one embodiment, the graphics core array 2714 provides a unified execution resource block for use in processing shader programs. In at least one embodiment, the multi-purpose execution logic (e.g., execution units) within one or more graphics cores 2715A - 2715B of the graphics core array 2714 includes support for various 3D API shader languages and can execute multiple simultaneously executing threads associated with multiple shaders.

[0383] In at least one embodiment, the graphics core array 2714 further includes execution logic for performing media functions, such as video and / or image processing. In at least one embodiment, in addition to graphics processing operations, the execution units also include general-purpose logic programmable to perform parallel general-purpose computing operations.

[0384] In at least one embodiment, the output data generated by the threads executing on the graphics core array 2714 can output data to memory in the unified return buffer (URB) 2718. In at least one embodiment, the URB 2718 can store data for multiple threads. In at least one embodiment, the URB 2718 can be used to send data between different threads executing on the graphics core array 2714. In at least one embodiment, the URB 2718 can also be used for synchronization between the threads on the graphics core array 2714 and the fixed functionality logic within the shared functional logic 2720.

[0385] In at least one embodiment, the graphics core array 2714 is scalable such that the graphics core array 2714 includes a variable number of graphics cores, each with a variable number of execution units based on the target power and performance levels of the GPE 2710. In at least one embodiment, the execution resources are dynamically scalable such that the execution resources can be enabled or disabled as needed.

[0386] In at least one embodiment, the grap...

Claims

1. A data center cooling system, comprising: A flow controller adapter for a cooling manifold, configured to interchangeably receive a first flow controller among a plurality of flow controllers, wherein the flow controller adapter is associated with a rack-side flow controller and a pipe therebetween, and wherein the flow controller adapter is configured to be movable within the cooling manifold to allow different positions for mating the flow controller with a server-side flow controller of a server tray or enclosure.

2. The data center cooling system according to claim 1, further comprising: At least one processor, associated with the flow controller adapter, for determining a cooling requirement associated with at least one computing device and causing coolant to flow through at least the flow controller adapter, the first flow controller, and the server-side flow controller for a cold plate associated with the cooling requirement.

3. The data center cooling system according to claim 1, further comprising: The flow controller adapter includes a groove for enabling movement in at least one direction along a dimension relative to the cooling manifold in a provided path.

4. The data center cooling system according to claim 1, further comprising: A position lock, associated with the provided path, for locking the flow controller adapter in a determined position to align the first flow controller with the server-side flow controller of the server tray or enclosure.

5. The data center cooling system according to claim 1, wherein the plurality of flow controllers include at least a different first orifice size or different first coupling features on at least a first side, and include a determined second orifice size and determined second coupling features on a second side, the determined second orifice size and determined second coupling features for mating with the flow controller adapter.

6. The data center cooling system according to claim 1, further comprising: At least one processor, for receiving sensor input from a sensor associated with the flow controller adapter, the at least one processor for determining a change in coolant state based at least in part on the sensor input and for causing a stop or change in coolant flow through the flow controller adapter.

7. The data center cooling system according to claim 6, further comprising: One or more neural networks, for receiving the sensor input and inferring the change in coolant state.

8. The data center cooling system according to claim 1, further comprising: At least one processor, which is associated with the first flow controller and with a second flow controller among the plurality of flow controllers, the first flow controller being associated with a first rated flow metric of the coolant flow passing through it, and the second flow controller being associated with a second rated flow metric of the coolant flow passing through it, the at least one processor enabling an expected flow metric for the cold plate from the first flow controller or the second flow controller based in part on information associated with the first rated flow metric and the second rated flow metric.

9. The data center cooling system according to claim 8, further comprising: At least one processor, which is adapted to adjust the flow controller adapter to enable the expected flow metric based in part on a proportional metric from the first rated flow metric and the second rated flow metric.

10. The data center cooling system according to claim 1, wherein each of the plurality of flow controllers includes at least different coupling features for mating with corresponding different mating features of the server-side flow controller.

11. A processor, comprising one or more circuits and being associated with a flow controller adapter, the flow controller adapter being configured to interchangeably receive a flow controller among a plurality of flow controllers, the flow controller adapter being associated with a rack-side flow controller and with a pipe therebetween, and being configured to be movable within a cooling manifold to allow different positions for mating the flow controller with a server-side flow controller of a server tray or enclosure, the one or more circuits for determining an expected flow metric associated with the cooling requirement of a cold plate, and the processor for causing the expected flow metric through the flow controller adapter.

12. The processor according to claim 11, further comprising: An output for providing a signal to the flow controller adapter to allocate coolant for the cold plate at the expected flow metric through the flow controller adapter.

13. The processor according to claim 11, further comprising: An input for receiving sensor input from a sensor associated with the flow controller adapter, the processor for determining a change in coolant state based in part on the sensor input and for causing a stop or change in the coolant flow through the flow controller adapter.

14. The processor according to claim 13, further comprising: One or more neural networks for receiving the sensor input and inferring the change in coolant state.

15. The processor according to claim 13, further comprising: At least one logic unit for determining a change in coolant state based in part on a classification or clustering of the sensor input relative to historical sensor input and associated historical coolant states for the flow controller adapter.

16. A method for a data center cooling system, comprising: Provide a flow controller adapter that is movable within a cooling manifold and is adapted to interchangeably receive a flow controller from a plurality of flow controllers; For a server-side flow controller of a server tray or enclosure, determine the flow controller to be used with the flow controller adapter, at least in part based on a determined orifice size of the server-side flow controller and a match of the determined coupling features with the flow controller; Associate the flow controller adapter with the flow controller, the flow controller adapter being in one of a plurality of available positions for mating the flow controller with the server-side flow controller; And Enable coolant flow to enter the server tray or enclosure through the flow controller adapter, the flow controller, and the server-side flow controller.

17. The method of claim 16, further comprising: Using at least one processor to determine a cooling requirement associated with at least one computing device; And Cause coolant flow through at least the flow controller adapter, the flow controller, and the server-side flow controller for a cold plate associated with the cooling requirement.

18. The method of claim 16, further comprising: Determine the position of the flow controller adapter among the plurality of available positions within the cooling manifold; And Using a position lock associated with a provided path within the cooling manifold to enable locking the flow controller adapter in the position to align the flow controller with the server-side flow controller of the server tray or enclosure.

19. The method of claim 16, further comprising: Enable the flow controller adapter to move within the cooling manifold along at least one direction relative to a dimension of the cooling manifold in a provided path via a plurality of provided grooves.

20. The method of claim 16, further comprising: Implement the plurality of flow controllers to include at least different first orifice sizes and different first coupling features on at least a first side, and a determined second orifice size and determined second coupling features on a second side, the determined second orifice size and the determined second coupling features being for mating with the flow controller adapter.

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