Flash memory structure and manufacturing method thereof

Abstract

The present invention provides a flash memory structure and a method for manufacturing the same, comprising: forming a gate oxide layer and a floating gate polysilicon layer on a substrate, forming a sacrificial silicon nitride layer that wraps the floating gate polysilicon layer before forming an isolation structure, and removing the sacrificial silicon nitride layer after forming the isolation structure, thereby forming a gap between the floating gate polysilicon layer and the isolation structure. Subsequently, an intergate dielectric layer and a control gate polysilicon layer are sequentially formed to cover the floating gate polysilicon layer and fill the gap, so that the control gate polysilicon layer wraps the floating gate polysilicon layer, increasing the surface overlap area of ​​the control gate and the floating gate, and improving the coupling capacitance between the control gate and the floating gate, thereby improving the programming efficiency of the flash memory device. Furthermore, the sacrificial layer formed between the floating gate polysilicon layer and the isolation structure acts as a silicon nitride sidewall, preventing the floating gate from being oxidized when a linear oxide layer is formed in the STI, thereby eliminating the smiling effect of the floating gate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a flash memory structure and a manufacturing method thereof. Background Art

[0002] Flash memory devices typically have two gates stacked together: a floating gate (FG) formed of polysilicon to store charge, and a control gate (CG) to control data access. The floating gate is typically located below the control gate, with a dielectric layer between them. The floating gate is so named because it is often in a floating state and does not require connection to external circuitry, whereas the control gate does. Furthermore, source and drain regions are located on the semiconductor substrate on either side of the gate.

[0003] In the manufacturing process of stacked flash memory structures with floating gates, when forming the STI isolation structure, there will be floating gate oxidation (FGPL Oxidation) and "smiling effect" (FG smiling effect) after the linear oxide layer (Liner Oxide) process. Figure 1A and Figure 1B As shown, during the manufacturing process, the height requirement of the logic region STI on the active area needs to be taken into consideration, and the overlap capacitance between the control gate and the floating gate will be limited.

[0004] Furthermore, the semiconductor market is trending toward smaller devices with lower operating voltages, lower prices, and higher speeds. One of the key characteristics of flash memory devices is the gate coupling ratio between the floating gate and the control gate, which affects the operating voltage and device speed. The gate coupling ratio is defined as the ratio of the induced voltage on the floating gate to the applied voltage on the control gate. Generally speaking, increasing the gate coupling ratio reduces the operating voltage while increasing device speed. Increasing the gate coupling ratio involves increasing the surface overlap between the floating gate and the control gate, reducing the thickness of the dielectric layer between the floating gate and the control gate, and increasing the dielectric constant of the dielectric layer between the floating gate and the control gate.

[0005] When considering increasing the surface overlap area between the floating gate and the control gate as a method of increasing the gate coupling ratio, generally speaking, the area of ​​the floating gate surface overlapping with the control gate is limited, and the gate coupling ratio is only about 60%. Therefore, it is urgent to develop a process method that can increase the surface overlap area between the floating gate and the control gate, thereby improving the gate coupling ratio. Summary of the Invention

[0006] The object of the present invention is to provide a flash memory structure and a manufacturing method thereof, so as to increase the coupling capacitance between the control gate and the floating gate, thereby improving the programming efficiency of the flash memory device.

[0007] To achieve the above object, the present invention provides a method for manufacturing a flash memory structure, comprising:

[0008] Providing a substrate, and sequentially forming a gate oxide layer, a floating gate polysilicon layer, and a sacrificial layer on the substrate;

[0009] Etching the sacrificial layer, the floating gate polysilicon layer, and the gate oxide layer to form an opening, and forming a sacrificial layer sidewall on the sidewall of the opening;

[0010] Using the sacrificial layer as a mask, etching the substrate to form a groove, and filling the groove with isolation oxide to form an isolation structure protruding from the surface of the substrate;

[0011] removing the sacrificial layer to form an inter-gate dielectric layer, wherein the inter-gate dielectric layer covers the top of the floating gate polysilicon layer, the sidewall of the gap left after removing the sacrificial layer close to the floating gate polysilicon layer, and the bottom of the gap;

[0012] A control gate polysilicon layer is formed, where the control gate polysilicon layer covers the inter-gate dielectric layer and fills the remaining portion of the gap.

[0013] Optionally, the sacrificial layer is a silicon nitride layer.

[0014] Optionally, the process of forming a sacrificial layer sidewall on the sidewall of the opening includes:

[0015] Continuing to deposit a sacrificial layer on the substrate, the sacrificial layer at least covers the sidewalls and the bottom of the opening;

[0016] The sacrificial layer at the bottom of the opening is removed by adopting a self-aligned etching process.

[0017] Optionally, the sacrificial layer is removed by a wet etching process.

[0018] Optionally, the inter-gate dielectric layer is a stacked structure of oxide / nitride / oxide.

[0019] Optionally, the isolation structure is an STI isolation structure.

[0020] Optionally, before filling the isolation oxide in the trench, a linear oxide layer is formed on the inner wall of the trench.

[0021] Optionally, the control gate polysilicon layer at least covers the isolation structure.

[0022] Optionally, the method for manufacturing a flash memory structure further includes etching the control gate polysilicon layer, the inter-gate dielectric layer, and the floating gate polysilicon layer to form a control gate and a floating gate, and subsequently manufacturing a word line.

[0023] Accordingly, the present invention also provides a flash memory structure, comprising:

[0024] substrate;

[0025] an isolation structure protruding from a surface of the substrate;

[0026] A gate stack structure, comprising a gate oxide layer, a floating gate polysilicon layer, an intergate dielectric layer and a control gate polysilicon layer;

[0027] Wherein, the gate oxide layer and the floating gate polysilicon layer are sequentially stacked on the surface of the substrate, and a gap is formed between them and the isolation structure;

[0028] The inter-gate dielectric layer covers the top of the floating gate polysilicon layer, the sidewall of the gap close to the floating gate polysilicon layer, and the bottom of the gap;

[0029] The control gate polysilicon layer covers the inter-gate dielectric layer and fills the remaining portion of the gap.

[0030] In summary, the present invention provides a flash memory structure and a manufacturing method thereof, comprising: after forming a gate oxide layer and a floating gate polysilicon layer on a substrate, forming a silicon nitride sacrificial layer wrapping the floating gate polysilicon layer before manufacturing an isolation structure, and removing the silicon nitride sacrificial layer after manufacturing the isolation structure, forming a gap between the floating gate polysilicon layer and the isolation structure, and then subsequently forming an inter-gate dielectric layer and a control gate polysilicon layer to sequentially cover the floating gate polysilicon layer and fill the gap, so that the control gate polysilicon layer wraps the floating gate polysilicon layer, increasing the surface overlapping area of ​​the control gate and the floating gate, and improving the coupling capacitance of the control gate and the floating gate, thereby improving the programming efficiency of the flash memory device.

[0031] Furthermore, the sacrificial layer formed between the floating gate polysilicon layer and the isolation structure is equivalent to a silicon nitride sidewall, which prevents the floating gate from being oxidized when the linear oxide layer is formed in the STI, thereby eliminating the smiling effect of the floating gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1A and Figure 1B This is a partial electron microscope image of a flash memory structure;

[0033] Figure 2 A flowchart of a method for manufacturing a flash memory structure provided by one embodiment of the present invention;

[0034] Figures 3A to 3I Schematic diagram of the structure of each step corresponding to the method for manufacturing a flash memory structure in one embodiment of the present invention;

[0035] Wherein, the accompanying drawings are marked as follows:

[0036] 100 - substrate; 101 - gate oxide layer; 102 - floating gate polysilicon layer; 103 - sacrificial layer; 104 - hard mask layer; 105 - isolation oxide layer; 106 - intergate dielectric layer; 107 - control gate polysilicon layer; 110 - opening; 120 - trench; 130 - gap. DETAILED DESCRIPTION

[0037] To make the content of the present invention more clear and understandable, the content of the present invention is further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the scope of protection of the present invention.

[0038] Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for the sake of ease of explanation, the schematic diagrams are not partially enlarged according to general proportions, and this should not be regarded as a limitation of the present invention.

[0039] Figure 2 A schematic diagram of a process for manufacturing a flash memory structure provided by an embodiment of the present invention is shown in FIG. Figure 2 As shown, the method for manufacturing the flash memory structure provided in this embodiment includes the following steps:

[0040] Step S01: providing a substrate, and sequentially forming a gate oxide layer, a floating gate polysilicon layer, and a sacrificial layer on the substrate;

[0041] Step S02: etching the sacrificial layer, the floating gate polysilicon layer, and the gate oxide layer to form an opening, and forming a sacrificial layer sidewall on the sidewall of the opening;

[0042] Step S03: etching the substrate to form a trench using the sacrificial layer as a mask, and filling the trench with an isolation oxide to form an isolation structure protruding from the substrate surface;

[0043] Step S04: removing the sacrificial layer to form an inter-gate dielectric layer, wherein the inter-gate dielectric layer covers the top of the floating gate polysilicon layer, the sidewall of the gap left after removing the sacrificial layer close to the floating gate polysilicon layer, and the bottom of the gap; and

[0044] Step S05: forming a control gate polysilicon layer, wherein the control gate polysilicon layer covers the inter-gate dielectric layer and fills the remaining gap.

[0045] Figures 3A to 3I This is a structural diagram of each step corresponding to the method for manufacturing a flash memory structure in one embodiment of the present invention. Figure 2 As shown, combined with Figures 3A to 3I , describes in detail the method for manufacturing the flash memory structure provided by the present invention.

[0046] refer to Figure 3AAs shown, step S01 is performed to provide a substrate 100 , and a gate oxide layer 101 , a floating gate polysilicon layer 102 and a sacrificial layer 103 are sequentially formed on the substrate 100 .

[0047] Specifically, a substrate 100 is first provided. The substrate 100 can be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC), or silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or it can be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the substrate 100 is a silicon substrate, the gate oxide layer 101 is a silicon oxide (SiO2) layer, and the sacrificial layer 103 is a silicon nitride (SiN) layer. This is for illustrative purposes only and the present invention is not limited thereto.

[0048] refer to Figures 3A to 3D As shown, step S02 is performed to etch the sacrificial layer 103, the floating gate polysilicon layer 102 and the gate oxide layer 101 to form an opening 110, and form a sacrificial layer sidewall on the sidewall of the opening 110, so that the sacrificial layer 103 wraps the etched floating gate polysilicon layer 102 and the gate oxide layer 101.

[0049] First, a hard mask layer 104 is formed on the sacrificial layer 103, the hard mask layer 104 is patterned, and the sacrificial layer 103, the floating gate polysilicon layer 102 and the gate oxide layer 101 are sequentially etched using the patterned hard mask layer 104 as a mask to form an opening 110. Figure 3B As shown;

[0050] Next, the hard mask layer 104 is removed, and a sacrificial layer 103 is deposited on the substrate 100. The sacrificial layer 103 at least covers the sidewalls and the bottom of the opening 110. Figure 3C As shown;

[0051] Then, the sacrificial layer 103 at the bottom of the opening 110 is removed by a self-aligned etching process. The sacrificial layer 103 formed finally wraps the etched floating gate polysilicon layer 102 and the gate oxide layer 101. Figure 3D shown.

[0052] refer to Figures 3E to 3F As shown, step S03 is performed to etch the substrate 100 using the sacrificial layer 103 as a mask to form a trench 120 , and fill the trench 120 with an isolation oxide 105 to form an isolation structure protruding from the substrate surface.

[0053] In this embodiment, the isolation structure is a shallow trench isolation (STI) structure. Before the isolation oxide 105 is filled in the trench 120, a linear oxide layer (not shown in the figure) is formed on the inner wall of the trench 120. The filled isolation oxide 105 protrudes from the substrate surface and covers the surface of the sacrificial layer on both sides of the trench 120. After CMP treatment, the filled isolation oxide 105 is flush with the sacrificial layer 103. In addition, the sacrificial layer 103 formed between the floating gate polysilicon layer 102 and the isolation structure is equivalent to a silicon nitride sidewall, which prevents the floating gate from being oxidized when the linear oxide layer is formed, thereby eliminating the FG Smiling effect.

[0054] refer to Figures 3G to 3H As shown, step S04 is performed to remove the sacrificial layer 103 and form an inter-gate dielectric layer 106. The inter-gate dielectric layer 106 covers the top of the floating gate polysilicon layer 102, the sidewall of the gap 120 left after removing the sacrificial layer 103 close to the floating gate polysilicon layer, and the bottom of the gap.

[0055] In this embodiment, a wet etching process is used to remove the sacrificial layer 103, for example, a phosphoric acid etchant is used to wet etch the sacrificial layer 103. After the sacrificial layer 103 is etched away, a gap 130 is formed between the stacked structure of the floating gate polysilicon layer 102 and the gate oxide layer 101 and the isolation structure. Figure 3G As shown, then, an inter-gate dielectric layer 106 is formed, and the inter-gate dielectric layer 106 covers the top of the floating gate polysilicon layer 102, the sidewall of the gap 120 close to the floating gate polysilicon layer 102, and the bottom of the gap. Figure 3H As shown, for example, in this embodiment, the inter-gate dielectric layer 106 is a stacked structure of oxide / nitride / oxide (ONO).

[0056] It should be noted that in this embodiment, the sacrificial layer adopts a silicon nitride (SIN) layer. In some other embodiments of the present invention, the sacrificial layer can also adopt a film layer of other materials, such as silicon oxynitride (SION), to play an isolation protection role and can be easily removed in subsequent processes.

[0057] refer to Figure 3IAs shown, step S05 is performed to form a control gate polysilicon layer 107, which covers the inter-gate dielectric layer 106 and fills the remaining gap 130. Specifically, the control gate polysilicon layer 107 is deposited on the substrate, covering the inter-gate dielectric layer 106, filling the remaining gap 130, and at least covering the isolation structure. That is, the gap 130 formed after the sacrificial layer 103 is removed is filled by the control gate polysilicon layer 107, so that the control gate polysilicon layer 107 wraps around the floating gate polysilicon layer 102, increasing the surface overlap area between the control gate and the floating gate, improving the coupling capacitance between the control gate and the floating gate, and thus improving the programming efficiency of the flash memory device.

[0058] Furthermore, the method for manufacturing the flash memory structure provided in this embodiment further includes: etching the control gate polysilicon layer 107 , the inter-gate dielectric layer 106 , and the floating gate polysilicon layer 102 to form a control gate and a floating gate, and subsequently manufacturing a word line.

[0059] Accordingly, the present invention also provides a flash memory structure, such as Figure 3I Shown, including:

[0060] substrate 100;

[0061] an isolation structure protruding from a surface of the substrate;

[0062] The gate stack structure includes a gate oxide layer 101, a floating gate polysilicon layer 102, an inter-gate dielectric layer 106 and a control gate polysilicon layer 107;

[0063] The gate oxide layer 101 and the floating gate polysilicon layer 102 are sequentially stacked on the surface of the substrate 100, and a gap 130 is formed between the gate oxide layer 101 and the isolation structure.

[0064] The inter-gate dielectric layer 106 covers the top of the floating gate polysilicon layer 102, the sidewall of the gap 130 close to the floating gate polysilicon layer, and the bottom of the gap 130;

[0065] The control gate polysilicon layer 107 covers the inter-gate dielectric layer 106 and fills the remaining portion of the gap 130 .

[0066] Furthermore, the inter-gate dielectric layer 106 is a stacked structure of oxide / nitride / oxide, and the isolation structure is an STI isolation structure.

[0067] In summary, the present invention provides a flash memory structure and a method for manufacturing the same, comprising: forming a gate oxide layer and a floating gate polysilicon layer on a substrate, forming a sacrificial silicon nitride layer that wraps around the floating gate polysilicon layer before forming an isolation structure, and removing the sacrificial silicon nitride layer after forming the isolation structure, thereby forming a gap between the floating gate polysilicon layer and the isolation structure. Subsequently formed intergate dielectric layers and control gate polysilicon layers sequentially cover the floating gate polysilicon layer and fill the gap, allowing the control gate polysilicon layer to wrap around the floating gate polysilicon layer, thereby increasing the surface overlap area between the control gate and the floating gate, and improving the coupling capacitance between the control gate and the floating gate, thereby improving the programming efficiency of the flash memory device. Furthermore, the sacrificial layer formed between the floating gate polysilicon layer and the isolation structure acts as a silicon nitride sidewall, preventing the floating gate from being oxidized when the linear oxide layer is formed in the STI, thereby eliminating the smiling effect of the floating gate.

[0068] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a flash memory structure, characterized in that: include: Providing a substrate, and sequentially forming a gate oxide layer, a floating gate polysilicon layer, and a sacrificial layer on the substrate; Etching the sacrificial layer, the floating gate polysilicon layer, and the gate oxide layer to form an opening, and forming a sacrificial layer sidewall on the sidewall of the opening; Using the sacrificial layer as a mask, etching the substrate to form a groove, and filling the groove with isolation oxide to form an isolation structure protruding from the surface of the substrate; removing the sacrificial layer to form an inter-gate dielectric layer, wherein the inter-gate dielectric layer covers the top of the floating gate polysilicon layer, the sidewall of the gap left after removing the sacrificial layer close to the floating gate polysilicon layer, and the bottom of the gap; A control gate polysilicon layer is formed, where the control gate polysilicon layer covers the inter-gate dielectric layer and fills the remaining portion of the gap.

2. The method for manufacturing a flash memory structure according to claim 1, wherein: The sacrificial layer is a silicon nitride layer.

3. The method for manufacturing a flash memory structure according to claim 2, wherein: The process of forming the sacrificial layer sidewalls on the sidewalls of the opening includes: Continuing to deposit a sacrificial layer on the substrate, the sacrificial layer at least covers the sidewalls and the bottom of the opening; The sacrificial layer at the bottom of the opening is removed by adopting a self-aligned etching process.

4. The method for manufacturing a flash memory structure according to claim 3, wherein: The sacrificial layer is removed by a wet etching process.

5. The method for manufacturing a flash memory structure according to claim 1, wherein: The inter-gate dielectric layer is a stacked structure of oxide / nitride / oxide.

6. The method for manufacturing a flash memory structure according to claim 1, wherein: The isolation structure is an STI isolation structure.

7. The method for manufacturing a flash memory structure according to claim 6, wherein: Before filling the trench with isolation oxide, the method further includes forming a linear oxide layer on the inner wall of the trench.

8. The method for manufacturing a flash memory structure according to claim 7, wherein: The control gate polysilicon layer at least covers the isolation structure.

9. The method for manufacturing a flash memory structure according to claim 1, wherein: The method also includes etching the control gate polysilicon layer, the inter-gate dielectric layer and the floating gate polysilicon layer to form a control gate and a floating gate, and subsequently manufacturing a word line.

10. A flash memory structure, characterized in that: include: substrate; an isolation structure protruding from a surface of the substrate; A gate stack structure, comprising a gate oxide layer, a floating gate polysilicon layer, an intergate dielectric layer and a control gate polysilicon layer; Wherein, the gate oxide layer and the floating gate polysilicon layer are sequentially stacked on the surface of the substrate, and a gap is formed between them and the isolation structure; The inter-gate dielectric layer covers the top of the floating gate polysilicon layer, the sidewall of the gap close to the floating gate polysilicon layer, and the bottom of the gap; The control gate polysilicon layer covers the inter-gate dielectric layer and fills the remaining portion of the gap.

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