Manufacturing method of NORD flash memory

Abstract

The present invention provides a method for manufacturing a NORD flash memory, comprising: providing a substrate; forming a sidewall structure on the sidewall of a first opening, and etching a control gate material layer, an inter-gate dielectric layer, and a floating gate material layer using the sidewall structure and a patterned mask layer to form a second opening; using the second opening, removing at least half of the thickness of a floating gate oxide layer by dry etching; removing the remaining floating gate oxide layer by wet etching to form an exposed substrate; forming a tunneling oxide layer and a word line in the second opening in sequence; and forming a storage unit on the substrate. In the present invention, at least half of the thickness of the floating gate oxide layer is removed by dry etching to uniformly etch the floating gate oxide layer at the bottom of the second opening, and then a relatively short time of wet etching is used to remove the remaining floating gate oxide layer to reduce the impact on the substrate, and the second opening is cleaned, so as to form a tunneling oxide layer and a word line with a better morphology in the second opening, and prevent the active area in the substrate from being short-circuited with the word line.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a NORD flash memory. Background Art

[0002] In the current semiconductor industry, memory accounts for a considerable proportion of integrated circuit products, and the development of flash memory in memory is particularly rapid. Its main feature is that it can retain stored information for a long time without power supply, and has many advantages such as high integration, fast access speed and easy erasure. Therefore, it has been widely used in many fields such as microcomputers and automatic control.

[0003] Compared with NAND flash memory, the storage cells of NORD flash memory can operate independently, and can more flexibly control the number of electrons entering the floating gate, and it also has many applications in some fields.

[0004] However, during the manufacturing process of NORD flash memory, short circuit problems between word lines and active areas often occur, resulting in low yield and seriously affecting manufacturing costs. Summary of the invention

[0005] The object of the present invention is to provide a method for manufacturing a NORD flash memory to solve the short circuit problem between a word line and an active area in the manufacturing process of the NORD flash memory.

[0006] In order to solve the above technical problems, the present invention provides a method for manufacturing a NORD flash memory, comprising:

[0007] Providing a substrate, on which a floating gate oxide layer, a floating gate material layer, an inter-gate dielectric layer, a control gate material layer and a patterned mask layer are sequentially formed, wherein the patterned mask layer has a plurality of first openings;

[0008] forming a sidewall structure on the sidewall of the first opening, and etching the control gate material layer, the inter-gate dielectric layer, and the floating gate material layer using the sidewall structure and the patterned mask layer to form a second opening;

[0009] Using the second opening, dry etching is used to remove at least half of the thickness of the floating gate oxide layer;

[0010] Using wet etching to remove the remaining floating gate oxide layer to expose the substrate, and sequentially forming a tunnel oxide layer and a word line in the second opening;

[0011] Memory cells are formed on the substrate, each of which includes a control gate structure, a floating gate structure and a word line.

[0012] Optionally, an active area and an isolation structure are also formed in the substrate, and the first opening is located above the active area and the isolation structure.

[0013] Optionally, the step of forming the sidewall structure includes:

[0014] Forming a sidewall material layer to cover the patterned mask layer and the inner wall of the first opening, wherein the sidewall material layer in the first opening has a recess, and the recess is used to define the second opening;

[0015] The sidewall material layer is etched by an anisotropic etching process to remove a portion of the sidewall material layer along the recess to expose the surface of the control gate material layer, and the remaining sidewall material layer covering the sidewall of the first opening is used as the sidewall structure.

[0016] Optionally, the sidewall structure and the patterned mask layer are used to etch the control gate material layer, the inter-gate dielectric layer, and the floating gate material layer using an anisotropic etching process to form the second opening, wherein the second opening exposes the floating gate oxide layer, and both sides of the bottom of the second opening are located above the isolation structure.

[0017] Optionally, when performing the dry etching, an etching selection ratio of the floating gate oxide layer to the floating gate material layer and the control gate material layer is greater than 10:1.

[0018] Optionally, anisotropic dry etching is used to remove the floating gate oxide layer.

[0019] Optionally, the material of the floating gate oxide layer includes silicon oxide, the materials of the floating gate material layer and the control gate material layer both include polysilicon, the etching gas for dry etching the floating gate oxide layer includes carbon fluoride gas, argon gas and oxygen, and the etching solution for wet etching includes diluted hydrofluoric acid.

[0020] Optionally, the material of the patterned mask layer includes silicon nitride or silicon carbonitride.

[0021] Optionally, the step of forming the tunnel oxide layer and the word line includes:

[0022] forming the tunneling oxide layer to cover the surface of the patterned mask layer and the inner wall of the second opening;

[0023] Forming a conductive material to fill the second opening to above the patterned mask layer;

[0024] A grinding process is performed using the surface of the patterned mask layer as a grinding stop layer, and the conductive material in the second opening is used as the word line.

[0025] Optionally, the step of forming the storage unit on the substrate includes:

[0026] removing the tunneling oxide layer on the patterned mask layer;

[0027] performing an oxidation process to form a cap layer on top of the word line and removing the patterned mask layer;

[0028] Using the sidewall structure and the cap layer as masks, the control gate material layer, the inter-gate dielectric layer, the floating gate material layer and the floating gate oxide layer are etched in sequence to expose the surface of the substrate, so that the control gate structure is formed by the control gate material layer and the inter-gate dielectric layer surrounding the word line, and the floating gate structure is formed by the floating gate material layer and the floating gate oxide layer surrounding the word line.

[0029] In summary, after forming the second opening by using the sidewall structure and the patterned mask layer, the present invention first uses dry etching to remove at least half the thickness of the floating gate oxide layer, and then uses ion bombardment to etch the floating gate oxide layer to quickly discharge the formed gaseous products to prevent the etchant from remaining in the second opening, thereby achieving a more uniform etching effect on the floating gate oxide layer at the bottom of the second opening, and a small amount of floating gate oxide layer remains, and the remaining floating gate oxide layer is removed by wet etching for a shorter time to reduce the impact on the substrate under the floating gate oxide layer, and the cleaning effect of the second opening can also be achieved, thereby forming a second opening with a relatively flat bottom to expose the substrate surface, thereby forming a tunneling oxide layer and word line with better morphology in the second opening, and preventing the active area in the substrate from short-circuiting with the word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0031] Figure 1 is a flow chart of a method for manufacturing a NORD flash memory provided in an embodiment of the present application;

[0032] Figure 2a to Figure 2k A schematic structural diagram corresponding to the corresponding steps of the method for manufacturing the NORD flash memory provided in an embodiment of the present application.

[0033] In the attached figure:

[0034] 10-substrate; 11-active area; 21-floating gate oxide layer; 22-floating gate material layer; 23-intergate dielectric layer; 24-control gate material layer; 31-patterned mask layer; 32-first opening; 33-sidewall material layer; 34-recess; 35-sidewall structure; 36-second opening; 37-tunneling oxide layer; 38-word line; 41-cap layer; 42-control gate structure; 43-floating gate structure; D1-first direction; D2-second direction. DETAILED DESCRIPTION

[0035] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0036] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0037] Figure 1 It is a flow chart of a method for manufacturing a NORD flash memory provided in an embodiment of the present application.

[0038] like Figure 1 As shown, the manufacturing method of the NORD flash memory provided in this embodiment includes:

[0039] S01: providing a substrate, on which a floating gate oxide layer, a floating gate material layer, an inter-gate dielectric layer, a control gate material layer and a patterned mask layer are sequentially formed, wherein the patterned mask layer has a plurality of first openings;

[0040] S02: forming a sidewall structure on the sidewall of the first opening, and etching the control gate material layer, the inter-gate dielectric layer, and the floating gate material layer using the sidewall structure and the patterned mask layer to form a second opening;

[0041] S03: using the second opening to remove at least half of the thickness of the floating gate oxide layer by dry etching;

[0042] S04: removing the remaining floating gate oxide layer by wet etching to expose the substrate, and sequentially forming a tunnel oxide layer and a word line in the second opening;

[0043] S05: forming memory cells on the substrate, each of the memory cells comprising a control gate structure, a floating gate structure and a word line.

[0044] Figure 2a to Figure 2k The structural diagram corresponding to the corresponding steps of the manufacturing method of the NORD flash memory provided in the embodiment of the present application is shown below in combination with Figure 2a to Figure 2k The manufacturing method of the NORD flash memory provided in this embodiment is described in detail.

[0045] First, please refer to Figure 2a and Figure 2b , perform step S01, provide a substrate 10, on which a floating gate oxide layer 21, a floating gate material layer 22, an inter-gate dielectric layer 23, a control gate material layer 24 and a patterned mask layer 31 are sequentially formed, and the patterned mask layer 31 has a plurality of first openings 32.

[0046] The substrate 10 may include any suitable substrate known to those skilled in the art, for example, at least one of the following materials: silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). In this embodiment, the material of the substrate 10 is described by taking silicon (silicon substrate) as an example.

[0047] Several active regions 11 are also formed in the substrate 10, and isolation structures are provided between adjacent active regions 11 for isolation. The active regions 11 may be formed by a doping process, and the shape of the active regions 11 may be, for example, strip-shaped and extend along the second direction D2. The isolation structure may be a shallow trench isolation structure, and the isolation material filled in the trench may include, for example, silicon oxide.

[0048] The film layers formed on the substrate 10 include, from bottom to top, a floating gate silicon oxide, a floating gate material layer 22, an inter-gate dielectric layer 23, a control gate material layer 24, and a mask material layer. The floating gate oxide layer 21 may be made of silicon oxide; the floating gate material layer 22 is used to form a floating gate, and its material may be undoped polysilicon, doped polysilicon, or other suitable conductive materials; the inter-gate dielectric layer 23 may be made of silicon oxide; the control gate material layer 24 is used to form a control gate, and its material may be undoped polysilicon, doped polysilicon, or other suitable conductive materials; the mask material layer may be made of any suitable hard material, such as silicon nitride or silicon carbonitride.

[0049] Next, please continue to refer to Figure 2a and Figure 2b , Figure 2a A top view diagram is shown. Figure 2b for Figure 2a , and then the mask material layer is patterned to form a patterned mask layer 31. The patterned mask layer 31 has a plurality of first openings 32 exposing the control gate material layer 24, and the first openings 32 are used to define a storage unit. The first openings 32 may be rectangular and the aspect ratio of the first openings 32 is less than or equal to 3:1 (e.g., 2:1). It should be noted that the flash memory formed in this embodiment is a NOR type memory, and each storage unit can not only operate independently but also flexibly control the number of electrons entering the floating gate, that is, each first opening 32 corresponds only to an active area 11 in the substrate 10 and each first opening 32 only corresponds to a floating gate structure, a control gate structure and a word line in the subsequent process. Therefore, it is not difficult to see that in this type of flash memory, a plurality of first openings 32 are arranged in an array on the substrate 10 along the first direction D1 and the second direction D2, and each storage unit corresponds to a first opening 32, that is, the number of first openings 32 provided on the substrate 10 is much greater than that of other types of memories (more dense) and the size of the first openings 32 is smaller. The other types of memories mentioned here may be, for example, a NOR flash memory having a floating gate structure, a control gate structure, and a word line structure, or any one of several of the floating gate structure, a control gate structure, and a word line structure used in conjunction with surrounding storage cells, or a NAND flash memory.

[0050] Next, step S02 is performed to form a spacer structure 35 on the sidewall of the first opening 32 , and to etch the control gate material layer 24 , the inter-gate dielectric layer 23 , and the floating gate material layer 22 using the spacer structure 35 and the patterned mask layer 31 to form a second opening 36 .

[0051] The specific steps of forming the second opening 36 include: Figure 2c, forming a sidewall material layer 33 to cover the patterned mask layer 31 and the inner wall of the first opening 32, and the sidewall material layer 33 in the first opening 32 has a recess 34, and the recess 34 is used to define the second opening 36. The material of the sidewall material layer 33 can be a hard material, such as one or more of silicon oxide, silicon nitride and silicon carbonitride, and a suitable deposition process (such as LPCVD process) is used to make it have better step coverage. It should be noted that the sidewall material layer 33 does not completely fill the first opening 32, but covers along the inner wall of the first opening 32 to form a recess 34.

[0052] Please refer to Figure 2d , an anisotropic etching process is used to etch away part of the spacer material layer 33 along the recess 34, exposing the surface of the control gate material layer 24, and the remaining spacer material layer 33 covering the sidewall of the first opening 32 is used as the spacer structure 35. The anisotropic etching can be a dry etching with strong physical etching (i.e., mainly sputtering etching), which removes the spacer material layer 33 on the patterned mask layer 31 and part of the spacer material layer 33 in the first opening 32. When etching part of the spacer material layer 33 in the first opening 32, the anisotropic etching will widen and deepen the recess 34 along the outer wall of the recess 34 until the surface of the control gate material layer 24 is exposed, and the bottom width of the widened first opening 32 is close to the bottom width of the word line 38 to be formed later. In a specific example, the bottom width of the widened first opening 32 can be greater than or equal to the width of the active area 11 under the first opening 32.

[0053] Please refer to Figure 2e , using the sidewall structure 35 and the patterned mask layer 31, an anisotropic etching process is used to etch the control gate material layer 24, the inter-gate dielectric layer 23, and the floating gate material layer 22 to form a second opening 36, the second opening 36 exposes the floating gate oxide layer 21, and the bottom of the second opening 36 is directly above the active area 11 and the isolation structure on both sides of the active area 11. The anisotropic etching used can be a dry etching method including an etchant matching the corresponding film layer, wherein when etching the floating gate material layer 22, an etchant with better etching selectivity relative to the floating gate oxide layer 21 (such as chlorine gas or an etchant including chloride ions) can be used to reduce the impact on the floating gate oxide layer 21, so that the formed second opening 36 has a relatively flat bottom wall (that is, the surface of the exposed floating gate oxide layer 21 has a relatively flat surface).

[0054] Next, please refer to Figure 2f , executing step S03, using the second opening 36 to remove at least half the thickness of the floating gate oxide layer 21 by dry etching.

[0055] When the floating gate oxide layer 21 is dry-etched, the floating gate oxide layer 21 has a large etching selectivity (e.g., an etching selectivity greater than 10:1) relative to the floating gate material layer 22 and the control gate material layer 24, so as to minimize the impact of the dry etching on the floating gate material layer 22 and the control gate material layer 24. In this embodiment, the floating gate oxide layer 21 is made of silicon oxide, the floating gate material layer 22 and the control gate material layer 24 are made of polysilicon, and the etchant used for the dry etching includes carbon fluoride gas, argon gas and oxygen. In addition, the use of dry etching with better etching selectivity to silicon can also prevent the floating gate oxide layer 21 in a partial area from being completely removed by etching, which will have a significant impact on the exposed active area 11.

[0056] It is understandable that, during the dry etching of the floating gate oxide layer 21, the generated plasma bombards and etches the floating gate oxide layer 21 and forms gaseous products that are quickly discharged, thereby forming a relatively uniform etching effect on the floating gate oxide layer 21 at the bottom of the second opening 36, preventing the bottom morphology of the second opening 36 from being abnormal (for example, forming a downward sharp corner at the bottom corner of the second opening 36). In comparison, the second opening formed by the sidewall structure in the first opening has a larger depth-to-width ratio than the first opening (for example, greater than 5:1). If wet etching is directly used to etch the floating gate oxide layer 21, during the etching process, since the number of second openings 36 on the substrate 10 is large and relatively small and deep, the etching liquid is very likely to remain at the corner of the bottom of some second openings 36, thereby forming a downward sharp corner at the bottom corner of the second opening 36, and the sharp corner may even extend to the isolation structure in the substrate 10.

[0057] In a preferred example, the above-mentioned dry etching method can be used to remove 1 / 2 to 3 / 4 of the thickness of the floating gate oxide layer 21, so as to facilitate control by etching time.

[0058] Next, step S04 is performed to remove the remaining floating gate oxide layer 21 by wet etching to form an exposed substrate 10 , and to sequentially form a tunnel oxide layer 37 and a word line 38 in the second opening 36 .

[0059] For details, please refer to Figure 2g, wet etching is used to remove the remaining floating gate oxide layer 21 to form an exposed substrate 10. Taking the floating gate oxide layer 21 as an example, since only a small amount of floating gate oxide layer 21 is left, diluted hydrofluoric acid can be used as an etching solution to quickly (in a short time, such as 5 seconds to 60 seconds) remove the remaining small amount of floating gate oxide layer 21 to expose the active area 11 and the isolation structure, and at the same time achieve the purpose of cleaning the second opening 36. It should be understood that since most of the floating gate oxide layer 21 in the second opening 36 is removed by dry etching in the aforementioned steps, when wet etching is used to remove the remaining floating gate oxide layer 21, the etching time can be reduced to prevent or inhibit the corrosion of the isolation structure by wet etching in the second opening 36, and make the second opening 36 have a better bottom morphology, thereby preventing the active area 11 from short-circuiting with the subsequently formed word line 38.

[0060] Please refer to Figure 2h , a tunnel oxide layer 37 and a word line 38 are sequentially formed in the second opening 36. The specific steps include: forming a tunnel oxide layer 37 to cover the surface of the patterned mask layer 31 and the inner wall of the second opening 36, the material of the tunnel oxide layer 37 may include silicon oxide, and may be formed by an LPCVD process; then forming a conductive material to fill the second opening 36 to the top of the patterned mask layer 31; performing a grinding process with the surface of the patterned mask layer 31 as a grinding stop layer, and using the remaining conductive material in the second opening 36 as the word line 38.

[0061] Therefore, the method in this embodiment can form a second opening with better bottom morphology, and thereby form a tunneling oxide layer and word line with better morphology in the second opening, ensuring sufficient electrical isolation between the word line and the active area in the substrate, thereby reducing the risk of short circuit between the word line and the active area.

[0062] Next, step S05 is performed to form memory cells on the substrate 10 . Each memory cell includes a control gate structure 42 , a floating gate structure 43 and a word line 38 .

[0063] For details, please refer to Figure 2i , remove the tunneling oxide layer 37 on the patterned mask layer 31 to expose the surface of the patterned mask layer 31, and then perform an oxidation process to form a cap layer 41 on the top surface of the word line 38, and use the cap layer 41 and the sidewall structure 35 to protect the word line 38, and then remove the patterned mask layer 31 to expose the surface of the control gate material layer 24.

[0064] Please refer to Figure 2j and Figure 2k , Figure 2j A top view diagram is shown. Figure 2k for Figure 2i, using the sidewall structure 35 and the cap layer 41 as masks, the control gate material layer 24, the inter-gate dielectric layer 23, the floating gate material layer 22 and the floating gate oxide layer 21 are etched in sequence to expose the surface of the substrate, and the control gate material layer 24 and the inter-gate dielectric layer 23 surrounding the word line 38 form a control gate structure 42, and the floating gate material layer 22 and the floating gate oxide layer 21 surrounding the word line 38 form a floating gate structure 43. Each memory cell formed in this way includes an independent floating gate structure 43, a control gate structure 42 and a word line 38, so that each memory cell can not only operate independently but also flexibly control the number of electrons entering the floating gate.

[0065] In summary, after forming the second opening by using the sidewall structure and the patterned mask layer, the present invention first uses dry etching to remove at least half the thickness of the floating gate oxide layer, and then uses ion bombardment to etch the floating gate oxide layer to quickly discharge the formed gaseous products to prevent the etchant from remaining in the second opening, thereby achieving a more uniform etching effect on the floating gate oxide layer at the bottom of the second opening, and a small amount of floating gate oxide layer remains, and the remaining floating gate oxide layer is removed by wet etching for a shorter time to reduce the impact on the substrate under the floating gate oxide layer, and the cleaning effect of the second opening can also be achieved, thereby forming a second opening with a relatively flat bottom to expose the substrate surface, thereby forming a tunneling oxide layer and word line with better morphology in the second opening, and preventing the active area in the substrate from short-circuiting with the word line.

[0066] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a NORD flash memory, characterized in that: include: Providing a substrate, on which a floating gate oxide layer, a floating gate material layer, an inter-gate dielectric layer, a control gate material layer and a patterned mask layer are sequentially formed, wherein the patterned mask layer has a plurality of first openings; forming a sidewall structure on the sidewall of the first opening, and etching the control gate material layer, the inter-gate dielectric layer, and the floating gate material layer using the sidewall structure and the patterned mask layer to form a second opening; Using the second opening, dry etching is used to remove at least half of the thickness of the floating gate oxide layer; Using wet etching to remove the remaining floating gate oxide layer to expose the substrate, and sequentially forming a tunnel oxide layer and a word line in the second opening; Memory cells are formed on the substrate, each of which includes a control gate structure, a floating gate structure and a word line.

2. The method for manufacturing a NORD flash memory according to claim 1, characterized in that: An active area and an isolation structure are also formed in the substrate, and the first opening is located above the active area and the isolation structure.

3. The method for manufacturing a NORD flash memory according to claim 1, characterized in that: The steps of forming the sidewall structure include: Forming a sidewall material layer to cover the patterned mask layer and the inner wall of the first opening, wherein the sidewall material layer in the first opening has a recess, and the recess is used to define the second opening; The sidewall material layer is etched by an anisotropic etching process to remove a portion of the sidewall material layer along the recess to expose the surface of the control gate material layer, and the remaining sidewall material layer covering the sidewall of the first opening is used as the sidewall structure.

4. The method for manufacturing a NORD flash memory according to claim 2, characterized in that: The control gate material layer, the inter-gate dielectric layer, and the floating gate material layer are etched by an anisotropic etching process using the sidewall structure and the patterned mask layer to form the second opening, wherein the second opening exposes the floating gate oxide layer, and the bottom sides of the second opening are located above the isolation structure.

5. The method for manufacturing a NORD flash memory according to claim 1, characterized in that: When performing the dry etching, the etching selection ratio of the floating gate oxide layer to the floating gate material layer and the control gate material layer is greater than 10:

1.

6. The method for manufacturing a NORD flash memory according to claim 1 or 5, characterized in that: The floating gate oxide layer is removed by anisotropic dry etching.

7. The method for manufacturing a NORD flash memory according to claim 6, characterized in that: The floating gate oxide layer is made of silicon oxide, the floating gate material layer and the control gate material layer are made of polysilicon, the etching gas for dry etching the floating gate oxide layer includes carbon fluoride gas, argon gas and oxygen, and the etching solution for wet etching includes diluted hydrofluoric acid.

8. The method for manufacturing a NORD flash memory according to claim 1, characterized in that: The material of the patterned mask layer includes silicon nitride or silicon carbonitride.

9. The method for manufacturing a NORD flash memory according to claim 1, characterized in that: The steps of forming the tunnel oxide layer and the word line include: forming the tunneling oxide layer to cover the surface of the patterned mask layer and the inner wall of the second opening; Forming a conductive material to fill the second opening to above the patterned mask layer; A grinding process is performed using the surface of the patterned mask layer as a grinding stop layer, and the conductive material in the second opening is used as the word line.

10. The method for manufacturing a NORD flash memory according to claim 1, characterized in that: The step of forming the memory cell on the substrate comprises: removing the tunneling oxide layer on the patterned mask layer; performing an oxidation process to form a cap layer on top of the word line and removing the patterned mask layer; Using the sidewall structure and the cap layer as masks, the control gate material layer, the inter-gate dielectric layer, the floating gate material layer and the floating gate oxide layer are etched in sequence to expose the surface of the substrate, so that the control gate structure is formed by the control gate material layer and the inter-gate dielectric layer surrounding the word line, and the floating gate structure is formed by the floating gate material layer and the floating gate oxide layer surrounding the word line.

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