Pixel circuit, driving method thereof and display device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2021-09-24
- Publication Date
- 2026-06-05
Smart Images
Figure CN116235238B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display technology, and in particular to a pixel circuit and its driving method, and a display device. Background Technology
[0002] With the development of display technology, people have increasingly higher requirements for the display effect of display devices. At present, the brightness adjustment method of active display devices usually uses direct current (DC) dimming. However, when achieving low grayscale brightness, DC dimming has the problem of flickering that can damage the eyes. Summary of the Invention
[0003] This application provides a pixel circuit and its driving method, as well as a display device.
[0004] In a first aspect, embodiments of this application provide a pixel circuit, including: a current control circuit, a duration control circuit, and a light-emitting element, wherein:
[0005] The current control circuit is used to receive a data signal and a first scan signal, and control the amplitude of the generated drive current according to the data signal and the first scan signal.
[0006] The duration control circuit is used to receive a mode control signal, a pulse control signal, a light emission control signal, and the drive current of the current control circuit. The duration control circuit is configured to control the duration for which the drive current is provided to the light emission element according to the amplitude of the mode control signal.
[0007] In some exemplary embodiments, the duration control circuit includes: a duration selection sub-circuit, a first duration control sub-circuit, a second duration control sub-circuit, and a light emission control circuit, wherein,
[0008] The duration selection sub-circuit is connected to the first voltage terminal, the mode control signal terminal, the second scan signal terminal, the third scan signal terminal, the first node, and the second node, respectively, and is used to write the mode control signal to the first node and the second node under the control of the mode control signal, the second scan signal output from the second scan signal terminal, and the third scan signal output from the third scan signal terminal;
[0009] The first duration control sub-circuit is connected to the first node, the third node and the pulse control signal terminal respectively. Under the control of the signal of the first node, the pulse control signal of the pulse control signal terminal is written to the third node.
[0010] The second duration control sub-circuit is connected to the second node, the third node and the light emission control signal terminal respectively, and is used to write the light emission control signal of the light emission control signal terminal to the third node under the control of the signal of the second node when the mode control signal is the second mode;
[0011] The light-emitting control circuit is connected to the third node, the first voltage terminal, the light-emitting control signal terminal, the first scan signal terminal, and the current control circuit, respectively. It is used to receive the driving current and, under the control of the signal from the third node, the light-emitting control signal output from the light-emitting control signal terminal, and the first scan signal output from the first scan signal terminal, control the duration for which the driving current flows through the light-emitting element.
[0012] In some exemplary embodiments, the duration selection sub-circuit includes a first duration selection sub-circuit and a second duration selection sub-circuit, wherein,
[0013] The first duration selection sub-circuit is connected to the first voltage terminal, the mode control signal terminal, the second scan signal terminal and the first node respectively, and is used to write the mode control signal to the first node under the control of the mode control signal and the second scan signal;
[0014] The second duration selection sub-circuit is connected to the first voltage terminal, the mode control signal terminal, the third scan signal terminal, and the second node, respectively, and is used to write the mode control signal to the second node under the control of the mode control signal and the third scan signal.
[0015] In some exemplary embodiments, the light-emitting control circuit is connected to the current control circuit, the third node, and the first voltage terminal, respectively, for receiving the driving current and controlling the duration for which the driving current flows through the light-emitting element under the control of the signal from the third node.
[0016] In some exemplary embodiments, the first duration control subcircuit includes a first transistor, wherein:
[0017] The control electrode of the first transistor is connected to the first node, the first electrode of the first transistor is connected to the pulse control signal terminal, and the second electrode of the first transistor is connected to the third node.
[0018] In some exemplary embodiments, the second duration control subcircuit includes a second transistor, wherein:
[0019] The control electrode of the second transistor is connected to the second node, the first electrode of the second transistor is connected to the light emission control signal terminal, and the second electrode of the second transistor is connected to the third node.
[0020] In some exemplary embodiments, the first duration selection sub-circuit includes a first capacitor and a third transistor, wherein:
[0021] The control electrode of the third transistor is connected to the second scan signal terminal, the first electrode of the third transistor is connected to the mode control signal terminal, and the second electrode of the third transistor is connected to the first node; the first terminal of the first capacitor is connected to the first voltage terminal, and the second terminal of the first capacitor is connected to the first node.
[0022] In some exemplary embodiments, the second duration selection sub-circuit includes a second capacitor and a fourth transistor, wherein:
[0023] The control electrode of the fourth transistor is connected to the third scan signal terminal, the first electrode of the fourth transistor is connected to the mode control signal terminal, and the second electrode of the fourth transistor is connected to the second node; the first terminal of the second capacitor is connected to the first voltage terminal, and the second terminal of the second capacitor is connected to the second node.
[0024] In some exemplary embodiments, the light-emitting control circuit includes a fifth transistor, wherein:
[0025] The control electrode of the fifth transistor is connected to the third node, the first electrode of the fifth transistor is connected to the current control circuit, and the second electrode of the fifth transistor is connected to the first voltage terminal.
[0026] In some exemplary embodiments, the current control circuit includes: a data writing circuit, a storage circuit, and a driving circuit;
[0027] The data writing circuit is used to write the data signal output from the data signal terminal to the fourth node under the control of the first scan signal.
[0028] The storage circuit is used to store the electrical energy at the fourth node;
[0029] The driving circuit is used to generate a driving current under the control of the signal from the fourth node.
[0030] In some exemplary embodiments, the data writing circuit includes an eighth transistor, the storage circuit includes a third capacitor, and the driving circuit includes a driving transistor, wherein:
[0031] The control electrode of the eighth transistor is connected to the first scan signal terminal, the first electrode of the eighth transistor is connected to the display data signal terminal, and the second electrode of the eighth transistor is connected to the fourth node;
[0032] The first end of the third capacitor is connected to the fourth node, and the second end of the third capacitor is connected to the fifth node;
[0033] The control electrode of the driving transistor is connected to the fourth node, the first electrode of the driving transistor is connected to the light-emitting element, and the second electrode of the driving transistor is connected to the fifth node.
[0034] In some exemplary embodiments, the pixel circuit further includes an external compensation circuit for compensating the threshold voltage.
[0035] In some exemplary embodiments, the external compensation circuit includes a sixth transistor, a seventh transistor, and a ninth transistor. The control electrode of the sixth transistor is connected to the light-emitting control signal terminal, the first electrode of the sixth transistor is connected to the current control circuit, and the second electrode of the sixth transistor is connected to the first electrode of the seventh transistor. The control electrode of the seventh transistor is connected to the first scan signal terminal, and the second electrode of the seventh transistor is connected to the first voltage terminal. The control electrode of the ninth transistor is connected to the fourth scan signal terminal, the first electrode of the ninth transistor is connected to the fifth node, and the second electrode of the ninth transistor is connected to the voltage output terminal.
[0036] Secondly, embodiments of this application also provide a display device, including: a pixel circuit as described in any of the preceding claims.
[0037] Thirdly, embodiments of this application also provide a driving method for a pixel circuit, used to drive the pixel circuit as described in any one of the first aspects above, wherein the pixel circuit has multiple scan cycles, and within one scan cycle, the driving method includes:
[0038] Receive a data signal and a first scan signal, and control the amplitude of the generated drive current according to the data signal and the first scan signal;
[0039] The duration control circuit receives the mode control signal, pulse control signal, light emission control signal, and drive current from the current control circuit, and controls the duration for which the drive current is provided to the light emission element according to the amplitude of the mode control signal.
[0040] Beneficial effects:
[0041] The pixel circuit, driving method, and display device provided in this application embodiment enable the light-emitting element to operate in a current path with a larger amplitude by setting the amplitude of the data signal provided by the data signal terminal. This ensures high uniformity of light emission brightness, high luminous efficiency, and stable color coordinates of the light-emitting element. When high grayscale brightness is achieved, the duration of providing driving current to the light-emitting element is the second duration; while when low grayscale brightness is achieved, the duration of providing driving current to the light-emitting element is the first duration. In this way, a high amplitude driving current combined with a short light emission time can achieve low grayscale brightness display, thereby improving the display effect of the display device at low grayscale. Attached Figure Description
[0042] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.
[0043] Figure 1 This is a schematic diagram of the pixel circuit structure in the related technology provided in the embodiments of this application;
[0044] Figure 2 Timing diagrams of pixel circuits in related technologies provided for embodiments of this application;
[0045] Figure 3 This is one of the schematic diagrams of the pixel circuit provided in the embodiments of this application;
[0046] Figure 4 This is a second schematic diagram of the pixel circuit provided in the embodiments of this application;
[0047] Figure 5 This is the third schematic diagram of the pixel circuit provided in the embodiments of this application;
[0048] Figure 6 This is a schematic diagram of the data writing circuit provided in an embodiment of this application;
[0049] Figure 7 This is the fifth schematic diagram of the pixel circuit provided in the embodiments of this application;
[0050] Figure 8a One of the equivalent circuit diagrams of the pixel circuit provided in the embodiments of this application;
[0051] Figure 8b A second equivalent circuit diagram of the pixel circuit provided in the embodiments of this application;
[0052] Figure 9 A schematic diagram of the pixel circuit provided in an embodiment of this application;
[0053] Figure 10A timing diagram of the pixel circuit provided in an embodiment of this application;
[0054] Figure 11 This is a schematic diagram of the pixel circuit operation in the T1 stage provided in an embodiment of this application;
[0055] Figure 12 This is a schematic diagram of the pixel circuit operation in the T2 stage provided in an embodiment of this application;
[0056] Figure 13 One of the schematic diagrams of pixel circuit operation in the T3 stage provided in the embodiments of this application;
[0057] Figure 14 This is the second schematic diagram of the pixel circuit operation in the T3 stage provided in the embodiments of this application;
[0058] Figure 15 This is a schematic diagram of the pixel circuit operation during the compensation stage provided in an embodiment of this application;
[0059] Figure 16 A pixel circuit timing diagram for the compensation stage provided in an embodiment of this application;
[0060] Figure 17 This is a schematic flowchart of a pixel circuit driving method provided in an embodiment of this application. Detailed Implementation
[0061] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.
[0062] Unless otherwise defined, the technical or scientific terms used in the embodiments of this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" indicate that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.
[0063] Those skilled in the art will understand that the transistors used in all embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Preferably, the thin-film transistors used in the embodiments of this application can be oxide semiconductor transistors. Since the source and drain of the transistors used here are symmetrical, their source and drain can be interchanged. In the embodiments of this application, to distinguish the two electrodes of the transistor other than the gate, one electrode is called the first electrode and the other electrode is called the second electrode. The first electrode can be the source, and the second electrode can be the drain.
[0064] like Figure 1 The diagram shows a schematic of a pixel circuit used to provide signals to a light-emitting diode in related technologies. Figure 2 The timing diagram shows the pixel circuit, which includes four transistors M5, M8, M9, and Md, and a capacitor C3. The circuit structure mainly relies on the voltage difference between the gate and source of transistor Md to provide current signals of different amplitudes to the light-emitting diode. Under the control of different amplitude current signals, the light-emitting diode can exhibit different brightness. However, due to the photoelectric characteristics of the light-emitting diode itself, such as the micro inorganic light-emitting diode, problems such as color coordinate drift, poor brightness uniformity, and decreased luminous efficiency will occur under smaller amplitude current signals. As a result, the micro inorganic light-emitting diode cannot accurately or stably present low grayscale brightness.
[0065] The pixel circuit, driving method, and display device provided in this application can at least enable light-emitting diodes to accurately represent low grayscale brightness. The pixel circuit, driving method, and display device provided in the embodiments of this application will be described in detail below.
[0066] like Figure 3 The diagram shown is a schematic representation of a pixel circuit according to an embodiment of this application. Figure 3 In this application embodiment, the pixel circuit includes: a current control circuit 301, a duration control circuit 302, and a light-emitting element 303.
[0067] The current control circuit 301 is connected to the data signal terminal DI and the first scan signal terminal GataA respectively, and is used to receive the data signal DI and the first scan signal GataA. Under the action of the first scan signal GataA, the amplitude of the drive current is controlled according to the amplitude of the data signal DI.
[0068] The duration control circuit 302 is connected to the mode control signal terminal DT, the pulse control signal terminal Hf, and the light emission control signal terminal EM_B, respectively. It is used to receive the mode control signal DT, the pulse control signal Hf, the light emission control signal EM_B, and the drive current of the current control circuit. Based on the amplitude of the mode control signal DT, it controls the duration for which the drive current is provided to the light emission element 303.
[0069] The pixel circuit provided in this application embodiment can control the duration of driving current supplied to the light-emitting element within each scan cycle. For example, the pulse control signal hf provided by the pulse control signal terminal Hf includes multiple effective time periods during the light-emitting phase. Each effective time period refers to the time period during which the light-emitting element is in a current path state. During the light-emitting phase, the effective pulse periods included in the pulse control signal hf constitute the first duration, and the duration of the light-emitting phase is the second duration, with the first duration being much shorter than the second duration. By setting the amplitude of the data signal DI provided by the data signal terminal DI, the light-emitting element can operate in a current path with a larger amplitude, ensuring high uniformity of light output brightness, high luminous efficiency, and stable color coordinates. When achieving high grayscale brightness, the duration of driving current supplied to the light-emitting element is the second duration, while when achieving low grayscale brightness, the duration of driving current supplied to the light-emitting element is the first duration. Taking 256 gray levels as an example, let's say gray levels 80-255 represent the high gray level brightness range. In achieving this range, the duration for which the driving current is supplied to the light-emitting element is called the second duration. Different amplitudes of the data signal DI are provided by setting the data signal terminal DI to achieve the corresponding gray level brightness. For the low gray level range of 0-79, the duration for which the driving current is supplied to the light-emitting element is called the first duration. Again, different amplitudes of the data signal DI are provided by setting the data signal terminal DI to achieve the corresponding gray level brightness. It's understandable that when achieving high and low gray level brightness, the amplitude ranges of the data signal DI provided by the data signal terminal DI overlap to ensure high uniformity of light output brightness, high luminous efficiency, and stable color coordinates of the light-emitting element.
[0070] In some exemplary embodiments, such as Figure 4 As shown, the duration control circuit 302 provided in this embodiment includes: a duration selection sub-circuit 3021, a first duration control sub-circuit 3022, a second duration control sub-circuit 3023, and a light emission control circuit 3024, wherein,
[0071] The duration selection sub-circuit 3021 is connected to the first voltage terminal LVSS, the mode control signal terminal DT, the second scan signal terminal GH, the third scan signal terminal GE, the first node N1, and the second node N2, respectively. It is used to write the mode control signal to the first node N1 and the second node N2 under the control of the mode control signal DT, the second scan signal GH output from the second scan signal terminal, and the third scan signal GE output from the third scan signal terminal.
[0072] The first duration control sub-circuit 3022 is connected to the first node N1, the third node N3 and the pulse control signal terminal Hf respectively, and is used to write the pulse control signal hf of the pulse control signal terminal Hf to the third node N3 under the control of the signal of the first node N1.
[0073] The second duration control sub-circuit 3023 is connected to the second node N2, the third node N3 and the light emission control signal terminal EM_B respectively, and is used to write the light emission control signal em_b of the light emission control signal terminal EM_B to the third node N3 under the control of the signal of the second node N2.
[0074] The light-emitting control circuit 3024 is connected to the third node N3, the first voltage terminal LVSS, the light-emitting control signal terminal EM_B, the first scan signal terminal GA, and the current control circuit, respectively. It is used to receive the driving current and control the duration of the driving current flowing through the light-emitting element under the control of the signal of the third node N3, the light-emitting control signal em_b output by the light-emitting control signal terminal EM_B, and the first scan signal GA output by the first scan signal terminal Gate_A.
[0075] In some exemplary embodiments, such as Figure 5 As shown, the duration selection sub-circuit 3021 includes a first duration selection sub-circuit 30211 and a second duration selection sub-circuit 30212, wherein,
[0076] The first duration selection sub-circuit 30211 is connected to the first voltage terminal LVSS, the mode control signal terminal DT, the second scan signal terminal GH and the first node N1 respectively, and is used to write the mode control signal DT to the first node N1 under the control of the mode control signal DT and the second scan signal GH.
[0077] The second duration selection sub-circuit 30212 is connected to the first voltage terminal LVSS, the mode control signal terminal DT, the third scan signal terminal GE, and the second node N2, respectively, and is used to write the mode control signal DT to the second node N2 under the control of the mode control signal DT and the third scan signal GE.
[0078] In some exemplary embodiments, such as Figure 8a As shown, the first duration control sub-circuit 3022 includes a first transistor M1, the second duration control sub-circuit 3023 includes a second transistor M2, the first duration selection sub-circuit 30211 includes a first capacitor C1 and a third transistor M3, the second duration selection sub-circuit 30212 includes a second capacitor C2 and a fourth transistor M4, and the light emission control circuit 3024 includes a fifth transistor M5.
[0079] In this configuration, the control electrode of the first transistor M1 is connected to the first node N1, the first electrode of the first transistor M1 is connected to the pulse control signal terminal, and the second electrode of the first transistor M1 is connected to the third node N3; the control electrode of the second transistor M2 is connected to the second node N2, the first electrode of the second transistor M2 is connected to the light emission control signal terminal, and the second electrode of the second transistor M2 is connected to the third node N3; the control electrode of the third transistor M3 is connected to the second scan signal terminal, the first electrode of the third transistor M3 is connected to the mode control signal terminal, and the second electrode of the third transistor M3 is connected to the first node N1; the first terminal of the first capacitor C1 is connected to the first voltage terminal, and the second terminal of the first capacitor C1 is connected to the first node N1; the control electrode of the fourth transistor M4 is connected to the third scan signal terminal, the first electrode of the fourth transistor M4 is connected to the mode control signal terminal, and the second electrode of the fourth transistor M4 is connected to the second node N2; the first terminal of the second capacitor C2 is connected to the first voltage terminal, and the second terminal of the second capacitor C2 is connected to the second node N2; the control electrode of the fifth transistor is connected to the third node N3, the first electrode of the fifth transistor M5 is connected to the current control circuit, and the second electrode of the fifth transistor M5 is connected to the first voltage terminal.
[0080] In some exemplary embodiments, such as Figure 6 As shown, the current control circuit 301 may include: a data writing circuit 3011, a storage circuit 3012, and a driving circuit 3013;
[0081] The data writing circuit 3011 is used to write the data signal DI output from the data signal terminal DI to the fourth node N4 under the control of the first scan signal GA.
[0082] Storage circuit 3012 is used to store electrical energy at the fourth node N4;
[0083] The drive circuit 3013 is used to generate drive current under the control of the signal of the fourth node N4.
[0084] like Figure 8a As shown, the data writing circuit 3011 may include an eighth transistor M8, the storage circuit 3012 may include a third capacitor C3, and the driving circuit 3013 may include a driving transistor Md. Specifically, the control electrode of the eighth transistor M8 is connected to the first scan signal terminal, the first electrode of the eighth transistor M8 is connected to the data signal terminal, and the second electrode of the eighth transistor M8 is connected to the fourth node N4; the first terminal of the third capacitor C3 is connected to the fourth node N4, and the second terminal of the third capacitor C3 is connected to the fifth node N5; the control electrode of the driving transistor Md is connected to the fourth node N4, the first electrode of the driving transistor Md is connected to the light-emitting element, and the second electrode of the driving transistor Md is connected to the fifth node N5.
[0085] In some exemplary embodiments, such as Figure 7 As shown, the pixel circuit provided in this application embodiment may further include an external compensation circuit 304, which is used to compensate for the threshold voltage.
[0086] like Figure 8a As shown, the external compensation circuit 304 may include a sixth transistor M6, a seventh transistor M7, and a ninth transistor M9. The control electrode of the sixth transistor M6 is connected to the light emission control signal terminal, the first electrode of the sixth transistor M6 is connected to the current control circuit, and the second electrode of the sixth transistor M6 is connected to the first electrode of the seventh transistor M7. The control electrode of the seventh transistor M7 is connected to the first scan signal terminal, and the second electrode of the seventh transistor M7 is connected to the first voltage terminal. The control electrode of the ninth transistor M9 is connected to the fourth scan signal terminal, the first electrode of the ninth transistor M9 is connected to the fifth node N5, and the second electrode of the ninth transistor M9 is connected to the threshold voltage output terminal Rdout.
[0087] Figure 8a The diagram illustrates exemplary structures of the data writing circuit 3011, storage circuit 3012, driving circuit 3013, external compensation circuit 304, first duration control sub-circuit 3022, second duration control sub-circuit 3023, first duration selection sub-circuit 30211, second duration selection sub-circuit 30212, and light emission control circuit 3024. It will be readily understood by those skilled in the art that the implementation of each circuit is not limited to these examples, as long as their respective functions are achieved.
[0088] In some exemplary embodiments, such as Figure 8b As shown, the control electrode of the third transistor M3 in the first duration selection sub-circuit 30211 and the control electrode of the fourth transistor M4 in the second duration selection sub-circuit 30212 can be connected to the same scan signal terminal GC. This scan signal terminal GC is a signal terminal different from the first scan signal terminal GA or the fourth scan signal terminal GB, and the effective level time of the scan signal terminal GC is earlier than the effective level time of the first scan signal terminal GA. In this case, the first electrode of the third transistor M3 in the first duration selection sub-circuit 30211 and the first electrode of the fourth transistor M4 in the second duration selection sub-circuit 30212 need to be connected to different data signal terminals. That is, the first electrode of the third transistor M3 in the first duration selection sub-circuit 30211 is connected to the first mode control signal terminal DT1, and the first electrode of the fourth transistor M4 in the second duration selection sub-circuit 30212 is connected to the second mode control signal terminal DT2. Therefore, the corresponding mode control signals can be written to both the first duration selection sub-circuit 30211 and the second duration selection sub-circuit 30212 simultaneously during the effective level time of the scan signal terminal GC.
[0089] In some exemplary embodiments, the light-emitting element can be a sub-millimeter light-emitting diode (Mini LED), a micro light-emitting diode (Micro LED), or other types of light-emitting diodes such as organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs). In practical applications, the structure of the light-emitting element 303 needs to be designed and determined according to the actual application environment, and is not limited here. The following description uses a micro light-emitting diode as the light-emitting element 303 as an example.
[0090] In some exemplary embodiments, the first transistor M1 to the ninth transistor M9 and the driving transistor Md can be N-type transistors or P-type transistors. In this application, the embodiments are described using an N-type transistor as an example.
[0091] In some exemplary embodiments, all transistors in the embodiments of this application can be N-type transistors. Specifically, the active layer material of the transistor can be low-temperature polycrystalline silicon or metal oxide.
[0092] In some exemplary embodiments, the pulse control signal Hf output from the pulse control signal terminal Hf can be generated by an external integrated circuit (IC).
[0093] In some exemplary embodiments, such as Figure 9 As shown, when multiple pixel circuit arrays are arranged, they include multiple first scan signal lines GL1, multiple second scan signal lines GL2, multiple third scan signal lines GL3, multiple fourth scan signal lines GL4, multiple first data signal lines DL1, multiple second data signal lines DL2, multiple compensation voltage control lines RL, as well as one light emission control signal line E1, one pulse control signal line E2, one first voltage line LV1, and one second voltage line LV2.
[0094] Understandably, the first scan signal terminal GataA, the second scan signal terminal GH, the third scan signal terminal GE, and the fourth scan signal terminal GB of each pixel circuit corresponding to a row of sub-pixels are coupled to multiple first scan signal lines GL1, multiple second scan signal lines GL2, multiple third scan signal lines GL3, and multiple fourth scan signal lines GL4, respectively. The mode control signal terminal DT, the data signal terminal DI, and the threshold voltage output terminal Rdout of each pixel circuit corresponding to a column of sub-pixels are coupled to multiple first data signal lines DL1, multiple second data signal lines DL2, and multiple compensation voltage control lines RL, respectively. The light emission control signal line E1, the pulse control signal line E2, the first voltage line LV1, and the second voltage line LV2 are common signal lines, which are coupled to the light emission control signal terminal EM_B, the pulse control signal terminal Hf, the first voltage terminal LVSS, and the second voltage terminal LVDD of all pixel circuits, respectively.
[0095] Figure 10 for Figure 8a The timing diagram of the pixel circuit shown below illustrates the technical solution of the embodiments of this application further through the operation process of the pixel circuit. Figure 9 As shown, the first voltage terminal LVSS continuously provides a low-level signal lvss, and the second voltage terminal LVDD continuously provides a high-level signal lvdd. The operation of the pixel circuit in each scan cycle includes:
[0096] Phase 1, T1, as follows Figure 11 As shown, the second scan signal GH output from the second scan signal terminal GH is a high-level signal, the third transistor M3 is turned on, the mode control signal DT is written to the first node N1, and the first capacitor C1 is charged.
[0097] Phase 2, T2, as follows Figure 12 As shown, the third scan signal GE output from the third scan signal terminal GE is a high-level signal, the fourth transistor M4 is turned on, the mode control signal DT is written to the second node N2, and the second capacitor C2 is charged.
[0098] In the third stage T3, the second scan signal GH output from the second scan signal terminal GH is a low-level signal, the third scan signal GE output from the third scan signal terminal GE is a low-level signal, the first scan signal GA output from the first scan signal terminal GataA is a high-level signal, the eighth transistor M8 is turned on, and the data signal DI provided by the data signal terminal DI is written and stored to the fourth node N4, that is, the gate of the driving transistor Md.
[0099] In the fourth stage T4, the light-emitting stage, the first scan signal GA output from the first scan signal terminal GataA becomes a low-level signal, the seventh transistor M7 and the eighth transistor M8 are turned off, and the fifth transistor M5 controls the duration for which the driving current is supplied to the light-emitting element according to the potential of the third node N3. In some embodiments, such as Figure 13 As shown, if the mode control signal DT is a high-level signal DTH in stage T1 and a low-level signal DTL in stage T2, then the first capacitor C1 is high, the second capacitor C2 is low, the second transistor M2 is off, the first transistor M1 is on, and the pulse control signal hf output from the pulse control terminal Hf is written to the third node N3, i.e., the control electrode of the fifth transistor M5, through the first transistor M1. Therefore, in the light-emitting stage, the light-emitting element achieves high grayscale brightness. In other embodiments, such as... Figure 14 As shown, in stage T1, the mode control signal DT is a low-level signal DTL, and in stage T2, the mode control signal DT is a high-level signal DTH. At this time, the first capacitor C1 is low-level, the second capacitor C2 is high-level, the second transistor M2 is turned on, the first transistor M1 is turned off, and the light emission control signal em_b output from the light emission control signal terminal EM_B is written to the third node N3, which is the control electrode of the fifth transistor M5, through the second transistor M2. Thus, in the light emission stage, the light emission element achieves high grayscale brightness.
[0100] For example, in the embodiments of this application, the pulse control signal hf is a high-frequency pulse signal. For example, the frequency of the pulse control signal hf can be between 3000Hz and 60000Hz, such as 3000Hz or 60000Hz; the frequency of the light emission control signal em_b can be between 60Hz and 120Hz, such as 60Hz or 120Hz.
[0101] In summary, by setting the amplitude of the data signal DI provided by the data signal terminal DI, the light-emitting element can operate in a current path with a larger amplitude, ensuring high uniformity of light output brightness, high luminous efficiency, and stable color coordinates. When achieving high grayscale brightness, the duration of providing driving current to the light-emitting element is the second duration; while when achieving low grayscale brightness, the duration of providing driving current to the light-emitting element is the first duration. In this way, a high amplitude driving current combined with a short light emission time can achieve low grayscale brightness display, thereby improving the display effect of the display device at low grayscale levels.
[0102] In some embodiments, the pixel circuit provided in this application, in addition to the aforementioned T1, T2, T3, and T4 stages, may also include a threshold voltage Vth reading stage during operation. For example, the threshold voltage output terminal Rdout can be connected to the reading circuit 40 to sample the threshold voltage Vth of the driving transistor Md, such as... Figure 15 As shown; specifically, the timing diagram of the reading circuit 40 is as follows. Figure 16 As shown, the reading circuit 40 operates during the Blanking time between two adjacent scan cycles. The Blanking time is the period during which the light emission control signal em_b output from the light emission control signal terminal EM_B is at a low level. It can be understood that one Blanking time and one scan cycle constitute one frame. The Blanking time includes:
[0103] During the initialization phase, the first scan signal GA provided by the first scan signal terminal GA and the fourth scan signal GB provided by the fourth scan signal terminal GB are both high-level signals. The eighth transistor M8 and the ninth transistor M9 are turned on, the switch Sw_ref is closed, and the node N5 and the threshold voltage output terminal Rdout are set to 0V by the external power supply terminal to achieve potential initialization.
[0104] During the threshold voltage output stage, the first scan signal GA provided by the first scan signal terminal GA and the fourth scan signal GB provided by the fourth scan signal terminal GB are high-level signals, while the light emission control signal em_b provided by the light emission control signal terminal EM_B and the pulse control signal hf provided by the pulse control signal terminal are low-level signals. The eighth transistor M8 and the ninth transistor M9 are turned on, the switch Sw_ref is turned off, the fifth transistor M5 and the sixth transistor M6 are turned off, the second terminal of the driving transistor Md (i.e., the fifth node N5) is charged to (Vdata-Vth), and the potential of the fifth node N5 is transmitted to the threshold voltage output terminal Rdout through the ninth transistor M9.
[0105] During the threshold voltage sampling phase, Sw_samp is closed, and the potential (Vdata-Vth) stored at the threshold voltage output terminal Rdout is transmitted to the external chip to extract Vth. Thus, in the third stage T3 of the scan cycle after the Blanking time, Vth can be compensated into the data signal DI provided by the data signal terminal DI, thereby making the amplitude of the driving current independent of the threshold voltage Vth of the driving transistor Md, that is, avoiding the threshold voltage Vth of the driving transistor Md from affecting the amplitude of the driving current supplied to the light-emitting element.
[0106] Understandably, during the Blanking (black screen) period, the pulse control signal terminal Hf provides a low-level signal to ensure accurate reading of the threshold voltage Vth of the driving transistor Md.
[0107] In some embodiments, the pixel circuit may also employ internal compensation to eliminate the influence of the threshold voltage Vth of the driving transistor Md on the driving current amplitude. For example, the driving transistor Md can be charged to the saturation region before the third stage T3 in the scan cycle, which is not limited here. This application also provides a display device comprising a plurality of sub-pixels arranged in an array, each sub-pixel including the pixel circuit described in any of the foregoing embodiments. The display device of this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.
[0108] Based on the same inventive concept, embodiments of this application also provide a method for driving a pixel circuit, used to drive the pixel circuit as described above, wherein the pixel circuit has multiple scan cycles, and within one scan cycle, such as Figure 17 As shown, the driving method includes steps S1700 to S1701.
[0109] Step S1700: The current control circuit receives a data signal and a first scan signal, and controls the amplitude of the generated drive current according to the data signal and the first scan signal.
[0110] Step S1701: The duration control circuit receives the mode control signal, pulse control signal, light emission control signal and the drive current of the current control circuit, and controls the duration for which the drive current is provided to the light emission element according to the amplitude of the mode control signal.
[0111] The pixel circuit, driving method, and display device provided in this application embodiment enable the light-emitting element to operate in a current path with a larger amplitude by setting the amplitude of the data signal DI provided by the data signal terminal DI. This ensures high uniformity of light output brightness, high luminous efficiency, and stable color coordinates of the light-emitting element. When high grayscale brightness is achieved, the duration of providing driving current to the light-emitting element is the second duration; while when low grayscale brightness is achieved, the duration of providing driving current to the light-emitting element is the first duration. In this way, a high amplitude driving current combined with a short light emission time can achieve low grayscale brightness display, thereby improving the display effect of the display device at low grayscale.
[0112] The following points need to be explained:
[0113] The accompanying drawings of the embodiments in this application only involve the structures involved in the embodiments of this application; other structures can refer to general designs.
[0114] Where there is no conflict, the embodiments of this application, i.e. the features in the embodiments, can be combined with each other to obtain new embodiments.
[0115] Although the embodiments disclosed in this application are as described above, the content described is merely for the purpose of understanding this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.
Claims
1. A pixel circuit, characterized in that, include: The circuit consists of a current control circuit, a duration control circuit, and a light-emitting element, wherein: The current control circuit is used to receive a data signal and a first scan signal, and control the amplitude of the generated drive current according to the data signal and the first scan signal. The duration control circuit is used to receive a mode control signal, a pulse control signal, a light emission control signal, and a drive current from the current control circuit. The duration control circuit is configured to control the duration for which the drive current is provided to the light emission element according to the amplitude of the mode control signal. The duration control circuit includes: a duration selection sub-circuit, a first duration control sub-circuit, a second duration control sub-circuit, and a light emission control circuit, wherein, The duration selection sub-circuit is connected to the first voltage terminal, the mode control signal terminal, the second scan signal terminal, the third scan signal terminal, the first node, and the second node, respectively, and is used to write the mode control signal to the first node and the second node under the control of the mode control signal, the second scan signal output from the second scan signal terminal, and the third scan signal output from the third scan signal terminal; The first duration control sub-circuit is connected to the first node, the third node and the pulse control signal terminal respectively, and is used to write the pulse control signal of the pulse control signal terminal to the third node under the control of the signal of the first node; The second duration control sub-circuit is connected to the second node, the third node and the light emission control signal terminal respectively, and is used to write the light emission control signal of the light emission control signal terminal to the third node under the control of the signal of the second node; The light-emitting control circuit is connected to the third node, the first voltage terminal, and the current control circuit respectively, and is used to receive the driving current and control the duration for which the driving current flows through the light-emitting element under the control of the signal from the third node, the light-emitting control signal output from the light-emitting control signal terminal, and the first scan signal output from the first scan signal terminal.
2. The pixel circuit as described in claim 1, characterized in that, The duration selection sub-circuit includes a first duration selection sub-circuit and a second duration selection sub-circuit, wherein, The first duration selection sub-circuit is connected to the first voltage terminal, the mode control signal terminal, the second scan signal terminal and the first node respectively, and is used to write the mode control signal to the first node under the control of the mode control signal and the second scan signal; The second duration selection sub-circuit is connected to the first voltage terminal, the mode control signal terminal, the third scan signal terminal, and the second node, respectively, and is used to write the mode control signal to the second node under the control of the mode control signal and the third scan signal.
3. The pixel circuit as described in claim 1, characterized in that, The light-emitting control circuit is connected to the current control circuit, the third node, and the first voltage terminal, respectively, and is used to receive the driving current and, under the control of the signal from the third node, control the duration for which the driving current flows through the light-emitting element.
4. The pixel circuit as described in claim 1, characterized in that, The first duration control sub-circuit includes a first transistor, wherein: The control electrode of the first transistor is connected to the first node, the first electrode of the first transistor is connected to the pulse control signal terminal, and the second electrode of the first transistor is connected to the third node.
5. The pixel circuit as described in claim 1 or 4, characterized in that, The second duration control sub-circuit includes a second transistor, wherein: The control electrode of the second transistor is connected to the second node, the first electrode of the second transistor is connected to the light emission control signal terminal, and the second electrode of the second transistor is connected to the third node.
6. The pixel circuit as described in claim 2, characterized in that, The first duration selection sub-circuit includes a first capacitor and a third transistor, wherein: The control electrode of the third transistor is connected to the second scan signal terminal, the first electrode of the third transistor is connected to the mode control signal terminal, and the second electrode of the third transistor is connected to the first node; the first terminal of the first capacitor is connected to the first voltage terminal, and the second terminal of the first capacitor is connected to the first node.
7. The pixel circuit as described in claim 2 or 6, characterized in that, The second duration selection sub-circuit includes a second capacitor and a fourth transistor, wherein: The control electrode of the fourth transistor is connected to the third scan signal terminal, the first electrode of the fourth transistor is connected to the mode control signal terminal, and the second electrode of the fourth transistor is connected to the second node; the first terminal of the second capacitor is connected to the first voltage terminal, and the second terminal of the second capacitor is connected to the second node.
8. The pixel circuit as described in claim 3, characterized in that, The light-emitting control circuit includes a fifth transistor, wherein: The control electrode of the fifth transistor is connected to the third node, the first electrode of the fifth transistor is connected to the current control circuit, and the second electrode of the fifth transistor is connected to the first voltage terminal.
9. The pixel circuit as described in claim 1, characterized in that, The current control circuit includes: a data writing circuit, a storage circuit, and a driving circuit; The data writing circuit is used to write the data signal output from the data signal terminal that provides the data signal to the fourth node under the control of the first scan signal. The storage circuit is used to store the electrical energy at the fourth node; The driving circuit is used to generate a driving current under the control of the signal from the fourth node.
10. The pixel circuit as described in claim 9, characterized in that, The data writing circuit includes an eighth transistor, the storage circuit includes a third capacitor, and the driving circuit includes a driving transistor, wherein: The control electrode of the eighth transistor is connected to the first scan signal terminal, the first electrode of the eighth transistor is connected to the data signal terminal, and the second electrode of the eighth transistor is connected to the fourth node. The first end of the third capacitor is connected to the fourth node, and the second end of the third capacitor is connected to the fifth node; The control electrode of the driving transistor is connected to the fourth node, the first electrode of the driving transistor is connected to the light-emitting element, and the second electrode of the driving transistor is connected to the fifth node.
11. The pixel circuit as described in claim 1, characterized in that, It also includes an external compensation circuit, which is used to compensate for the threshold voltage.
12. The pixel circuit as described in claim 11, characterized in that, The external compensation circuit includes a sixth transistor, a seventh transistor, and a ninth transistor. The control electrode of the sixth transistor is connected to the light emission control signal terminal, the first electrode of the sixth transistor is connected to the current control circuit, and the second electrode of the sixth transistor is connected to the first electrode of the seventh transistor. The control electrode of the seventh transistor is connected to the first scan signal terminal, and the second electrode of the seventh transistor is connected to the first voltage terminal. The control electrode of the ninth transistor is connected to the fourth scan signal terminal, the first electrode of the ninth transistor is connected to the fifth node, and the second electrode of the ninth transistor is connected to the voltage output terminal.
13. A display device, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 12.
14. A driving method for a pixel circuit, characterized in that, For driving a pixel circuit as described in any one of claims 1 to 12, the pixel circuit having a plurality of scan cycles, wherein in one scan cycle, the driving method includes: The current control circuit receives a data signal and a first scan signal, and controls the amplitude of the generated drive current according to the data signal and the first scan signal. The duration control circuit receives the mode control signal, pulse control signal, light emission control signal, and drive current from the current control circuit, and controls the duration for which the drive current is provided to the light emission element according to the amplitude of the mode control signal.