Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention aims to manufacture a semiconductor device suitable for high-frequency transmission and reception. The method for manufacturing a semiconductor device of the present invention comprises the following steps: forming a first conductive portion on a first surface of a substrate by electroplating; forming a first insulating film that covers the first conductive portion and the first surface of the substrate; forming an opening in a portion of the first insulating film to expose a portion of the first conductive portion; electroplating the first conductive portion as an electrode to form a conductive plug within the opening; forming a second conductive portion that is electrically connected to an end opposite the conductive plug; arranging a semiconductor element electrically connected to the second conductive portion; sealing the semiconductor element and at least a portion of the second conductive portion with a sealing material; and peeling the first conductive portion, the first insulating film, the conductive plug, the second conductive portion, the semiconductor element, and the sealing material from the substrate as a whole.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] A semiconductor device has been proposed in which a wiring serving as an antenna and a semiconductor element are housed in a single package (see Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: U.S. Patent Application Publication No. 2017 / 0236776 Summary of the Invention

[0006] Problems to be solved by the invention

[0007] In the manufacturing method disclosed in Patent Document 1, a semiconductor device comprising a semiconductor chip (semiconductor element) and wiring is separately formed, and a carrier having an antenna formed on the surface of a dielectric layer is separately formed. The semiconductor device and the carrier are then bonded together to produce a semiconductor device. Consequently, unwanted resistance or capacitance is easily generated at the electrical junction between the semiconductor element included in the semiconductor device and the antenna included in the carrier. Consequently, it is difficult to manufacture a semiconductor device suitable for high-frequency transmission and reception.

[0008] Furthermore, in the semiconductor device disclosed in Patent Document 1, since the antenna is in contact with the surface of the dielectric layer included in the carrier and is exposed from the dielectric layer, there is a problem in that the mechanical durability is poor.

[0009] Solutions to Problems

[0010] According to a first embodiment, a method for manufacturing a semiconductor device comprises the following steps: forming a first conductive portion on at least a portion of a first surface of a substrate by electroplating; forming a first insulating film, the first insulating film covering the first conductive portion and at least a portion of the first surface of the substrate where the first conductive portion is not formed; forming an opening in a portion of the first insulating film to expose a portion of the first conductive portion; no seed layer is formed on the inner peripheral surface of the opening of the first insulating film, the first conductive portion is used as an electrode for electroplating, and a conductive plug is formed inside the opening of the first insulating film; forming a second conductive portion, the second conductive portion being electrically connected to the end of the conductive plug on the side opposite to the first conductive portion; configuring a semiconductor element to be electrically connected to the second conductive portion; sealing the semiconductor element and at least a portion of the second conductive portion with a sealing material; and peeling the first conductive portion, the first insulating film, the conductive plug, the second conductive portion, the semiconductor element, and the sealing material off the substrate as a whole.

[0011] According to the second scheme, the semiconductor device includes: a semiconductor element; a first conductive part serving as an antenna; a second conductive part electrically connected to the semiconductor element; a conductive plug electrically connected to the first conductive part and the second conductive part; and a first insulating film covering at least a portion of the first conductive part and the second conductive part, and the conductive plug, wherein the surface of the first conductive part on the side opposite to the conductive plug side is exposed from the first insulating film, and the surface other than the surface of the first conductive part is covered by the first insulating film.

[0012] Effects of the Invention

[0013] According to the manufacturing method of the present invention, a semiconductor device having excellent high-frequency conductive characteristics can be manufactured.

[0014] According to the semiconductor device of the present invention, it is possible to realize a semiconductor device having an antenna portion having excellent mechanical durability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a diagram for explaining a method for manufacturing a semiconductor device according to one embodiment, and is a diagram showing an initial step.

[0016] Figure 2 This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, and shows a connection diagram. Figure 1 Diagram of the process.

[0017] Figure 3 This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, and shows a connection diagram. Figure 2 Diagram of the process.

[0018] Figure 4This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, and shows a connection diagram. Figure 3 Diagram of the process.

[0019] Figure 5 This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, and shows a connection diagram. Figure 4 Diagram of the process.

[0020] Figure 6 This is a diagram showing a semiconductor device according to one embodiment.

[0021] Figure 7 These are diagrams showing various examples of the shape of the first conductive portion. DETAILED DESCRIPTION

[0022] (Method for Manufacturing a Semiconductor Device According to One Embodiment)

[0023] Figure 6 FIG. 1 is a diagram showing a semiconductor device 100 according to an embodiment of the present invention. Figures 1 to 5 Figures are used to illustrate a method for manufacturing semiconductor device 100. The X, Y, and Z directions indicated by arrows in each figure represent the same direction in each figure, with the direction indicated by the arrow being the positive direction. Furthermore, the X, Y, and Z directions are orthogonal to each other. Throughout this specification, the position in the X direction is referred to as the X position, and the position in the Y direction is referred to as the Y position.

[0024] (Substrate)

[0025] Figure 1 (a) is a cross-sectional view showing a substrate 10 used to manufacture the semiconductor device 100. The substrate 10 includes a support substrate 11, and a first metal layer 12 and a second metal layer 13 formed on the upper surface (+Z side) of the support substrate 11 in this order from the support substrate 11 side.

[0026] Hereinafter, the surface on the +Z side of the substrate 10 is referred to as a “first surface” S1 .

[0027] exist Figure 1 In (a) and the following figures, for ease of understanding, the length in the direction (Z direction) perpendicular to the surface of the substrate 10 is exaggerated relative to the in-plane direction (X direction) of the substrate 10.

[0028] In addition, Figure 1 In each of the drawings following (b), a portion of the thickness of the support substrate 11 is omitted.

[0029] The support substrate 11 is made of, for example, glass, and as an example, the thickness of the support substrate 11 is approximately 100 to 2000 μm.

[0030] As an example, the first metal layer 12 is a layer containing titanium. As an example, the thickness of the first metal layer 12 is about 0.05 to 1.0 μm. The first metal layer 12 may also include a titanium (Ti) alloy layer (e.g., tungsten titanium (WTi), titanium aluminum (TiAl)), nickel (Ni), chromium (Cr), tantalum (Ta), etc. instead of titanium.

[0031] As an example, the second metal layer 13 is a layer containing copper. As an example, the thickness of the second metal layer 13 is about 0.1 to 3.0 μm. The second metal layer 13 may also include a copper (Cu) alloy layer (for example, titanium copper (TiCu), titanium copper iron (TiCuFe)), nickel (Ni), chromium (Cr), tantalum (Ta), etc. instead of copper.

[0032] A peeling layer (not shown) containing carbon or the like as a main component may be formed between the support substrate 11 and the first metal layer 12 .

[0033] If a supporting substrate 11 having at least the first metal layer 12 and the second metal layer 13 formed thereon and meeting the above conditions is available for sale, it can be purchased and used.

[0034] (Formation of the First Conductive Portion)

[0035] Figure 1 (b) shows a state where the first conductive portion 15 and the alignment mark 16 are formed on the first surface S1, which is the +Z side surface of the substrate 10, that is, on the second metal layer 13. To form the first conductive portion 15 and the alignment mark 16, a photoresist 14 is first formed over the entire surface of the first surface S1, that is, on the second metal layer 13. The photoresist 14 then forms openings corresponding to the shapes of the first conductive portion 15 and the alignment mark 16. Then, the substrate 10 is immersed in a plating solution and electrolytic copper plating is performed. Copper is plated to the exposed portion of the second metal layer 13 (that is, the opening in the photoresist 14), thereby forming the first conductive portion 15 and the alignment mark 16.

[0036] Thereafter, the photoresist 14 is removed.

[0037] The first conductive portion 15 is a portion that serves as an antenna in the semiconductor device 100 described below.

[0038] Figure 1 (c) is a top view of the substrate 10 on which the first conductive portion 15 and the alignment mark 16 are formed, viewed from the +Z direction. Figure 1 As shown in (c), the first conductive portion 15 constitutes an antenna portion, and as an example, the antenna portion includes two substantially elliptical conductive portions that are arranged at a predetermined interval in the X direction and extend in the Y direction.

[0039] The X direction may refer to a first direction within the plane of the first surface S1 that coincides with the XY plane.

[0040] Furthermore, the first conductive portion 15 may further include portions other than the antenna portion. Furthermore, the number of antenna portions is not limited to two, and the first conductive portion 15 may include three or more conductive portions arranged at predetermined intervals in the X direction.

[0041] Because the first conductive portion 15 and the alignment mark 16 are formed using openings formed simultaneously in the same photolithography process, their positional relationship in the X and Y directions can be accurately determined. Therefore, in the following steps, by measuring the X and Y positions of the alignment mark 16, the X and Y positions of the first conductive portion 15 can be accurately determined.

[0042] (Formation of First Insulating Film)

[0043] Figure 2 (a) shows a state where the first insulating film 17 is formed on the substrate 10 so as to cover the first conductive portion 15 and the alignment mark 16. The first insulating film 17 is formed so as to cover at least a portion of the first surface S1 of the substrate 10 where the first conductive portion 15 and the alignment mark 16 are not formed.

[0044] As an example, the first insulating film 17 is formed by attaching an ABF film (Ajinomoto build-up film) to the support substrate 11 including the first conductive portion 15 and the alignment mark 16. As an example, the thickness T1 of the first insulating film 17 is greater than 100 μm. Alternatively, the first insulating film 17 can be formed by applying a liquid material.

[0045] (Formation of opening)

[0046] Figure 2 (b) shows a state where an opening 17a is formed in the first insulating film 17 in a portion above (in the +Z direction) a portion of the first conductive portion 15. The opening 17a is formed by irradiating a predetermined portion of the first insulating film 17 with shaped light, such as a laser, to evaporate a portion of the first insulating film 17. A portion of the first conductive portion 15 is exposed through the opening 17a.

[0047] Before forming the opening 17a, a position detection device (not shown) is used to measure the X and Y positions of the alignment mark 16. Then, based on the position measurement results of the alignment mark 16, light is irradiated to the X and Y positions of the first insulating film 17 corresponding to the desired portion of the first conductive portion 15 so as to form the opening 17a.

[0048] (Formation of Conductive Plugs)

[0049] exist Figure 2 Inside the opening 17a shown in (b), the first conductive portion 15 is plated as an electrode.

[0050] Figure 2 (c) shows a state where a conductive plug 18 composed mainly of copper is formed within the opening 17a by electrolytic copper plating using the first conductive portion 15 as an electrode. As an example, the length of the conductive plug 18 (length in the Z direction) is 100 μm or greater. Alternatively, the length of the conductive plug 18 may be shorter than the thickness T1 of the first insulating film 17.

[0051] Furthermore, when a seed layer is formed on the inner circumference of opening 17a and then electroplated onto conductive plug 18, the plating speed increases because metal is more readily supplied from the plating solution to the inner circumference near the +Z end of opening 17a than near the -Z end. Consequently, it is possible that only the area near the +Z end of opening 17a will be filled with metal, while the area near the -Z end will become hollow. Consequently, it may be impossible to form conductive plug 18 with sufficiently low resistance.

[0052] In contrast, in one embodiment, as described above, a seed layer is not formed on the inner circumference of the opening 17a, and the first conductive portion 15 is plated as an electrode. Therefore, the metal is sequentially filled into the opening 17a starting from the -Z side end (the side closer to the first conductive portion 15). Therefore, a conductive plug 18 having a sufficiently low resistance and no voids can be formed inside the relatively deep opening 17a formed by the first insulating film 17 having a thickness of, for example, 100 μm or more.

[0053] Furthermore, since a seed layer is not formed on the surface of the first conductive portion 15, and instead copper is electroplated on the surface of the first conductive portion 15 formed by electroplating to serve as the conductive plug 18, the first conductive portion 15 and the conductive plug 18 can be firmly bonded. Furthermore, since there is no seed layer between the first conductive portion 15 and the conductive plug 18, the capacitance formed between the first conductive portion 15 and the conductive plug 18 can be minimized. Consequently, the impedance to the high-frequency current flowing between the first conductive portion 15 and the conductive plug 18 can be minimized.

[0054] Furthermore, the diameter of the conductive plug 18 is substantially the same as the diameter D1 of the opening 17a. Therefore, to reduce the resistance of the conductive plug 18, the larger the diameter D1 of the opening 17a, the better. However, if the diameter D1 of the opening 17a is too large, the capacitance formed between the first conductive portion 15 and the conductive plug 18 will increase.

[0055] Therefore, as an example, the diameter D1 of the opening 17a is set to be approximately the same as the thickness T1 of the first insulating film 17. Alternatively, as an example, the diameter D1 of the opening 17a may be greater than 100 μm. As a further example, the diameter D1 of the opening 17a may be greater than or equal to 0.5 times and less than or equal to 4 times the thickness T1 of the first insulating film 17.

[0056] Here, the diameter D1 of the opening 17a is equivalent to the diameter if the opening 17a is circular, or the length of one side if the opening 17a is square. Furthermore, if the opening 17a is substantially elliptical, the diameter D1 is equivalent to the sum of its major and minor radii. If the opening 17a is substantially rectangular, the diameter D1 is equivalent to the average length of two non-opposing sides.

[0057] (Formation of First and Second Wiring)

[0058] exist Figure 2 The conductive plug 18 shown in (c), the end surface on the +Z side of the first insulating film 17, and a portion of the inner peripheral surface of the opening 17a are formed into a conductive seed layer by electroless copper plating or the like.

[0059] Figure 2 (d) is a diagram showing a state where the seed layer 19 is formed.

[0060] Figure 3 (a) shows a state where first wiring 21 is formed on seed layer 19 (on the +Z side). To form first wiring 21, dry film resist 20 is formed on seed layer 19 (on the +Z side) by lamination or other means. Predetermined portions of dry film resist 20 are exposed and then developed, thereby forming openings at predetermined locations in dry film resist 20. Then, using seed layer 19 as an electrode, a metal such as copper is electroplated inside the openings in dry film resist 20, thereby forming first wiring 21.

[0061] Thereafter, the dry film resist 20 is removed by etching or the like, and the seed layer 19 is removed by etching using the first wiring 21 as an etching mask.

[0062] Figure 3 (b) shows a state where the first wiring 21 is formed and the dry film resist 20 and the seed layer 19 are removed.

[0063] Figure 3 (c) shows a state where the second insulating film 22 is formed on the first wiring 21 (+Z side), and an opening 22 a is formed in a portion of the second insulating film 22 .

[0064] The second insulating film 22 is formed on the first insulating film 17 and the first wiring 21 (on the +Z side) by laminating an ABF film in the same manner as the first insulating film 17. As an example, the thickness of the second insulating film 22 is about 30 to 50 μm.

[0065] The opening 22a is formed by irradiating a predetermined portion of the second insulating film 22 with shaped light such as laser light to evaporate a portion of the second insulating film 22. Figure 3 As shown in (c), a portion of the first wiring 21 is exposed through the opening 22a.

[0066] exist Figure 3 The +Z side end surface of the second insulating film 22 shown in (c), a portion of the first wiring 21 exposed from the opening 22a, and the inner peripheral surface of the opening 22a are formed with a conductive seed layer by electroless copper plating or the like.

[0067] Figure 3 (d) is a diagram showing a state where the seed layer 23 is formed.

[0068] Figure 4 (a) shows a state where second wirings 25a and 25b are formed on the seed layer 23 (on the +Z side). Hereinafter, the second wirings 25a and 25b are collectively referred to as second wirings 25. Similar to the first wirings 21 described above, the second wirings 25 are formed by forming openings at predetermined positions in a dry film resist 24 formed on the seed layer 23 (on the +Z side) and electroplating the seed layer 23 with a metal such as copper as an electrode.

[0069] Then, the dry film resist 24 is removed by etching or the like.

[0070] Figure 4 (b) shows a state where a post 27 is formed on the second wiring 25b (on the +Z side). Like the second wiring 25 described above, the post 27 is formed by forming an opening 26a at a predetermined position in the dry film resist 26 formed on the seed layer 23 and the second wiring 25 (on the +Z side), and electroplating a metal such as copper in the opening 26a, using the second wiring 25 as an electrode.

[0071] Thereafter, the dry film resist 26 is removed by etching or the like, and the seed layer 23 is removed by etching using the second wiring 25 as an etching mask.

[0072] (Configuration of semiconductor elements)

[0073] Figure 4(c) shows a state where a semiconductor element 29 is bonded to a second wiring 25a formed on the substrate 10 via a pillar 28. The semiconductor element 29 is a semiconductor integrated circuit chip cut from a semiconductor wafer, such as a radio frequency (RF) integrated circuit (IC), a logic circuit IC such as a central processing unit (CPU), or a memory IC such as a dynamic random access memory (DRAM).

[0074] Pillars 28 and solder (not shown) are formed on a portion of the main surface (-Z side) of the semiconductor element 29 where the semiconductor integrated circuit is formed before bonding to the second wiring 25a. Bonding of the semiconductor element 29 can be performed using various flip chip bonders.

[0075] Before being bonded to the substrate 10 , the back surface (the surface opposite to the main surface) may be polished to make the semiconductor element 29 have a thickness of approximately 70 μm to 150 μm.

[0076] In this specification, the seed layer 19, first wiring 21, seed layer 23, second wiring 25, pillars 27, and at least a portion of pillars 28 described above are also referred to as the "second conductive portion." The second conductive portion is electrically connected to the end of the conductive plug 18 on the side opposite to the first conductive portion 15 (the +Z side). Furthermore, the semiconductor element 29 is configured to be electrically connected to the second conductive portion.

[0077] In addition, due to Figure 4 (c) shows a cross-section of a portion of the substrate 10 and semiconductor element 29 on which the second conductive portion and the like are formed. Therefore, although the second wiring 25a and the second wiring 25b are shown as insulated, the second wiring 25a and the second wiring 25b may be partially electrically connected. Furthermore, the first conductive portion 15 and the second wiring 25b may also be partially electrically connected.

[0078] (Sealed by sealing material)

[0079] The semiconductor element 29 , the pillar 28 , the second wiring 25 , and at least a portion of the column 27 are sealed with a sealing material.

[0080] Figure 5 (a) shows a state in which at least a portion of the semiconductor element 29 , the pillar 28 , the second wiring 25 , and the column 27 formed on the second insulating film 22 on the substrate 10 are sealed by the sealing material 30 .

[0081] Sealing material 30 can be, for example, an epoxy-based resin filled with a filler such as silica. The seal can be formed using compression molding, where liquid resin is pressurized using a mold. Alternatively, transfer molding can be used. For example, the thickness of sealing material 30 is approximately 200 to 700 μm.

[0082] The pillars 28, the second wiring 25, and the columns 27 are all included in the second conductive portion. Therefore, in other words, the sealing can be said to be sealing the semiconductor element 29 and at least a portion of the second conductive portion with the sealing material.

[0083] (Formation of Third Wiring)

[0084] Figure 5 (b) shows a state where third wiring 31 is formed on the sealing material 30 (on the +Z side). When forming the third wiring 31, an opening 30a is formed by photolithography in a portion of the sealing material 30 whose X and Y positions coincide with at least a portion of the pillar 27. A seed layer (not shown) is then formed on the upper end surface of the sealing material 30, the inner circumference of the opening 30a, and the upper end of the pillar 27 exposed through the opening 30a.

[0085] Then, similarly to the first wiring 21 described above, openings are formed at predetermined positions in a dry film resist (not shown) formed on the seed layer (not shown) (on the +Z side), and a metal such as copper is electroplated using the seed layer as an electrode to form the third wiring 31. After the third wiring 31 is formed, the dry film resist (not shown) is removed, and the seed layer (not shown) is removed by etching using the third wiring 31 as an etching mask.

[0086] Below, we will Figure 5 The first conductive part 15, the first insulating film 17, the second insulating film 22, the conductive plug 18, the second conductive parts 19, 21, 23, 25, 27, 28, the semiconductor element 29, the sealing material 30, and the third wiring 31 shown in (b) are collectively referred to as the "intermediate generated body" 50.

[0087] (Peeling from substrate)

[0088] The intermediate product 50 is peeled off integrally from the substrate 10 . Figure 5 (c) shows the intermediate product 50 peeled from the substrate 10 .

[0089] When peeling the intermediate product 50 from the substrate 10, as an example, the support substrate 11 constituting the substrate 10 may be first peeled from the intermediate product 50, and the second metal layer 13 and the first metal layer 12 integrally formed with the intermediate product 50. Subsequently, the first metal layer 12 and the second metal layer 13 may be sequentially removed from the intermediate product 50 by etching or the like.

[0090] By peeling the substrate 10 from the intermediate product 50, the first conductive portion 15, which is formed in close contact with the second metal layer 13 of the substrate 10, is exposed at the -Z side end surface of the intermediate product 50. However, the portion of the first conductive portion 15 exposed from the first insulating film 17 is only the -Z side end surface, that is, the surface of the first conductive portion 15 opposite to the conductive plug 18 side. Furthermore, the surface of the first conductive portion 15 other than the -Z side end surface is covered by the first insulating film 17.

[0091] (Formation of the Third Metal Layer and Solder Balls)

[0092] Figure 6 1 is a diagram showing a cross section of the completed semiconductor device 100 .

[0093] for Figure 5 The intermediate product 50 shown in (c) is formed by forming a third metal layer 32 on the -Z side end face of the first conductive portion 15 exposed from the first insulating film 17, and forming a solder ball 33 on at least a portion of the +Z side end face of the third wiring 31, thereby completing Figure 6 The semiconductor device 100 is shown.

[0094] As an example, the third metal layer 32 is formed by laminating a layer mainly composed of nickel, a layer mainly composed of palladium, and a layer mainly composed of gold by plating in this order from the side of the first conductive portion 15. In this case, the lower end portion (end portion on the -Z side) of the third metal layer 32 is covered with gold, which has high corrosion resistance.

[0095] Furthermore, formation of at least one of the layer containing nickel as a main component and the layer containing palladium as a main component may be omitted.

[0096] The solder ball 33 is formed on the +Z side end surface of the third wiring 31 by placing the solder ball 33 on the +Z side end surface of the third wiring 31 and performing heat reflow.

[0097] Through the above process, the Figure 6 The semiconductor device 100 is shown.

[0098] In the above description, the first conductive portion 15 , the conductive plug 18 , the first wiring 21 , the second wiring 25 , and the third wiring 31 are formed by electrolytic copper plating. However, at least a portion of them may be formed by electroplating of other metals.

[0099] However, particularly regarding the first conductive portion 15 and the conductive plug 18 , by forming them from the same material (metal), their bonding strength can be further improved.

[0100] In addition, although the first insulating film 17 is formed of a single material in the above description, it can also be formed by overlapping multiple films composed of different materials. As multiple films, for example, films of materials with different linear expansion coefficients can also be used. For example, a film of a material with a relatively large linear expansion coefficient but high adhesion to the first conductive portion 15, etc., can be overlapped with a film with a relatively small linear expansion coefficient. In this case, it is possible to improve the adhesion to the first conductive portion 15, etc., and suppress the linear expansion coefficient of the first insulating film 17 as a whole to a small value.

[0101] In addition, the formation of the seed layer 19 for forming the first wiring 21 is not limited to the following. Figure 2 As shown in (d), the seed layer 19 is formed directly on the end surface of the conductive plug 18 and the first insulating film 17 on the +Z side and a part of the inner peripheral surface of the opening 17a. Figure 2 In the state shown in (c) of FIG1 , a third insulating film is formed using an ABF film or the like on the first insulating film 17 and the conductive plugs 18 (on the +Z side), and an opening is formed in the third insulating film at a portion where the X and Y positions coincide with the conductive plugs 18. Furthermore, a seed layer 19 may be formed on the conductive plugs 18 exposed from the opening, on the end surface of the third insulating film on the +Z side, and on the inner peripheral surface of the opening.

[0102] In addition, the alignment mark 16 may not be Figure 1 (b) and Figure 1 As shown in (c), the alignment mark 16 is formed not near the first conductive portion 15, but at a position away from the first conductive portion 15 in the X direction or the Y direction. For example, the alignment mark 16 may be formed in a peripheral portion of the first surface S1 of the substrate 10 that is not covered by the first insulating film 17 in a subsequent step.

[0103] In addition, although Figures 1 to 5 , the manufacturing process of one semiconductor device 100 is shown. However, the substrate 10 may be made sufficiently larger than the semiconductor device 100, and a plurality of semiconductor devices 100 may be arranged in the X direction or the Y direction on the substrate 10. In this case, after the substrate 10 is peeled off from the plurality of integrally formed intermediate products 50, the plurality of integrally formed intermediate products 50 may be cut into individual pieces.

[0104] In this case, the alignment marks 16 may be formed corresponding to each of the plurality of semiconductor devices 100. Alternatively, a smaller number of alignment marks 16 than the number of arranged semiconductor devices 100 may be provided. In this case, the alignment marks 16 may be formed in the peripheral portion not covered by the first insulating film 17 in a subsequent step.

[0105] Furthermore, while the above description assumes that three layers of wiring are formed on substrate 10, namely, first wiring 21, second wiring 25, and third wiring 31, the number of wiring layers formed on substrate 10 is not limited to this. In other words, wiring layers may be formed in one layer or in four or more layers. Formation of wiring layers having four or more layers can be performed using the same method as described above for forming first wiring 21, second wiring 25, or third wiring 31.

[0106] In addition, depending on the application of the semiconductor device 100 , at least one of the solder balls 33 and the third metal layer 32 may be omitted.

[0107] Furthermore, the shape of the first surface S1 of the substrate 10, which is the portion of the semiconductor device 100 that serves as the antenna, that is, the first conductive portion 15, is not limited to having Figure 1 The two parts are roughly elliptical in shape as shown in (c). Other shapes are also possible.

[0108] Figure 7 (a) to Figure 7 (c) are diagrams showing examples of other shapes of the first conductive portion 15 formed in the first surface S1 of the substrate 10. Figure 7 In the example shown in (a), the first conductive portion 15 has a shape of four substantially square conductive portions arranged in two rows in the X direction and two rows in the Y direction.

[0109] exist Figure 7 In the example shown in (b), the first conductive portion 15 is a substantially circular conductive portion arranged in two rows in the X direction and in two rows in the Y direction, a total of four. Figure 7 In the example shown in (c), the first conductive portion 15 has a substantially square shape, with four rows of conductive portions arranged in the X direction and four rows in the Y direction, totaling sixteen portions.

[0110] (Effects of the Method for Manufacturing a Semiconductor Device According to One Embodiment)

[0111] (1) The above method for manufacturing a semiconductor device comprises the following steps: forming a first conductive portion 15 by electroplating on at least a portion of the first surface S1 of the substrate 10; forming a first insulating film 17, which covers the first conductive portion 15 and at least a portion of the portion of the first surface S1 of the substrate 10 where the first conductive portion 15 is not formed; forming an opening 17a in a portion of the first insulating film 17 to expose a portion of the first conductive portion 15; and without forming a seed layer on the inner peripheral surface of the opening 17a of the first insulating film 17, electroplating is performed using the first conductive portion 15 as an electrode, and forming a conductive plug 18 inside the opening 17a of the first insulating film 17. The present invention further comprises the following steps: forming a second conductive portion 19, 21, 23, 25, 27, 28, which is electrically connected to the end of the conductive plug 18 on the side opposite to the first conductive portion 15; configuring a semiconductor element 29 electrically connected to the second conductive portion; sealing the semiconductor element 29 and at least a portion of the second conductive portion by a sealing material 30; and peeling off the first conductive portion 15, the first insulating film 17, the conductive plug 18, the second conductive portion, the semiconductor element 29, and the sealing material 30 from the substrate 10 as a whole.

[0112] This structure allows the conductive plugs 18 to be reliably formed inside the openings 17a even when the first insulating film 17 is thick and the openings 17a are deep, enabling the production of conductive plugs 18 with low resistance and impedance. Consequently, a semiconductor device with excellent high-frequency conductive characteristics can be manufactured.

[0113] (2) By forming an insulating film having a thickness of 100 μm or greater as the first insulating film 17 and forming a plug having a length of 100 μm or greater as the conductive plug 18, the distance between the first conductive portion 15 and the first wiring 21 can be set to 100 μm or greater. Consequently, when the first conductive portion 15 is used as an antenna, the adverse electromagnetic effects of the first wiring 21 on the antenna can be reduced, thereby enabling the manufacture of a high-performance semiconductor device for communications.

[0114] (Semiconductor Device According to One Embodiment)

[0115] As mentioned above, Figure 6 FIG1 is a diagram showing a semiconductor device 100 according to an embodiment manufactured by the method for manufacturing a semiconductor device according to the above-described embodiment. Since the structures and features of the semiconductor device 100 described in the method for manufacturing a semiconductor device according to the above-described embodiment are all used in the semiconductor device 100 according to the embodiment, their descriptions are omitted to avoid duplication.

[0116] (Effects of the Semiconductor Device According to One Embodiment)

[0117] (3) Semiconductor device 100 includes: a semiconductor element 29; a first conductive portion 15 serving as an antenna; second conductive portions 19, 21, 23, 25, 27, and 28 electrically connected to semiconductor element 29; and a conductive plug 18 electrically connected to the first conductive portion 15 and the second conductive portion. Semiconductor device 100 further includes: a first insulating film 17 covering at least a portion of the first conductive portion 15 and the second conductive portion, as well as the conductive plug 18. The surface of the first conductive portion 15 opposite to the conductive plug 18 is exposed from the first insulating film 17, and the surfaces of the first conductive portion 15 other than the surface opposite to the conductive plug 18 are covered by the first insulating film 17.

[0118] In this structure, since the first conductive portion 15, serving as the antenna, is almost entirely embedded within the first insulating film 17, even if foreign matter comes into contact with the first conductive portion 15 from the outside, the first conductive portion 15 will not be peeled off or damaged. This allows for a semiconductor device with excellent mechanical durability of the antenna portion.

[0119] (4) The interval between the first conductive part 15 and the second conductive parts 19, 21, 23, 25, 27, and 28 is set to be greater than 100 μm, and the length of the conductive plug 18 is set to be greater than 100 μm. This can reduce the adverse effects of the electromagnetic properties of the first conductive part 15 serving as an antenna from the second conductive part, thereby realizing a high-performance semiconductor device for communication.

[0120] (5) By adopting a structure in which a metal film containing gold is formed on the surface of the first conductive portion 15 opposite to the conductive plug 18, a semiconductor device can be realized in which the corrosion resistance of the first conductive portion 15 serving as an antenna is improved.

[0121] The present invention is not limited to the above description, and other embodiments that can be conceived within the scope of the technical concept of the present invention are also included in the scope of the present invention.

[0122] Explanation of symbols

[0123] 100—semiconductor device; 11—support substrate; 12—first metal layer; 13—second metal layer; 15—first conductive portion; 16—alignment mark; 17—first insulating film; 17a—opening; 18—conductive plug; 21—first wiring; 25 (25a, 25b)—second wiring; 27—pillar; 28—column; 29—semiconductor element; 30—sealing material; 32—third metal layer; 33—solder ball.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are required: forming a first conductive portion on at least a portion of the first surface of the substrate by electroplating; forming a first insulating film having a thickness of 100 μm or greater, the first insulating film covering the first conductive portion and at least a portion of the first surface of the substrate where the first conductive portion is not formed; forming an opening in a portion of the first insulating film to expose a portion of the first conductive portion; No seed layer is formed on the inner peripheral surface of the opening of the first insulating film, and the first conductive portion is used as an electrode for electroplating to form a conductive plug with a length of 100 μm or more inside the opening of the first insulating film; forming a second conductive portion electrically connected to an end portion of the conductive plug on a side opposite to the first conductive portion; A semiconductor element is configured to be electrically connected to the second conductive portion; sealing the semiconductor element and at least a portion of the second conductive portion with a sealing material; as well as The first conductive portion, the first insulating film, the conductive plug, the second conductive portion, the semiconductor element, and the sealing material are integrally peeled off from the substrate. The first conductive portion includes an antenna.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: A diameter of the opening is not less than 0.5 times and not more than 4 times the thickness of the first insulating film.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The first insulating film is formed by overlapping a plurality of films having different linear expansion coefficients.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: After the first conductive portion, the first insulating film, the conductive plug, the second conductive portion, the semiconductor element, and the sealing material are integrally peeled off from the substrate, a metal containing gold is plated on the surface of the first conductive portion on the side opposite to the conductive plug.

5. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The first conductive portion includes an antenna portion having a plurality of conductive portions spaced apart and arranged at predetermined intervals in at least a first direction within the first plane.

6. A semiconductor device, characterized in that: have: semiconductor components; A first conductive portion serving as an antenna; a second conductive portion electrically connected to the semiconductor element; a conductive plug electrically connected to the first conductive portion and the second conductive portion; as well as a first insulating film covering at least a portion of the first conductive portion and the second conductive portion, and the conductive plug; The surface of the first conductive portion on the side opposite to the conductive plug is exposed from the first insulating film. The surfaces other than the surface of the first conductive portion are covered by the first insulating film, The distance between the first conductive portion and the second conductive portion is greater than 100 μm, and the length of the conductive plug is greater than 100 μm. No seed layer is formed on the inner peripheral surface of the opening of the first insulating film, and electroplating is performed using the first conductive portion as an electrode, thereby forming the conductive plug inside the opening of the first insulating film.

7. The semiconductor device according to claim 6, wherein: The first conductive portion and the conductive plug are made of the same material.

8. The semiconductor device according to claim 6 or 7, wherein: A metal film containing gold is formed on a surface of the first conductive portion on the side opposite to the conductive plug.

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