Semiconductor device with contact check circuit

Abstract

A semiconductor device with contact inspection circuit is provided. The semiconductor device includes a plurality of pads, internal circuitry, and a contact inspection circuit. The pads include a first pad and a second pad. The internal circuitry is coupled to the pads. The contact inspection circuit is coupled to at least the first pad and the second pad and is configured to inspect a plurality of contact connections of the first pad and the second pad when the semiconductor device is under inspection to generate an inspection result signal based on a comparison between a first test signal received from the first pad and a second test signal received from the second pad and at least one reference signal.

Description

Technical Field

[0001] This invention relates to an integrated circuit, and more particularly to a semiconductor device having a contact inspection circuit. Background Technology

[0002] In electronic products, an electronic fuse (e-fuse) is a technology that allows for the dynamic reprogramming of a semiconductor device (or chip) on an instantaneous basis. Theoretically, computer logic is typically "etched" or "written" onto a chip and cannot be changed after the chip is manufactured. By using a set of electronic fuses in a semiconductor device, chip manufacturers can make changes to the circuitry on the chip while it is running or before the chip is shipped to downstream customers.

[0003] In the melting operation of an electronic fuse, signals from a semiconductor testing device are input to the semiconductor device via multiple probes of the testing device that contact multiple pads of the semiconductor device. If the probes do not make proper contact with the pads, melting cannot proceed correctly. Summary of the Invention

[0004] The object of this invention is to provide a semiconductor device having a contact inspection circuit. The semiconductor device includes a contact inspection circuit that, when testing the semiconductor device, for example, using a semiconductor test apparatus connected to at least two pads of the semiconductor device, is capable of inspecting multiple contact connections between a first pad and a second pad to generate an inspection result signal.

[0005] To achieve at least the above-mentioned objectives, the present invention provides a semiconductor device having a contact inspection circuit. The semiconductor device includes a plurality of solder pads, internal circuitry, and the contact inspection circuitry. The solder pads include a first solder pad and a second solder pad. The internal circuitry is coupled to the solder pads. The contact inspection circuitry is at least coupled to the first solder pad and the second solder pad, and is used to inspect the plurality of contact connections between the first solder pad and the second solder pad when the semiconductor device is under test to generate an inspection result signal. The inspection result signal is generated based on a comparison between a first test signal received from the first solder pad and a second test signal received from the second solder pad, and at least one reference signal.

[0006] In some embodiments, the contact inspection circuit includes a voltage detection circuit and a comparison circuit. The voltage detection circuit is coupled to a first solder pad and a second solder pad and is used to generate at least one voltage detection signal. The comparison circuit is coupled to the voltage detection circuit and is used to generate an inspection result signal based on at least one voltage detection signal and at least one reference signal.

[0007] In some embodiments, the voltage detection circuit includes a voltage divider coupled between a first pad and a second pad, and is used to generate at least one voltage detection signal.

[0008] In some embodiments, the comparison circuit includes a comparator for generating a check result signal based on at least one voltage detection signal and at least one reference signal.

[0009] In some embodiments, at least one reference signal includes a first reference signal and a second reference signal. The comparison circuit is configured to generate a first comparison signal based on at least one voltage detection signal and the first reference signal; and the comparison circuit is configured to generate a second comparison signal based on at least one voltage detection signal and the second reference signal, wherein the comparison circuit is configured to generate a check result signal based on the first comparison signal and the second comparison signal.

[0010] In some embodiments, the comparison circuit includes a first comparator, a second comparator, and a logic unit. The first comparator is used to generate a first comparison signal based on at least one voltage detection signal and a first reference signal. The second comparator is used to generate a second comparison signal based on at least one voltage detection signal and a second reference signal. The logic unit is coupled to the first and second comparators and is used to generate a check result signal based on the first and second comparison signals.

[0011] In some embodiments, at least one voltage detection signal includes a first voltage detection signal and a second voltage detection signal, and the voltage detection circuit is configured to generate the first voltage detection signal based on a first test signal and a first power supply signal; and the voltage detection circuit is configured to generate the second voltage detection signal based on a second power supply signal and a second test signal.

[0012] In some embodiments, at least one voltage detection signal includes a first voltage detection signal and a second voltage detection signal, and the voltage detection circuit includes a first voltage divider and a second voltage divider. The first voltage divider is coupled between a first pad and a first power supply terminal and is used to generate the first voltage detection signal. The second voltage divider is coupled between a second power supply terminal and a second pad and is used to generate the second voltage detection signal.

[0013] In some embodiments, at least one voltage detection signal includes a first voltage detection signal and a second voltage detection signal; at least one reference signal includes a first reference signal and a second reference signal; a comparison circuit is configured to generate a first comparison signal based on the first voltage detection signal and the first reference signal; and a comparison circuit is configured to generate a second comparison signal based on the second voltage detection signal and the second reference signal, wherein the comparison circuit is configured to generate a check result signal based on the first comparison signal and the second comparison signal.

[0014] In some embodiments, the comparison circuit includes a first comparator, a second comparator, and a logic unit. The first comparator is used to generate a first comparison signal based on a first voltage detection signal and a first reference signal. The second comparator is used to generate a second comparison signal based on a second voltage detection signal and a second reference signal. The logic unit is used to generate a check result signal based on the first comparison signal and the second comparison signal.

[0015] In some embodiments, the internal circuitry includes an electronic fuse coupled between a first solder pad and a second solder pad.

[0016] In some embodiments, the semiconductor device further includes output logic circuitry for generating a test result signal based on the inspection result signal and the response code.

[0017] Therefore, embodiments of a semiconductor device with contact inspection circuitry are provided. The semiconductor device includes contact inspection circuitry, for example, when testing the semiconductor device using a semiconductor test apparatus connected to at least two solder pads, to inspect multiple contact connections of the at least two solder pads to generate an inspection result signal. The inspection result signal can be used to indicate whether contact connections with the first and second solder pads have failed, and the semiconductor test apparatus can be configured to determine whether to continue testing based on the inspection result signal. This improves the reliability of semiconductor device testing. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings required in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram depicting an example architecture of a semiconductor device with contact inspection circuitry, representing various embodiments of the present invention, wherein the semiconductor device is tested by a semiconductor test apparatus.

[0020] Figure 2 It is used for Figure 1 A block diagram of an embodiment of the contact inspection circuit of the example architecture.

[0021] Figure 3 It is a description used for Figure 1 A block diagram of another embodiment of the contact checking circuit in the example architecture.

[0022] Figure 4 It is a description used for Figure 1 A block diagram of yet another embodiment of the contact checking circuit in the example architecture.

[0023] Figure 5 It is a description used for Figure 1 A block diagram of an embodiment of a semiconductor device in an example architecture.

[0024] Figure 6 It is a description used for Figure 5 A schematic diagram of an embodiment of the output logic unit in the example architecture.

[0025] In the attached figures, the following labels are used:

[0026] 1. Semiconductor device

[0027] 1A Semiconductor Device

[0028] 10. Contact inspection circuit

[0029] 110 Voltage Detection Circuit

[0030] 120 Comparator Circuit

[0031] 111 voltage divider

[0032] 2. Internal Circuitry

[0033] 20 Contact inspection circuit

[0034] 220 Comparator Circuit

[0035] 30 Contact inspection circuit

[0036] 310 Voltage Detection Circuit

[0037] 311 First voltage divider

[0038] 312 Second voltage divider

[0039] 320 Comparator Circuit

[0040] 5. Contact inspection circuit

[0041] 510 decoder

[0042] 520 Electronic Fuse Unit

[0043] 600 Output Logic Units

[0044] 9. Semiconductor testing equipment

[0045] CMD command line

[0046] CMP comparator

[0047] CMP1 First Comparator

[0048] CMP2 Second Comparator

[0049] DQ Data Terminal

[0050] IN response code

[0051] LU Logic Unit

[0052] OUT test result signal

[0053] P1 First solder pad

[0054] P2 Second solder pad

[0055] PS1 First Power Supply

[0056] PS2 Second Power Supply

[0057] PB probe

[0058] R1 resistor

[0059] R11 resistor

[0060] R12 resistor

[0061] R2 resistor

[0062] R21 resistor

[0063] R22 resistor

[0064] S n Voltage detection signal

[0065] S C1 First comparison signal

[0066] S C2 Second comparison signal

[0067] S CR Inspection result signal

[0068] S D1 First voltage detection signal

[0069] S D2 Second voltage detection signal

[0070] V REF Reference signal

[0071] V REF1 First reference signal

[0072] V REF2 Second reference signal Detailed Implementation

[0073] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. It is worth noting that the directional terms used in the following embodiments, such as up, down, left, right, front, or back, are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention. Furthermore, in the following embodiments, the same or similar components will be referred to by the same or similar reference numerals.

[0074] Reference Figure 1 It depicts an example architecture of a semiconductor device 1 having a contact inspection circuit, representing various embodiments of the present invention.

[0075] like Figure 1 As shown, the semiconductor device 1 includes a plurality of solder pads, internal circuitry 2, and contact inspection circuitry 5. The solder pads include a first solder pad P1 and a second solder pad P2. The internal circuitry 2 is coupled to the solder pads. The contact inspection circuitry 5 is at least coupled to the first solder pad P1 and the second solder pad P2, and is used to inspect the contact connection of the first solder pad P1 and the second solder pad P2 to generate an inspection result signal when the semiconductor device 1 is tested using a semiconductor test apparatus 9 connected to the first solder pad P1 and the second solder pad P2 (e.g., using test probes). The inspection result signal is generated based on a comparison between a first test signal and a second test signal received from the first solder pad P1 and the second solder pad P2 and at least one reference signal.

[0076] In a practical scenario, the internal circuit 2 may include circuitry for a specific purpose (e.g., controllers, memory, logic circuits, etc.) and an electronic fuse unit, which includes one or more electronic fuses for selectively altering the function or operation of the circuit. During the testing of the electronic fuse melting operation, signals from the semiconductor test equipment 9 are input to the semiconductor device 1 via multiple probes PB of the semiconductor test equipment 9 that are in contact with multiple pads of the semiconductor device 1. If the probes PB do not make proper contact with the pads, melting cannot be performed correctly. In this scenario, a test result signal can be used to indicate whether the contact connection with the first pad P1 and the second pad P2 is correctly tested.

[0077] In some embodiments, the contact detection circuit 5 may be implemented as including a voltage detection circuit (e.g., Figure 2 110 or Figure 4 310 in the middle) and comparator circuit (e.g., Figure 2 120 in Figure 3 220 or Figure 4 (320 in the text). The voltage detection circuit is coupled to the first pad P1 and the second pad P2, and is used to generate at least one voltage detection signal (e.g., in the context of...). Figure 2 Sn What it represents; Figure 4 S in D1 and S D2 The comparator circuit is coupled to the voltage detection circuit and is used to determine the voltage detection signal and the reference signal (e.g., based on at least one voltage detection signal and at least one reference signal). Figure 2 V in REF What is represented; or Figure 3 , 4 V in REF1 and V REF2 The signal (represented by the device) is used to generate the inspection result signal (e.g., S). CR (represented by). At least one reference signal, which may be obtained, for example, by one or more bandgap voltage circuits of semiconductor device 1, or by an external power supply or voltage source.

[0078] Reference Figure 2 It describes the use of Figure 1 An example embodiment of a contact check circuit with an exemplary architecture. Figure 2 In the circuit, the contact detection circuit 10 includes a voltage detection circuit 110 and a comparison circuit 120.

[0079] In this embodiment, the voltage detection circuit 10 includes a voltage divider 111. The voltage divider 111, coupled between the first pad P1 and the second pad P2, is used to generate a voltage detection signal S. n .

[0080] For example, the comparator circuit 120 includes a comparator CMP, which is used to detect voltage signal S. n and reference signal V REF Generate inspection result signal S CR .

[0081] By Figure 2 In the embodiments depicted, the contact inspection circuit 10 can be configured or designed to indicate whether the contact connection of the probe to the first solder pad P1 and the second solder pad P2 has failed. For example, suppose the semiconductor device 1 is implemented including the first solder pad P1 and the second solder pad P2, which are designed to receive the required positive and negative supply voltages, such as 4 volts and -2 volts DC voltages, respectively. To indicate whether the contact connection is correct or reliable during testing, a voltage divider 111 can be designed by setting the resistance values ​​of resistors R1 and R2, such that when the first solder pad P1 and the second solder pad P2 do indeed receive the required voltage supply signal, the detection signal S... n (For example, the voltage signal level (magnitude) is equal to or greater than the reference signal V.) REF (e.g. V) REF =1.25 volts), plus the test result signal S CRThen, an output is given at, for example, a logic high level, to indicate that the contact connection is correct. Conversely, during testing, if the first pad P1 and the second pad P2 do not make correct contact with their corresponding probes, the detection signal S... n It will be less than the reference signal V REF (e.g. V) REF =1.25 volts), check result signal S CR Then, the output is at the lowest logic level, which indicates that the contact connection has failed.

[0082] To perform contact checks more accurately, the contact check circuit 5 can be configured such that the detection signal (e.g., Figure 2 S in n It is compared with two or more reference signals representing different reference values, rather than with... Figure 2 A reference signal (e.g., V) REF (Compare)

[0083] Reference Figure 3 Its description is used for Figure 1 Another embodiment of the contact checking circuit of the example architecture. Figure 3 In the middle, the contact inspection circuit 20 includes a voltage detection circuit 110 and a comparison circuit 220. Figure 3 Contact inspection circuit 20 and Figure 2 The difference in the contact inspection circuit 10 is that at least one reference signal includes a first reference signal V. REF1 and the second reference signal V REF2 ; and the comparison circuit 220 of the contact detection circuit 20 is configured to detect voltage signal S n and the first reference signal V REF1 Generate the first comparison signal S C1 And according to the voltage detection signal S n and the second reference signal V REF2 Generate the first comparison signal S C2 And according to the first comparison signal S C1 and the first comparison signal S C2 Generate inspection result signal S CR .

[0084] like Figure 3 As shown, the comparator circuit 220 includes a first comparator CMP1, a second comparator CMP2, and a logic unit LU.

[0085] The first comparator CMP1 is used to detect the voltage signal S. n and the first reference signal V REF1 Generate the first comparison signal S C1 For example, the first comparator CMP1 has a function for receiving a voltage detection signal S.n A positive input and a input for receiving the first reference signal V REF1 The inverting input.

[0086] The second comparator CMP2 is used to detect the voltage signal S. n and the second reference signal V REF2 Generate a second comparison signal S C2 For example, the second comparator CMP2 has features for receiving the second reference signal V. REF2 The positive input and the input for receiving voltage detection signal S n The inverting input.

[0087] The logic unit LU, coupled to the first comparator CMP1 and the second comparator CMP2, is used to determine the first comparison signal S. C1 and the second comparison signal S C2 Generate inspection result signal S CR In this embodiment, the logic unit LU includes an AND gate. The AND gate is used to receive a first comparison signal S. C1 and the second comparison signal S C2 And used to output the inspection result signal S CR .

[0088] like Figure 3 In the example shown, comparator circuit 220 can be implemented to determine the voltage detection signal S. n Is it between the first reference signal V? REF1 and the second reference signal V REF2 Between (e.g., V) REF1 ≤S n ≤V REF2 For example, the first reference signal V REF1 and the second reference signal V REF2 They can be set to V respectively. REF –D and V REF The voltage value of +D (e.g., V) REF =1.25V, D=0.25V).

[0089] By Figure 3In the depicted embodiment, the contact inspection circuit 20 can be configured or designed to indicate whether the contact connection of the probe to the first pad P1 and the second pad P2 has failed. For example, suppose the semiconductor device 1 is implemented including the first pad P1 and the second pad P2, which are designed to receive the required positive and negative supply voltages, such as 4 volts and -2 volts DC voltages, respectively. To indicate whether the contact connection is correct or reliable during testing, a voltage divider 111 can be designed by setting the resistance values ​​of resistors R1 and R2, such that when the first pad P1 and the second pad P2 do indeed receive the required voltage supply signal, the detection signal S is detected. n (For example, the voltage signal level (magnitude) is between the first reference signal V) REF1 and the second reference signal V REF2 Between (e.g., V) REF1 ≤S n ≤V REF2 ), plus the inspection result signal S CR Then, an output is given at, for example, a logic high level, to indicate that the contact connection is correct. Conversely, during testing, if the first pad P1 and the second pad P2 do not make correct contact with their corresponding probes, the detection signal S... n It will be less than the first reference signal V REF1 (e.g. V) REF1 =1.0 volt) or greater than the second reference signal V REF2 (e.g. V) REF2 =1.5 volts), check result signal S CR Then, an output is given at a low logic level, indicating a failed contact connection. For example, if the first pad P1 correctly receives a positive supply voltage (e.g., 4 volts) and the second pad P2 does not correctly receive a negative supply voltage (e.g., the corresponding probe is not contacting the second pad P2 or there is incorrect contact), the detection signal S... n (For example, 2 volts, 3 volts, 3.8 volts, or 4 volts) may be greater than the second reference signal V. REF2 (e.g. V) REF2 =1.5 volts). In other embodiments, conversely, if the first pad P1 does not correctly receive a positive supply voltage (e.g., the corresponding probe is not in contact with the first pad P1 or is making incorrect contact), and the second pad P2 correctly receives a negative supply voltage (e.g., -2 volts), the detection signal S... n (For example, -2 volts, -1 volt, 0 volts, or 0.5 volts) may be less than the first reference signal V. REF1 (e.g. V) REF1 =1.0 volts).

[0090] To perform contact checks more accurately, the contact check circuit 5 can be configured to obtain two corresponding voltage detection signals (e.g., using a first test signal received from the first pad P1 and a second test signal received from the second pad P2). Figure 4 S in D1 or S D2 ), instead of from Figure 2 or Figure 3 One of the detection signals (e.g., S) n ).

[0091] Reference Figure 4 Its description is used for Figure 1 Another embodiment of the contact checking circuit of the example architecture. Figure 4 In the circuit, the contact detection circuit 30 includes a voltage detection circuit 310 and a comparison circuit 320. Figure 4 The contact check circuit 30 in the middle and Figure 3 The difference in the contact detection circuit 20 is that at least one voltage detection signal includes a first voltage detection signal S. D1 and the second voltage detection signal S D2 ; and the voltage detection circuit 310 of the contact inspection circuit 30 is configured to generate a first voltage detection signal S based on the first test signal and the first power supply signal. D1 And a second voltage detection signal S is generated based on the second power supply signal and the second test signal. D2 Furthermore, the comparison circuit 320 of the contact inspection circuit 30 is configured to detect the first voltage signal S. D1 and the first reference signal V REF1 To generate the first comparison signal S C1 And according to the second voltage detection signal S D2 and the second reference signal V REF2 To generate the second comparison signal S C2 .

[0092] like Figure 4 As shown, the voltage detection circuit 310 includes, for example, a first voltage divider 311 and a second voltage divider 312. The first voltage divider 311, coupled between the first pad P1 and the first power supply terminal PS1, is used to generate a first voltage detection signal S. D1 The second voltage divider 312, coupled between the second power supply terminal PS2 and the second pad P2, is used to generate the second voltage detection signal S. D2 .

[0093] like Figure 4 As shown, the comparator circuit 320 includes a first comparator CMP1, a second comparator CMP2, and a logic unit LU. Compared to Figure 3Comparator circuit 220 and comparator circuit 320 receive the first voltage detection signal S. D1 and the second voltage detection signal S D2 Instead of receiving a voltage detection signal S n .

[0094] The first comparator CMP1 of the comparator circuit 320 is used to detect the first voltage signal S. D1 and the first reference signal V REF1 To generate the first comparison signal S C1 For example, the first comparator CMP1 has a function for receiving a first voltage detection signal S. D1 The positive input and the input for receiving the first reference signal V REF1 The inverting input.

[0095] The second comparator CMP2 of the comparator circuit 320 is used to detect the second voltage signal S. D2 and the second reference signal V REF2 To generate the first comparison signal S C1 For example, the second comparator CMP2 has features for receiving the second reference signal V. REF2 The positive input and the input for receiving the second voltage detection signal S D2 The inverting input.

[0096] The logic unit LU, coupled to the first comparator CMP1 and the second comparator CMP2, is used to determine the first comparison signal S. C1 and the second comparison signal S C2 To generate the inspection result signal S CR For example, the logic unit LU of comparator circuit 320 is similar to that of comparator circuit 220.

[0097] like Figure 4 For example, the comparator circuit 320 can be implemented to determine the first voltage detection signal S. D1 Is it greater than or equal to the first reference signal V? REF1 and the second reference signal V REF2 Is it greater than or equal to the second voltage detection signal S? D2 (For example: S) D1 ≥V REF1 And V REF2 ≥S D2 For example, the first reference signal V REF1 and the second reference signal V REF2 It can be set to the same voltage value or different voltage values.

[0098] By Figure 4The described method allows the contact inspection circuit 30 to be configured or designed to indicate whether the contact connection of the probe to the first pad P1 and the second pad P2 has failed. For example, suppose the semiconductor device 1 is implemented including the first pad P1 and the second pad P2. The first pad P1 and the second pad P2 are used to receive the required positive and negative supply voltages, such as 4 volts and -2 volts DC voltages, respectively. To indicate whether the contact connection is correct or reliable during testing, voltage dividers 311 and 312 can be designed by setting the resistance values ​​of resistors R11, R12, R21, and R22, such that when the first pad P1 and the second pad P2 do indeed receive a voltage supply signal, a first voltage detection signal S is detected. D1 Greater than or equal to the first reference signal V REF1 Add the second reference signal V REF2 Greater than or equal to the second voltage detection signal S D2 (For example: S) D1 ≥V REF1 And V REF2 ≥S D2 V REF1 ≥V REF2 ), plus the inspection result signal S CR Then, an output is given at, for example, a logic high level, to indicate that the contact connection is correct. Conversely, during testing, if either the first pad P1 or the second pad P2 does not correctly contact the corresponding probe, the first voltage detection signal S... D1 It will be less than the first reference signal V REF1 (For example: S) D1 <V REF1 ), or the second reference signal V REF2 Less than the second voltage detection signal S D2 (For example: V) REF2 D2 ), Inspection result signal S CR Then, an output is given at, for example, a low logic level to indicate that the contact connection is faulty. In this way, the contact check circuit 30 can perform contact checks more accurately.

[0099] In some embodiments, the logic unit LU of the contact detection circuit 20 or 30 may include one or more logic gates, such as AND gate, OR gate, NOT gate, XOR gate, or XNOR gate, or for outputting the detection result signal S. CR Any reasonable combination of the same objectives. For example, the configuration of the first comparator CMP1 in the contact check circuit 20 is modified so that its inverting and non-inverting inputs respectively receive the first reference signal V. REF1 and voltage detection signal S n In order to output the inspection result signal S​CR For the same purpose, the logic unit LU of the contact check circuit 20 can be replaced with another logic circuit to execute the Boolean equation (SC1'+SC2)' using the reverse gate and the mutually exclusive OR gate (NOR). The logic unit LU of the contact check circuit 30 can be implemented in a similar manner. In addition, the logic unit LU can also be modified in other ways. Therefore, the implementation of the present invention is not limited to these embodiments.

[0100] In some embodiments, the semiconductor device 1 may be configured to... Figure 2 , 3 Contact inspection circuit 5 can be implemented using contact inspection circuits 10, 20, or 30 as shown in diagram 4, so that at least the first solder pad P1 and the second solder pad P2 are contact inspected during testing. In response to the test request signal from semiconductor test equipment 9, semiconductor device 1 then outputs an inspection result signal S to semiconductor test equipment 9. CR This can be used as a test result signal, or based on the inspection result signal S. CR And one or more additional results that can be obtained from additional logic tests performed in semiconductor device 1, to output a test result signal.

[0101] Reference Figure 5 Its description is used for Figure 1 Examples of semiconductor device architectures. Figure 5 In the example of semiconductor device 1, semiconductor device 1A includes multiple pads, internal circuitry, and contact inspection circuitry 5.

[0102] The solder pads include a first solder pad P1, a second solder pad P2, a data terminal DQ, and a command terminal CMD. The internal circuitry is coupled to the solder pads.

[0103] The internal circuitry may include a decoder 510 and an electronic fuse unit 520. The decoder 510 is coupled to the data input DQ, the command input CMD, and the electronic fuse unit 520. The electronic fuse unit 520 may include multiple electronic fuses. For example, at least one of the electronic fuses may have its two ends coupled to a first solder pad P1 and a second solder pad P2. Figure 5 As shown, both the first pad P1 and the second pad P2 are coupled to the contact check circuit 5.

[0104] To respond to data signals and command signals received from the data terminal DQ and the command terminal CMD, the decoder 510 can be implemented to execute different modes. For example, a test can be performed before the operation of melting the electronic fuse. The semiconductor test equipment 9 generates data signals, command signals, positive supply voltages, and negative supply voltages for the data terminal DQ, the command terminal CMD, the first pad P1, and the second pad P2, respectively. The data signals represent specific codes or addresses, and the command signals represent test commands used to check whether the semiconductor device 1A is ready for the procedure of melting the electronic fuse. If the semiconductor device 1A is logically ready, the decoder 510 can generate a response code (e.g., 110011001100) to respond to the data signals and command signals.

[0105] On the other hand, such as Figure 2 , Figure 3 or Figure 4 The described contact inspection circuit 5 checks the contact connection between the first solder pad P1 and the second solder pad P2 to generate an inspection result signal S. CR Inspection result signal S CR It is generated based on the comparison between the first test signal received from the first pad P1 and the second test signal received from the second pad P2 and at least one reference signal.

[0106] In this embodiment, the response code generated by the self-decoder 510 and the inspection result signal S generated by the contact inspection circuit 5 are... CR It can be sent back to the semiconductor testing equipment 9.

[0107] In other embodiments, such as Figure 6 As shown, the semiconductor device 1A may further include an output logic unit 600 to output logic based on the check result signal S. CR The response code (e.g., represented as IN) generates the test result signal OUT. For example, output logic unit 600 may include a dedicated anti-mutex OR gate. If the response code IN, for example, "110011001100" in binary, indicates that semiconductor device 1A is logically ready, and the test result signal S... CR (For example, logic 1) indicates that the contact connection is correct, and the test result signal OUT and the response code IN present the same code. If the response code IN indicates that semiconductor device 1A is logically ready, however, the test result signal S... CR (For example, logic 0) indicates an incorrect contact connection, and the test result signal OUT is represented in binary as "001100110011". In other embodiments, the output logic unit 600 may include one or more logic gates, such as AND, OR, NOT, XOR, or XNOR, or any reasonable combination thereof.

[0108] In this manner, the semiconductor test equipment 9 can be configured to terminate the test upon receiving a test result signal OUT, for example, indicating a contact connection failure (e.g., "001100110011"). Thus, as... Figure 2 , Figure 3 or Figure 4 The semiconductor device 1A shown using the contact inspection circuit 5 can be used to prevent the semiconductor test equipment 9 from erroneously performing tests or even burning operations (e.g., for electronic fuses) when the probes are not properly connected to the pads.

[0109] As described above, various embodiments of a semiconductor device with contact inspection circuitry have been provided. The semiconductor device includes contact inspection circuitry that, when tested using a semiconductor test apparatus connected to the semiconductor device, for example, at least two solder pads, checks the contact connection of the at least two solder pads to generate an inspection result signal. The inspection result signal can be used to indicate whether the contact connection between the first and second solder pads has failed, and the semiconductor test apparatus can be configured to determine whether to continue testing based on the inspection result signal. Therefore, the reliability of semiconductor device testing can be improved.

[0110] The above description is merely an embodiment of the present invention and is not intended to limit the patent scope of the present invention.

Claims

1. A semiconductor device having a contact inspection circuit, characterized in that, Include: Multiple solder pads, including a first solder pad and a second solder pad; Internal circuitry, coupled to the solder pads; and A contact inspection circuit, at least coupled to the first pad and the second pad, is used to inspect a plurality of contact connections of the first pad and the second pad when the semiconductor device is being tested to generate an inspection result signal, the inspection result signal being generated based on a comparison between a first test signal received from the first pad and a second test signal received from the second pad and at least one reference signal; The contact inspection circuit includes: A voltage detection circuit, coupled to the first solder pad and the second solder pad, is configured to generate at least one voltage detection signal, wherein the at least one voltage detection signal includes a first voltage detection signal and a second voltage detection signal; and the voltage detection circuit is configured to generate the first voltage detection signal based on a first test signal and a first power supply signal; and the voltage detection circuit is configured to generate the second voltage detection signal based on a second power supply signal and the second test signal; and A comparison circuit, coupled to the voltage detection circuit, is used to generate the inspection result signal based on the at least one voltage detection signal and the at least one reference signal.

2. The semiconductor device according to claim 1, characterized in that, The voltage detection circuit includes a voltage divider coupled between the first pad and the second pad to generate the at least one voltage detection signal.

3. The semiconductor device according to claim 1, characterized in that, The comparison circuit includes a comparator for generating the inspection result signal based on the at least one voltage detection signal and the at least one reference signal.

4. The semiconductor device according to claim 1, characterized in that, The at least one reference signal includes a first reference signal and a second reference signal. The comparison circuit is configured to generate a first comparison signal based on the at least one voltage detection signal and the first reference signal; as well as The comparison circuit is configured to generate a second comparison signal based on the at least one voltage detection signal and the second reference signal; The comparison circuit is configured to generate the inspection result signal based on the first comparison signal and the second comparison signal.

5. The semiconductor device according to claim 4, characterized in that, The comparison circuit includes: A first comparator is configured to generate the first comparison signal based on the at least one voltage detection signal and the first reference signal; A second comparator is configured to generate a second comparison signal based on the at least one voltage detection signal and the second reference signal; and A logic unit, coupled to the first comparator and the second comparator, is used to generate the inspection result signal based on the first comparison signal and the second comparison signal.

6. The semiconductor device according to claim 1, characterized in that, The voltage detection circuit includes: A first voltage divider, coupled between the first pad and the first power supply terminal, is used to generate the first voltage detection signal; and The second voltage divider is coupled between the second power supply terminal and the second pad to generate the second voltage detection signal.

7. The semiconductor device according to claim 1, characterized in that, The at least one reference signal includes a first reference signal and a second reference signal; The comparison circuit is configured to generate a first comparison signal based on the first voltage detection signal and the first reference signal; as well as The comparison circuit is configured to generate a second comparison signal based on the second voltage detection signal and the second reference signal; The comparison circuit is configured to generate the inspection result signal based on the first comparison signal and the second comparison signal.

8. The semiconductor device according to claim 7, characterized in that, The comparison circuit includes: A first comparator is configured to generate the first comparison signal based on the first voltage detection signal and the first reference signal; A second comparator is configured to generate a second comparison signal based on the second voltage detection signal and the second reference signal; and A logic unit is configured to generate the inspection result signal based on the first comparison signal and the second comparison signal.

9. The semiconductor device according to claim 1, characterized in that, The internal circuitry includes an electronic fuse coupled between the first solder pad and the second solder pad.

10. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes an output logic unit for generating a test result signal based on the inspection result signal and the response code.

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