A GPGPU micro-architecture system for fence synchronization

Abstract

The present invention discloses a GPGPU micro-architecture system for fence synchronization, comprising: a thread block sorting module based on fence synchronization, a warp priority sorting module, a warp emission module, a cache module and a cache bypass determination module based on fence synchronization. The thread block sorting module based on fence synchronization dynamically collects the number of warps that hit the fence synchronization point in each thread block, and sorts the warps based on this information, and the cache bypass determination module based on fence synchronization combines the dynamic miss rate of the cache during program execution and the judgment result of whether there is a warp that hits the fence synchronization in each thread block to dynamically determine whether the memory access request task needs to perform a cache bypass operation, thereby reducing the blocking delay of the cache buffer module, and then reducing the fence synchronization overhead, so as to achieve the purpose of improving the performance of the GPGPU.

Description

Technical Field

[0001] The present invention belongs to the technical field of GPGPU architecture, and in particular relates to a GPGPU micro-architecture system for fence synchronization. Background Art

[0002] The performance of general-purpose computing on graphics processing units (GPGPU) in executing fence synchronization operations has a crucial impact on the execution performance of fence-operation-intensive programs. How to improve the execution performance of fence synchronization operations is an issue that cannot be ignored during the research process. Fence synchronization is an important operation of the GPGPU architecture. This operation statically inserts synchronization points in the instruction stream, and all warps in a thread block need to perform synchronization operations at the synchronization points to unify the execution progress and execution status of each warp. The fence synchronization mechanism can ensure that each warp accesses the GPGPU shared storage resources in the correct order, thereby ensuring the functional correctness of multi-threaded execution instruction tasks.

[0003] However, the existing fence synchronization operation itself will introduce certain overhead, because the warp that hits the synchronization point first in a thread block will be in a blocked state and cannot be executed until all warps in the thread block execute to the synchronization point and release the fence. During the whole process, the number of executable warps in the GPGPU streaming multiprocessor will gradually decrease, which will cause the GPGPU computing resources to be idle during some execution cycles, thereby damaging the execution performance of the program. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a GPGPU micro-architecture system for fence synchronization. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The embodiment of the present invention provides a GPGPU micro-architecture system for barrier synchronization, including a thread block sorting module based on barrier synchronization, a warp priority sorting module, a warp emission module, a cache caching module and a cache bypass determination module based on barrier synchronization, wherein:

[0006] The thread block sorting module based on barrier synchronization is used to count the barrier synchronization overhead corresponding to each thread block in the barrier synchronization status record table, and to prioritize all thread blocks in the barrier synchronization status record table according to the counted barrier overhead to obtain a thread block sequence;

[0007] The warp priority sorting module is connected to the barrier synchronization-based thread block sorting module, and is used to receive the thread block sequence, and perform priority sorting of all warps according to the thread block sequence and the most recently executed warp ID to obtain a warp sequence;

[0008] The warp emission module is connected to the warp priority sorting module, and is used to receive the warp sequence and determine whether each warp in the warp sequence meets the memory access instruction task emission execution condition, and if so, output the memory access instruction task corresponding to the warp;

[0009] The Cache module is connected to the warp emission module and is used to receive the memory access instruction task, determine whether the data requested by the memory access instruction task exists in the Cache, and if so, directly return the corresponding data; if not, output the thread block ID corresponding to the memory access instruction task and the dynamic miss rate of the current Cache;

[0010] The Cache bypass determination module based on barrier synchronization is connected to the Cache module, and is used to receive the thread block ID corresponding to the memory access instruction task and the dynamic miss rate of the current Cache; at the same time, output the thread block ID corresponding to the memory access instruction task;

[0011] The thread block sorting module based on barrier synchronization is connected to the cache bypass determination module based on barrier synchronization, and is also used to receive the thread block ID corresponding to the memory access instruction task, and determine the existence of the warp corresponding to the thread block ID in the barrier synchronization status record table according to the thread block ID corresponding to the memory access instruction task to obtain a determination result;

[0012] The cache bypass determination module based on barrier synchronization is connected to the thread block sorting module based on barrier synchronization, and is also used to receive the determination result, and determine whether the memory access instruction task executes cache bypass according to the dynamic miss rate of the current cache and the determination result;

[0013] The cache module is connected to the cache bypass determination module based on fence synchronization, and is also used to receive a cache bypass determination result, and determine whether the cache needs to reserve data storage space for data requested by a memory access instruction task according to the cache bypass determination result.

[0014] In one embodiment of the present invention, the barrier synchronization status record table includes thread block IDs and the number of warps that hit barrier synchronization; wherein the number of warps that hit barrier synchronization is used to characterize the barrier synchronization overhead value corresponding to each thread block ID.

[0015] In one embodiment of the present invention, in the thread block sorting module based on barrier synchronization, all thread blocks in the barrier synchronization status record table are prioritized according to the statistical barrier overhead to obtain a thread block sequence, including:

[0016] Different thread blocks have different fence synchronization overhead values. The thread blocks are prioritized according to the fence synchronization overhead values ​​corresponding to each thread block recorded in the fence synchronization status record table to obtain a thread block sequence; wherein, the thread block with a larger fence synchronization overhead value has a higher corresponding sorting priority.

[0017] In one embodiment of the present invention, in the thread block sorting module based on barrier synchronization, all thread blocks in the barrier synchronization status record table are prioritized according to the statistical barrier overhead to obtain a thread block sequence, including:

[0018] For different thread blocks with the same barrier synchronization overhead value, the thread blocks are prioritized according to the thread block IDs corresponding to the thread blocks recorded in the barrier synchronization status record table to obtain a thread block sequence; wherein, the thread block with a smaller thread block ID has a higher priority.

[0019] In one embodiment of the present invention, in the warp priority sorting module, priority sorting of all warps is performed according to the thread block sequence and the most recently executed warp ID to obtain a warp sequence, including:

[0020] Find the thread block ID corresponding to the most recently executed warp ID in the thread block sequence, take the most recently executed warp ID as the first warp in the thread block ID, and arrange the remaining warps in the thread block ID in order after the first warp;

[0021] The warp with the smallest thread block ID corresponding to the other thread blocks is the first warp, and the remaining warps in the thread block ID are arranged in sequence after the first warp.

[0022] In one embodiment of the present invention, in the cache bypass determination module based on barrier synchronization, judging whether the memory access instruction task executes cache bypass according to the dynamic miss rate of the current cache and the judgment result includes:

[0023] Determine whether the dynamic miss rate of the current cache is greater than a first threshold value. If so, output the cache bypass determination result as executing cache bypass. If not, determine whether the dynamic miss rate of the current cache is less than a second threshold value. If so, output the cache bypass determination result as not executing cache bypass. If not, determine whether the determination result is greater than 0. If so, output the cache bypass determination result as executing cache bypass. If not, output the cache bypass determination result as not executing cache bypass.

[0024] In one embodiment of the present invention, the warp emission module is further used to determine whether the warp corresponding to the memory access instruction task is a barrier synchronization operation, and if so, output the thread block ID corresponding to the warp;

[0025] The barrier synchronization-based thread block sorting module is connected to the warp emission module, and is further used to receive the thread block ID corresponding to the warp, and update the barrier synchronization state record table according to the thread block ID corresponding to the warp.

[0026] In one embodiment of the present invention, in the thread block sorting module based on barrier synchronization, updating the barrier synchronization state record table according to the thread block ID corresponding to the warp includes:

[0027] According to the thread block ID corresponding to the warp, the number of warps that hit the barrier synchronization corresponding to the thread block ID in the barrier synchronization status record table is increased;

[0028] If it is determined that the number of warps that hit the barrier synchronization is the same as the total number of warps included in the thread block ID, the number of warps that hit the barrier synchronization corresponding to the thread block ID in the barrier synchronization status record table is cleared.

[0029] In one embodiment of the present invention, a lower-level storage module is also included; correspondingly,

[0030] The Cache module is also used to output the memory access instruction task;

[0031] The lower-level storage module is connected to the Cache module and the Cache bypass determination module based on fence synchronization, and is used to receive the memory access instruction task and the Cache bypass determination result, and decide whether to output the data corresponding to the memory access instruction task to the Cache module according to the Cache bypass determination result.

[0032] Beneficial effects of the present invention:

[0033] The GPGPU micro-architecture system for barrier synchronization proposed by the present invention is a new strategy for barrier synchronization, specifically: a thread block sorting module based on barrier synchronization dynamically counts the barrier synchronization overhead corresponding to each thread block in the barrier synchronization status record table, and prioritizes all thread blocks in the barrier synchronization status record table according to the statistical barrier overhead to obtain a thread block sequence; a warp priority sorting module prioritizes all warps according to the thread block sequence and the most recently executed warp ID to obtain a warp sequence; a cache bypass determination module based on barrier synchronization determines whether a memory access instruction task executes cache bypass according to the dynamic miss rate of the current cache cache and a determination result, wherein the determination result is that the warp emission module, the cache bypass determination module based on barrier synchronization and the thread block sorting module based on barrier synchronization cooperate to output the existence of the warp corresponding to the thread block ID in the barrier synchronization status record table according to the memory access instruction task corresponding to the warp; and the cache cache module determines whether the cache cache needs to reserve data storage space for the data requested by the memory access instruction task according to the cache bypass determination result. It can be seen that the thread block sorting module based on barrier synchronization of the present invention dynamically collects the number of warps that hit the barrier synchronization point in each thread block, and sorts the warps based on this information, and the cache bypass determination module based on barrier synchronization combines the dynamic miss rate of the cache during program execution with the judgment result of whether there are warps that hit the barrier synchronization in each thread block to dynamically determine whether the memory access request task needs to perform a cache bypass operation, thereby reducing the blocking delay of the cache buffer module, and further reducing the barrier synchronization overhead, thereby achieving the purpose of improving GPGPU performance.

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a structural schematic diagram of a GPGPU micro-architecture system for barrier synchronization provided by an embodiment of the present invention;

[0036] Figure 2 is an example schematic diagram of a barrier synchronization state record table provided by an embodiment of the present invention;

[0037] Figure 3 It is a schematic diagram of the structure of another GPGPU micro-architecture system for barrier synchronization provided by an embodiment of the present invention;

[0038] Figure 4 It is a flowchart of determining whether a memory access instruction task executes cache bypass provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0040] The inventor has found that due to the idle Cache capacity, until there is free space in the Cache to store data, some memory access instruction tasks issued by the thread block that is executing the barrier synchronization operation will always be blocked in the Cache, resulting in an increase in the barrier synchronization overhead. In the entire Cache process, considering the impact of the warp scheduling strategy on barrier synchronization alone cannot achieve good results. Theoretical analysis comprehensively considering the impact of the warp scheduling strategy and the Cache strategy on barrier synchronization can effectively solve the problem, but there is currently a lack of a feasible solution that comprehensively considers the impact of the warp scheduling strategy and the Cache strategy on barrier synchronization.

[0041] For the above analysis, see Figure 1 The embodiment of the present invention provides a GPGPU micro-architecture system for barrier synchronization, including a thread block sorting module based on barrier synchronization, a warp priority sorting module, a warp emission module, a cache module and a cache bypass determination module based on barrier synchronization, wherein:

[0042] The thread block sorting module based on barrier synchronization is used to count the barrier synchronization overhead corresponding to each thread block in the barrier synchronization status record table, and to prioritize all thread blocks in the barrier synchronization status record table according to the counted barrier overhead to obtain a thread block sequence;

[0043] The warp priority sorting module is connected to the thread block sorting module based on the fence synchronization, and is used to receive the thread block sequence and sort the priorities of all warps according to the thread block sequence and the most recently executed warp ID to obtain the warp sequence;

[0044] A warp emission module, connected to the warp priority sorting module, is used to receive a warp sequence and determine whether each warp in the warp sequence meets the memory access instruction task emission execution condition, and if so, output the memory access instruction task corresponding to the warp;

[0045] The cache module is connected to the warp emission module and is used to receive memory access instruction tasks and determine whether the data requested by the memory access instruction tasks exists in the cache. If so, the corresponding data is directly returned. If not, the thread block ID corresponding to the memory access instruction task and the dynamic miss rate of the current cache are output;

[0046] The cache bypass determination module based on fence synchronization is connected to the cache module, and is used to receive the thread block ID corresponding to the memory access instruction task and the dynamic miss rate of the current cache; at the same time, it outputs the thread block ID corresponding to the memory access instruction task;

[0047] The thread block sorting module based on barrier synchronization is connected to the cache bypass determination module based on barrier synchronization, and is also used to receive the thread block ID corresponding to the memory access instruction task, and determine the existence of the warp corresponding to the thread block ID in the barrier synchronization status record table according to the thread block ID corresponding to the memory access instruction task to obtain a determination result;

[0048] The cache bypass determination module based on barrier synchronization is connected to the thread block sorting module based on barrier synchronization, and is also used to receive the determination result, and determine whether the memory access instruction task executes cache bypass according to the dynamic miss rate of the current cache and the determination result;

[0049] The cache module is connected to the cache bypass determination module based on fence synchronization, and is also used to receive the cache bypass determination result, and determine whether the cache needs to reserve data storage space for the data requested by the memory access instruction task according to the cache bypass determination result.

[0050] Next, each module is introduced in detail. Specifically:

[0051] The embodiment of the present invention provides an alternative solution. For a GPGPU system with barrier synchronization, a thread block sorting module based on barrier synchronization dynamically counts the barrier synchronization overhead. Specifically: the thread block sorting module based on barrier synchronization contains a barrier synchronization status record table, which includes a thread block ID and the number of warps that hit barrier synchronization; wherein the number of warps that hit barrier synchronization is used to characterize the barrier synchronization overhead value corresponding to each thread block ID. It can be seen that the barrier synchronization status record table records the number of warps that hit the barrier synchronization point of each thread block in the current cycle, which is used to represent the barrier synchronization overhead value of the thread block. The larger the barrier synchronization overhead value, the greater the barrier synchronization overhead of the thread block.

[0052] Further, all thread blocks in the barrier synchronization status record table are prioritized according to the statistical barrier synchronization overhead values ​​to obtain a thread block sequence. There are two situations here:

[0053] Different thread blocks have different fence synchronization overhead values. The thread blocks are prioritized according to the fence synchronization overhead values ​​corresponding to each thread block recorded in the fence synchronization status record table to obtain a thread block sequence; wherein, the thread block with a larger fence synchronization overhead value has a higher corresponding priority and is closer to the top of the thread block sequence.

[0054] For different thread blocks with the same barrier synchronization overhead value, the thread blocks are prioritized according to the thread block IDs corresponding to the thread blocks recorded in the barrier synchronization status record table to obtain a thread block sequence; wherein, the thread block with a smaller thread block ID has a higher priority.

[0055] As Figure 2 For example, the number of warps hitting the fence synchronization point in thread block 0 is 2, the number of warps hitting the fence synchronization point in thread block 1 is 1, the number of warps hitting the fence synchronization point in thread block 2 is 3, the number of warps hitting the fence synchronization point in thread block 3 is 0, the number of warps hitting the fence synchronization point in thread block 4 is 3, and so on. You can know the number of warps hitting the fence synchronization point corresponding to each thread block ID. Figure 2 It can be seen that the number of warps with fence synchronization points in thread blocks 0 to 4 is 2, 1, 3, 0, and 3 respectively. The order of warps with fence synchronization points from large to small is thread block 2, thread block 4, thread block 0, thread block 1, and thread block 3. Thread block 2 and thread block 4 have the same number of warps with fence synchronization points, so they are ordered from small to large according to thread block IDs as thread block 2 and thread block 4. Finally, the thread block sequence obtained by priority sorting of the thread block sorting module based on fence synchronization is: thread block 2, thread block 4, thread block 0, thread block 1, and thread block 3.

[0056] Furthermore, the embodiment of the present invention provides an alternative solution, for the barrier synchronization GPGPU system, the warp priority sorting module takes the barrier synchronization into consideration, and prioritizes all warps according to the thread block sequence output by the barrier synchronization-based thread block sorting module and the most recently executed warp ID to obtain the warp sequence. Specifically:

[0057] Find the thread block ID corresponding to the most recently executed warp ID in the thread block sequence, take the most recently executed warp ID as the first warp in the thread block ID, and arrange the remaining warps in the thread block ID in sequence after the first warp; other thread blocks take the warp with the smallest thread block ID as the first warp, and arrange the remaining warps in the thread block ID in sequence after the first warp.

[0058] by Figure 2As shown in the figure, for example, if the thread block sequence output by the thread block sorting module based on barrier synchronization is: thread block 2, thread block 4, thread block 0, thread block 1, thread block 3, thread block 2 includes warp8 to warp11, thread block 4 includes warp16 to warp19, thread block 0 includes warp0 to warp3, thread block 1 includes warp4 to warp7, thread block 3 includes warp12 to warp15, the most recently executed warp ID is warp2 and its corresponding thread block ID is thread block 0, then find the thread block 0 corresponding to the most recently executed warp ID in the thread block sequence, and use the most recently executed warp ID as the starting point. The ID is the first warp, and the remaining warps in the thread block 0 are arranged in sequence after the first warp. The final warp sorting result of thread block 0 is: warp2, warp3, warp0, warp1, and the smallest warp corresponding to thread block 2 is warp8 as the first warp, and the remaining warps in the thread block ID are arranged in sequence after the first warp. The final warp sorting result of thread block 2 is: warp8~warp11, the smallest warp corresponding to thread block 4 is warp16 as the first warp, and the remaining warps in the thread block ID are arranged in sequence after the first warp. The final warp sorting result of thread block 4 is: warp16~warp19, and so on. The warp priority sorting of other thread blocks in the thread block sequence is completed to generate the final warp sequence.

[0059] It should be noted here that the priority sorting of thread blocks is higher than the priority sorting of warps. For example, if the thread block sequence is thread block 2, thread block 4, thread block 0, thread block 1, and thread block 3, after the corresponding warp priority sorting, the thread block sequence is still thread block 2, thread block 4, thread block 0, thread block 1, and thread block 3, but the warps corresponding to each thread block in the thread block sequence are prioritized according to the warp sorting strategy of the warp priority sorting module.

[0060] Furthermore, the thread block sorting module based on barrier synchronization in the embodiment of the present invention can also update the barrier synchronization state record table according to the thread block ID corresponding to the warp provided by the subsequent warp emission module. Specifically:

[0061] When the thread block sorting module based on barrier synchronization receives the thread block ID corresponding to the warp, it finds the corresponding entry in the barrier synchronization status record table according to the thread block ID corresponding to the warp, and increases the value of the number of warps that hit the barrier synchronization corresponding to the thread block ID in the entry by one, indicating that a warp that hits the barrier synchronization is added to the thread block.

[0062] When it is determined that the number of warps that hit the barrier synchronization is the same as the total number of warps contained in the thread block ID, the number of warps that hit the barrier synchronization corresponding to the thread block ID in the barrier synchronization status record table is cleared to zero, indicating that the barrier synchronization operation of the thread block is completed.

[0063] Here, after being cleared to zero, it does not mean that the barrier synchronization state record table corresponding to the thread block ID is no longer used, but that the barrier synchronization state record table continues to be repeatedly updated according to the received memory access instruction task corresponding to the warp.

[0064] Furthermore, an embodiment of the present invention provides an optional solution, in which the warp emission module determines whether each warp meets the memory access instruction task emission execution condition according to the warp sequence. Whether the memory access instruction task emission execution condition is met can refer to the prior art and will not be described in detail here. If a warp in the warp sequence does not meet the memory access instruction task emission execution condition, it switches to the next warp for another judgment. If a warp in the warp sequence meets the memory access instruction task emission execution condition, the memory access instruction task corresponding to the warp is output to the subsequent Cache cache module.

[0065] At the same time, the warp emission module can also determine whether the warp corresponding to the memory access instruction task is a fence synchronization operation. If so, that is, the warp hits the fence synchronization task during execution, then the thread block ID corresponding to the warp is output to the thread block sorting module based on fence synchronization, for updating the fence synchronization status record table in the thread block sorting module based on fence synchronization. If not, no operation is performed. Here, the fence synchronization judgment operation can be specifically determined by the hit fence synchronization point of the warp corresponding to the current memory access instruction task.

[0066] Furthermore, an embodiment of the present invention provides an optional solution, whereby the cache module determines whether the data requested by the received memory access instruction task exists in the cache. If so, the corresponding data is directly returned, such as in the required register. If not, the thread block ID corresponding to the memory access instruction task and the dynamic miss rate of the current cache are output to a subsequent cache bypass determination module based on fence synchronization for determining the cache bypass operation.

[0067] At the same time, the cache module can also decide whether the cache needs to reserve data storage space for the data requested by the memory access instruction task according to the cache bypass judgment result provided by the subsequent cache bypass judgment module based on fence synchronization. For example, if the cache bypass judgment result is to execute cache bypass, there is no need to reserve data storage space for the data requested by the memory access instruction task. If the cache bypass judgment result is not to execute cache bypass, data storage space can be reserved for the data requested by the memory access instruction task.

[0068] Furthermore, the embodiment of the present invention provides an alternative solution, which formulates a new strategy for determining whether a memory access instruction task should perform cache bypass. The strategy combines the dynamic miss rate of the current cache buffer module with the result of determining whether each thread block has a warp that hits the fence synchronization to jointly determine whether the memory access instruction task should perform cache bypass. The result of determining whether each thread block has a warp that hits the fence synchronization is obtained by reading the fence synchronization status record table. Please refer to Figure 3 The process of judging whether the memory access instruction task executes cache bypass in the cache bypass determination module based on fence synchronization is as follows:

[0069] Determine whether the dynamic miss rate of the current cache is greater than the first threshold. If so, output the cache bypass judgment result to execute cache bypass. If not, determine whether the dynamic miss rate of the current cache is less than the second threshold. If so, output the cache bypass judgment result to not execute cache bypass. If not, determine whether the judgment result is greater than 0. If so, output the cache bypass judgment result to execute cache bypass. If not, output the cache bypass judgment result to not execute cache bypass.

[0070] For example, the first threshold value is 0.8, the second threshold value is 0.6, or Figure 2As shown in the example, if the dynamic cache miss rate is greater than 0.8, the cache bypass judgment result is determined to execute cache bypass; if the dynamic cache miss rate is less than 0.6, the cache bypass judgment result is determined not to execute cache bypass; if the dynamic cache miss rate is between 0.6 and 0.8, it is further determined whether there is a warp that hits fence synchronization in the thread block, that is, the thread block sorting module based on fence synchronization uses the thread block ID corresponding to the memory access instruction task given by the cache bypass judgment module based on fence synchronization, and counts the number of warps that hit fence synchronization corresponding to the thread block ID as the judgment result and outputs it to the cache bypass judgment module based on fence synchronization; if the judgment result received by the cache bypass judgment module based on fence synchronization is greater than 0, indicating that there is a warp that hits fence synchronization in the thread block, the cache bypass judgment result is determined to execute cache bypass; if the judgment result received by the cache bypass judgment module based on fence synchronization is 0, indicating that there is no warp that hits fence synchronization in the thread block, the cache bypass judgment result is determined not to execute cache bypass.

[0071] Furthermore, the embodiment of the present invention provides an alternative solution, see Figure 4 ,The GPGPU micro-architecture system for fence synchronization also includes a lower-level storage module; correspondingly,

[0072] The cache module is also used to output memory access instruction tasks;

[0073] The lower-level storage module is connected to the Cache module and the Cache bypass determination module based on fence synchronization, and is used to receive the memory access instruction task and the Cache bypass determination result, and decide whether to output the data corresponding to the memory access instruction task to the Cache module according to the Cache bypass determination result. It can be seen that the data requested by the memory access instruction task is found and taken out, and it is decided whether to return the data retrieved by the memory access request task to the Cache module according to the Cache bypass determination result. For example, if the Cache bypass determination result is to execute the Cache bypass, then the data retrieved by the memory access request task does not need to be returned to the Cache module, and the data is stored in the data space reserved by the Cache module. If the Cache bypass determination result is not to execute the Cache bypass, then the data retrieved by the memory access request task can be returned to the Cache module.

[0074] In summary, the GPGPU micro-architecture system for barrier synchronization proposed in the embodiment of the present invention is a new strategy for barrier synchronization, specifically: a thread block sorting module based on barrier synchronization dynamically counts the barrier synchronization overhead corresponding to each thread block in the barrier synchronization status record table, and prioritizes all thread blocks in the barrier synchronization status record table according to the statistical barrier overhead to obtain a thread block sequence; a warp priority sorting module prioritizes all warps according to the thread block sequence and the most recently executed warp ID to obtain a warp sequence; a cache bypass determination module based on barrier synchronization determines whether a memory access instruction task executes cache bypass according to the dynamic miss rate of the current cache cache and the judgment result, wherein the judgment result is that the warp emission module, the cache bypass determination module based on barrier synchronization and the thread block sorting module based on barrier synchronization jointly cooperate to output the existence of the warp corresponding to the thread block ID in the barrier synchronization status record table according to the memory access instruction task corresponding to the warp; and the cache cache module determines whether the cache cache needs to reserve data storage space for the data requested by the memory access instruction task according to the cache bypass judgment result. It can be seen that the thread block sorting module based on barrier synchronization in the embodiment of the present invention dynamically collects the number of warps that hit the barrier synchronization point in each thread block, and sorts the warps based on this information, and the cache bypass determination module based on barrier synchronization combines the dynamic miss rate of the cache during program execution with the judgment result of whether there are warps that hit the barrier synchronization in each thread block to dynamically determine whether the memory access request task needs to perform a cache bypass operation, thereby reducing the blocking delay of the cache buffer module, and further reducing the barrier synchronization overhead, thereby achieving the purpose of improving GPGPU performance.

[0075] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0076] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the specification and its drawings. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude multiple situations. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0077] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A GPGPU micro-architecture system for fence synchronization, characterized in that: It includes a thread block sorting module based on fence synchronization, a warp priority sorting module, a warp emission module, a cache cache module and a cache bypass determination module based on fence synchronization, wherein: The thread block sorting module based on barrier synchronization is used to count the barrier synchronization overhead corresponding to each thread block in the barrier synchronization status record table, and to prioritize all thread blocks in the barrier synchronization status record table according to the counted barrier overhead to obtain a thread block sequence; The warp priority sorting module is connected to the barrier synchronization-based thread block sorting module, and is used to receive the thread block sequence, and perform priority sorting of all warps according to the thread block sequence and the most recently executed warp ID to obtain a warp sequence; The warp emission module is connected to the warp priority sorting module, and is used to receive the warp sequence and determine whether each warp in the warp sequence meets the memory access instruction task emission execution condition, and if so, output the memory access instruction task corresponding to the warp; The Cache module is connected to the warp emission module and is used to receive the memory access instruction task, determine whether the data requested by the memory access instruction task exists in the Cache, and if so, directly return the corresponding data; if not, output the thread block ID corresponding to the memory access instruction task and the dynamic miss rate of the current Cache; The Cache bypass determination module based on barrier synchronization is connected to the Cache module, and is used to receive the thread block ID corresponding to the memory access instruction task and the dynamic miss rate of the current Cache; at the same time, output the thread block ID corresponding to the memory access instruction task; The thread block sorting module based on barrier synchronization is connected to the cache bypass determination module based on barrier synchronization, and is also used to receive the thread block ID corresponding to the memory access instruction task, and determine the existence of the warp corresponding to the thread block ID in the barrier synchronization status record table according to the thread block ID corresponding to the memory access instruction task to obtain a determination result; The cache bypass determination module based on barrier synchronization is connected to the thread block sorting module based on barrier synchronization, and is also used to receive the determination result, and determine whether the memory access instruction task executes cache bypass according to the dynamic miss rate of the current cache and the determination result; The cache module is connected to the cache bypass determination module based on fence synchronization, and is also used to receive a cache bypass determination result, and determine whether the cache needs to reserve data storage space for data requested by a memory access instruction task according to the cache bypass determination result.

2. The GPGPU micro-architecture system for barrier synchronization according to claim 1, characterized in that: The barrier synchronization state record table includes thread block IDs and the number of warps that hit barrier synchronization; wherein the number of warps that hit barrier synchronization is used to represent the barrier synchronization overhead value corresponding to each thread block ID.

3. The GPGPU micro-architecture system for barrier synchronization according to claim 2, characterized in that: In the thread block sorting module based on barrier synchronization, all thread blocks in the barrier synchronization status record table are prioritized according to the statistical barrier overhead to obtain a thread block sequence, including: Different thread blocks have different fence synchronization overhead values. The thread blocks are prioritized according to the fence synchronization overhead values ​​corresponding to each thread block recorded in the fence synchronization status record table to obtain a thread block sequence; wherein, the thread block with a larger fence synchronization overhead value has a higher corresponding sorting priority.

4. The GPGPU micro-architecture system for barrier synchronization according to claim 2, characterized in that: In the thread block sorting module based on barrier synchronization, all thread blocks in the barrier synchronization status record table are prioritized according to the statistical barrier overhead to obtain a thread block sequence, including: For different thread blocks with the same barrier synchronization overhead value, the thread blocks are prioritized according to the thread block IDs corresponding to the thread blocks recorded in the barrier synchronization status record table to obtain a thread block sequence; wherein, the thread block with a smaller thread block ID has a higher priority.

5. The GPGPU micro-architecture system for barrier synchronization according to claim 1, characterized in that: In the warp priority sorting module, priority sorting of all warps is performed according to the thread block sequence and the most recently executed warp ID to obtain a warp sequence, including: Find the thread block ID corresponding to the most recently executed warp ID in the thread block sequence, take the most recently executed warp ID as the first warp in the thread block ID, and arrange the remaining warps in the thread block ID in order after the first warp; The warp with the smallest thread block ID corresponding to the other thread blocks is the first warp, and the remaining warps in the thread block ID are arranged in sequence after the first warp.

6. The GPGPU micro-architecture system for barrier synchronization according to claim 1, characterized in that: In the cache bypass determination module based on barrier synchronization, judging whether the memory access instruction task executes cache bypass according to the dynamic miss rate of the current cache and the judgment result includes: Determine whether the dynamic miss rate of the current cache is greater than a first threshold value. If so, output the cache bypass determination result as executing cache bypass. If not, determine whether the dynamic miss rate of the current cache is less than a second threshold value. If so, output the cache bypass determination result as not executing cache bypass. If not, determine whether the determination result is greater than 0. If so, output the cache bypass determination result as executing cache bypass. If not, output the cache bypass determination result as not executing cache bypass.

7. The GPGPU micro-architecture system for barrier synchronization according to claim 2, characterized in that: The warp emission module is further used to determine whether the warp corresponding to the memory access instruction task is a fence synchronization operation, and if so, output the thread block ID corresponding to the warp; The barrier synchronization-based thread block sorting module is connected to the warp emission module, and is further used to receive the thread block ID corresponding to the warp, and update the barrier synchronization state record table according to the thread block ID corresponding to the warp.

8. The GPGPU micro-architecture system for barrier synchronization according to claim 7, characterized in that: In the thread block sorting module based on barrier synchronization, updating the barrier synchronization state record table according to the thread block ID corresponding to the warp includes: According to the thread block ID corresponding to the warp, the number of warps that hit the barrier synchronization corresponding to the thread block ID in the barrier synchronization status record table is increased; If it is determined that the number of warps that hit the barrier synchronization is the same as the total number of warps included in the thread block ID, the number of warps that hit the barrier synchronization corresponding to the thread block ID in the barrier synchronization status record table is cleared.

9. The GPGPU micro-architecture system for barrier synchronization according to claim 1, characterized in that: Also includes a lower-level storage module; correspondingly, The Cache module is also used to output the memory access instruction task; The lower-level storage module is connected to the Cache module and the Cache bypass determination module based on fence synchronization, and is used to receive the memory access instruction task and the Cache bypass determination result, and decide whether to output the data corresponding to the memory access instruction task to the Cache module according to the Cache bypass determination result.

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