Wafer level chip scale package image generation and stitching system and method

Abstract

The application provides a wafer level chip package image generation and splicing system and method, which comprises an image generation submodule, an image splicing submodule, an image browsing submodule and a configuration control submodule; the image generation submodule acquires a local image of a wafer surface and scans the whole wafer surface in a preset order to obtain a global sequence image of the wafer and position coordinates of the image; the image splicing submodule is connected with the image generation submodule, acquires the global sequence image of the wafer and the position coordinates of the image, registers and fuses adjacent images into a global image, and performs down-sampling on the global image to obtain an image pyramid; the image browsing submodule is connected with the image splicing submodule, acquires the image pyramid, and displays images at corresponding levels in the image pyramid according to user operations; and the configuration control submodule is connected with the image generation submodule, the image splicing submodule and the image browsing submodule, and outputs control instructions for the modules. The application effectively reduces the time required for overall wafer surface image processing and improves industrial production efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image processing, in particular to a wafer level chip package image generation and splicing system and method. BACKGROUND

[0002] The generation and splicing of wafer surface images under wafer level chip packaging provides original image data for subsequent wafer defect detection, and determines the correctness and accuracy of defect detection, which puts high requirements on image generation and splicing algorithms under the requirements of high accuracy and high resolution. The existing generation and splicing technology mainly uses feature point matching and phase correlation method for image registration, and fuses and splices the micro-collected images into one large image or stores them in a pyramid layer by layer.

[0003] In the Chinese patent document with publication number CN114723757A, a high-precision wafer defect detection method and system based on a deep learning algorithm are disclosed, which uses improved SIFT feature point detection and fast nearest neighbor matching to match wafer images, and splices and fuses them into one global image for defect detection. For the problem of insufficient feature points for a specific wafer, and the problems of time-consuming feature point extraction and matching, and the inability to adapt to large resolution images when splicing and fusing into one global image.

[0004] In the Chinese patent document with publication number CN106290395A, a wafer detection device and method based on image processing are disclosed, which uses a moving object table, a microscope and a camera to scan and photograph a wafer, and uses a phase correlation method to obtain adjacent image translation parameters, and then splices the images to obtain a complete wafer image. This technology only uses two translation parameters for splicing, which has the problem of large splicing error, and only uses ordinary phase correlation method, which has the problems of repeated frequency spectrum calculation and large calculation overhead, and the inability to adapt to large resolution images when splicing and fusing into one global image. SUMMARY

[0005] In view of the defects in the prior art, the present application aims to provide a wafer level chip package image generation and splicing system and method.

[0006] According to the wafer level chip package image generation and splicing system provided by the present application, the wafer level chip package image generation and splicing system comprises:

[0007] The image generation submodule acquires local images of the wafer surface, and scans the entire wafer surface in a predetermined order to obtain sequence images of the entire wafer and position coordinates of the images.

[0008] The image splicing submodule is connected to the image generation submodule, acquires the sequence images of the entire wafer and the position coordinates of the images, registers and fuses adjacent images into a global image, and down-samples the global image to obtain an image pyramid.

[0009] image browsing submodule: connected with the image splicing submodule, obtaining the image pyramid, and displaying the image in the corresponding level of the image pyramid according to the user operation;

[0010] configuration control submodule: connected with the image generating submodule, the image splicing submodule and the image browsing submodule, outputting control instructions for each module.

[0011] According to the wafer level chip package image generation and splicing method provided by the application, the following steps are included:

[0012] Step S1: fixing the wafer on the object table, configuring the experimental parameters through the configuration control submodule, and then issuing the initialization instruction;

[0013] Step S2: the image generating submodule obtains the experimental parameter configuration and initializes the experimental data;

[0014] Step S3: the image splicing submodule obtains the experimental parameter configuration and initializes the experimental data;

[0015] Step S4: the configuration control submodule outputs the "start experiment" instruction to the image generating submodule and the image splicing submodule;

[0016] Step S5: the image generating submodule obtains the "start experiment" instruction and starts collecting the wafer surface image;

[0017] Step S6: the image splicing submodule obtains the "start experiment" instruction, splices the collected image, and generates the image pyramid;

[0018] Step S7: the image browsing submodule displays the image in the corresponding level of the image pyramid according to the user operation.

[0019] Preferably, the experimental parameters include wafer parameters, image generation parameters and image splicing parameters.

[0020] Preferably, the step S2 includes:

[0021] Step S2.1: the image generating submodule obtains the wafer parameters and the image generation parameters;

[0022] Step S2.2: the image generating submodule controls the object table to position the initial starting point according to the wafer parameters and the image generation parameters, and initializes the scanning control instruction parameters.

[0023] Preferably, the step S3 includes:

[0024] Step S3.1: the image splicing submodule obtains the wafer parameters and the image splicing parameters;

[0025] Step S3.2: The image stitching submodule initializes and sets the image registration, image fusion, pyramid tile generation, and storage parameters according to the wafer parameters and image stitching parameters.

[0026] Preferably, step S4 includes:

[0027] Step S4.1: The registration control submodule issues a "start experiment" command;

[0028] Step S4.2: The registration control submodule receives the scanning position and stitched image index fed back by the image generation submodule and the image stitching submodule, and displays the progress of image generation and stitching.

[0029] Preferably, step S5 includes:

[0030] Step S5.1: The image generation submodule receives the "Start Experiment" command, controls the camera to acquire wafer images at the scanning start position, and supplies them to the image stitching submodule;

[0031] Step S5.2: The image generation submodule scans the wafer at a set scanning speed. When it reaches the set scanning interval position, it controls the light field and camera to acquire a local image of the wafer at that position and supplies the coordinate information of that position to the image stitching submodule. At the same time, it feeds back the scanning coordinate information to the registration control submodule.

[0032] Step S5.3: The image generation submodule returns to the beginning of the current row and moves to the beginning of the next row according to the scanning interval, repeating step S5.2 until all wafer rows have been scanned.

[0033] Preferably, step S6 includes:

[0034] Step S6.1: The image stitching submodule obtains the sequence images and corresponding scan coordinate information provided by the image generation submodule;

[0035] Step S6.2: The image stitching submodule uses the phase correlation method to perform checkerboard registration of each pair of images in the sequence, and obtains the translation parameters and peak response of each image with the four neighboring images above, below, left, and right.

[0036] Step S6.3: The image stitching submodule performs global registration optimization based on minimum spanning tree according to the peak response between the two-dimensionally arranged sequence images, and obtains the global coordinates of each sequence image in this way;

[0037] Step S6.4: The image stitching submodule generates and stores the bottom layer tiles of the pyramid based on the global coordinates of each sequence of images.

[0038] Step S6.5: The image stitching sub-module performs pyramid upper layer tile generation storage on the pyramid bottom layer tile down-sampling.

[0039] Preferably, the step S6.2 comprises:

[0040] Step S6.2.1: Fourier transform is performed on the first row first column image by using the FPGA to calculate the spectrum thereof, and the spectrum is saved in the FPGA global memory for reuse in subsequent steps;

[0041] Step S6.2.2: Fourier transform is performed on the first row second column image by using the FPGA to calculate the spectrum thereof, and the spectrum is saved in the FPGA global memory, and the cross power spectrum is calculated with the spectrum of the first row first column image, and then inverse Fourier transform is performed to obtain a two-dimensional impulse function graph, and the translation parameters and peak value response of the left and right images are obtained according to the impulse peak value coordinates;

[0042] Step S6.2.3: The translation parameters and peak value response between the images in the first row are obtained, and the spectrum of the images in the row is cached in the global memory;

[0043] Step S6.2.4: Fourier transform is performed on the second row first column image by using the FPGA to calculate the spectrum thereof, and the cross power spectrum is calculated with the spectrum of the first row first column image, and then inverse Fourier transform is performed to obtain the translation parameters and peak value response of the upper and lower images, and the spectrum of the second row first column image is used to replace the spectrum of the first row first column image;

[0044] Step S6.2.5: Fourier transform is performed on the second row second column image by using the FPGA to calculate the spectrum thereof, and the cross power spectrum is calculated with the spectrum of the second row first column image, and then inverse Fourier transform is performed to obtain the translation parameters and peak value response of the left and right images, and the spectrum of the second row second column image is used to replace the spectrum of the first row second column image;

[0045] Step S6.2.6: The operation of the second row image is completed according to step S6.2.5, and the operation of all the row images is completed according to step S6.2.4 and step S6.2.5, and the translation parameters and peak value response of each image and the four adjacent images are obtained;

[0046] The step S6.3 comprises:

[0047] Step S6.3.1: A directed graph is generated, in which each sequence image is taken as a point, and there is an edge between the upper and lower or left and right adjacent images;

[0048] Step S6.3.2: For each edge, obtain the image two two registration translation parameters and the corresponding scanning coordinate information of the image, if the difference between the two exceeds a certain threshold, it is considered that the registration is wrong, and 0 is taken as the weight of the edge, otherwise the opposite of the peak response is taken as the weight of the edge;

[0049] Step S6.3.3: The minimum spanning tree algorithm is used in the undirected graph to obtain its minimum spanning tree, that is, the path with the minimum error from the starting graph to any graph is obtained;

[0050] Step S6.3.4: The global coordinates of all sequence images are calculated according to the minimum error path.

[0051] Preferably, the step S6.5 comprises:

[0052] Step S6.5.1: In the bottom tile generation process, when a tile row that can be down-sampled is generated, start down-sampling the bottom layer tile to generate the upper layer tile;

[0053] Step S6.5.2: The bottom BR row generation is completed, the number of consecutive 1s from right to left in the BR binary representation is calculated, and is set as maxL;

[0054] Step S6.5.3: If maxL is 0, there is no row that can be down-sampled, and the step S6.5.2 is directly returned to wait for the next bottom row generation; otherwise, the current layer L is set as 0, and the current operation row R is set as BR;

[0055] Step S6.5.4: Two rows of tiles of L layer R row and R-1 row are obtained, and are down-sampled and combined to generate one row of tiles of L+1 layer R / 2 row;

[0056] Step S6.5.5: L is set as L+1, and R is set as R / 2, if L is less than maxL, the step S6.5.4 is repeated to continue generating higher layer tile rows, otherwise the step S6.5.2 is repeated to wait for the subsequent bottom tile row, until all bottom tile rows are generated, and if there is a row deficiency at the end, the row is filled and generated according to the row deficiency.

[0057] Compared with the prior art, the present application has the following beneficial effects:

[0058] 1. The present application reduces the time required for overall wafer surface image processing and improves industrial production efficiency through hardware acceleration, intermediate spectrum cache multiplexing, and image generation, registration and tile generation process pipelining;

[0059] 2. The present application obtains a wafer super-resolution surface global image by adopting scanning and photographing wafer local images, and solves the problem of small local imaging range of a single microscope;

[0060] 3、The application solves the problem of too much memory occupied by wafer sequence images by using a sliding window to process wafer sequence images in the memory, and solves the problem of too long time consumption of sequence image phase correlation method registration by using a hardware acceleration and spectrum cache multiplexing implementation mode.

[0061] 4、The application solves the problem of super-resolution image storage and browsing by storing wafer surface images of different resolutions in a pyramid layering manner and storing in each layer in a tile manner.

[0062] 5、The application improves the efficiency of tile generation by generating tiles in the order of tile rows that can be down-sampled, and utilizes the locality in the tile generation process.

[0063] 6、The application realizes the configuration and coordination of the wafer image generation and splicing process by the registration control sub-module through configurable wafer parameters, image generation and splicing parameters.

[0064] Other beneficial effects of the application will be described in the specific embodiments through the introduction of specific technical features and technical solutions, and those skilled in the art should be able to understand the beneficial technical effects brought by the technical features and technical solutions through the introduction of the technical features and technical solutions. BRIEF DESCRIPTION OF DRAWINGS

[0065] Other features, objects and advantages of the application will become more apparent through reading the detailed description of the non-limiting embodiments with reference to the following drawings:

[0066] Figure 1 It is a whole module block diagram of the image generation and splicing system of the application;

[0067] Figure 2 It is a module function diagram of the image generation and splicing system of the application;

[0068] Figure 3 It is a data flow diagram of the phase correlation method algorithm of the application;

[0069] Figure 4 It is a hardware implementation data flow diagram of the phase correlation method of the application;

[0070] Figure 5 It is a chessboard registration and optimization flowchart of the application;

[0071] Figure 6 It is a top layer tile generation flowchart of the application. DETAILED DESCRIPTION

[0072] The application will be described in detail below with specific embodiments. The following examples will help those skilled in the art to further understand the application, but do not limit the application in any form. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the application. These are within the scope of protection of the application.

[0073] The application discloses a wafer-level chip package image generation and splicing system, which refers to Figure 1 and Figure 2 as shown, mainly includes configuration control sub-module, image generation sub-module, image splicing sub-module, image browsing sub-module.

[0074] Configuration control sub-module: connected with image generation sub-module, image splicing sub-module and image browsing sub-module, outputs control instructions to each module, responsible for overall parameter configuration and image generation splicing process control, main functions include: wafer parameter configuration, image generation parameter configuration, image splicing parameter configuration, process control instruction. Among them, wafer parameter configuration includes wafer diameter and edge width, grain size and interval, grain layout row and column number, etc., image generation parameter configuration includes light field and illumination, scanning starting point position, scanning sequence, scanning field of view repetition rate, scanning speed, exposure time, etc., image splicing parameter configuration includes splicing registration method, image overlap rate, tile size, storage image format, storage location, etc., process control instruction includes initialization instruction, image generation and splicing start and pause instruction, etc. When image generation and splicing initialization, each configuration parameter of configuration control sub-module is sent to corresponding sub-module for initialization setting, and start instruction is issued.

[0075] Image generation sub-module: obtains local image of wafer surface, and scans entire wafer surface according to preset sequence to obtain global sequence image of wafer and position coordinates of image. Specifically includes light field and microscope, electrically controlled object table and industrial camera. Wafer is placed on the object table, high-performance light field provides bright field and dark field illumination, fully presents various defects of wafer, and the wafer surface image is collected by area array industrial camera through high-power microscope microscopic imaging. The above surface image is only a local image of wafer surface, in order to obtain global image, the electrically controlled object table moves according to the preset scanning sequence under the control of the module, and the sequence image covering the entire wafer is gradually collected. In the splicing process, the image generation sub-module controls the movement of the object table according to the scanning configuration, controls the camera exposure in time to obtain the local image of the wafer surface, so as to gradually scan the entire wafer surface, and the local image of the wafer is used together with the corresponding object table coordinates for image splicing sub-module registration and splicing.

[0076] Image stitching sub-module: connected with the image generation sub-module, obtains the sequence image of the wafer globally and the position coordinates of the image, registers and fuses adjacent images into a global image, and down-samples the global image to obtain an image pyramid. Among them, the stitching sub-module receives the sequence image collected by the image acquisition module and the stage coordinates of each image, completes the registration of adjacent images through a field programmable logic gate array (FPGA), and performs image fusion to divide and generate bottom tile images, and then down-sample to generate upper tile image pyramid, and each level of tile image in the pyramid is stored in the form of a file under the pyramid level directory. In the stitching process, the image stitching sub-module obtains the sequence image of the wafer surface scanned by the image generation sub-module and the corresponding stage coordinates, thereby dividing, generating and storing tile image pyramids covering the entire wafer, which can be displayed and browsed by the image browsing sub-module, and can support subsequent wafer image defect detection.

[0077] Image browsing sub-module: connected with the image stitching sub-module, obtains the image pyramid, and displays the images of the corresponding level in the image pyramid according to user operation. The user browses the current wafer surface image, and initially only the top tile is displayed, and the required same layer or other layer tiles are loaded as needed during translation and scaling operation. When translating, the tile image corresponding to the current layer is obtained according to the coordinates after translation and is loaded and displayed; when scaling, the current global coordinates need to be updated according to the scaling multiple, and the adjacent layer tiles are obtained using the new coordinates, such as zooming in the image, the current global coordinates are reduced, and the lower layer tiles are obtained and displayed. During browsing, the browsing sub-module obtains user translation and scaling interaction input, thereby updating the coordinates to obtain the required pyramid tile image for loading and display.

[0078] Taking the single image generation and stitching process as an example, the experimental process is described in steps:

[0079] The present application provides a wafer level chip package image generation and stitching method, comprising:

[0080] Step S1: fix the wafer on the stage, configure the experimental parameters through the configuration control sub-module, and then issue the initialization instruction;

[0081] Step S2: the image generation sub-module obtains the experimental parameter configuration and initializes the experimental data;

[0082] Step S3: the image stitching sub-module obtains the experimental parameter configuration and initializes the experimental data;

[0083] Step S4: the configuration control sub-module outputs the "start experiment" instruction to the image generation sub-module and the image stitching sub-module;

[0084] Step S5: the image generation sub-module obtains the "start experiment" instruction and starts collecting the wafer surface image;

[0085] Step S6: the image stitching sub-module acquires a "start experiment" instruction, stitches the collected images, and generates an image pyramid;

[0086] Step S7: the image generation sub-module scans and feeds back the configuration control sub-module, waits for the image stitching sub-module to complete the stitching process, issues an "end experiment" instruction, and the image generation and image stitching sub-modules end the experiment after receiving the instruction;

[0087] Step S8: the image browsing sub-module displays the images of the corresponding levels in the image pyramid according to user operations.

[0088] The following describes each step in detail.

[0089] The step S1 includes the following steps:

[0090] Step S1.1: the configuration control sub-module edits configuration wafer parameters, including wafer diameter and edge width, die size and interval, die layout row and column number, etc.

[0091] Step S1.2: the configuration control sub-module edits configuration image generation parameters, including light field and illumination, scanning starting point position, scanning sequence, scanning field of view repetition rate, scanning speed, exposure time, etc.

[0092] Step S1.3: the configuration control sub-module edits configuration image stitching parameters, including stitching registration method, image overlap rate, tile size, storage image format, storage location, etc.

[0093] Step S1.4: the configuration control sub-module issues an initialization instruction.

[0094] The step S2 includes the following steps:

[0095] Step S2.1: the image generation sub-module acquires wafer parameters and image generation parameters;

[0096] Step S2.2: the image generation sub-module controls the stage positioning to the starting point, initializes the scanning control instruction parameters, etc. according to the wafer parameters and image generation parameters.

[0097] The step S3 includes the following steps:

[0098] Step S3.1: the image stitching sub-module acquires wafer parameters and image stitching parameters;

[0099] Step S3.2: the image stitching sub-module initializes the image registration, image fusion, tile generation, and storage parameters, etc. according to the wafer parameters and image stitching parameters.

[0100] The step S4 includes the following steps:

[0101] Step S4.1: The registration control submodule issues a "start experiment instruction";

[0102] Step S4.2: The registration control submodule accepts the scanning position and the stitching image index fed back by the image generation and image stitching module, and displays the progress of image generation and stitching.

[0103] The step S5 comprises:

[0104] Step S5.1: The image generation submodule receives the "start experiment" instruction, controls the camera to collect wafer images at the scanning starting position point, and supplies the image stitching submodule;

[0105] Step S5.2: The image generation submodule controls the wafer stage to scan a wafer row, controls the wafer stage to scan a row in the X direction at a set scanning speed, controls the light field and the camera to collect a wafer local image at each time when reaching a set scanning interval position, supplies the image stitching submodule with the local image and the position coordinate information, and feeds back the scanning coordinate information to the registration control submodule.

[0106] Step S5.3: The image generation submodule controls the wafer stage to return to the current row head position, controls the wafer stage to move to the next row head position in the Y direction according to the scanning interval, and repeats step S5.2 until all wafer rows are scanned.

[0107] The step S6 comprises:

[0108] Step S6.1: The image stitching submodule acquires the sequence images and the corresponding scanning coordinate information provided by the image generation submodule;

[0109] Step S6.2: The image stitching submodule uses the phase correlation method to perform chessboard registration of two images for each sequence image, and obtains the translation parameters and the peak value response of each image and the four adjacent images;

[0110] Step S6.3: The image stitching submodule performs global registration optimization based on the minimum spanning tree according to the peak value responses between the two-dimensionally arranged sequence images, and obtains the global coordinates of each sequence image;

[0111] Step S6.4: The image stitching submodule performs pyramid bottom tile generation and storage according to the obtained global coordinates of each sequence image.

[0112] Step S6.5: The image stitching submodule performs pyramid upper tile generation and storage by downsampling the pyramid bottom tile.

[0113] Referring to Figures 3-5 The step S6.2 comprises:

[0114] Step S6.2.1: Get the first row first column (hereinafter referred to as R1C1) image, and calculate its frequency spectrum by using the FPGA to perform Fourier transform. The frequency spectrum is stored in the global memory of the FPGA for reuse in subsequent steps.

[0115] Step S6.2.2: Get the first row second column (hereinafter referred to as R1C2) image, and calculate its frequency spectrum by using the FPGA to perform Fourier transform. At the same time, calculate the cross power spectrum with the frequency spectrum of the R1C1 image, and then perform inverse Fourier transform to obtain a two-dimensional impulse function image. According to the coordinates of the impulse peak, obtain the translation parameters and peak response of the left and right images.

[0116] Step S6.2.3: Obtain the translation parameters and peak response between the images in the first row, and simultaneously cache the frequency spectrum of the images in the global memory.

[0117] Step S6.2.4: Get the second row first column (R2C1) image, and calculate its frequency spectrum by using the FPGA to perform Fourier transform. Calculate the cross power spectrum with the frequency spectrum of the R1C1 image, and perform inverse Fourier transform to obtain the translation parameters and peak response of the upper and lower images. Replace the R1C1 frequency spectrum with the frequency spectrum of the second row first column.

[0118] Step S6.2.5: Get the second row second column (R2C2) image, and calculate its frequency spectrum by using the FPGA to perform Fourier transform. Similarly, obtain the translation parameters and peak response of the left and right images by operating with R2C1, and obtain the translation parameters and peak response of the upper and lower images by operating with R1C2. Replace the R1C2 frequency spectrum with the frequency spectrum of the R2C2 image.

[0119] Step S6.2.6: According to the operation of the second row image completed in step S6.2.5, complete the operation of all row images according to steps S6.2.4 and S6.2.5, to obtain the translation parameters and peak response of each image with the four neighboring images in the upper, lower, left and right directions.

[0120] The step S6.3 includes:

[0121] Step S6.3.1: Take each sequence image as a point, and there is an edge between the images adjacent in the upper and lower directions or the left and right directions, to generate an undirected graph.

[0122] Step S6.3.2: For each edge, obtain the image-to-image registration translation parameters and the corresponding scanning coordinate information of the images. If the difference between the two exceeds a certain threshold, it is considered that the registration is wrong, and 0 is taken as the weight of the edge. Otherwise, the inverse of the peak response is taken as the weight of the edge.

[0123] Step S6.3.3: Obtain the minimum spanning tree of the undirected graph by using the minimum spanning tree algorithm, that is, obtain the path with the minimum error from the starting image to any image.

[0124] Step S6.3.4: Calculate the global coordinates of all sequence images according to the error minimum path accumulation.

[0125] The step S6.4 includes the following steps:

[0126] Step S6.4.1: The image stitching sub-module obtains the global coordinates of all sequence images, and can obtain the global coordinates of each bottom layer tile according to the configured tile size;

[0127] Step S6.4.2: For the global coordinates and tile size of the first row and first column bottom layer tile, the sequence images required to generate the bottom layer tile are calculated and obtained in the sliding window buffer;

[0128] Step S6.4.3: According to the image size of the global coordinates of the sequence images required to generate the bottom layer tile, the overlapping of each sequence image in the area of the bottom layer tile is calculated, and the average value is taken according to the number of overlaps to generate the bottom layer tile and store it;

[0129] Step S6.4.4: Repeat the above two steps regularly until the generation of the first row of bottom layer tiles is completed;

[0130] Step S6.4.5: For the second row and first column bottom layer tile, it is generated according to step 6.4.3, and if the required sequence images exceed the sliding window size, the corresponding sequence images of the previous row are obtained and the window is moved to remove them;

[0131] Step S6.4.6: Repeat the above steps regularly to complete the generation of the bottom layer tiles of the second row and all subsequent rows.

[0132] Referring to Figure 6 The step S6.5 includes the following steps:

[0133] Step S6.5.1: During the generation of the bottom layer tile, when a tile row that can be operated by downsampling is generated, start downsampling the bottom layer (considered as the zero layer) tile to generate the upper layer tile;

[0134] Step S6.5.2: When the first row and the second row of bottom layer tiles are generated, four bottom layer tiles in the first two columns of the first row and the first two columns of the second row are obtained to generate the first layer and the first column tile of the pyramid by downsampling and merging, and four bottom layer tiles in the third four columns of the first row and the third four columns of the second row are obtained to generate the first layer and the second column tile of the pyramid by downsampling and merging;

[0135] Step S6.5.3: Generate all first layer and first row tiles according to the above steps;

[0136] Step S6.5.4: When the third and fourth rows of tiles in the bottom layer are generated, the first row of tiles in the first layer is generated in the same way;

[0137] Step S6.5.5: At this time, the first and second rows of tiles in the first layer are generated, and the second row of tiles in the first layer is generated by down-sampling and merging;

[0138] Step S6.5.6: The generation and storage of the rows of tiles in the upper layers of the pyramid are completed according to the above rules during the continuous generation of the rows of tiles in the bottom layer. If there is a shortage of rows at the end, the rows are generated by filling in the missing rows.

[0139] It is worth noting that the above step of the row of tiles that can be operated by down-sampling can be better explained by the number of consecutive 1s from right to left in the binary representation of the current generated bottom tile row number (starting from 0):

[0140] Step S6.5.1: During the generation of the bottom layer tiles, when a row of tiles that can be operated by down-sampling is generated, start down-sampling the bottom layer (considered as the zero layer) tiles to generate the upper layer tiles;

[0141] Step S6.5.2: The BR (starting from 0) row in the bottom layer is generated, and the number of consecutive 1s from right to left in the binary representation of BR is calculated, which is set as maxL;

[0142] Step S6.5.3: If maxL is 0, there is no row that can be down-sampled, and directly return to step S6.5.2 to wait for the next bottom layer row to be generated. Otherwise, set the current layer L as 0, and the current operation row R as BR;

[0143] Step S6.5.4: Get the L layer R row and R-1 row of tiles, and generate an L+1 layer R / 2 row of tiles by down-sampling and merging;

[0144] Step S6.5.5: Set L as L+1 and R as R / 2. If L is less than maxL, repeat step S6.5.4 to continue generating higher layer tile rows. Otherwise, repeat step S6.5.2 to wait for the subsequent bottom layer tile row to be generated. Until all bottom layer tile rows are generated, if there is a shortage of rows at the end, the rows are generated by filling in the missing rows.

[0145] The step S8 includes the following steps:

[0146] Step S8.1: Open the image browsing submodule interface, and display the top layer tile of the pyramid in the viewport;

[0147] Step S8.2: Perform zoom-in operation, update the zoom-in coordinate system range, map the original viewport coordinates to the new coordinate system, and load the tiles in the corresponding position of the lower layer to display the browsing;

[0148] Step S8.3: performing a translation operation, updating the coordinates in the current coordinate system range, loading the current layer tile display browsing newly entered into the viewport;

[0149] Step S8.4: performing a zoom-out operation, updating the zoom-out coordinate system range, mapping the original viewport coordinates into the new coordinate system, loading the tile display browsing of the corresponding position of the upper layer;

[0150] Step S8.5: closing the image browsing sub-module interface, ending the browsing.

[0151] The specific embodiments of the present application are described above. It needs to be understood that the present application is not limited to the specific embodiments described above, and various changes or modifications can be made by those skilled in the art within the scope of the claims, which does not affect the essential content of the present application. In the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A wafer-level chip packaging image generation and stitching system, characterized in that, include: Image generation submodule: Acquires local images of the wafer surface and scans the entire wafer surface in a preset order to obtain a global sequence of images of the wafer and the position coordinates of the images; Image stitching submodule: Connected to the image generation submodule, it obtains the global sequence image of the wafer and the position coordinates of the image, registers adjacent images and merges them into a global image, and downsamples the global image to obtain an image pyramid; Image browsing submodule: Connects to the image stitching submodule, obtains the image pyramid, and displays the images of the corresponding levels in the image pyramid according to user operations; Configuration control submodule: Connects to the image generation submodule, image stitching submodule, and image browsing submodule, and outputs control commands to each module; Also includes: Step S6.1: The image stitching submodule obtains the sequence images and corresponding scan coordinate information provided by the image generation submodule; Step S6.2: The image stitching submodule uses the phase correlation method to perform checkerboard registration of each pair of images in the sequence, and obtains the translation parameters and peak response of each image with the four neighboring images above, below, left, and right. Step S6.3: The image stitching submodule performs global registration optimization based on minimum spanning tree according to the peak response between the two-dimensionally arranged sequence images, and obtains the global coordinates of each sequence image in this way; Step S6.4: The image stitching submodule generates and stores the bottom layer tiles of the pyramid based on the global coordinates of each sequence of images. Step S6.5: The image stitching submodule downsamples the bottom layer tiles of the pyramid to generate and store the upper layer tiles of the pyramid; Step S6.2 includes: Step S6.2.1: Obtain the image of the first row and first column, perform Fourier transform on the FPGA to calculate its spectrum, and save it in the FPGA global memory for reuse in subsequent steps; Step S6.2.2: Obtain the image in the first row and second column, use the FPGA to perform Fourier transform to calculate its spectrum and store it in the FPGA global memory. At the same time, calculate the cross power spectrum with the spectrum of the image in the first row and first column, and then perform inverse Fourier transform to obtain a two-dimensional pulse function graph. Based on the pulse peak coordinates, obtain the translation parameters and peak response of the left and right images. Step S6.2.3: Obtain the translation parameters and peak response between each pair of images in the first row, and cache the spectrograms of the images in the row in global memory; Step S6.2.4: Obtain the spectrum of the second row and first column image by performing Fourier transform using FPGA. Calculate the cross power spectrum with the spectrum of the first row and first column image. Similarly, perform inverse Fourier transform to obtain the translation parameters and peak response of the two images. Replace the spectrum of the first row and first column image with the spectrum of the second row and first column image. Step S6.2.5: Obtain the second row and second column image and use the FPGA to perform Fourier transform to calculate its spectrum. Similarly, the left and right image translation parameters and peak response are obtained by operating with the first column of the second row, and the top and bottom image translation parameters and peak response are obtained by operating with the second column of the first row. Replace the spectrum of the first row and second column with the spectrum of the second row and second column image. Step S6.2.6: Complete the second row image operation according to step S6.2.5, and complete the operation of all rows of images according to steps S6.2.4 and S6.2.5 to obtain the translation parameters and peak response of each image with the four neighboring images above, below, left, and right. Step S6.3 includes: Step S6.3.1: Using each image sequence as a point, and with an edge between adjacent images (either vertically or horizontally), generate an undirected graph; Step S6.3.2: For each edge, obtain the pairwise registration translation parameters of the image and the corresponding scan coordinate information of the image. If the difference between the two exceeds a certain threshold, it is considered that the registration is wrong, and 0 is taken as the weight of the edge; otherwise, the negative number of the peak response is taken as the weight of the edge. Step S6.3.3: Use the minimum spanning tree algorithm to obtain the minimum spanning tree of the undirected graph, that is, obtain the path with the minimum error from the initial graph to any graph; Step S6.3.4: Calculate the global coordinates of all sequence images based on the path with the minimum error.

2. A method for generating and stitching wafer-level chip packaging images, based on the wafer-level chip packaging image generation and stitching system of claim 1, characterized in that, include: Step S1: Fix the wafer on the stage, configure the experimental parameters through the configuration control submodule, and then issue the initialization command; Step S2: The image generation submodule acquires the experimental parameter configuration and initializes the experimental data; Step S3: The image stitching submodule acquires the experimental parameter configuration and initializes the experimental data; Step S4: The configuration control submodule outputs a "Start Experiment" command to the image generation submodule and the image stitching submodule; Step S5: The image generation submodule receives the "Start Experiment" command and begins to acquire images of the wafer surface; Step S6: The image stitching submodule receives the "Start Experiment" command, stitches the acquired images, and generates an image pyramid; Step S7: The image browsing submodule displays images at the corresponding levels of the image pyramid according to user operations.

3. The wafer-level chip packaging image generation and stitching method according to claim 2, characterized in that, The experimental parameters include wafer parameters, image generation parameters, and image stitching parameters.

4. The wafer-level chip packaging image generation and stitching method according to claim 3, characterized in that, Step S2 includes: Step S2.1: The image generation submodule acquires wafer parameters and image generation parameters; Step S2.2: The image generation submodule controls the stage to position the initial starting point and initializes the scanning control command parameters according to the wafer parameters and image generation parameters.

5. The wafer-level chip packaging image generation and stitching method according to claim 3, characterized in that, Step S3 includes: Step S3.1: The image stitching submodule acquires wafer parameters and image stitching parameters; Step S3.2: The image stitching submodule initializes and sets the image registration, image fusion, pyramid tile generation, and storage parameters according to the wafer parameters and image stitching parameters.

6. The wafer-level chip packaging image generation and stitching method according to claim 3, characterized in that, Step S4 includes: Step S4.1: The configuration control submodule issues the "Start Experiment" command; Step S4.2: The configuration control submodule receives the scanning position and stitching image index fed back by the image generation submodule and the image stitching submodule, and displays the progress of image generation and stitching.

7. The wafer-level chip packaging image generation and stitching method according to claim 2, characterized in that, Step S5 includes: Step S5.1: The image generation submodule receives the "Start Experiment" command, controls the camera to acquire wafer images at the scanning start position, and supplies them to the image stitching submodule; Step S5.2: The image generation submodule scans the wafer line by line at a set scanning speed. When it reaches the set scanning interval position, it controls the light field and camera to acquire a local image of the wafer at that position and supplies the coordinate information of that position to the image stitching submodule. At the same time, it feeds back the scanning coordinate information to the configuration control submodule. Step S5.3: The image generation submodule returns to the beginning of the current row and moves to the beginning of the next row according to the scanning interval, repeating step S5.2 until all wafer rows have been scanned.

8. The wafer-level chip packaging image generation and stitching method according to claim 2, characterized in that, Step S6.5 includes: Step S6.5.1: During the generation of the bottom layer tiles, when a row of tiles that can be downsampled is generated, the generation of the top layer tiles is started by downsampling the bottom layer tiles of the pyramid. Step S6.5.2: After the underlying BR row is generated, calculate the number of consecutive 1s from right to left in the binary representation of BR, and set it as maxL; Step S6.5.3: If maxL is 0, there are no rows that can be downsampled, and the process returns directly to step S6.5.2 to wait for the generation of the next bottom-level row; otherwise, set the current layer L to 0 and the current row to be operated on R to BR. Step S6.5.4: Obtain two rows of tiles, R row and R-1 row of layer L, downsample and merge them to generate one row of tiles, R / 2 row of layer L+1; Step S6.5.5: Set L to L+1 and R to R / 2. If L is less than maxL, repeat step S6.5.4 to continue generating higher-level tile rows. Otherwise, repeat step S6.5.2 to wait for the subsequent bottom-level tile rows to be obtained until all bottom-level tile rows are generated. If there are insufficient rows at the end, fill in the missing rows to generate the remaining rows.

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