Display substrate and display device

Abstract

The application provides a display substrate and a display device. The display substrate comprises: a substrate, comprising a display area and a peripheral area on at least one side of the display area; a pixel array, located in the display area, comprising a plurality of pixel units; and a scan driving module, located in a driving circuit area in the peripheral area, comprising a plurality of shift register units, a plurality of signal lines are arranged in one of the shift register units, and the plurality of signal lines extend along a first direction; the ratio of the width of the plurality of signal lines in a second direction to the width W2 of the one shift register unit in the second direction is W1 / W2, the length of at least one of the pixel units along the first direction is a pixel pitch value; and the product of W1 / W2 and the pixel pitch value is greater than 18 um and less than 40 um. The application can realize a narrow frame in the case of high resolution.

Description

[0001] This application is a divisional application of Chinese patent application No. 202111465296.0, filed on December 3, 2021. Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0003] In related technologies, in OLED (Organic Light Emitting Diode) display products, the shift register unit is coupled to the gate scan control signal terminal or the light emission control scan signal terminal in the pixel unit to provide the gate scan drive signal or the light emission control scan signal. As pixel resolution gradually increases and pixel pitch gradually decreases, the corresponding layout space for the shift register unit also gradually decreases. Consequently, related display products cannot achieve both high resolution and narrow bezels. Summary of the Invention

[0004] The main objective of this invention is to provide a display substrate and a display device that solves the problem that existing display devices cannot achieve both high resolution and narrow bezels.

[0005] To achieve the above objectives, embodiments of the present invention provide a display substrate, comprising:

[0006] The substrate includes a display area and a peripheral area located on at least one side of the display area;

[0007] A pixel array, located in the display area, includes multiple pixel units; and,

[0008] The scanning drive module, located in the drive circuit area of ​​the peripheral area, includes multiple shift register units. In one of the multiple shift register units, multiple signal lines are provided, and the multiple signal lines extend along a first direction.

[0009] The ratio of the width W1 of the plurality of signal lines in the second direction to the width W2 of the shift register unit in the second direction is W1 / W2; the length of at least one pixel unit along the first direction is the pixel pitch value; the first direction intersects the second direction;

[0010] The product of W1 / W2 and the pixel pitch value is greater than 18µm but less than 40µm.

[0011] Optionally, the plurality of signal lines includes all the signal lines in the one shift register unit.

[0012] Optionally, the plurality of signal lines includes all signal lines that overlap with the orthographic projection of the shift register unit onto the substrate.

[0013] Optionally, W1 / W2 is greater than 0.4 but less than 0.7.

[0014] Optionally, the product of W1 / W2 and the pixel pitch value is greater than 27µm but less than 36µm.

[0015] Optionally, the product of W1 / W2 and the pixel pitch value is greater than 18µm and less than or equal to 27µm.

[0016] Optionally, the product of W1 / W2 and the pixel pitch value is greater than or equal to 36µm but less than 40µm.

[0017] Optionally, the product of W1 / W2 and the pixel pitch value is greater than 29µm but less than 35µm.

[0018] Optionally, the display substrate includes a first conductive layer, an insulating layer, and a second conductive layer, wherein the insulating layer is disposed between the first conductive layer and the second conductive layer;

[0019] At least one of the plurality of signal lines is disposed on the first conductive layer, and at least one of the plurality of signal lines is disposed on the second conductive layer.

[0020] Optionally, the shift register unit includes at least one transistor disposed in the driving circuit region, wherein the first electrode of the transistor, the second electrode of the transistor, and the plurality of signal lines are located on the same layer.

[0021] Optionally, the shift register unit includes at least one transistor disposed in the driving circuit region, wherein the first electrode of the transistor and the second electrode of the transistor are located on the same layer, and the plurality of signal lines are located on different layers from the first electrode of the transistor.

[0022] Optionally, the shift register unit includes at least one signal line disposed in the driving circuit region, the at least one signal line being configured to provide a DC power supply signal;

[0023] The ratio W3 / W2 of the width W3 of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.15.

[0024] Optionally, the shift register unit includes at least one signal line disposed in the driving circuit region, the at least one signal line being configured to provide a DC power supply signal;

[0025] The ratio W3 / W2 of the width W3 of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.3.

[0026] Optionally, the shift register unit includes at least one signal line disposed in the driving circuit region, the at least one signal line being configured to provide a clock signal;

[0027] The ratio W4 / W2 of the width W4 of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.015.

[0028] Optionally, the shift register unit includes at least one signal line disposed in the driving circuit region, the at least one signal line being configured to provide a clock signal;

[0029] The ratio W4 / W2 of the width W4 of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.03.

[0030] Optionally, the shift register unit includes at least two transistors disposed in the driving circuit region;

[0031] The active layers of the at least two transistors are formed of continuous semiconductor layers, and the orthographic projection of one of the multiple signal lines on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate.

[0032] Optionally, the shift register unit includes a fourth transistor, a fifth transistor, an eighth transistor, and a thirteenth transistor; the second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the eighth transistor, the first electrode of the fifth transistor, and the first electrode of the thirteenth transistor are coupled to each other;

[0033] The active layers of the fourth transistor, the fifth transistor, the thirteenth transistor, and the eighth transistor are formed from a continuous first semiconductor layer.

[0034] The orthographic projection of the active layer of the fourth transistor on the substrate, the orthographic projection of the active layer of the fifth transistor on the substrate, the orthographic projection of the active layer of the eighth transistor on the substrate, and the orthographic projection of part of the active layer of the thirteenth transistor on the substrate together form an E-shaped pattern or an F-shaped pattern.

[0035] The orthographic projection of the active layer of the fourth transistor onto the substrate and the orthographic projection of the active layer of the fifth transistor onto the substrate together form an L-shaped pattern.

[0036] Optionally, the shift register unit includes multiple signal lines, including a first voltage line;

[0037] The orthographic projection of the first voltage line on the substrate partially overlaps with the orthographic projection of the first semiconductor layer on the substrate.

[0038] Optionally, the shift register unit includes multiple signal lines, including a second clock signal line;

[0039] The orthogonal projection of the second clock signal line on the substrate partially overlaps with the orthogonal projection of the first semiconductor layer on the substrate.

[0040] Optionally, the channel of the fourth transistor extends along a second direction, the channel of the fifth transistor extends along a first direction, the channel of the thirteenth transistor extends along a second direction, and the channel of the eighth transistor extends along a first direction.

[0041] Optionally, the shift register unit includes a second transistor and a third transistor; the second electrode of the second transistor is coupled to the second electrode of the third transistor;

[0042] The active layers of the second transistor and the third transistor are formed by a continuous fourth semiconductor layer. The orthographic projection of the active layer of the second transistor onto the substrate and the orthographic projection of the active layer of the third transistor onto the substrate together form an I-shaped pattern.

[0043] Optionally, the channel of the second transistor extends along the first direction, and the channel of the third transistor extends along the first direction.

[0044] Optionally, the shift register unit includes a second transistor, a third transistor, and an eleventh transistor; the second electrode of the second transistor is coupled to the second electrode of the third transistor; the first electrode of the eleventh transistor is coupled to the second electrode of the third transistor.

[0045] The active layers of the second transistor, the third transistor, and the eleventh transistor are formed by a continuous fifth semiconductor layer. The orthographic projections of the active layers of the second transistor, the third transistor, and the eleventh transistor on the substrate together form a T-shaped pattern.

[0046] Optionally, the plurality of signal lines includes a third start signal line;

[0047] The orthographic projection of the fifth semiconductor layer on the substrate partially overlaps with the orthographic projection of the third starting signal line on the substrate.

[0048] Optionally, the channels of the second transistor and the third transistor both extend along a first direction, and the channel of the eleventh transistor extends along a second direction.

[0049] Optionally, the shift register unit includes a sixth transistor, a seventh transistor, and an eighth transistor;

[0050] The second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor, and the first electrode of the eighth transistor is coupled to the second electrode of the seventh transistor;

[0051] The orthographic projection of the active layer of the eighth transistor onto the substrate, the orthographic projection of the active layer of the seventh transistor onto the substrate, and the orthographic projection of the active layer of the sixth transistor onto the substrate together form an n-type pattern.

[0052] Optionally, the shift register unit further includes a fourth transistor, a fifth transistor, an eighth transistor, and a thirteenth transistor; the second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the eighth transistor, the first electrode of the fifth transistor, and the first electrode of the thirteenth transistor are coupled to each other;

[0053] The active layers of the fourth transistor, the fifth transistor, the thirteenth transistor, the eighth transistor, the seventh transistor, and the sixth transistor are formed from a continuous second semiconductor layer.

[0054] Optionally, the shift register unit includes multiple signal lines, including a first voltage line;

[0055] The orthographic projection of the first voltage line on the substrate partially overlaps with the orthographic projection of the second semiconductor layer on the substrate.

[0056] Optionally, the channel of the fourth transistor extends along a second direction, the channel of the fifth transistor extends along a first direction, the channel of the thirteenth transistor extends along a second direction, the channel of the eighth transistor extends along a first direction, the channel of the seventh transistor extends along a first direction, and the channel of the sixth transistor extends along a second direction.

[0057] Optionally, the shift register unit includes a first transistor, a fifth transistor, an eighth transistor, a twelfth transistor, and a thirteenth transistor;

[0058] The second electrode of the eighth transistor, the first electrode of the fifth transistor, and the first electrode of the thirteenth transistor are coupled to each other; the first electrode of the twelfth transistor is coupled to the second electrode of the first transistor, and the second electrode of the twelfth transistor is coupled to the second electrode of the thirteenth transistor.

[0059] The orthographic projections of the active layer of the first transistor, the active layer of the fifth transistor, the active layer of the eighth transistor, the active layer of the twelfth transistor, and the active layer of the thirteenth transistor on the substrate together form an H-shaped pattern.

[0060] Optionally, the shift register unit further includes a fourth transistor, a seventh transistor, and a sixth transistor;

[0061] The second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor; the first electrode of the sixth transistor is coupled to the first electrode of the seventh transistor; the first electrode of the fourth transistor is coupled to the first electrode of the sixth transistor.

[0062] The active layers of the first transistor, the fourth transistor, the fifth transistor, the thirteenth transistor, the twelfth transistor, the eighth transistor, the seventh transistor, and the sixth transistor are formed from a continuous third semiconductor layer.

[0063] Optionally, the shift register unit includes multiple signal lines, including a first voltage line;

[0064] The orthographic projection of the first voltage line on the substrate partially overlaps with the orthographic projection of the third semiconductor layer on the substrate.

[0065] Optionally, the channel of the fourth transistor extends along a second direction, the channel of the fifth transistor extends along a first direction, the channel of the thirteenth transistor extends along a second direction, the channels of the twelfth transistor and the first transistor extend along a first direction, the channels of the eighth transistor and the seventh transistor extend along a first direction, and the channel of the sixth transistor extends along a second direction.

[0066] Optionally, the shift register unit includes at least two transistors disposed in the driving circuit region; the active layer of the at least two transistors is formed of a continuous semiconductor layer;

[0067] The semiconductor layer includes at least a portion of semiconductor patterns that are π-shaped.

[0068] Optionally, the shift register unit includes multiple signal lines, multiple transistors, and multiple capacitors;

[0069] The plurality of signal lines include: a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, and a third clock signal line; the plurality of transistors include: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; the plurality of capacitors include: a first capacitor, a second capacitor, and a third capacitor.

[0070] The gate of the first transistor is coupled to the third clock signal line, the first electrode of the first transistor is coupled to the input terminal, and the second electrode of the first transistor is coupled to the gate of the second transistor.

[0071] The first electrode of the second transistor is coupled to the third clock signal line, and the second electrode of the second transistor is coupled to the second electrode of the third transistor;

[0072] The gate of the third transistor is coupled to the third clock signal line, and the first electrode of the third transistor is coupled to the second voltage line;

[0073] The gate of the fourth transistor is coupled to the gate of the tenth transistor, the first electrode of the fourth transistor is coupled to the first clock signal line, and the second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor.

[0074] The gate of the fifth transistor is coupled to the second electrode of the third transistor, and the first electrode of the fifth transistor is coupled to the first voltage line;

[0075] The gate of the sixth transistor is coupled to the second electrode of the eleventh transistor, the first electrode of the sixth transistor is coupled to the first clock signal line, and the second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor.

[0076] The gate of the seventh transistor is coupled to the first clock signal line, and the second electrode of the seventh transistor is coupled to the gate of the ninth transistor.

[0077] The gate of the eighth transistor is coupled to the gate of the thirteenth transistor, the first electrode of the eighth transistor is coupled to the gate of the ninth transistor, and the second electrode of the eighth transistor is coupled to the first voltage line.

[0078] The first electrode of the ninth transistor is coupled to the first voltage line, and the second electrode of the ninth transistor is coupled to the drive signal output terminal;

[0079] The first electrode of the tenth transistor is coupled to the drive signal output terminal, and the second electrode of the tenth transistor is coupled to the second voltage line;

[0080] The gate of the eleventh transistor is coupled to the second voltage line, and the first electrode of the eleventh transistor is coupled to the gate of the fifth transistor.

[0081] The gate of the twelfth transistor is coupled to the second voltage line, the first electrode of the twelfth transistor is coupled to the second electrode of the first transistor, and the second electrode of the twelfth transistor is electrically connected to the gate of the tenth transistor.

[0082] The gate of the thirteenth transistor is coupled to the second clock signal line, the first electrode of the thirteenth transistor is coupled to the first voltage line, and the second electrode of the thirteenth transistor is coupled to the gate of the second transistor.

[0083] The first plate of the first capacitor is coupled to the gate of the sixth transistor, and the second plate of the first capacitor is coupled to the second electrode of the sixth transistor;

[0084] The first plate of the second capacitor is coupled to the gate of the ninth transistor, and the second plate of the second capacitor is coupled to the first voltage line;

[0085] The first plate of the third capacitor is coupled to the gate of the tenth transistor, and the second plate of the third capacitor is coupled to the second electrode of the fourth transistor.

[0086] Optionally, one of the plurality of shift register units includes multiple signal lines, multiple transistors, and multiple capacitors;

[0087] The plurality of signal lines include a first voltage line, a second voltage line, a first clock signal line, and a second clock signal line; the plurality of transistors include: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; the plurality of capacitors include: a first capacitor, a second capacitor, and a third capacitor;

[0088] The gate of the first transistor is coupled to the first clock signal line, the first electrode of the first transistor is coupled to the input terminal, and the second electrode of the first transistor is coupled to the gate of the second transistor.

[0089] The first electrode of the second transistor is coupled to the first clock signal line, and the second electrode of the second transistor is coupled to the second electrode of the third transistor;

[0090] The gate of the third transistor is coupled to the first clock signal line, and the first electrode of the third transistor is coupled to the second voltage line;

[0091] The gate of the fourth transistor is coupled to the second clock signal line, the first electrode of the fourth transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the fourth transistor is coupled to the gate of the second transistor.

[0092] The gate of the fifth transistor is coupled to the second electrode of the third transistor, and the first electrode of the fifth transistor is coupled to the first voltage line;

[0093] The gate of the sixth transistor is coupled to the second electrode of the eleventh transistor, the first electrode of the sixth transistor is coupled to the second clock signal line, and the second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor.

[0094] The gate of the seventh transistor is coupled to the second clock signal line, and the second electrode of the seventh transistor is coupled to the gate of the ninth transistor.

[0095] The gate of the eighth transistor is coupled to the gate of the second transistor, the first electrode of the eighth transistor is coupled to the first voltage line, and the second electrode of the eighth transistor is coupled to the gate of the ninth transistor.

[0096] The first electrode of the ninth transistor is coupled to the first voltage line, and the second electrode of the ninth transistor is coupled to the drive signal output terminal;

[0097] The gate of the tenth transistor is coupled to the second electrode of the twelfth transistor, the first electrode of the tenth transistor is coupled to the second voltage line, and the second electrode of the tenth transistor is coupled to the drive signal output terminal;

[0098] The gate of the eleventh transistor is coupled to the second voltage line, and the first electrode of the eleventh transistor is coupled to the second electrode of the second transistor.

[0099] The gate of the twelfth transistor is coupled to the second voltage line, and the first electrode of the twelfth transistor is coupled to the gate of the second transistor.

[0100] The first plate of the first capacitor is coupled to the gate of the sixth transistor, and the second plate of the first capacitor is coupled to the second electrode of the sixth transistor;

[0101] The first plate of the second capacitor is coupled to the gate of the ninth transistor, and the second plate of the second capacitor is coupled to the first voltage line;

[0102] The first plate of the third capacitor is coupled to the gate of the tenth transistor, and the second plate of the third capacitor is coupled to the second clock signal line.

[0103] The present invention also provides a display device, including the display substrate described above.

[0104] The display substrate and display device described in the embodiments of the present invention can achieve narrow bezels at high resolution. Attached Figure Description

[0105] Figure 1 This is a circuit diagram of at least one embodiment of a shift register unit;

[0106] Figure 2A For corresponding Figure 1 A layout schematic diagram of at least one embodiment of the shift register unit shown;

[0107] Figure 2B yes Figure 2A Layout diagram of the active layer in the diagram;

[0108] Figure 2C yes Figure 2A Layout diagram of the first gate metal layer in the middle;

[0109] Figure 2D yes Figure 2A Layout diagram of the second gate metal layer;

[0110] Figure 2E yes Figure 2A Layout diagram of the first source / drain metal layer in the image;

[0111] Figure 2F yes Figure 2A Layout diagram of the second source / drain metal layer in the image;

[0112] Figure 2G Is Figure 2A A schematic diagram with pixel unit P1 added to the existing structure;

[0113] Figure 3A For corresponding Figure 1 A layout schematic diagram of at least one embodiment of the shift register unit shown;

[0114] Figure 3B yes Figure 3A Layout diagram of the active layer in the diagram;

[0115] Figure 3C yes Figure 3ALayout diagram of the first gate metal layer in the middle;

[0116] Figure 3D yes Figure 3A Layout diagram of the second gate metal layer;

[0117] Figure 3E yes Figure 3A Layout diagram of the first source / drain metal layer in the image;

[0118] Figure 3F yes Figure 3A Layout diagram of the second source / drain metal layer in the image;

[0119] Figure 3G Is Figure 3A A schematic diagram with pixel unit P1 added to the existing structure;

[0120] Figure 4A For corresponding Figure 1 A layout schematic diagram of at least one embodiment of the shift register unit shown;

[0121] Figure 4B yes Figure 4A Layout diagram of the active layer in the diagram;

[0122] Figure 4C yes Figure 4A Layout diagram of the first gate metal layer in the middle;

[0123] Figure 4D yes Figure 4A Layout diagram of the second gate metal layer;

[0124] Figure 4E yes Figure 4A Layout diagram of the first source / drain metal layer in the image;

[0125] Figure 4F yes Figure 4A Layout diagram of the second source / drain metal layer in the image;

[0126] Figure 4G Is Figure 4A A schematic diagram with pixel unit P1 added to the existing structure;

[0127] Figure 5A For corresponding Figure 1 A layout schematic diagram of at least one embodiment of the shift register unit shown;

[0128] Figure 5B yes Figure 5A Layout diagram of the active layer in the diagram;

[0129] Figure 5C yes Figure 5A Layout diagram of the first gate metal layer in the middle;

[0130] Figure 5D yes Figure 5A Layout diagram of the second gate metal layer;

[0131] Figure 5E yes Figure 5A Layout diagram of the first source / drain metal layer in the image;

[0132] Figure 5F yes Figure 5A Layout diagram of the second source / drain metal layer in the image;

[0133] Figure 5G Is Figure 5A A schematic diagram with pixel unit P1 added to the existing structure;

[0134] Figure 6A For corresponding Figure 1 A layout schematic diagram of at least one embodiment of the shift register unit shown;

[0135] Figure 6B yes Figure 6A Layout diagram of the active layer in the diagram;

[0136] Figure 6C yes Figure 6A Layout diagram of the first gate metal layer in the middle;

[0137] Figure 6D yes Figure 6A Layout diagram of the second gate metal layer;

[0138] Figure 6E yes Figure 6A Layout diagram of the first source / drain metal layer in the image;

[0139] Figure 6F yes Figure 6A Layout diagram of the second source / drain metal layer in the image;

[0140] Figure 6G Is Figure 6A A schematic diagram with pixel unit P1 added to the existing structure;

[0141] Figure 7A For corresponding Figure 1 A layout schematic diagram of at least one embodiment of the shift register unit shown;

[0142] Figure 7B yes Figure 7A Layout diagram of the active layer in the diagram;

[0143] Figure 7C yes Figure 7A Layout diagram of the first gate metal layer in the middle;

[0144] Figure 7D yes Figure 7A Layout diagram of the second gate metal layer;

[0145] Figure 7E yes Figure 7A Layout diagram of the first source / drain metal layer in the image;

[0146] Figure 7F yes Figure 7A Layout diagram of the second source / drain metal layer in the image;

[0147] Figure 7G Is Figure 7A A schematic diagram with pixel unit P1 added to the existing structure;

[0148] Figure 8A This is a schematic diagram of an I-shaped pattern formed by the orthographic projection of the active layers of at least two transistors included in the shift register unit onto the substrate.

[0149] Figure 8B This is a schematic diagram of an L-shaped pattern formed by the orthographic projection of the active layers of at least two transistors included in the shift register unit onto the substrate.

[0150] Figure 8C This is a schematic diagram of a T-shaped pattern formed by the orthographic projection of the active layers of at least two transistors included in the shift register unit onto the substrate.

[0151] Figure 8D This is a schematic diagram of an F-shaped pattern formed by the orthographic projection of the active layers of at least two transistors included in the shift register unit onto the substrate.

[0152] Figure 8E This is a schematic diagram of an E-shaped pattern formed by the orthographic projection of the active layers of at least two transistors included in the shift register unit onto the substrate.

[0153] Figure 8F This is a schematic diagram of an n-type pattern formed by the orthographic projection of the active layers of at least two transistors included in the shift register unit onto the substrate.

[0154] Figure 8G This is a schematic diagram of the orthographic projection of the active layers of at least two transistors included in the shift register unit onto the substrate to form a π-shaped pattern.

[0155] Figure 8H This is a schematic diagram of an H-shaped pattern formed by the orthographic projection of the active layers of at least two transistors included in the shift register unit onto the substrate.

[0156] Figure 9 This is a circuit diagram of at least one embodiment of a shift register unit. Detailed Implementation

[0157] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0158] In all embodiments of this invention, the transistors used can be bipolar junction transistors (BJTs), thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. In these embodiments, to distinguish between the two terminals of the transistor other than the control terminal, one terminal is referred to as the first terminal, and the other as the second terminal.

[0159] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0160] The display substrate described in this embodiment of the invention includes:

[0161] The substrate includes a display area and a peripheral area located on at least one side of the display area;

[0162] A pixel array, located in the display area, includes multiple pixel units; and,

[0163] The scanning drive module, located in the drive circuit area of ​​the peripheral area, includes multiple shift register units. In one of the multiple shift register units, multiple signal lines are provided, and the multiple signal lines extend along a first direction.

[0164] The ratio of the width W1 of the plurality of signal lines in the second direction to the width W2 of the shift register unit in the second direction is W1 / W2; the length of at least one pixel unit along the first direction is the pixel pitch value; the first direction intersects the second direction;

[0165] The product of W1 / W2 and the pixel pitch value is greater than 18µm but less than 40µm.

[0166] In related technologies, in OLED (Organic Light Emitting Diode) display products, the shift register unit is coupled to the gate scan control signal terminal or the light emission control scan signal terminal in the pixel unit to provide a gate scan drive signal or a light emission control scan signal. As pixel resolution gradually increases and pixel pitch gradually decreases, the corresponding layout space for the shift register unit also gradually decreases. To achieve a narrow bezel design at the highest possible resolution, this invention provides a display substrate where the shift register unit is located in the driving circuit area of ​​the peripheral region. The product of the ratio of the bus width in the second direction of the signal line in one of the multiple shift register units to the width of the shift register unit in the second direction and the pixel pitch value is greater than 18µm and less than 40µm, thereby achieving a narrow bezel.

[0167] In at least one embodiment of the present invention, the product of W1 / W2 and the pixel pitch value can be greater than 19um and less than 40um, greater than 20um and less than 40um, greater than 21um and less than 40um, greater than 22um and less than 40um, greater than 23um and less than 40um, greater than 24um and less than 40um, greater than 25um and less than 40um, greater than 26um and less than 40um, greater than 27um and less than 40um, greater than 28um and less than 40um, greater than 29um and less than 40um, greater than 30um and less than 40um, greater than 31um and less than 40um, greater than 32um and less than 40um, greater than 33um and less than 40um, greater than

[0168] 34um and less than 40um, greater than 35um and less than 40um, greater than 36um and less than 40um, greater than

[0169] 37um and less than 40um, greater than 38um and less than 40um, greater than 39um and less than 40um, greater than

[0170] 18um and less than 39um, greater than 19um and less than 39um, greater than 20um and less than 39um, greater than

[0171] 21um and less than 39um, greater than 22um and less than 39um, greater than 23um and less than 39um, greater than

[0172] 24um and less than 39um, greater than 25um and less than 39um, greater than 26um and less than 39um, greater than

[0173] 27um and less than 39um, greater than 28um and less than 39um, greater than 29um and less than 39um, greater than

[0174] 30um and less than 39um, greater than 31um and less than 39um, greater than 32um and less than 39um, greater than

[0175] 33um and less than 39um, greater than 34um and less than 39um, greater than 35um and less than 39um, greater than

[0176] 36um and less than 39um, greater than 37um and less than 39um, greater than 38um and less than 39um, greater than

[0177] 18um and less than 38um, greater than 19um and less than 38um, greater than 20um and less than 38um, greater than

[0178] 21um and less than 38um, greater than 22um and less than 38um, greater than 23um and less than 38um, greater than

[0179] 24um and less than 38um, greater than 25um and less than 38um, greater than 26um and less than 38um, greater than

[0180] 27um and less than 38um, greater than 28um and less than 38um, greater than 29um and less than 38um, greater than

[0181] 30um and less than 38um, greater than 31um and less than 38um, greater than 32um and less than 38um, greater than

[0182] 33um and less than 38um, greater than 34um and less than 38um, greater than 35um and less than 38um, greater than

[0183] 36um and less than 38um, greater than 37um and less than 38um, greater than 18um and less than 37um, greater than

[0184] 19um and less than 37um, greater than 20um and less than 37um, greater than 21um and less than 37um, greater than

[0185] 22um and less than 37um, greater than 23um and less than 37um, greater than 24um and less than 37um, greater than

[0186] 25um and less than 37um, greater than 26um and less than 37um, greater than 27um and less than 37um, greater than

[0187] 28um and less than 37um, greater than 29um and less than 37um, greater than 30um and less than 37um, greater than

[0188] 31um and less than 37um, greater than 32um and less than 37um, greater than 33um and less than 37um, greater than

[0189] 34um and less than 37um, greater than 35um and less than 37um, greater than 36um and less than 37um, greater than

[0190] 18um and less than 36um, greater than 19um and less than 36um, greater than 20um and less than 36um, greater than

[0191] 21um and less than 36um, greater than 22um and less than 36um, greater than 23um and less than 36um, greater than

[0192] 24um and less than 36um, greater than 25um and less than 36um, greater than 26um and less than 36um, greater than

[0193] 27um and less than 36um, greater than 28um and less than 36um, greater than 29um and less than 36um, greater than

[0194] 30um and less than 36um, greater than 31um and less than 36um, greater than 32um and less than 36um, greater than

[0195] 33um and less than 36um, greater than 34um and less than 36um, greater than 35um and less than 36um, greater than

[0196] 18um and less than 35um, greater than 19um and less than 35um, greater than 20um and less than 35um, greater than

[0197] 21um and less than 35um, greater than 22um and less than 35um, greater than 23um and less than 35um, greater than

[0198] 24um and less than 35um, greater than 25um and less than 35um, greater than 26um and less than 35um, greater than

[0199] 27um and less than 35um, greater than 28um and less than 35um, greater than 29um and less than 35um, greater than

[0200] 30um and less than 35um, greater than 31um and less than 35um, greater than 32um and less than 35um, greater than

[0201] 33um and less than 35um, greater than 34um and less than 35um, greater than 18um and less than 34um, greater than

[0202] 19um and less than 34um, greater than 20um and less than 34um, greater than 21um and less than 34um, greater than

[0203] 22um and less than 34um, greater than 23um and less than 34um, greater than 24um and less than 34um, greater than

[0204] 25um and less than 34um, greater than 26um and less than 34um, greater than 27um and less than 34um, greater than

[0205] 28um and less than 34um, greater than 29um and less than 34um, greater than 30um and less than 34um, greater than

[0206] 31um less than 34um, greater than 32um less than 34um, greater than 33um less than 34um, greater than

[0207] 18um and less than 33um, greater than 19um and less than 33um, greater than 20um and less than 33um, greater than

[0208] 21um and less than 33um, greater than 22um and less than 33um, greater than 23um and less than 33um, greater than

[0209] 24um and less than 33um, greater than 25um and less than 33um, greater than 26um and less than 33um, greater than

[0210] 27um and less than 33um, greater than 28um and less than 33um, greater than 29um and less than 33um, greater than

[0211] 30um and less than 33um, greater than 31um and less than 33um, greater than 32um and less than 33um, greater than

[0212] 18um and less than 32um, greater than 19um and less than 32um, greater than 20um and less than 32um, greater than

[0213] 21um and less than 32um, greater than 22um and less than 32um, greater than 23um and less than 32um, greater than

[0214] 24um and less than 32um, greater than 25um and less than 32um, greater than 26um and less than 32um, greater than

[0215] 27um and less than 32um, greater than 28um and less than 32um, greater than 29um and less than 32um, greater than

[0216] 30um and less than 32um, greater than 31um and less than 32um, greater than 18um and less than 31um, greater than

[0217] 19um and less than 31um, greater than 20um and less than 31um, greater than 21um and less than 31um, greater than

[0218] 22um and less than 31um, greater than 23um and less than 31um, greater than 24um and less than 31um, greater than

[0219] 25um and less than 31um, greater than 26um and less than 31um, greater than 27um and less than 31um, greater than

[0220] 28um and less than 31um, greater than 29um and less than 31um, greater than 30um and less than 31um, greater than

[0221] 18um and less than 30um, greater than 19um and less than 30um, greater than 20um and less than 30um, greater than

[0222] 21um and less than 30um, greater than 22um and less than 30um, greater than 23um and less than 30um, greater than

[0223] 24um and less than 30um, greater than 25um and less than 30um, greater than 26um and less than 30um, greater than

[0224] 27um and less than 30um, greater than 28um and less than 30um, greater than 29um and less than 30um, greater than

[0225] 18um and less than 29um, greater than 19um and less than 29um, greater than 20um and less than 29um, greater than 21um and less than 29um, greater than 22um and less than 29um, greater than 23um and less than 29um, greater than 24um and less than 29um, greater than 25um and less than 29um, greater than 26um and less than 29um, greater than 27um and less than 29um, greater than 28um and less than 29um, greater than 18um and less than 28um, greater than 19um and less than 28um, greater than 20um and less than 28um, greater than 21um and less than 28um, greater than 22um and less than 28um, greater than 23um and Less than 28um, greater than 24um but less than 28um, greater than 25um but less than 28um, greater than 26um but less than 28um, greater than 27um but less than 28um, greater than 18um but less than 27um, greater than 19um but less than 27um, greater than 20um but less than 27um, greater than 21um but less than 27um, greater than 22um but less than 27um, greater than 23um but less than 27um, greater than 24um but less than 27um, greater than 25um but less than 27um, greater than 26um but less than 27um, greater than 19um but less than 26um, greater than 20um but less than 26um, greater than 21um but less than 26um Greater than 22um and less than 26um, greater than 23um and less than 26um, greater than 24um and less than 26um, greater than 25um and less than 26um, greater than 18um and less than 25um, greater than 19um and less than 25um, greater than 20um and less than 25um, greater than 21um and less than 25um, greater than 22um and less than 25um, greater than 23um and less than 25um, greater than 24um and less than 25um, greater than 18um and less than 24um, greater than 19um and less than 24um, greater than 20um and less than 24um, greater than 21um and less than 24um, greater than 22um and less than 24um, greater than 23 ... um and less than 24um, greater than 18um and less than 23um, greater than 19um and less than 23um, greater than 20um and less than 23um, greater than 21um and less than 23um, greater than 22um and less than 23um, greater than 18um and less than 22um, greater than 19um and less than 22um, greater than 20um and less than 22um, greater than 21um and less than 22um, greater than 18um and less than 21um, greater than 19um and less than 21um, greater than 20um and less than 21um, greater than 18um and less than 20um, greater than 18um and less than 19um, or greater than 19um and less than 20um, but not limited to these.For example, the product of W1 / W2 and the pixel pitch value can be equal to 18.5um, 19um, 19.5um, 20um, 20.5um, 21um, 22.5um, 23um, 23.5um, 24um, 24.5um, 25um, 25.5um, 26um, 26.5um, 27um, 27.5um, 28um, 28.5um, 29um, 29.5um, 30um, 30.5um, 31um, 31.5um, 32um, 32.5um, 33um, 33.5um, 34um, 34.5um, 35um, 35.5um, 36um, 36.5um, 37um, 37.5um, 38um, 38.5um, 39um, or 39.5um, but is not limited to these values.

[0226] In at least one embodiment of the present invention, "one of the plurality of shift register units is provided with multiple signal lines" does not mean that only one of the plurality of shift register units is provided with multiple signal lines;

[0227] "The multiple shift register units are provided with multiple signal lines" can mean that each shift register unit in at least one of the multiple shift register units is provided with multiple signal lines.

[0228] In at least one embodiment of the present invention, when the orthographic projections of different signal lines among the plurality of signal lines on the substrate overlap each other, the width of the plurality of signal lines in the second direction and W1 is: the sum of the widths of the different signal lines among the plurality of signal lines in the second direction respectively.

[0229] Optionally, in the driving circuit region, a plurality of shift register units may be provided along the second direction. The sum of the widths of the signal lines in each shift register unit in the second direction and the product of the ratio of the width of each shift register unit in the second direction and the pixel pitch value is greater than 18µm and less than 40µm.

[0230] Optionally, the plurality of signal lines may include all the signal lines in one of the plurality of shift register units.

[0231] In at least one embodiment of the present invention, the plurality of signal lines include all signal lines that overlap with the orthographic projection of one of the plurality of shift register units onto the substrate.

[0232] Optionally, the type of shift register unit included in the scanning drive module may include: a first shift register unit providing an n-type drive signal, a second shift register unit providing a p-type drive signal, and a third shift register unit providing a light emission control signal. When one of the multiple shift register units is the first shift register unit, the multiple signal lines may include: all signal lines included in the first shift register unit, a second start signal line, and a third start signal line; but not limited thereto.

[0233] The second start signal line can be a signal line that provides an input signal to the second shift register unit, and the third start signal line can be a signal line that provides an input signal to the third shift register unit, but is not limited thereto.

[0234] In practice, W1 / W2 can be greater than 0.4 and less than 0.7, but is not limited to this. For example, W1 / W2 can be greater than 0.45 and less than 0.7, greater than 0.5 and less than 0.7, greater than 0.55 and less than 0.7, greater than 0.6 and less than 0.7, greater than 0.65 and less than 0.7, greater than 0.4 and less than 0.65, greater than 0.45 and less than 0.65, greater than 0.5 and less than 0.65, greater than 0.55 and less than 0.65, greater than 0.6 and less than 0.65, greater than 0.4 and less than 0.6, greater than 0.45 and less than 0.6, greater than 0.5 and less than 0.6, greater than 0.55 and less than 0.6, greater than 0.4 and less than 0.55, greater than 0.45 and less than 0.5, or greater than 0.4 and less than 0.45; but it is not limited to these. For example, W1 / W2 can be equal to 0.41, 0.42, 0.43, 0.44, 0.45, 0.46, 0.47, 0.48, 0.49, 0.5, 0.51, 0.52, 0.53, 0.54, 0.55, 0.56, 0.57, 0.58, 0.59, 0.6, 0.61, 0.62, 0.63, 0.64, 0.65, 0.46, 0.67, 0.68, or 0.69;

[0235] Optionally, the product of W1 / W2 and the pixel pitch value is greater than 27µm and less than 36µm; for example, the product of W1 / W2 and the pixel pitch value can be greater than 27µm and less than 36µm, greater than 28µm and less than 36µm, greater than 29µm and less than 36µm, greater than 30µm and less than 36µm, greater than 31µm and less than 36µm, greater than 32µm and less than 36µm, greater than 33µm and less than 36µm, greater than 34µm and less than 36µm, greater than 35µm and less than 36µm, greater than 27µm and less than 35µm, greater than 28µm and less than 35µm, greater than 29µm and less than 35µm, greater than 30µm and less than 35µm, and greater than 31µm and less than 35µm. Greater than 32um and less than 35um, greater than 33um and less than 35um, greater than 34um and less than 35um, greater than 27um and less than 34um, greater than 28um and less than 34um, greater than 29um and less than 34um, greater than 30um and less than 34um, greater than 31um and less than 34um, greater than 32um and less than 34um, greater than 27um and less than 33um, greater than 28um and less than 33um, greater than 29um and less than 33um, greater than 30um and less than 33um, greater than 31um and less than 33um, greater than 32um and less than 33um, greater than 27um and less than 32um, greater than 28um and less than 32um, greater than 29um and less than 32um. The pixel pitch values ​​can be greater than 30µm and less than 32µm, greater than 31µm and less than 32µm, greater than 27µm and less than 31µm, greater than 28µm and less than 31µm, greater than 29µm and less than 31µm, greater than 30µm and less than 31µm, greater than 27µm and less than 30µm, greater than 28µm and less than 30µm, greater than 29µm and less than 30µm, greater than 27µm and less than 29µm, greater than 28µm and less than 29µm, or greater than 27µm and less than 28µm, but are not limited thereto; for example, the product of W1 / W2 and the pixel pitch value can be equal to 27.1µm, 27.2µm, 27.3µm, 27.4µm, 27.5µm, 27.6µm, 27.7µm. um, 27.8um, 27.9um, 28um, 28.1um, 28.2um, 28.3um, 28.4um, 28.5um, 28.6um, 28.7um, 28.8um, 28.9um, 29um, 29.1um, 29.2um, 29.3um, 29.4um, 29.5um, 29.6um, 29.7um, 29.8um, 29.9um, 31um, 30.1um, 30.2um, 30.3um, 30.4um, 30.5um, 30.6um, 30.7um, 30.8um, 30.9um, 31um, 31.1um, 31.2um, 31.3um, 31.4um, 31.5um, 31.6um, 31.7um, 31.8um, 31.9um, 32um, 32.1um, 32.2um, 32.3um, 32.4um, 32.5um, 32.6um, 32.7um, 32.8um, 32.9um, 33um, 33.1um, 33.2um, 33.3um, 33.4um, 33.5um, 33.6um, 33 .7um, 33.8um, 33.9um, 34um, 34.1um, 34.2um, 34.3um, 34.4um, 34.5um, 34.6um, 34.7um, 34.8um, 34.9um, 35um, 35.1um, 35.2um, 35.3um, 35.4um, 35.5um, 35.6um, 35.7um, 35.8um or 35.9um.

[0236] Optionally, the product of W1 / W2 and the pixel pitch value is greater than 18µm and less than or equal to 27µm; for example, the product of W1 / W2 and the pixel pitch value can be greater than 18.5µm and less than or equal to 27µm, greater than 19µm and less than or equal to 27µm, greater than 19.5µm and less than or equal to 27µm, greater than 20µm and less than or equal to 27µm, greater than 20.5µm and less than or equal to 27µm, greater than 21µm and less than or equal to 27µm, greater than 21.5µm and less than or equal to 27µm, greater than 22µm and less than or equal to 27µm, greater than 22.5µm and less than or equal to 27µm, greater than 23µm and less than or equal to 27µm, greater than 23.5µm and less than or equal to 27µm, greater than 24um less than or equal to 27um, greater than 24.5um less than or equal to 27um, greater than 25um less than or equal to 27um, greater than 25.5um less than or equal to 27um, greater than 26um less than or equal to 27um, greater than 26.5um less than or equal to 27um, greater than 18um less than or equal to 26.5um, greater than 18.5um less than or equal to 26.5um, greater than 19um less than or equal to 26.5um, greater than 19.5um less than or equal to 26.5um, greater than 20um less than or equal to 26.5um, greater than 20.5um less than or equal to 26.5um, greater than 21um less than or equal to 26.5um, greater than 21.5um less than or equal to 26.5um. um, greater than 22um and less than or equal to 26.5um, greater than 22.5um and less than or equal to 26.5um, greater than 23um and less than or equal to 26.5um, greater than 23.5um and less than or equal to 26.5um, greater than 24um and less than or equal to 26.5um, greater than 24.5um and less than or equal to 26.5um, greater than 25um and less than or equal to 26.5um, greater than 25.5um and less than or equal to 26.5um, greater than 26um and less than or equal to 26.5um, greater than 18um and less than or equal to 26um, greater than 18.5um and less than or equal to 26um, greater than 19um and less than or equal to 26um, greater than 19.5um and less than or equal to 26um, greater than 20um and Less than or equal to 26um, greater than 20.5um but less than or equal to 26um, greater than 21um but less than or equal to 26um, greater than 21.5um but less than or equal to 26um, greater than 22um but less than or equal to 26um, greater than 22.5um but less than or equal to 26um, greater than 23um but less than or equal to 26um, greater than 23.5um but less than or equal to 26um, greater than 24um but less than or equal to 26um, greater than 24.5um but less than or equal to 26um, greater than 25um but less than or equal to 26um, greater than 25.5um but less than or equal to 26um, greater than 18um but less than or equal to 25.5um, greater than 18.5um but less than or equal to 25.5um, greater than 19um but less than or equal to 25um.5um, greater than 19.5um and less than or equal to 25.5um, greater than 20um and less than or equal to 25.5um, greater than 20.5um and less than or equal to 25.5um, greater than 21um and less than or equal to 25.5um, greater than 21.5um and less than or equal to 25.5um, greater than 22um and less than or equal to 25.5um, greater than 22.5um and less than or equal to 25.5um, greater than 23um and less than or equal to 25.5um, greater than 23.5um and less than or equal to 25.5um, greater than 24um and less than or equal to 25.5um, greater than 24.5um and less than or equal to 25.5um, greater than 25um and less than or equal to 25.5um, greater than 18um and less than or equal to 25um. Greater than 18.5um and less than or equal to 25um, greater than 19um and less than or equal to 25um, greater than 19.5um and less than or equal to 25um, greater than 20um and less than or equal to 25um, greater than 20.5um and less than or equal to 25um, greater than 21um and less than or equal to 25um, greater than 21.5um and less than or equal to 25um, greater than 22um and less than or equal to 25um, greater than 22.5um and less than or equal to 25um, greater than 23um and less than or equal to 25um, greater than 23.5um and less than or equal to 25um, greater than 24um and less than or equal to 25um, greater than 24.5um and less than or equal to 25um, greater than 18um and less than or equal to 24.5um, greater than 18.5um The values ​​are: less than or equal to 24.5 μm, greater than 19 μm but less than or equal to 24.5 μm, greater than 19.5 μm but less than or equal to 24.5 μm, greater than 20 μm but less than or equal to 24.5 μm, greater than 20.5 μm but less than or equal to 24.5 μm, greater than 21 μm but less than or equal to 24.5 μm, greater than 21.5 μm but less than or equal to 24.5 μm, greater than 21.5 μm but less than or equal to 24.5 μm, greater than 22 μm but less than or equal to 24.5 μm, greater than 22.5 μm but less than or equal to 24.5 μm, greater than 23 μm but less than or equal to 24.5 μm, greater than 23.5 μm but less than or equal to 24.5 μm, greater than 24 μm but less than or equal to 24.5 μm, greater than 18 μm but less than or equal to 24 μm, greater than 18.5 μm but less than or equal to 24.5 μm. The values ​​are: 24um, greater than 19um and less than or equal to 24um, greater than 19.5um and less than or equal to 24um, greater than 20um and less than or equal to 24um, greater than 20.5um and less than or equal to 24um, greater than 21um and less than or equal to 24um, greater than 21.5um and less than or equal to 24um, greater than 22um and less than or equal to 24um, greater than 22.5um and less than or equal to 24um, greater than 23um and less than or equal to 24um, greater than 23.5um and less than or equal to 24um, greater than 18um and less than or equal to 23.5um, greater than 18.5um and less than or equal to 23.5um, greater than 19um and less than or equal to 23.5um, and greater than 19.5um and less than or equal to 23.5um, greater than 20um and less than or equal to 23.5um, greater than 20.5um and less than or equal to 23.5um, greater than 21um and less than or equal to 23.5um, greater than 21.5um and less than or equal to 23.5um, greater than 22um and less than or equal to 23.5um, greater than 22.5um and less than or equal to 23.5um, greater than 23um and less than or equal to 23.5um, greater than 18um and less than or equal to 23um, greater than 18.5um and less than or equal to 23um, greater than 19um and less than or equal to 23um, greater than 19.5um and less than or equal to 23um, greater than 20um and less than or equal to 23um, greater than 20.5um and less than or equal to 23um, greater than 21um and less than or equal to 23um. The values ​​are: 23um, greater than 21.5um and less than or equal to 23um, greater than 22um and less than or equal to 23um, greater than 22.5um and less than or equal to 23um, greater than 18um and less than or equal to 22.5um, greater than 18.5um and less than or equal to 22.5um, greater than 19um and less than or equal to 22.5um, greater than 19.5um and less than or equal to 22.5um, greater than 20um and less than or equal to 22.5um, greater than 20.5um and less than or equal to 22.5um, greater than 21um and less than or equal to 22.5um, greater than 21.5um and less than or equal to 22.5um, greater than 22um and less than or equal to 22.5um, greater than 18um and less than or equal to 22um, and greater than 18um. 5um less than or equal to 22um, greater than 19um less than or equal to 22um, greater than 19.5um less than or equal to 22um, greater than 20um less than or equal to 22um, greater than 20.5um less than or equal to 22um, greater than 21um less than or equal to 22um, greater than 21.5um less than or equal to 22um, greater than 18um less than or equal to 21.5um, greater than 18.5um less than or equal to 21.5um, greater than 19um less than or equal to 21.5um, greater than 19.5um less than or equal to 21.5um, greater than 20um less than or equal to 21.5um, greater than 20.5um less than or equal to 21.5um, greater than 21um less than or equal to 21.5um, greater than 18um less than or equal to 21um, greater than 18.5um less than or equal to 21um, greater than 19um less than or equal to 21um, greater than 19.5um less than or equal to 21um, greater than 20um less than or equal to 21um, greater than 20.5um less than or equal to 21um, greater than 18um less than or equal to 20.5um, greater than 18.5um less than or equal to 20.5um, greater than 19um less than or equal to 20.5um, greater than 19.5um less than or equal to 20.5um, greater than 20um less than or equal to 20.5um, greater than 18um less than or equal to 20um, greater than 18.5um less than or equal to 20um, greater than 19um less than or equal to 20um, greater than 19um.The pixel pitch values ​​are: 5um and less than or equal to 20um, greater than 18um and less than or equal to 19.5um, greater than 18.5um and less than or equal to 19.5um, greater than 19um and less than or equal to 19.5um, greater than 18um and less than or equal to 19um, greater than 18.5um and less than or equal to 19um; or greater than 18um and less than or equal to 18.5um. For example, the product of W1 / W2 and the pixel pitch value can be equal to 18.1um, 18.2um, 18.3um, 18.4um, 18.5um, 18.6um, 18.7um, 18.8um, 18.9um, 19um, 19.1um, 19.2um, 19.3um, 19.4um, 19.5um, 19.6um, 19.7um, 19.8um, 19.9um, 20um. , 20.1um, 20.2um, 20.3um, 20.4um, 20.5um, 20.6um, 20.7um, 20.8um, 20.9um, 21um, 21.1um, 21. 2um, 21.3um, 21.4um, 21.5um, 21.6um, 21.7um, 21.8um, 21.9um, 22um, 22.1um, 22.2um, 22.3um, 2 2.4um, 22.5um, 22.6um, 22.7um, 22.8um, 22.9um, 23um, 23.1um, 23.2um, 23.3um, 23.4um, 23.5u m, 23.6um, 23.7um, 23.8um, 23.9um, 24um, 24.1um, 24.2um, 24.3um, 24.4um, 24.5um, 24.6um, 24. 7um, 24.8um, 24.9um, 25um, 25.1um, 25.2um, 25.3um, 25.4um, 25.5um, 25.6um, 25.7um, 25.8um, 25.9um, 26um, 26.1um, 26.2um, 26.3um, 26.4um, 26.5um, 26.6um, 26.7um, 26.8um, 26.9um or 27um. .

[0237] Optionally, the product of W1 / W2 and the pixel pitch value is greater than or equal to 36µm and less than 40µm; for example, the product of W1 / W2 and the pixel pitch value can be greater than 36.5µm and less than 40µm, greater than 37µm and less than 40µm, greater than 37.5µm and less than 40µm, greater than 38µm and less than 40µm, greater than 38.5µm and less than 40µm, greater than 39µm and less than 40µm, greater than 39.5µm and less than 40µm, greater than or equal to 36µm and less than 39.5µm, greater than 36.5µm and less than 39.5µm, greater than 37µm and less than 39.5µm, greater than 37.5µm and less than 39.5µm, greater than 38µm and less than 39.5µm, greater than 38.5µm and less than 39.5µm, greater than 39µm and less than 39.5µm, greater than or equal to 36µm and less than 39µm, greater than 36.5µm and less than 39µm, etc. The values ​​are: greater than 37um and less than 39um, greater than 37.5um and less than 39um, greater than 38um and less than 39um, greater than 38.5um and less than 39um, greater than or equal to 36um and less than 38.5um, greater than 36.5um and less than 38.5um, greater than 37um and less than 38.5um, greater than 37.5um and less than 38.5um, greater than 38um and less than 38.5um, greater than or equal to 36um and less than 38um, greater than 36.5um and less than 38um, greater than 37um and less than 38um, greater than 37.5um and less than 38um, greater than or equal to 36um and less than 37.5um, greater than 36.5um and less than 37.5um, greater than or equal to 36um and less than 37um, greater than 36.5um and less than 37um, or greater than or equal to 36um and less than 36.5um. For example, the product of W1 / W2 and the pixel pitch value can be equal to 36um, 36.1um, 36.2um, 36.3um, 36.4um, 36.5um, 36.6um, 36.7um, 36.8um, 36.9um, 37um, 37.1um, 37.2um, 37.3um, 37.4um, 37.5um, 37.6um, 37.7um, 37... .8um, 37.9um, 38um, 38.1um, 38.2um, 38.3um, 38.4um, 38.5um, 38.6um, 38.7um, 38.8um, 3 8.9um, 39um, 39.1um, 39.2um, 39.3um, 39.4um, 39.5um, 39.6um, 39.7um, 39.8um or 39.9um.

[0238] Optionally, the product of W1 / W2 and the pixel pitch value is greater than 29µm and less than 35µm; for example, the product of W1 / W2 and the pixel pitch value can be greater than 29.5µm and less than 35µm, greater than 30µm and less than or equal to 35µm, greater than 30.5µm and less than 35µm, greater than 31µm and less than or equal to 35µm, greater than 31.5µm and less than 35µm, greater than 32µm and less than or equal to 35µm, greater than 32.5µm and less than 35µm, greater than 33µm and less than or equal to 35µm, greater than 33.5µm and less than 35µm, greater than 34µm and less than or equal to 35µm, greater than 34.5µm and less than 35µm, or greater than 29µm and less than 34.5µm. Greater than 29.5um and less than 34.5um, greater than 30um and less than or equal to 34.5um, greater than 30.5um and less than 34.5um, greater than 31um and less than or equal to 34.5um, greater than 31.5um and less than 34.5um, greater than 32um and less than or equal to 34.5um, greater than 32.5um and less than 34.5um, greater than 32.5um and less than 34.5um, greater than 33um and less than or equal to 34.5um, greater than 33.5um and less than 34.5um, greater than 34um and less than or equal to 34.5um, greater than 29um and less than 34um, greater than 29.5um and less than 34um, greater than 30um and less than or equal to 34um, greater than 30.5um and less than 34um, greater than 31um The values ​​are: less than or equal to 34um, greater than 31.5um but less than 34um, greater than 32um but less than or equal to 34um, greater than 32.5um but less than 34um, greater than 33um but less than or equal to 34um, greater than 33.5um but less than 34um, greater than 29um but less than 33.5um, greater than 29.5um but less than 33.5um, greater than 30um but less than or equal to 33.5um, greater than 30.5um but less than 33.5um, greater than 31um but less than or equal to 33.5um, greater than 31.5um but less than 33.5um, greater than 32um but less than or equal to 33.5um, greater than 32.5um but less than 33.5um, and greater than 33um but less than or equal to 33.5um. m, greater than 29um and less than 33um, greater than 29.5um and less than 33um, greater than 30um and less than or equal to 33um, greater than 30.5um and less than 33um, greater than 31um and less than or equal to 33um, greater than 31.5um and less than 33um, greater than 32um and less than or equal to 33um, greater than 32.5um and less than 33um, greater than 29um and less than 32.5um, greater than 29.5um and less than 32.5um, greater than 30um and less than or equal to 32.5um, greater than 30.5um and less than 32.5um, greater than 31um and less than or equal to 32.5um, greater than 31.5um and less than 32.5um, greater than 32um and less than or equal to 32.5um, greater than 29um and less than 32um, greater than 29.5um and less than 32um, greater than 30um and less than or equal to 32um, greater than 30.5um and less than 32um, greater than 31um and less than or equal to 32um, greater than 31.5um and less than 32um, greater than 29um and less than 31.5um, greater than 29.5um and less than 31.5um, greater than 30um and less than or equal to 31.5um, greater than 30.5um and less than 31.5um, greater than 31um And less than or equal to 31.5um, greater than 29um but less than 31um, greater than 29.5um but less than 31um, greater than 30um but less than or equal to 31um, greater than 30.5um but less than 31um, greater than 29um but less than 30.5um, greater than 29.5um but less than 30.5um, greater than 30um but less than or equal to 30.5um, greater than 29um but less than 30um, greater than 29.5um but less than 30um, or greater than 29um but less than 29.5um. For example, the product of W1 / W2 and the pixel pitch value can be equal to 29.1um, 29.2um, 29.3um, 29.4um, 29.5um, 29.6um, 29.7um, 29.8um, 29.9um, 30um, 30.1um, 30.2um, 30.3um, 30.4um, 30.5um, 30.6um, 30.7um, 30.8um, 30.9um, 31um, 31.1um, 31.2um, 31.3um, 31.4um, 31.5um, 31.6um, 31.7um, 31.8um. m、31.9um、32um、32.1um、32.2um、32.3um、32.4um、32.5um、32.6um、32.7um、32.8um、32.9um、33um、33.1um、33.2um、33.3um、33. 4um, 33.5um, 33.6um, 33.7um, 33.8um, 33.9um, 34um, 34.1um, 34.2um, 34.3um, 34.4um, 34.5um, 34.6um, 34.7um, 34.8um or 34.9um. .

[0239] like Figure 1 As shown, at least one embodiment of the shift register unit includes multiple signal lines, multiple transistors, and multiple capacitors;

[0240] The plurality of signal lines may include: a first voltage line VGH, a second voltage line VGL, a first clock signal line CK1, a second clock signal line CK2, and a third clock signal line CK3; the plurality of transistors include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13; the plurality of capacitors include: a first capacitor C1, a second capacitor C2, and a third capacitor C3;

[0241] The gate G1 of the first transistor T1 is coupled to the third clock signal line CK3, the first electrode S1 of the first transistor T1 is coupled to the input terminal INPUT, and the second electrode D1 of the first transistor T1 is coupled to the gate G2 of the second transistor T2.

[0242] The first electrode S2 of the second transistor T2 is coupled to the third clock signal line CK3, and the second electrode D2 of the second transistor T2 is coupled to the second electrode D3 of the third transistor T3.

[0243] The gate G3 of the third transistor T3 is coupled to the third clock signal line CK3, and the first electrode S3 of the third transistor T3 is coupled to the second voltage line VGL.

[0244] The gate G4 of the fourth transistor T4 is coupled to the gate G10 of the tenth transistor T10, the first electrode S4 of the fourth transistor T4 is coupled to the first clock signal line CK1, and the second electrode D4 of the fourth transistor T4 is coupled to the second electrode D5 of the fifth transistor T5.

[0245] The gate G5 of the fifth transistor T5 is coupled to the second electrode D3 of the third transistor T3, and the first electrode S5 of the fifth transistor T5 is coupled to the first voltage line VGH.

[0246] The gate G6 of the sixth transistor T6 is coupled to the second electrode D11 of the eleventh transistor T11, the first electrode S6 of the sixth transistor T6 is coupled to the first clock signal line CK1, and the second electrode D6 of the sixth transistor T6 is coupled to the first electrode S7 of the seventh transistor T7.

[0247] The gate G7 of the seventh transistor T7 is coupled to the first clock signal line CK1, and the second electrode D7 of the seventh transistor T7 is coupled to the gate G9 of the ninth transistor T9.

[0248] The gate G8 of the eighth transistor T8 is coupled to the second electrode D13 of the thirteenth transistor T13, the first electrode S8 of the eighth transistor T8 is coupled to the gate G9 of the ninth transistor T9, and the second electrode D8 of the eighth transistor T8 is coupled to the first voltage line VGH.

[0249] The first electrode S9 of the ninth transistor T9 is coupled to the first voltage line VGH, and the second electrode D9 of the ninth transistor T9 is coupled to the drive signal output terminal OUTPUT.

[0250] The first electrode S10 of the tenth transistor T10 is coupled to the drive signal output terminal OUT, and the second electrode D10 of the tenth transistor T10 is coupled to the second voltage line VGL.

[0251] The gate G11 of the eleventh transistor T11 is coupled to the second voltage line VGL, and the first electrode S11 of the eleventh transistor T11 is coupled to the gate G5 of the fifth transistor T5.

[0252] The gate G12 of the twelfth transistor T12 is coupled to the second voltage line VGL, the first electrode S12 of the twelfth transistor T12 is coupled to the second electrode D1 of the first transistor T1, and the second electrode D12 of the twelfth transistor T12 is electrically connected to the gate G10 of the tenth transistor T10.

[0253] The gate G13 of the thirteenth transistor is coupled to the second clock signal line CK2, the first electrode S13 of the thirteenth transistor T13 is coupled to the first voltage line VGH, and the second electrode D13 of the thirteenth transistor T13 is coupled to the gate G2 of the second transistor T2.

[0254] The first plate C1a of the first capacitor C1 is coupled to the gate G6 of the sixth transistor T6, and the second plate C1b of the first capacitor C1 is coupled to the second electrode D6 of the sixth transistor T6.

[0255] The first plate C2a of the second capacitor C2 is coupled to the gate G9 of the ninth transistor T9, and the second plate C2b of the second capacitor C2 is coupled to the first voltage line VGH.

[0256] The first plate C3a of the third capacitor C3 is coupled to the gate G10 of the tenth transistor T10, and the second plate C3b of the third capacitor C3 is coupled to the second electrode D4 of the fourth transistor T4.

[0257] In at least one embodiment of the present invention, the first voltage line may be a high voltage line and the second voltage line may be a low voltage line, but this is not a limitation.

[0258] exist Figure 1 In at least one embodiment of the shift register unit shown, all transistors may be low-temperature polycrystalline silicon thin-film transistors, but are not limited thereto. Figure 1 At least one embodiment of the shift register unit shown is a shift register unit for providing n-type drive signals.

[0259] Figure 2A For corresponding Figure 1 A layout schematic diagram of at least one embodiment of the shift register unit shown;

[0260] Figure 3A For corresponding Figure 1 A layout schematic diagram of at least one embodiment of the shift register unit shown; Figure 4A For corresponding Figure 1 A layout schematic diagram of at least one embodiment of the shift register unit shown; Figure 5A For corresponding Figure 1 A layout schematic diagram of at least one embodiment of the shift register unit shown; Figure 6A For corresponding Figure 1 A layout schematic diagram of at least one embodiment of the shift register unit shown; Figure 7A For corresponding Figure 1 The diagram shows a layout schematic of at least one embodiment of the shift register unit.

[0261] exist Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A and Figure 7A In this context, the first direction can be vertical, and the second direction can be horizontal, but is not limited to these two directions.

[0262] exist Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A and Figure 7A In the diagram, area A1 is the first driving circuit region. In the first driving circuit region A1, there is a shift register unit, a second start signal line GSTVP, and a third start signal line ESTV. The width of the shift register unit in the horizontal direction is W2.

[0263] In at least one embodiment of the present invention, a first driving circuit region A1 is included in the driving circuit region.

[0264] exist Figure 2G , Figure 3G , Figure 4G , Figure 5G, Figure 6G and Figure 7G In this context, the pixel spacing value is labeled P0.

[0265] Figure 2G Is Figure 2A A diagram with pixel unit P1 added to the existing structure. Figure 3G Is Figure 3A A diagram with pixel unit P1 added to the existing structure. Figure 4G Is Figure 4A A diagram with pixel unit P1 added to the existing structure. Figure 5G Is Figure 5A A diagram with pixel unit P1 added to the existing structure. Figure 6G Is Figure 6A A diagram with pixel unit P1 added to the existing structure. Figure 7G Is Figure 7A A schematic diagram with pixel unit P1 added to the existing structure.

[0266] like Figure 2G , Figure 3G , Figure 4G , Figure 5G , Figure 6G and Figure 7G As shown, the pixel spacing value P0 is the length of the pixel unit P1 along a first direction (the first direction can be, for example, the vertical direction).

[0267] like Figure 2A , Figure 3A , Figure 4A and Figure 5A As shown, the orthographic projection of the second start signal line GSTVP on the substrate overlaps with the orthographic projection of the plate of the first capacitor C1 included in the shift register unit on the substrate, and the orthographic projection of the plate of the third capacitor C3 included in the shift register unit on the substrate; the orthographic projection of the third start signal line ESTV on the substrate overlaps with the orthographic projection of the plate of the third capacitor C3 on the substrate.

[0268] like Figure 6A and Figure 7A As shown, the orthographic projection of the second start signal line GSTVP on the substrate and the orthographic projection of the third start signal line ESTV on the substrate partially overlap with the orthographic projection of the plate of the third capacitor C3 on the substrate.

[0269] In at least one embodiment of the present invention, the display substrate includes a first conductive layer, an insulating layer and a second conductive layer, wherein the insulating layer is disposed between the first conductive layer and the second conductive layer;

[0270] At least one of the plurality of signal lines is disposed on the first conductive layer, and at least one of the plurality of signal lines is disposed on the second conductive layer.

[0271] In a specific implementation, at least one of the signal lines is placed on the first conductive layer and at least one of the signal lines is placed on the second conductive layer to reduce the horizontal space occupied by the shift register unit, which is beneficial to achieving a narrow bezel.

[0272] In a specific implementation, the display substrate may include an active layer, a gate insulating layer, a first gate metal layer, an interlayer dielectric layer, a second gate metal layer, a passivation layer, a first source / drain metal layer, a planarization layer, and a second source / drain metal layer, which are sequentially disposed on the substrate.

[0273] like Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A and Figure 7A As shown, a first voltage line VGH, a first second voltage line VGL-1, a second second voltage line VGL-2, a first start signal line GSTVN, a second start signal line GSTVP, and a third start signal line ESTV are formed using a second source / drain metal layer.

[0274] The first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3, and the input terminal INPUT are formed using the first source-drain metal layer;

[0275] That is, the first conductive layer can be a first source / drain metal layer, and the second conductive layer can be a second source / drain metal layer, but is not limited thereto.

[0276] Optionally, the first start signal line GSTVP is coupled to the input terminal of the first stage first shift register unit in the first scan drive module, and is used to provide an input signal to the first stage first shift register unit; the second start signal line GSTVP is coupled to the input terminal of the first stage second shift register unit in the second scan drive module, and is used to provide an input signal to the first stage second shift register unit in the second scan drive module; the third start signal line ESTV is coupled to the input terminal of the first stage third shift register unit in the third scan drive module, and is used to provide an input signal to the first stage third shift register unit in the third scan drive module.

[0277] The first scan driver module may include multiple levels of the first shift register unit, the second scan driver module may include multiple levels of the second shift register unit, and the third scan driver module may include multiple levels of the third shift register unit.

[0278] In at least one embodiment of the present invention, the shift register unit may include at least one transistor disposed in the driving circuit region, wherein the first electrode of the transistor, the second electrode of the transistor, and the plurality of signal lines are located on the same layer.

[0279] In a specific implementation, the first electrode and the second electrode of at least one transistor in the shift register unit can be located on the same layer as the multiple signal lines, so that the first electrode, the second electrode and the multiple signal lines of the at least one transistor can be made using the same metal layer, which is beneficial to achieving a narrow bezel.

[0280] like Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A and Figure 7A As shown, the first electrode of at least one transistor in the shift register unit, the second electrode of the at least one transistor, the first clock signal line CK1, the second clock signal line CK2 and the third clock signal line CK3 are fabricated using the first source-drain metal layer.

[0281] In at least one embodiment of the present invention, the shift register unit includes at least one transistor disposed in the driving circuit region, wherein the first electrode of the transistor and the second electrode of the transistor are located on the same layer, and the plurality of signal lines are located on different layers from the first electrode of the transistor.

[0282] In a specific implementation, the first electrode of at least one transistor and the second electrode of the at least one transistor included in the shift register unit may be located on the same layer, while the multiple signal lines and the first electrode of the at least one transistor may be located on different layers.

[0283] like Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A and Figure 7A As shown, the first electrode and the second electrode of at least one transistor in the shift register unit are fabricated using the first source-drain metal layer, and the first voltage line VGH, the first second voltage line VGL-1, the second second voltage line VGL-2, the first start signal line GSTVN, the second start signal line GSTVP, and the third start signal line ESTV are fabricated using the second source-drain metal layer.

[0284] In at least one embodiment of the present invention, the shift register unit includes at least one signal line disposed in the driving circuit region, the at least one signal line being configured to provide a DC power supply signal;

[0285] The ratio W3 / W2 of the width W3 of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.15; for example, W3 / W2 can be equal to 0.15, 0.16, 0.17, 0.18, 0.19, 0.2, 0.21, 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29 or 0.3, but is not limited thereto.

[0286] In practice, in order to reduce the IR voltage drop (IR voltage drop refers to a phenomenon in which the voltage drops or rises on the power and ground networks in an integrated circuit) on the signal line used to provide DC power signals, the width of at least one signal line configured to provide DC power signals in the second direction can be set to be larger.

[0287] like Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A and Figure 7A As shown, the signal lines used to provide DC power signals may include: a first voltage line VGH, a first second voltage line VGL-1, and a second second voltage line VGL-2;

[0288] The ratio between at least one of the widths of the first voltage line VGH in the horizontal direction, the widths of the first second voltage line VGL-1 in the horizontal direction, and the widths of the second second voltage line VGL-2 in the horizontal direction, and the width W2 of the shift register unit in the horizontal direction, can be greater than or equal to 0.15; for example, the ratio can be equal to 0.15, 0.16, 0.17, 0.18, 0.19, 0.2, 0.21, 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, or 0.3, but is not limited thereto.

[0289] In at least one embodiment of the present invention, the shift register unit includes at least one signal line disposed in the driving circuit region, the at least one signal line being configured to provide a DC power supply signal;

[0290] The ratio W3 / W2 of the width W3 of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.3; for example, W3 / W2 can be equal to 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, 0.41, 0.42, 0.43, 0.44, 0.45, 0.46, 0.47, 0.48, 0.49 or 0.5, but is not limited thereto.

[0291] like Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A and Figure 7A As shown, the signal lines used to provide DC power signals may include: a first voltage line VGH, a first second voltage line VGL-1, and a second second voltage line VGL-2;

[0292] The ratio between at least one of the widths of the first voltage line VGH in the horizontal direction, the widths of the first second voltage line VGL-1 in the horizontal direction, and the widths of the second second voltage line VGL-2 in the horizontal direction, and the width W2 of the shift register unit in the horizontal direction, can be greater than or equal to 0.3; for example, the ratio can be equal to 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, 0.41, 0.42, 0.43, 0.44, 0.45, 0.46, 0.47, 0.48, 0.49, or 0.5, but is not limited thereto.

[0293] In at least one embodiment of the present invention, the first voltage line VGH, the first second voltage line VGL-1, and the second second voltage line VGL-2 may be disposed on the second source-drain metal layer, and the first electrode and the second electrode of each transistor may be disposed on the first source-drain metal layer. The second source-drain metal layer has sufficient space to be disposed on the first voltage line VGH, the first second voltage line VGL-1, and the second second voltage line VGL-2, ensuring that the IR voltage drop on the signal line configured to provide at least a DC power signal is small.

[0294] In at least one embodiment of the present invention, the shift register unit includes at least one signal line disposed in the driving circuit region, the at least one signal line being configured to provide a clock signal;

[0295] The ratio W4 / W2 of the width W4 of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.015; for example, W4 / W2 can be equal to 0.015, 0.016, 0.017, 0.018, 0.019, 0.02, 0.021, 0.022, 0.023, 0.024, 0.025, 0.026, 0.027, 0.028, 0.029 or 0.03, but is not limited thereto.

[0296] In practice, in order to reduce the IR voltage drop (IR voltage drop refers to a phenomenon in which the voltage drops or rises on the power and ground networks in an integrated circuit) on the signal line used to provide the clock signal, the width of at least one signal line configured to provide the clock signal in the second direction can be set to be larger.

[0297] like Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A and Figure 7A As shown, at least one signal line for providing a clock signal may include: a first clock signal line CK1, a second clock signal line CK2, and a third clock signal line CK3;

[0298] The ratio of at least one of the horizontal widths of the first clock signal line CK1, the second clock signal line CK2, and the third clock signal line CK3 to the horizontal width W2 of the shift register unit is greater than or equal to 0.015; for example, this ratio may be equal to 0.015, 0.016, 0.017, 0.018, 0.019, 0.02, 0.021, 0.022, 0.023, 0.024, 0.025, 0.026, 0.027, 0.028, 0.029, or 0.03, but is not limited thereto.

[0299] In at least one embodiment of the present invention, the shift register unit includes at least one signal line disposed in the driving circuit region, the at least one signal line being configured to provide a clock signal;

[0300] The ratio W4 / W2 of the width W4 of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.03; for example, W4 / W2 can be equal to 0.03, 0.031, 0.032, 0.033, 0.034, 0.035, 0.036, 0.037, 0.038, 0.039, 0.04, 0.041, 0.042, 0.043, 0.044, 0.045, 0.046, 0.047, 0.048, 0.049, 0.05, 0.051, 0.052, 0.053, 0.054, 0.055, 0.056, 0.057, 0.058, 0.059 or 0.06, but is not limited thereto.

[0301] like Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A and Figure 7A As shown, at least one signal line for providing a clock signal may include: a first clock signal line CK1, a second clock signal line CK2, and a third clock signal line CK3;

[0302] The ratio of at least one of the horizontal widths of the first clock signal line CK1, the second clock signal line CK2, and the third clock signal line CK3 to the horizontal width W2 of the shift register unit is greater than or equal to 0.03; for example, this ratio can be 0.03, 0.031, 0.032, 0.033, 0.034, 0.035, or 0. .036, 0.037, 0.038, 0.039, 0.04, 0.041, 0.042, 0.043, 0.044, 0.045, 0.046, 0.047, 0.048, 0.049, 0.05, 0.051, 0.052, 0.053, 0.054, 0.055, 0.056, 0.057, 0.058, 0.059 or 0.06, but not limited to these.

[0303] Optionally, the shift register unit includes at least two transistors disposed in the driving circuit region;

[0304] The active layers of the at least two transistors are formed of continuous semiconductor layers, and the orthographic projection of one of the multiple signal lines on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate.

[0305] like Figure 2A As shown, a first voltage line VGH, a first second voltage line VGL-1, a second second voltage line VGL-2, a first start signal line GSTVN, a second start signal line GSTVP, and a third start signal line ESTV are formed using a second source / drain metal layer.

[0306] The first clock signal line CK1, the second clock signal line CK2, and the third clock signal line CK3 are formed using a first source-drain metal layer;

[0307] like Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A and Figure 4BAs shown, the active layers of the fourth transistor T4, the fifth transistor T5, the thirteenth transistor T13, and the eighth transistor T8 are formed by a continuous first semiconductor layer 100. The orthographic projection of the first voltage line VGH on the substrate overlaps with the orthographic projection of the first semiconductor layer 100 on the substrate. The orthographic projection of the second clock signal line CK2 on the substrate overlaps with the orthographic projection of the first semiconductor layer 100 on the substrate, thereby reducing the width of the driving circuit region in the second direction.

[0308] exist Figure 2B , Figure 3B and Figure 4B In the diagram, channel number 40 is T4, channel number 50 is T5, channel number 130 is T13, and channel number 80 is T8.

[0309] like Figure 5A As shown, the orthographic projection of the second clock signal line CK2 on the substrate partially overlaps with the orthographic projection of the first voltage line VGH on the substrate.

[0310] like Figure 5B As shown, the active layers of the fourth transistor T4, the fifth transistor T5, the thirteenth transistor T13, and the eighth transistor T8 are formed by a continuous first semiconductor layer 100, as follows. Figure 5A As shown, the orthographic projection of the first semiconductor layer 100 on the substrate partially overlaps with the orthographic projection of the second clock signal line CK2 on the substrate, and the orthographic projection of the first semiconductor layer 100 on the substrate partially overlaps with the orthographic projection of the first voltage line VGH on the substrate.

[0311] exist Figure 5B In the diagram, channel number 40 is T4, channel number 50 is T5, channel number 130 is T13, and channel number 80 is T8.

[0312] like Figure 6A and Figure 6B As shown, the active layers of the fourth transistor T4, the fifth transistor T5, the thirteenth transistor T13, the eighth transistor T8, the seventh transistor T7, and the sixth transistor T6 are formed by continuous second semiconductor layers 200, as shown. Figure 6AAs shown, the orthographic projection of the second semiconductor layer 200 on the substrate partially overlaps with the orthographic projection of the second clock signal line CK2 on the substrate, and the orthographic projection of the second semiconductor layer 200 on the substrate partially overlaps with the orthographic projection of the first voltage line VGH on the substrate.

[0313] exist Figure 6B In the diagram, 40 represents the T4 channel, 50 represents the T5 channel, 130 represents the T13 channel, 80 represents the T8 channel, 70 represents the T7 channel, and 60 represents the T6 channel.

[0314] like Figure 7A and Figure 7B As shown, the active layers of the first transistor T1, the fourth transistor T4, the fifth transistor T5, the thirteenth transistor T13, the twelfth transistor T12, the eighth transistor T8, the seventh transistor T7, and the sixth transistor T6 are formed by a continuous third semiconductor layer 300; the orthographic projection of the third semiconductor layer 300 on the substrate partially overlaps with the orthographic projection of the second clock signal line CK2 on the substrate, and the orthographic projection of the third semiconductor layer 300 on the substrate partially overlaps with the orthographic projection of the first voltage line VGH on the substrate. Figure 7B In the diagram, channel number 10 is T1, channel number 40 is T4, channel number 50 is T5, channel number 130 is T13, channel number 120 is T12, channel number 80 is T8, channel number 70 is T7, and channel number 60 is T6.

[0315] In at least one embodiment of the present invention, the shift register unit may include at least two transistors disposed in the driving circuit region;

[0316] The active layers of the at least two transistors are formed of continuous semiconductor layers, and the at least two transistors are connected in series.

[0317] Optionally, the shift register unit includes at least two transistors disposed in the driving circuit region;

[0318] The active layers of the at least two transistors are formed of continuous semiconductor layers, and the at least two transistors are connected in parallel with each other.

[0319] like Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A and Figure 7AAs shown, the active layers of the fourth transistor T4 and the fifth transistor T5 are formed by continuous semiconductor layers, and the fourth transistor T4 and the fifth transistor T5 are connected in series.

[0320] like Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A and Figure 7A As shown, the active layers of the fifth transistor T5, the eighth transistor T8, and the thirteenth transistor T13 are formed by continuous semiconductor layers.

[0321] The first electrode of the fifth transistor T5 is coupled to the second electrode of the eighth transistor T8, and the eighth transistor T8 is connected in series with the thirteenth transistor T13.

[0322] Optionally, the shift register unit includes at least two transistors disposed in the driving circuit region; the active layer of the at least two transistors is formed of a continuous semiconductor layer;

[0323] The at least two transistors have the same channel orientation.

[0324] In a specific implementation, the active layers of at least two transistors included in the shift register unit can be formed by continuous semiconductor layers, and the channel directions of the at least two transistors can be the same.

[0325] For example, such as Figure 3B As shown, the active layers of the second transistor T2 and the third transistor T3 are formed by a continuous fourth semiconductor layer 400, and the direction of the channel 20 of the second transistor T2 and the direction of the channel 30 of the third transistor T3 are vertical.

[0326] In at least one embodiment of the present invention, the shift register unit may include at least two transistors disposed in the driving circuit region; the active layer of the at least two transistors is formed of a continuous semiconductor layer;

[0327] The at least two transistors have different channel orientations.

[0328] In a specific implementation, the active layers of at least two transistors included in the shift register unit can be formed from continuous semiconductor layers, and the channel directions of the at least two transistors can be different.

[0329] For example, such as Figure 6B As shown, the active layer of the sixth transistor T6 and the active layer of the seventh transistor T7 are formed of continuous semiconductors, and the direction of the channel 60 of the sixth transistor T6 is different from the direction of the channel 70 of the seventh transistor T7.

[0330] Optionally, the shift register unit includes at least two transistors disposed in the driving circuit region; the active layer of the at least two transistors is formed of a continuous semiconductor layer;

[0331] One of the transistors has a channel extending along the first direction, and the other transistor has a channel extending along the second direction.

[0332] In at least one embodiment of the present invention, the first direction may be a vertical direction and the second direction may be a horizontal direction, but is not limited thereto.

[0333] In a specific implementation, the active layers of at least two transistors in the shift register unit can be formed by continuous semiconductor layers, and the channels of the two transistors extend along a first direction and a second direction, respectively.

[0334] For example, the active layer of the sixth transistor T6 and the active layer of the seventh transistor T7 are formed of continuous semiconductors, the direction of the channel 60 of the sixth transistor T6 can be horizontal, and the direction of the channel 70 of the seventh transistor T7 can be vertical.

[0335] In a specific implementation, the shift register unit may include at least two transistors disposed in the driving circuit region; the active layer of the at least two transistors is formed of a continuous semiconductor layer;

[0336] The semiconductor layer includes at least a portion of semiconductor patterns with shapes that are at least one of the following: type I, type L, type T, type F, type E, type N, type π, and type H.

[0337] In at least one embodiment of the present invention, the shift register unit may include a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, and a thirteenth transistor T13; the second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, the first electrode of the fifth transistor T5, and the first electrode of the thirteenth transistor T13 are coupled to each other.

[0338] like Figure 2B , Figure 3B and Figure 4B As shown, the active layers of the fourth transistor T4, the fifth transistor T5, the thirteenth transistor T13, and the eighth transistor T8 are formed by a continuous first semiconductor layer 100.

[0339] The orthographic projections of the active layer of the fourth transistor T4, the active layer of the fifth transistor T5, the active layer of the eighth transistor T8, and a portion of the active layer of the thirteenth transistor T13 onto the substrate together form an E-shaped pattern.

[0340] The orthographic projection of the active layer of the fourth transistor T4 onto the substrate and the orthographic projection of the active layer of the fifth transistor T5 onto the substrate together form an L-shaped pattern.

[0341] like Figures 2A-2F , Figures 3A-3F , Figures 4A-4F As shown, the shift register unit includes a first voltage line VGH and a second clock signal line CK2;

[0342] The orthographic projection of the first voltage line VGH on the substrate overlaps with the orthographic projection of the first semiconductor layer 100 on the substrate, and the orthographic projection of the second clock signal line CK2 on the substrate overlaps with the orthographic projection of the first semiconductor layer 100 on the substrate.

[0343] like Figure 2B , Figure 3B and Figure 4B As shown, the channel 40 of the fourth transistor T4 extends horizontally, the channel 50 of the fifth transistor T5 extends vertically, the channel 130 of the thirteenth transistor T13 extends horizontally, and the channel 80 of the eighth transistor T8 extends vertically.

[0344] In at least one embodiment of the present invention, the shift register unit may include a second transistor T2 and a third transistor T3; the second electrode of the second transistor T2 is coupled to the second electrode of the third transistor T3;

[0345] like Figure 3B As shown, the active layers of the second transistor T2 and the third transistor T3 are formed by a fourth semiconductor layer 400. The orthographic projection of the active layer of the second transistor T2 onto the substrate and the orthographic projection of the active layer of the third transistor T3 onto the substrate together form an I-shaped pattern.

[0346] like Figure 3B As shown, the channel 20 of the second transistor T2 extends in the vertical direction, and the channel 30 of the third transistor T3 extends in the vertical direction.

[0347] In at least one embodiment of the present invention, the shift register unit includes a second transistor T2, a third transistor T3, and an eleventh transistor T11; the second electrode of the second transistor T2 is coupled to the second electrode of the third transistor T3; the first electrode of the eleventh transistor T11 is coupled to the second electrode of the third transistor T3.

[0348] like Figure 4B As shown, the active layer of the second transistor T2, the active layer of the third transistor T3, and the active layer of the eleventh transistor T11 are formed by the fifth semiconductor layer 500. The orthographic projection of the active layer of the second transistor T2 onto the substrate, the orthographic projection of the active layer of the third transistor T3 onto the substrate, and the orthographic projection of the active layer of the eleventh transistor T11 onto the substrate together form a T-shaped pattern.

[0349] like Figures 4A-4F As shown, the plurality of signal lines include a third start signal line ESTV; the orthographic projection of the fifth semiconductor layer 500 on the substrate partially overlaps with the orthographic projection of the third start signal line ESTV on the substrate.

[0350] like Figure 4B As shown, the channel 20 of the second transistor T2 and the channel 130 of the thirteenth transistor T13 both extend in the vertical direction, while the channel of the eleventh transistor T11 extends in the horizontal direction.

[0351] like Figure 5B As shown, the active layers of the fourth transistor T4, the fifth transistor T5, the thirteenth transistor T13, and the eighth transistor T8 are formed by a continuous first semiconductor layer 100.

[0352] The orthographic projections of the active layers of the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 onto the substrate, together with the orthographic projections of a portion of the active layer of the thirteenth transistor T13 onto the substrate, together form an F-shaped pattern.

[0353] The orthographic projection of the active layer of the fourth transistor T4 onto the substrate and the orthographic projection of the active layer of the fifth transistor T5 onto the substrate together form an L-shaped pattern.

[0354] like Figures 5A-5F As shown, the shift register unit includes a first voltage line VGH and a second clock signal line CK2;

[0355] The orthographic projection of the first voltage line VGH on the substrate overlaps with the orthographic projection of the first semiconductor layer 100 on the substrate, and the orthographic projection of the second clock signal line CK2 on the substrate overlaps with the orthographic projection of the first semiconductor layer 100 on the substrate.

[0356] like Figure 5B As shown, the channel 40 of the fourth transistor T4 extends horizontally, the channel 50 of the fifth transistor T5 extends vertically, the channel 130 of the thirteenth transistor T13 extends horizontally, and the channel 80 of the eighth transistor T8 extends vertically.

[0357] In at least one embodiment of the present invention, the shift register unit includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a fourth transistor T4, a fifth transistor T5, and a thirteenth transistor T13;

[0358] The second electrode of the sixth transistor T6 is coupled to the first electrode of the seventh transistor T7; the second electrode of the eighth transistor T8 is coupled to the first electrode of the fifth transistor T5; the first electrode of the eighth transistor T8 is coupled to the second electrode of the seventh transistor T7; the second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5; and the second electrode of the eighth transistor T8, the first electrode of the fifth transistor T5, and the first electrode of the thirteenth transistor T13 are coupled to each other.

[0359] like Figure 6B As shown, the active layers of the fourth transistor T4, the fifth transistor T5, the thirteenth transistor T13, the eighth transistor T8, the seventh transistor T7, and the sixth transistor T6 are formed by a continuous second semiconductor layer 200.

[0360] The orthographic projection of the active layer of the eighth transistor T8 onto the substrate, the orthographic projection of the active layer of the seventh transistor T7 onto the substrate, and the orthographic projection of the active layer of the sixth transistor T6 onto the substrate together form an n-type pattern.

[0361] like Figures 6A-6F As shown, the shift register unit includes multiple signal lines, including a first voltage line VGH;

[0362] The orthographic projection of the first voltage line VGH on the substrate partially overlaps with the orthographic projection of the second semiconductor layer 200 on the substrate.

[0363] like Figures 6A-6FAs shown, the shift register unit includes multiple signal lines, including a second clock signal line CK2;

[0364] The orthographic projection of the second clock signal line CK2 on the substrate overlaps with the orthographic projection of the second semiconductor layer 200 on the substrate.

[0365] like Figure 6B As shown, the channel 40 of the fourth transistor T4 extends horizontally, the channel 50 of the fifth transistor T5 extends vertically, the channel 130 of the thirteenth transistor T13 extends horizontally, the channel 80 of the eighth transistor T8 extends vertically, the channel 70 of the seventh transistor T7 extends vertically, and the channel 60 of the sixth transistor T6 extends horizontally.

[0366] In at least one embodiment of the present invention, the shift register unit includes a first transistor T1, a fifth transistor T5, an eighth transistor T8, a twelfth transistor T12, a thirteenth transistor T13, a fourth transistor T4, a seventh transistor T7, and a sixth transistor T6.

[0367] The second electrode of the eighth transistor T8, the first electrode of the fifth transistor T5, and the first electrode of the thirteenth transistor T13 are coupled to each other; the first electrode of the twelfth transistor T12 is coupled to the second electrode of the first transistor T1, and the second electrode of the twelfth transistor T12 is coupled to the second electrode of the thirteenth transistor T13; the second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor; the first electrode of the sixth transistor is coupled to the first electrode of the seventh transistor; and the first electrode of the fourth transistor is coupled to the first electrode of the sixth transistor.

[0368] like Figure 7B As shown, the active layers of the first transistor T1, the fourth transistor T4, the fifth transistor T5, the thirteenth transistor T13, the twelfth transistor T12, the eighth transistor T8, the seventh transistor T7, and the sixth transistor T6 are formed by a continuous third semiconductor layer 300. The orthographic projections of the active layers of the first transistor T1, the fifth transistor T5, the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13 on the substrate form an H-shaped pattern.

[0369] like Figures 7A-7F As shown, the shift register unit includes multiple signal lines, including a first voltage line VGH;

[0370] The orthographic projection of the first voltage line VGH on the substrate partially overlaps with the orthographic projection of the third semiconductor layer 300 on the substrate.

[0371] like Figures 7A-7F As shown, the multiple signal lines include a second start signal line GSTVP, and the shift register unit also includes a second clock signal line CK2;

[0372] The orthographic projection of the two start signal lines GSTVP on the substrate overlaps with the orthographic projection of the third semiconductor layer 300 on the substrate, and the orthographic projection of the second clock signal line CK2 on the substrate overlaps with the orthographic projection of the third semiconductor layer 300 on the substrate.

[0373] like Figure 7B As shown, the channel 40 of the fourth transistor T4 extends horizontally, the channel 50 of the fifth transistor T5 extends vertically, the channel 130 of the thirteenth transistor T13 extends horizontally, the channel 120 of the twelfth transistor T12 and the channel 10 of the first transistor T1 extend vertically, the channels of the eighth transistor T8 and the seventh transistor T7 extend vertically, and the channel 60 of the sixth transistor T6 extends horizontally.

[0374] like Figure 8A As shown, the active layers of at least two transistors in the shift register unit form an I-shaped pattern when projected onto the substrate.

[0375] like Figure 8B As shown, the active layers of at least two transistors in the shift register unit form an L-shaped pattern when projected onto the substrate.

[0376] like Figure 8C As shown, the active layers of at least two transistors in the shift register unit form a T-shaped pattern when projected onto the substrate.

[0377] like Figure 8D As shown, the active layers of at least two transistors in the shift register unit form an F-shaped pattern when projected onto the substrate.

[0378] like Figure 8E As shown, the active layers of at least two transistors in the shift register unit form an E-shaped pattern when projected onto the substrate.

[0379] like Figure 8F As shown, the active layers of at least two transistors in the shift register unit form an n-type pattern when projected onto the substrate.

[0380] like Figure 8G As shown, the active layers of at least two transistors in the shift register unit form a π-shaped pattern when projected onto the substrate.

[0381] like Figure 8H As shown, the active layers of at least two transistors in the shift register unit form an H-shaped pattern when projected onto the substrate.

[0382] Figure 2B yes Figure 2A Layout diagram of the active layer in the middle. Figure 2C yes Figure 2A Layout diagram of the first gate metal layer in the middle. Figure 2D yes Figure 2A The layout diagram of the second gate metal layer in the middle, Figure 2E yes Figure 2A Layout diagram of the first source / drain metal layer in the middle. Figure 2F yes Figure 2A The layout diagram of the second source / drain metal layer in the image.

[0383] Figure 3B yes Figure 3A Layout diagram of the active layer in the middle. Figure 3C yes Figure 3A Layout diagram of the first gate metal layer in the middle. Figure 3D yes Figure 3A The layout diagram of the second gate metal layer in the middle, Figure 3E yes Figure 3A Layout diagram of the first source / drain metal layer in the middle. Figure 3F yes Figure 3A The layout diagram of the second source / drain metal layer in the image.

[0384] Figure 4B yes Figure 4A Layout diagram of the active layer in the middle. Figure 4C yes Figure 4A Layout diagram of the first gate metal layer in the middle. Figure 4D yes Figure 4A The layout diagram of the second gate metal layer in the middle, Figure 4E yes Figure 4A Layout diagram of the first source / drain metal layer in the middle. Figure 4F yes Figure 4A The layout diagram of the second source / drain metal layer in the image.

[0385] like Figure 2B , Figure 3B and Figure 4BAs shown, channel 10 is T1, channel 20 is T2, channel 30 is T3, channel 40 is T4, channel 50 is T5, channel 60 is T6, channel 70 is T7, channel 80 is T8, channel 90 is T9, channel C10 is T10, channel 110 is T11, channel 120 is T12, and channel 130 is T13.

[0386] like Figure 2C , Figure 3C and Figure 4C As shown, C1a is the first plate of the first capacitor C1, C2a is the first plate of the second capacitor C2, and C3a is the first plate of the third capacitor C3.

[0387] The gate labeled G1 is the gate of T1, the gate labeled G2-1 is the first gate of T2, the gate labeled G2-2 is the second gate of T2, the gate labeled G3 is the gate of T3, the gate labeled G4 is the gate of T4, the gate labeled G5 is the gate of T5, the gate labeled G6 is the gate of T6, the gate labeled G7 is the gate of T7, the gate labeled G8 is the gate of T8, the gate labeled G9 is the gate of T9, the gate labeled G10 is the gate of T10, the gate labeled G11 is the gate of T11, the gate labeled G12 is the gate of T12, and the gate labeled G13 is the gate of T13.

[0388] like Figure 2D , Figure 3D and Figure 4D As shown, C1b is the second plate of the first capacitor C1, C2b is the second plate of the second capacitor C2, and C3b is the second plate of the third capacitor C3.

[0389] The part labeled L1 is the first conductive connection part.

[0390] like Figure 2E , Figure 3E and Figure 4E As shown, the terminal labeled INPUT is the input terminal, and the terminal labeled OUTPUT is the drive signal output terminal;

[0391] The electrode labeled S1 is the first electrode of T1, and the electrode labeled D1 is the second electrode of T1; the electrode labeled S2 is the first electrode of T2, and the electrode labeled D2 is the second electrode of T2.

[0392] The electrode labeled S3 is the first electrode of T3;

[0393] The electrode labeled S4 is the first electrode of T4, and the electrode labeled D4 is the second electrode of T4;

[0394] The electrode labeled S6 is the first electrode of T6, and the electrode labeled D6 is the second electrode of T6; the electrode labeled S7 is the first electrode of T7, and the electrode labeled D7 is the second electrode of T7; the electrode labeled S8 is the first electrode of T8; the electrode labeled S9 is the first electrode of T9, and the electrode labeled D9 is the second electrode of T9; the electrode labeled S10 is the first electrode of T10, and the electrode labeled D10 is the second electrode of T10; the electrode labeled D11 is the second electrode of T11; the electrode labeled S12 is the first electrode of T12, and the electrode labeled D12 is the second electrode of T12; the electrode labeled S13 is the first electrode of T13, and the electrode labeled D13 is the second electrode of T13; the first electrode S13 of T13 is reused as the first electrode of T5 and the second electrode of T8; the second electrode D4 of T4 is reused as the second electrode D5 of T5;

[0395] The line labeled CK1 is the first clock signal line, the line labeled CK2 is the second clock signal line, and the line labeled CK3 is the third clock signal line.

[0396] exist Figure 2E In the diagram, the electrode labeled S11 is the first electrode of T11. Figure 3E and Figure 4E In this process, the second electrode D3 of T3 is reused as the first electrode of T11;

[0397] exist Figure 2E and Figure 3E In the diagram, the electrode labeled D3 is the second electrode of T3; in Figure 4E In this process, the second electrode D2 of T2 is reused as the second electrode of T3.

[0398] exist Figure 2F , Figure 3F and Figure 4F In the diagram, VGL-1 is the first second voltage line, ESTV is the third start signal line, GSTTVN is the first start signal line, GSTVP is the second start signal line, VGH is the first voltage line, and VGL-2 is the second second voltage line.

[0399] exist Figure 2A , Figure 2G , Figure 3A , Figure 3G and Figure 4A , Figure 4G The diagram shows a via through the interlayer dielectric layer for connecting the active layer and the first source / drain metal layer, a via through the passivation layer for connecting the gate metal layer and the first source / drain metal layer, and a via through the planarization layer for connecting the first source / drain metal layer and the second source / drain metal layer.

[0400] In this design, vias penetrating the interlayer dielectric layer are marked with black circles, vias penetrating the passivation layer are marked with black squares, and vias penetrating the planarization layer are marked with a mark containing a multiplication sign within a rectangle.

[0401] like Figures 2A-2G , Figures 3A-3G , Figures 4A-4G As shown, the third clock signal line CK3, the first clock signal line CK1, the first second voltage line VGL-1, the third start signal line ESTV, the first start signal line GSTTVN, the second start signal line GSTVP, the second clock signal line CK2, the first voltage line VGH, and the second second voltage line VGL-2 are arranged sequentially along the direction closest to the display area.

[0402] The third clock signal line CK3, the first clock signal line CK1, the first second voltage line VGL-1, the third start signal line ESTV, the first start signal line GSTVN, the second start signal line GSTVP, the second clock signal line CK2, the first voltage line VGH, and the second second voltage line VGL-2 all extend vertically.

[0403] The sum of the horizontal widths of the third clock signal line CK3, the first clock signal line CK1, the first second voltage line VGL-1, the third start signal line ESTV, the first start signal line GSTTVN, the second start signal line GSTVP, the second clock signal line CK2, the first voltage line VGH, and the second second voltage line VGL-2 is W1.

[0404] The product of W1 / W2 and the pixel pitch value P0 is greater than 18µm but less than 40µm;

[0405] The ratio of at least one of the horizontal widths of the first second voltage line VGL-1, the first voltage line VGH, and the second second voltage line VGL-2 to W2 is greater than or equal to 0.15; for example, the ratio can be 0.15, 0.16, 0.17, 0.18, 0.19, 0.2, 0.21, 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, or 0.3, but is not limited thereto;

[0406] The ratio of at least one of the horizontal widths of the third clock signal line CK3, the first clock signal line CK1, and the second clock signal line CK2 to W2 is greater than or equal to 0.015; for example, the ratio may be equal to 0.015, 0.016, 0.017, 0.018, 0.019, 0.02, 0.021, 0.022, 0.023, 0.024, 0.025, 0.026, 0.027, 0.028, 0.029, or 0.03, but is not limited thereto.

[0407] exist Figures 2A-2G , Figures 3A-3G , Figures 4A-4G In the illustrated embodiment, the ratio of at least one of the horizontal width of the first second voltage line VGL-1, the horizontal width of the first voltage line VGH, and the horizontal width of the second second voltage line VGL-2 to W2 can also be greater than or equal to 0.3; for example, the ratio can be equal to 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, 0.41, 0.42, 0.43, 0.44, 0.45, 0.46, 0.47, 0.48, 0.49, or 0.5, but is not limited thereto;

[0408] The ratio of at least one of the horizontal widths of the third clock signal line CK3, the first clock signal line CK1, and the second clock signal line CK2 to W2 can also be greater than 0.03; for example, this ratio can be equal to 0.03, 0.031, 0.032, 0.033, 0.034, 0.035, 0.036, 0.037, etc. 0.038, 0.039, 0.04, 0.041, 0.042, 0.043, 0.044, 0.045, 0.046, 0.047, 0.048, 0.049, 0.05, 0.051, 0.052, 0.053, 0.054, 0.055, 0.056, 0.057, 0.058, 0.059 or 0.06; but not limited to these values.

[0409] like Figures 2A-2G , Figures 3A-3G , Figures 4A-4G As shown, T1, T12, T11, T2 and T3 are set between CK1 and GSTVP. T12, T3 and T1 are set from top to bottom, and T11 and T2 are set from top to bottom.

[0410] The orthographic projection of the first electrode plate C2a on the substrate and the orthographic projection of the first voltage line VGH on the substrate partially overlap; the orthographic projection of the second electrode plate C2b on the substrate and the orthographic projection of the first voltage line VGH on the substrate partially overlap.

[0411] T4, T5, T13, T8, T7 and T6 are set between GSTTVN and VGL-2.

[0412] like Figure 2E , Figure 3E and Figure 4E As shown, the second electrode D9 of T9 is connected to the first electrode S10 of T10. The first electrode S10 of T10 is coupled to the first conductive connection L1 through a via. The first conductive connection L1 is coupled to the drive signal output terminal OUTPUT through a via, so that the second electrode D9 of T9 and the first electrode S10 of T10 are both coupled to the drive signal output terminal OUTPUT.

[0413] exist Figure 2C , Figure 3C , Figure 4C In the diagram, L2 is the second conductive connection part, which is connected to the gate G10 of T10; the second conductive connection part L2 is coupled to the second electrode D12 of T12 through a via, so that the gate G10 of T10 is coupled to the second electrode D12 of T12.

[0414] like Figures 2A-2G , Figures 3A-3G , Figures 4A-4G As shown, the part labeled L3 is the third conductive connection part;

[0415] The third conductive connection part L3 is coupled to the first electrode S12 of T12 through a via, and the third conductive connection part L3 is coupled to the second electrode D13 of T13 through a via, so that the first electrode S12 of T12 and the second electrode D13 of T13 are coupled.

[0416] The part labeled L4 is the fourth conductive connection part;

[0417] The fourth conductive connection part L4 is coupled to the third conductive connection part L3. The fourth conductive connection part L4 is coupled to the second electrode D1 of T1 through a through hole, so that the first electrode S12 of T12 is coupled to the second electrode D1 of T1.

[0418] The part labeled L5 is the fifth conductive connection part, and the part labeled L6 is the sixth conductive connection part;

[0419] The fifth conductive connection part L5 is coupled to the first clock signal line CK1 through a via. The fifth conductive connection part L5 is coupled to the first electrode S6 of T6 through a via. The first electrode S6 of T6 is connected to the first electrode S4 of T4, so that the first electrode S6 of T6 is coupled to the first clock signal line CK1, and the first electrode S4 of T4 is coupled to the first clock signal line CK1.

[0420] like Figures 2A-2G , Figures 3A-3G , Figures 4A-4G As shown, the first electrode S13 of T13 is coupled to the sixth conductive connection L6.

[0421] like Figures 2A-2G , Figures 3A-3G , Figures 4A-4G As shown, the second electrode D10 of T10 is coupled to the second voltage line VGL-2 through a via;

[0422] The first electrode S13 of T13 is coupled to the first voltage line VGH through a via;

[0423] The first electrode S9 of T9 is coupled to the sixth conductive connection L6, and the sixth conductive connection L6 is coupled to the second electrode plate C2b of C2 through a through hole.

[0424] Figure 5B yes Figure 5A Layout diagram of the active layer in the middle. Figure 5C yes Figure 5A Layout diagram of the first gate metal layer in the middle. Figure 5D yes Figure 5A The layout diagram of the second gate metal layer in the middle, Figure 5E yes Figure 5A Layout diagram of the first source / drain metal layer in the middle. Figure 5F yes Figure 5A The layout diagram of the second source / drain metal layer in the image.

[0425] like Figure 5B As shown, channel 10 is T1, channel 20 is T2, channel 30 is T3, channel 40 is T4, channel 50 is T5, channel 60 is T6, channel 70 is T7, channel 80 is T8, channel 90 is T9, channel C10 is T10, channel 110 is T11, channel 120 is T12, and channel 130 is T13.

[0426] like Figure 5CAs shown, C1a is the first plate of the first capacitor C1, C2a is the first plate of the second capacitor C2, and C3a is the first plate of the third capacitor C3.

[0427] The gate labeled G1 is the gate of T1, the gate labeled G2-1 is the first gate of T2, the gate labeled G2-2 is the second gate of T2, the gate labeled G3 is the gate of T3, the gate labeled G4 is the gate of T4, the gate labeled G5 is the gate of T5, the gate labeled G6 is the gate of T6, the gate labeled G7 is the gate of T7, the gate labeled G8 is the gate of T8, the gate labeled G9 is the gate of T9, the gate labeled G10 is the gate of T10, the gate labeled G11 is the gate of T11, the gate labeled G12 is the gate of T12, and the gate labeled G13 is the gate of T13.

[0428] like Figure 5D As shown, C1b is the second plate of the first capacitor C1, C2b is the second plate of the second capacitor C2, and C3b is the second plate of the third capacitor C3.

[0429] The part labeled L1 is the first conductive connection part.

[0430] like Figure 5E As shown, the terminal labeled INPUT is the input terminal, and the terminal labeled OUTPUT is the drive signal output terminal;

[0431] The electrode labeled S1 is the first electrode of T1, and the electrode labeled D1 is the second electrode of T1;

[0432] The electrode labeled S2 is the first electrode of T2, and the electrode labeled D2 is the second electrode of T2;

[0433] The electrode labeled S3 is the first electrode of T3, and the electrode labeled D3 is the second electrode of T3;

[0434] The electrode labeled S4 is the first electrode of T4, and the electrode labeled D4 is the second electrode of T4;

[0435] The electrode labeled S6 is the first electrode of T6, and the electrode labeled D6 is the second electrode of T6;

[0436] The electrode labeled S7 is the first electrode of T7, the electrode labeled D7 is the second electrode of T7, and the electrode labeled S8 is the first electrode of T8.

[0437] The electrode labeled S9 is the first electrode of T9, and the electrode labeled D9 is the second electrode of T9;

[0438] The electrode labeled S10 is the first electrode of T10, and the electrode labeled D10 is the second electrode of T10;

[0439] The electrode labeled S11 is the first electrode of T11, and the electrode labeled D11 is the second electrode of T11.

[0440] The electrode labeled S12 is the first electrode of T12, and the electrode labeled D12 is the second electrode of T12;

[0441] The electrode labeled S13 is the first electrode of T13, and the electrode labeled D13 is the second electrode of T13;

[0442] The first electrode S13 of T13 is reused as the first electrode of T5 and the second electrode of T8; the second electrode D4 of T4 is reused as the second electrode D5 of T5.

[0443] The line labeled CK1 is the first clock signal line, the line labeled CK2 is the second clock signal line, and the line labeled CK3 is the third clock signal line.

[0444] exist Figure 5F In the diagram, VGL-1 is the first second voltage line, ESTV is the third start signal line, GSTTVN is the first start signal line, GSTVP is the second start signal line, VGH is the first voltage line, and VGL-2 is the second second voltage line.

[0445] exist Figure 5A and 5G The diagram shows a via through the interlayer dielectric layer for connecting the active layer and the first source / drain metal layer, and a via through the passivation layer for connecting the gate metal layer and the first source / drain metal layer.

[0446] Vias penetrating the interlayer dielectric layer are marked with black circles, and vias penetrating the passivation layer are marked with black squares.

[0447] like Figures 5A-5G As shown, the orthographic projection of the second clock signal line CK2 on the substrate partially overlaps with the orthographic projection of the first voltage line VGH on the substrate.

[0448] like Figures 5A-5G As shown, the third clock signal line CK3, the first clock signal line CK1, the first second voltage line VGL-1, the third start signal line ESTV, the first start signal line GSTTVN, the second start signal line GSTVP, the first voltage line VGH, and the second second voltage line VGL-2 are arranged along the direction closest to the display area.

[0449] The third clock signal line CK3, the first clock signal line CK1, the first second voltage line VGL-1, the third start signal line ESTV, the first start signal line GSTVN, the second start signal line GSTVP, the first voltage line VGH, the second clock signal line CK2, and the second second voltage line VGL-2 extend vertically.

[0450] like Figures 5A-5G As shown, the sum of the horizontal widths of the first voltage line VGH, the second clock signal line CK2, the third clock signal line CK3, the first clock signal line CK1, the first second voltage line VGL-1, the third start signal line ESTV, the first start signal line GSTVN, the second start signal line GSTVP, and the second clock signal line CK2 is W1.

[0451] The product of W1 / W2 and the pixel pitch value P0 is greater than 18µm but less than 40µm;

[0452] The sum of the horizontal width of the first second voltage line VGL-1, the horizontal width of the first voltage line VGH, and the horizontal width of the second second voltage line VGL-2 is W3.

[0453] W3 / W2 is greater than or equal to 0.15; or, W3 / W2 is greater than or equal to 0.3; for example, W3 / W2 can be equal to 0.015, 0.16, 0.17, 0.18, 0.19, 0.2, 0.21, 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, 0.41, 0.42, 0.43, 0.44, 0.45, 0.46, 0.47, 0.48, 0.49, or 0.5, but is not limited to these values;

[0454] The sum of the horizontal width of the third clock signal line CK3, the horizontal width of the first clock signal line CK1, and the horizontal width of the second clock signal line CK2 is W4.

[0455] W4 / W2 is greater than or equal to 0.015; or, W4 / W2 is greater than or equal to 0.03; for example, W4 / W2 can be equal to 0.015, 0.016, 0.017, 0.018, 0.019, 0.02, 0.021, 0.022, 0.023, 0.024, 0.025, 0.026, 0.027, 0.028, 0. 029, 0.03, 0.031, 0.032, 0.033, 0.034, 0.035, 0.036, 0.037, 0.038, 0.039, 0.04, 0.041, 0.042, 0.043, 0.044, 0.045, 0.046, 0.047, 0.048, 0.049 or 0.05, but not limited to these.

[0456] like Figures 5A-5G As shown, T1, T12, T11, T2 and T3 are set between CK1 and GSTVP. T12, T3 and T1 are set from top to bottom, and T11 and T2 are set from top to bottom.

[0457] The orthographic projection of the first electrode plate C2a on the substrate and the orthographic projection of the first voltage line VGH on the substrate partially overlap; the orthographic projection of the second electrode plate C2b on the substrate and the orthographic projection of the first voltage line VGH on the substrate partially overlap.

[0458] T4, T5, T13, T8, T7 and T6 are set between GSTTVN and VGL-2.

[0459] like Figure 5E As shown, the second electrode D9 of T9 is connected to the first electrode S10 of T10. The first electrode S10 of T10 is coupled to the first conductive connection L1 through a via. The first conductive connection L1 is coupled to the drive signal output terminal OUTPUT through a via, so that the second electrode D9 of T9 and the first electrode S10 of T10 are both coupled to the drive signal output terminal OUTPUT.

[0460] exist Figure 5C In the diagram, L2 is the second conductive connection part L2, which is connected to the gate G10 of T10; the second conductive connection part L2 is coupled to the second electrode D12 of T12 through a via, so that the gate G10 of T10 is coupled to the second electrode D12 of T12.

[0461] like Figure 5G As shown, the part labeled L3 is the third conductive connection part;

[0462] The third conductive connection part L3 is coupled to the first electrode S12 of T12 through a via, and the third conductive connection part L3 is coupled to the second electrode D13 of T13 through a via, so that the first electrode S12 of T12 and the second electrode D13 of T13 are coupled.

[0463] The part labeled L4 is the fourth conductive connection part;

[0464] The fourth conductive connection part L4 is coupled to the third conductive connection part L3. The fourth conductive connection part L4 is coupled to the second electrode D1 of T1 through a through hole, so that the first electrode S12 of T12 is coupled to the second electrode D1 of T1.

[0465] The part labeled L5 is the fifth conductive connection part;

[0466] The fifth conductive connection part L5 is coupled to the first clock signal line CK1 through a via. The fifth conductive connection part L5 is coupled to the first electrode S6 of T6 through a via. The first electrode S6 of T6 is connected to the first electrode S4 of T4, so that the first electrode S6 of T6 is coupled to the first clock signal line CK1, and the first electrode S4 of T4 is coupled to the first clock signal line CK1.

[0467] like Figures 5A-5G As shown, the first electrode S13 of T13 is coupled to the sixth conductive connection L6.

[0468] like Figures 5A-5G As shown, the second electrode D10 of T10 is coupled to the second voltage line VGL-2 through a via;

[0469] The first electrode S13 of T13 is coupled to the first voltage line VGH through a via;

[0470] The first electrode S9 of T9 is coupled to the sixth conductive connection L6. The sixth conductive connection L6 is coupled to the second electrode C2b of C2 through a via, so that the first electrode S9 of T9, the first electrode S13 of T13, the second electrode C2b of C2 and the first voltage line VGH are coupled to each other.

[0471] Figure 6B yes Figure 6A Layout diagram of the active layer in the middle. Figure 6C yes Figure 6A Layout diagram of the first gate metal layer in the middle. Figure 6D yes Figure 6A The layout diagram of the second gate metal layer in the middle, Figure 6E yes Figure 6A Layout diagram of the first source / drain metal layer in the middle. Figure 6F yes Figure 6A The layout diagram of the second source / drain metal layer in the image.

[0472] like Figure 6B As shown, channel 10 is T1, channel 20 is T2, channel 30 is T3, channel 40 is T4, channel 50 is T5, channel 60 is T6, channel 70 is T7, channel 80 is T8, channel 90 is T9, channel C10 is T10, channel 110 is T11, channel 120 is T12, and channel 130 is T13.

[0473] like Figure 6C As shown, C1a is the first plate of the first capacitor C1, C2a is the first plate of the second capacitor C2, and C3a is the first plate of the third capacitor C3.

[0474] The gate labeled G1 is the gate of T1, the gate labeled G2-1 is the first gate of T2, the gate labeled G2-2 is the second gate of T2, the gate labeled G3 is the gate of T3, the gate labeled G4 is the gate of T4, the gate labeled G5 is the gate of T5, the gate labeled G6 is the gate of T6, the gate labeled G7 is the gate of T7, the gate labeled G8 is the gate of T8, the gate labeled G9 is the gate of T9, the gate labeled G10 is the gate of T10, the gate labeled G11 is the gate of T11, the gate labeled G12 is the gate of T12, and the gate labeled G13 is the gate of T13.

[0475] like Figure 6D As shown, C1b is the second plate of the first capacitor C1, C2b is the second plate of the second capacitor C2, and C3b is the second plate of the third capacitor C3.

[0476] The part labeled L1 is the first conductive connection part.

[0477] like Figure 6E As shown, the terminal labeled INPUT is the input terminal, and the terminal labeled OUTPUT is the drive signal output terminal;

[0478] The electrode labeled S1 is the first electrode of T1, and the electrode labeled D1 is the second electrode of T1;

[0479] The electrode labeled S2 is the first electrode of T2, and the electrode labeled D2 is the second electrode of T2;

[0480] The electrode labeled S3 is the first electrode of T3, and the electrode labeled D3 is the second electrode of T3;

[0481] The electrode labeled S4 is the first electrode of T4, and the electrode labeled D4 is the second electrode of T4;

[0482] The electrode labeled S6 is the first electrode of T6, and the electrode labeled D6 is the second electrode of T6;

[0483] The electrode labeled S8 is the first electrode of T8;

[0484] The second electrode D6 of T6 is reused as the first electrode of T7, and the first electrode S8 of T8 is reused as the second electrode of T7;

[0485] The electrode labeled S9 is the first electrode of T9, and the electrode labeled D9 is the second electrode of T9;

[0486] The electrode labeled S10 is the first electrode of T10, and the electrode labeled D10 is the second electrode of T10;

[0487] The electrode labeled S11 is the first electrode of T11, and the electrode labeled D11 is the second electrode of T11.

[0488] The electrode labeled S12 is the first electrode of T12, and the electrode labeled D12 is the second electrode of T12;

[0489] The electrode labeled S13 is the first electrode of T13, and the electrode labeled D13 is the second electrode of T13;

[0490] The first electrode S13 of T13 is reused as the first electrode of T5 and the second electrode of T8; the second electrode D4 of T4 is reused as the second electrode D5 of T5.

[0491] The line labeled CK1 is the first clock signal line, the line labeled CK2 is the second clock signal line, and the line labeled CK3 is the third clock signal line.

[0492] exist Figure 6F In the diagram, VGL-1 is the first second voltage line, ESTV is the third start signal line, GSTTVN is the first start signal line, GSTVP is the second start signal line, VGH is the first voltage line, and VGL-2 is the second second voltage line.

[0493] exist Figure 6A and Figure 6G The diagram shows a via through the interlayer dielectric layer for connecting the active layer and the first source / drain metal layer, and a via through the passivation layer for connecting the gate metal layer and the first source / drain metal layer.

[0494] Vias penetrating the interlayer dielectric layer are marked with black circles, and vias penetrating the passivation layer are marked with black squares.

[0495] like Figures 6A-6GAs shown, the third clock signal line CK3, the first clock signal line CK1, the first second voltage line VGL-1, the third start signal line ESTV, the first start signal line GSTTVN, the second start signal line GSTVP, the second clock signal line CK2, the first voltage line VGH, and the second second voltage line VGL-2 are arranged sequentially along the direction closest to the display area.

[0496] The third clock signal line CK3, the first clock signal line CK1, the first second voltage line VGL-1, the third start signal line ESTV, the first start signal line GSTVN, the second start signal line GSTVP, the second clock signal line CK2, the first voltage line VGH, and the second second voltage line VGL-2 all extend vertically.

[0497] The sum of the horizontal widths of the third clock signal line CK3, the first clock signal line CK1, the first second voltage line VGL-1, the third start signal line ESTV, the first start signal line GSTTVN, the second start signal line GSTVP, the second clock signal line CK2, the first voltage line VGH, and the second second voltage line VGL-2 is W1.

[0498] The product of W1 / W2 and the pixel pitch value P0 is greater than 18µm but less than 40µm;

[0499] The sum of the horizontal width of the first second voltage line VGL-1, the horizontal width of the first voltage line VGH, and the horizontal width of the second second voltage line VGL-2 is W3.

[0500] W3 / W2 is greater than or equal to 0.15; or, W3 / W2 is greater than 0.3; for example, W3 / W2 can be equal to 0.015, 0.16, 0.17, 0.18, 0.19, 0.2, 0.21, 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, 0.41, 0.42, 0.43, 0.44, 0.45, 0.46, 0.47, 0.48, 0.49, or 0.5, but is not limited to these values;

[0501] The sum of the horizontal width of the third clock signal line CK3, the horizontal width of the first clock signal line CK1, and the horizontal width of the second clock signal line CK2 is W4.

[0502] W4 / W2 is greater than or equal to 0.015; or, W4 / W2 is greater than or equal to 0.03; for example, W4 / W2 can be equal to 0.015, 0.016, 0.017, 0.018, 0.019, 0.02, 0.021, 0.022, 0.023, 0.024, 0.025, 0.026, 0.027, 0.028, 0. 029, 0.03, 0.031, 0.032, 0.033, 0.034, 0.035, 0.036, 0.037, 0.038, 0.039, 0.04, 0.041, 0.042, 0.043, 0.044, 0.045, 0.046, 0.047, 0.048, 0.049 or 0.05, but not limited to these.

[0503] like Figures 6A-6G As shown, T1, T12, T11, T2 and T3 are set between CK1 and GSTVP. T12, T3 and T1 are set from top to bottom, and T11 and T2 are set from top to bottom.

[0504] The orthographic projection of the first electrode plate C2a on the substrate and the orthographic projection of the first voltage line VGH on the substrate partially overlap; the orthographic projection of the second electrode plate C2b on the substrate and the orthographic projection of the first voltage line VGH on the substrate partially overlap.

[0505] T4, T5, T13, T8, T7 and T6 are set between GSTTVN and VGL-2.

[0506] like Figure 6E As shown, the second electrode D9 of T9 is connected to the first electrode S10 of T10. The first electrode S10 of T10 is coupled to the first conductive connection L1 through a via. The first conductive connection L1 is coupled to the drive signal output terminal OUTPUT through a via, so that the second electrode D9 of T9 and the first electrode S10 of T10 are both coupled to the drive signal output terminal OUTPUT.

[0507] exist Figure 6C In the diagram, L2 is the second conductive connection part, which is connected to the gate G10 of T10; the second conductive connection part L2 is coupled to the second electrode D12 of T12 through a via, so that the gate G10 of T10 is coupled to the second electrode D12 of T12.

[0508] like Figures 6A-6G As shown, the part labeled L3 is the third conductive connection part;

[0509] The third conductive connection part L3 is coupled to the first electrode S12 of T12 through a via, and the third conductive connection part L3 is coupled to the second electrode D13 of T13 through a via, so that the first electrode S12 of T12 and the second electrode D13 of T13 are coupled.

[0510] The part labeled L4 is the fourth conductive connection part;

[0511] The fourth conductive connection part L4 is coupled to the third conductive connection part L3. The fourth conductive connection part L4 is coupled to the second electrode D1 of T1 through a through hole, so that the first electrode S12 of T12 is coupled to the second electrode D1 of T1.

[0512] The part labeled L5 is the fifth conductive connection part, and the part labeled L6 is the sixth conductive connection part;

[0513] The fifth conductive connection L5 is coupled to the first clock signal line CK1 through a via, and the fifth conductive connection L5 is coupled to the sixth conductive connection L6 through a via. The sixth conductive connection L6 is connected to the first electrode S4 of T4, so that the first electrode S4 of T4 is coupled to the first clock signal line CK1.

[0514] The fifth conductive connection part L5 is also coupled to the first electrode S6 of T6 through a via, so that the first electrode S6 of T6 is coupled to the first clock signal line CK1.

[0515] The second electrode D6 of T6 is coupled to the second electrode plate C1b of C1 through a via.

[0516] like Figures 6A-6G As shown, the first electrode S13 of T13 is coupled to the seventh conductive connection L7.

[0517] like Figures 6A-6G As shown, the second electrode D10 of T10 is coupled to the second voltage line VGL-2 through a via;

[0518] The first electrode S13 of T13 is coupled to the first voltage line VGH through a via;

[0519] The first electrode S9 of T9 is coupled to the seventh conductive connection L7. The seventh conductive connection L7 is coupled to the second electrode C2b of C2 through a via, so that the first electrode S9 of T9, the first electrode S13 of T13, the second electrode C2b of C2 and the first voltage line VGH are coupled to each other.

[0520] Figure 7B yes Figure 7A Layout diagram of the active layer in the middle. Figure 7C yes Figure 7A Layout diagram of the first gate metal layer in the middle. Figure 7D yes Figure 7AThe layout diagram of the second gate metal layer in the middle, Figure 7E yes Figure 7A Layout diagram of the first source / drain metal layer in the middle. Figure 7F yes Figure 7A The layout diagram of the second source / drain metal layer in the image.

[0521] like Figure 7B As shown, channel 10 is T1, channel 20 is T2, channel 30 is T3, channel 40 is T4, channel 50 is T5, channel 60 is T6, channel 70 is T7, channel 80 is T8, channel 90 is T9, channel C10 is T10, channel 110 is T11, channel 120 is T12, and channel 130 is T13.

[0522] like Figure 7C As shown, C1a is the first plate of the first capacitor C1, C2a is the first plate of the second capacitor C2, and C3a is the first plate of the third capacitor C3.

[0523] The gate labeled G1 is the gate of T1, the gate labeled G2-1 is the first gate of T2, the gate labeled G2-2 is the second gate of T2, the gate labeled G3 is the gate of T3, the gate labeled G4 is the gate of T4, the gate labeled G5 is the gate of T5, the gate labeled G6 is the gate of T6, the gate labeled G7 is the gate of T7, the gate labeled G8 is the gate of T8, the gate labeled G9 is the gate of T9, the gate labeled G10 is the gate of T10, the gate labeled G11 is the gate of T11, the gate labeled G12 is the gate of T12, and the gate labeled G13 is the gate of T13.

[0524] like Figure 7D As shown, C1b is the second plate of the first capacitor C1, C2b is the second plate of the second capacitor C2, and C3b is the second plate of the third capacitor C3.

[0525] The part labeled L1 is the first conductive connection part.

[0526] like Figure 7E As shown, the terminal labeled INPUT is the input terminal, and the terminal labeled OUTPUT is the drive signal output terminal;

[0527] The electrode labeled S1 is the first electrode of T1; the first electrode S12 of T12 is reused as the second electrode of T1.

[0528] The electrode labeled S2 is the first electrode of T2, and the electrode labeled D2 is the second electrode of T2;

[0529] The electrode labeled S3 is the first electrode of T3, and the electrode labeled D3 is the second electrode of T3;

[0530] The electrode labeled S4 is the first electrode of T4, and the electrode labeled D4 is the second electrode of T4;

[0531] The electrode labeled S6 is the first electrode of T6, and the electrode labeled D6 is the second electrode of T6;

[0532] The second electrode D6 of T6 is reused as the first electrode of T7, and the first electrode of T8 is reused as the second electrode of T7;

[0533] The electrode labeled S9 is the first electrode of T9, and the electrode labeled D9 is the second electrode of T9;

[0534] The electrode labeled S10 is the first electrode of T10, and the electrode labeled D10 is the second electrode of T10;

[0535] The electrode labeled S11 is the first electrode of T11, and the electrode labeled D11 is the second electrode of T11.

[0536] The electrode labeled S12 is the first electrode of T12, and the electrode labeled D12 is the second electrode of T12;

[0537] The electrode labeled S13 is the first electrode of T13, and the electrode labeled D13 is the second electrode of T13;

[0538] The first electrode S13 of T13 is reused as the first electrode of T5 and the second electrode of T8; the second electrode D4 of T4 is reused as the second electrode of T5.

[0539] The line labeled CK1 is the first clock signal line, the line labeled CK2 is the second clock signal line, and the line labeled CK3 is the third clock signal line.

[0540] exist Figure 7F In the diagram, VGL-1 is the first second voltage line, ESTV is the third start signal line, GSTTVN is the first start signal line, GSTVP is the second start signal line, VGH is the first voltage line, and VGL-2 is the second second voltage line.

[0541] exist Figure 7A and Figure 7G The diagram shows a via through the interlayer dielectric layer for connecting the active layer and the first source / drain metal layer, and a via through the passivation layer for connecting the gate metal layer and the first source / drain metal layer.

[0542] Vias penetrating the interlayer dielectric layer are marked with black circles, and vias penetrating the passivation layer are marked with black squares.

[0543] like Figures 7A-7G As shown, the third clock signal line CK3, the first clock signal line CK1, the first second voltage line VGL-1, the third start signal line ESTV, the first start signal line GSTTVN, the second start signal line GSTVP, the second clock signal line CK2, the first voltage line VGH, and the second second voltage line VGL-2 are arranged sequentially along the direction closest to the display area.

[0544] The third clock signal line CK3, the first clock signal line CK1, the first second voltage line VGL-1, the third start signal line ESTV, the first start signal line GSTVN, the second start signal line GSTVP, the second clock signal line CK2, the first voltage line VGH, and the second second voltage line VGL-2 all extend vertically.

[0545] The sum of the horizontal widths of the third clock signal line CK3, the first clock signal line CK1, the first second voltage line VGL-1, the third start signal line ESTV, the first start signal line GSTTVN, the second start signal line GSTVP, the second clock signal line CK2, the first voltage line VGH, and the second second voltage line VGL-2 is W1.

[0546] The product of W1 / W2 and the pixel pitch value P0 is greater than 18µm but less than 40µm;

[0547] The sum of the horizontal width of the first second voltage line VGL-1, the horizontal width of the first voltage line VGH, and the horizontal width of the second second voltage line VGL-2 is W3.

[0548] W3 / W2 is greater than or equal to 0.15; or, W3 / W2 is greater than or equal to 0.3; for example, W3 / W2 can be equal to 0.15, 0.16, 0.17, 0.18, 0.19, 0.2, 0.21, 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, 0.41, 0.42, 0.43, 0.44, 0.45, 0.46, 0.47, 0.48, 0.49, or 0.5, but is not limited to these values;

[0549] The sum of the horizontal width of the third clock signal line CK3, the horizontal width of the first clock signal line CK1, and the horizontal width of the second clock signal line CK2 is W4.

[0550] W4 / W2 is greater than or equal to 0.015; or, W4 / W2 is greater than or equal to 0.03; for example, W4 / W2 can be equal to 0.015, 0.016, 0.017, 0.018, 0.019, 0.02, 0.021, 0.022, 0.023, 0.024, 0.025, 0.026, 0.027, 0.028, 0. 029, 0.03, 0.031, 0.032, 0.033, 0.034, 0.035, 0.036, 0.037, 0.038, 0.039, 0.04, 0.041, 0.042, 0.043, 0.044, 0.045, 0.046, 0.047, 0.048, 0.049 or 0.05, but not limited to these.

[0551] like Figures 7A-7G As shown, T12, T11, T2 and T3 are set between CK1 and GSTVP. T12, T3 and T1 are set from top to bottom, and T11 and T2 are set from top to bottom.

[0552] The orthographic projection of the first electrode plate C2a on the substrate and the orthographic projection of the first voltage line VGH on the substrate partially overlap; the orthographic projection of the second electrode plate C2b on the substrate and the orthographic projection of the first voltage line VGH on the substrate partially overlap.

[0553] T1, T4, T5, T13, T8, T7 and T6 are set between GSTTVN and VGL-2.

[0554] like Figure 7E As shown, the second electrode D9 of T9 is connected to the first electrode S10 of T10. The first electrode S10 of T10 is coupled to the first conductive connection L1 through a via. The first conductive connection L1 is coupled to the drive signal output terminal OUTPUT through a via, so that the second electrode D9 of T9 and the first electrode S10 of T10 are both coupled to the drive signal output terminal OUTPUT.

[0555] exist Figure 7C In the diagram, L2 is the second conductive connection part, which is connected to the gate G10 of T10; the second conductive connection part L2 is coupled to the first plate C3b of C3, so that the gate G10 of T10 is coupled to the first plate C3b of C3.

[0556] The gate G4 of T4 is coupled to the second conductive connection L2, so that the gate G4 of T4 is coupled to the gate G10 of T10.

[0557] The second electrode D12 of T12 is coupled to the gate G4 of T4 through a via;

[0558] like Figures 7A-7G As shown, the first electrode S12 of T12 is coupled to the second electrode D13 of T13;

[0559] The part labeled L5 is the fifth conductive connection part, and the part labeled L6 is the sixth conductive connection part;

[0560] The fifth conductive connection L5 is coupled to the first clock signal line CK1 through a via, and the fifth conductive connection L5 is coupled to the sixth conductive connection L6 through a via. The sixth conductive connection L6 is connected to the first electrode S4 of T4, so that the first electrode S4 of T4 is coupled to the first clock signal line CK1.

[0561] The fifth conductive connection part L5 is also coupled to the first electrode S6 of T6 through a via, so that the first electrode S6 of T6 is coupled to the first clock signal line CK1.

[0562] The second electrode D6 of T6 is coupled to the eighth conductive connection L8 through a via. The eighth conductive connection L8 is coupled to the ninth conductive connection L9 through a via. The ninth conductive connection L9 is coupled to the second electrode C1b of C1 through a via, so that the second electrode D6 of T6 is coupled to the second electrode C1b of C1. The second electrode C1b of C1 is connected to the gate G6 of T6.

[0563] like Figures 7A-7G As shown, the first electrode S13 of T13 is coupled to the seventh conductive connection L7.

[0564] like Figures 7A-7G As shown, the second electrode D10 of T10 is coupled to the second voltage line VGL-2 through a via;

[0565] The first electrode S13 of T13 is coupled to the first voltage line VGH through a via, and the first electrode S9 of T9 is coupled to the seventh conductive connection L7. The seventh conductive connection L7 and the second electrode C2b of C2 are coupled through a via, so that the first electrode S9 of T9, the first electrode S13 of T13, the second electrode C2b of C2 and the first voltage line VGH are coupled to each other.

[0566] In at least one embodiment of the present invention, the shift register unit may include multiple signal lines, multiple transistors, and multiple capacitors;

[0567] like Figure 9As shown, the multiple signal lines include a first voltage line VGH, a second voltage line VGL, a first clock signal line CK1, and a second clock signal line CK2; the multiple transistors include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12; the multiple capacitors include: a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0568] The gate of the first transistor T1 is coupled to the first clock signal line CK1, the first electrode of the first transistor T1 is coupled to the input terminal INPUT, and the second electrode of the first transistor T1 is coupled to the gate of the second transistor T2.

[0569] The first electrode of the second transistor T2 is coupled to the first clock signal line CK1, and the second electrode of the second transistor T2 is coupled to the second electrode of the third transistor T3;

[0570] The gate of the third transistor T3 is coupled to the first clock signal line, and the first electrode of the third transistor T3 is coupled to the second voltage line VGL.

[0571] The gate of the fourth transistor T4 is coupled to the second clock signal line CK2, the first electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5, and the second electrode of the fourth transistor T4 is coupled to the gate of the second transistor T2.

[0572] The gate of the fifth transistor T5 is coupled to the second electrode of the third transistor T3, and the first electrode of the fifth transistor T5 is coupled to the first voltage line VGH.

[0573] The gate of the sixth transistor T6 is coupled to the second electrode of the eleventh transistor T11, the first electrode of the sixth transistor T6 is coupled to the second clock signal line CK2, and the second electrode of the sixth transistor T6 is coupled to the first electrode of the seventh transistor T7.

[0574] The gate of the seventh transistor T7 is coupled to the second clock signal line CK2, and the second electrode of the seventh transistor T7 is coupled to the gate of the ninth transistor T9.

[0575] The gate of the eighth transistor T8 is coupled to the gate of the second transistor T2, the first electrode of the eighth transistor T8 is coupled to the first voltage line VGH, and the second electrode of the eighth transistor T8 is coupled to the gate of the ninth transistor T9.

[0576] The first electrode of the ninth transistor T9 is coupled to the first voltage line VGH, and the second electrode of the ninth transistor T9 is coupled to the drive signal output terminal OUT.

[0577] The gate of the tenth transistor T10 is coupled to the second electrode of the twelfth transistor T12, the first electrode of the tenth transistor T10 is coupled to the second voltage line VGL, and the second electrode of the tenth transistor T10 is coupled to the drive signal output terminal OUT.

[0578] The gate of the eleventh transistor T11 is coupled to the second voltage line VGL, and the first electrode of the eleventh transistor T11 is coupled to the second electrode of the second transistor T2.

[0579] The gate of the twelfth transistor T12 is coupled to the second voltage line VGL, and the first electrode of the twelfth transistor T12 is coupled to the gate of the second transistor T2.

[0580] The first plate of the first capacitor C1 is coupled to the gate of the sixth transistor T6, and the second plate of the first capacitor C1 is coupled to the second electrode of the sixth transistor T6.

[0581] The first plate of the second capacitor C2 is coupled to the gate of the ninth transistor T9, and the second plate of the second capacitor C2 is coupled to the first voltage line VGH.

[0582] The first plate of the third capacitor C3 is coupled to the gate of the tenth transistor T10, and the second plate of the third capacitor C3 is coupled to the second clock signal line CK2.

[0583] In this embodiment of the invention, the structure of the shift register unit is not limited to... Figure 1 , Figure 9 As shown, the structure of the shift register unit can have other variations.

[0584] The display device described in this embodiment of the invention includes the display substrate described above.

[0585] The display device provided in this embodiment of the invention can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0586] The following is a diagram showing the relationship between the width W1 of multiple signal lines in the second direction of the drive circuit area where the shift register unit is located in various display products, the width W2 of the shift register unit in the second direction, and the pixel pitch value P0:

[0587] For display product 1, and the shift register unit is the first shift register unit providing n-type drive signals, W1 equals 94um, W2 equals 147um, W1 / W2 equals 0.64, the resolution is 1440×3088, the PPI is 494, the pixel pitch value P0 is 51.4um, 1000×(W1 / W2)×PPI equals 1.29, P0×(W1 / W2) equals 32.9um; PPI is the number of pixels per inch;

[0588] For display product 2, and the shift register unit is the first shift register unit that provides n-type drive signals, W1 equals 101.5um, W2 equals 243um, W1 / W2 equals 0.42, the resolution is 1768×2208, the PPI is 373, the pixel pitch value P0 is 68.01um, 1000×(W1 / W2)×PPI equals 1.12, and P0×(W1 / W2) equals 28.56um;

[0589] For display product 3, and the shift register unit is the first shift register unit that provides n-type drive signals, W1 equals 84.1um, W2 equals 151.6um, W1 / W2 equals 0.55, the resolution is 1440×3200, the PPI is 515, the pixel pitch value P0 is 49.32um, 1000×(W1 / W2)×PPI equals 1.08, and P0×(W1 / W2) equals 27.13um.

[0590] For the display product in a further extended embodiment, the relationship between the width W1 of the multiple signal lines in the driving circuit area where the shift register unit is located in the second direction, the width W2 of the shift register unit in the second direction, and the pixel pitch value P0 is as follows:

[0591] For display products with higher resolution, W1 equals 85um, W2 equals 150um, W1 / W2 equals 0.57, PPI is 500, pixel pitch P0 equals 46.2um, 100×(W1 / W2) / PPI equals 1.03, and P0×(W1 / W2) equals 26.32um.

[0592] For display products with narrower bezels, W1 equals 85um, W2 equals 130um, W1 / W2 equals 0.65, PPI equals 500, pixel pitch P0 equals 50.8um, 100×(W1 / W2) / PPI equals 1.3, and P0×(W1 / W2) equals 33.02um.

[0593] For display products with higher resolution and narrower bezels, W1 equals 85um, W2 equals 130um, W1 / W2 equals 0.65, PPI is 500, pixel pitch P0 equals 46.2um, 100×(W1 / W2) / PPI equals 1.19, and P0×(W1 / W2) equals 30.02um.

[0594] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A display substrate, characterized in that, include: The substrate includes a display area and a peripheral area located on at least one side of the display area; A pixel array, located in the display area, includes multiple pixel units; as well as, The scanning drive module, located in the drive circuit area of ​​the peripheral area, includes multiple shift register units. In one of the multiple shift register units, multiple signal lines are provided, and the multiple signal lines extend along a first direction. The shift register unit includes at least two transistors disposed in the driving circuit region; The active layers of the at least two transistors are formed of continuous semiconductor layers, and the orthographic projection of one of the multiple signal lines on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate. At least one of the at least two transistors includes a first electrode located on a first conductive layer, and one of the plurality of signal lines is located on a second conductive layer, configured to provide a DC power signal.

2. The display substrate as described in claim 1, characterized in that, The multiple signal lines include all the signal lines in the shift register unit.

3. The display substrate as described in claim 1, characterized in that, The plurality of signal lines includes all signal lines that overlap with the orthographic projection of the shift register unit onto the substrate.

4. The display substrate as described in claim 1, characterized in that, The ratio of the width W1 of the plurality of signal lines in the second direction to the width W2 of the shift register unit in the second direction is W1 / W2; the length of at least one pixel unit along the first direction is the pixel pitch value; the first direction intersects the second direction; The product of W1 / W2 and the pixel pitch value is greater than 18µm but less than 40µm.

5. The display substrate as described in claim 1, characterized in that, The ratio of the width of the plurality of signal lines in the second direction, W1, to the width of the shift register unit in the second direction, W2, is W1 / W2, where W1 / W2 is greater than 0.4 and less than 0.

7.

6. The display substrate as described in claim 4, characterized in that, The product of W1 / W2 and the pixel pitch value is greater than 18µm and less than or equal to 27µm.

7. The display substrate according to any one of claims 1 to 6, characterized in that, The display substrate includes a first conductive layer, an insulating layer, and a second conductive layer, wherein the insulating layer is disposed between the first conductive layer and the second conductive layer; At least one of the plurality of signal lines is disposed on the first conductive layer, and at least one of the plurality of signal lines is disposed on the second conductive layer.

8. The display substrate according to any one of claims 1 to 6, characterized in that, The shift register unit includes at least one transistor disposed in the driving circuit region, wherein the first electrode of the transistor, the second electrode of the transistor, and at least one of the plurality of signal lines are located on the same layer.

9. The display substrate according to any one of claims 1 to 6, characterized in that, The shift register unit includes at least one transistor disposed in the driving circuit region, wherein the first electrode of the transistor and the second electrode of the transistor are located on the same layer, and at least one of the plurality of signal lines is located on a different layer from the first electrode of the transistor.

10. The display substrate according to any one of claims 1 to 6, characterized in that, The shift register unit includes at least one signal line disposed in the driving circuit region, and the at least one signal line is configured to provide a DC power supply signal; The ratio W3 / W2 of the width W3 of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.

15.

11. The display substrate according to any one of claims 1 to 6, characterized in that, The shift register unit includes at least one signal line disposed in the driving circuit region, and the at least one signal line is configured to provide a clock signal; The ratio W4 / W2 of the width W4 of at least one of the at least one signal lines in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.

015.

12. The display substrate according to any one of claims 1 to 6, characterized in that, The shift register unit includes a fourth transistor and a fifth transistor; the second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor; The active layer of the fourth transistor and the active layer of the fifth transistor are formed from a continuous first semiconductor layer. The orthographic projection of the active layer of the fourth transistor onto the substrate and the orthographic projection of the active layer of the fifth transistor onto the substrate together form an L-shaped pattern.

13. The display substrate as described in claim 12, characterized in that, The shift register unit includes multiple signal lines, including a first voltage line; The orthographic projection of the first voltage line on the substrate partially overlaps with the orthographic projection of the first semiconductor layer on the substrate.

14. The display substrate according to any one of claims 1 to 6, characterized in that, The shift register unit includes a second transistor and a third transistor; the second electrode of the second transistor is coupled to the second electrode of the third transistor. The active layers of the second transistor and the third transistor are formed by a continuous fourth semiconductor layer. The orthographic projection of the active layer of the second transistor onto the substrate and the orthographic projection of the active layer of the third transistor onto the substrate together form an I-shaped pattern.

15. The display substrate as claimed in claim 14, characterized in that, The channel of the second transistor extends along the first direction, and the channel of the third transistor extends along the first direction.

16. The display substrate according to any one of claims 1 to 6, characterized in that, The shift register unit includes a sixth transistor, a seventh transistor, and an eighth transistor; The second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor, and the first electrode of the eighth transistor is coupled to the second electrode of the seventh transistor; The active layer of the sixth transistor, the active layer of the seventh transistor, and the active layer of the eighth transistor are formed by a continuous second semiconductor layer. The orthographic projection of the active layer of the eighth transistor onto the substrate, the orthographic projection of the active layer of the seventh transistor onto the substrate, and the orthographic projection of the active layer of the sixth transistor onto the substrate together form an n-type pattern.

17. The display substrate as claimed in claim 16, characterized in that, The shift register unit includes multiple signal lines; At least one of the multiple signal lines is configured to provide a DC power signal, the orthographic projection of which on the substrate partially overlaps with the orthographic projection of the second semiconductor layer on the substrate.

18. The display substrate according to any one of claims 1 to 6, characterized in that, The shift register unit includes at least two transistors disposed in the driving circuit region; the active layer of the at least two transistors is formed of a continuous semiconductor layer; The semiconductor layer includes at least a portion of semiconductor patterns that are π-shaped.

19. The display substrate according to any one of claims 1 to 6, characterized in that, The shift register unit includes multiple signal lines, multiple transistors, and multiple capacitors; The plurality of signal lines include: a first voltage line, a second voltage line, a first clock signal line, a second clock signal line, and a third clock signal line; the plurality of transistors include: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; the plurality of capacitors include: a first capacitor, a second capacitor, and a third capacitor. The gate of the first transistor is coupled to the third clock signal line, the first electrode of the first transistor is coupled to the input terminal, and the second electrode of the first transistor is coupled to the gate of the second transistor. The first electrode of the second transistor is coupled to the third clock signal line, and the second electrode of the second transistor is coupled to the second electrode of the third transistor; The gate of the third transistor is coupled to the third clock signal line, and the first electrode of the third transistor is coupled to the second voltage line; The first electrode of the fourth transistor is coupled to the first clock signal line, and the second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor; The gate of the fifth transistor is coupled to the second electrode of the third transistor, and the first electrode of the fifth transistor is coupled to the first voltage line; The gate of the sixth transistor is coupled to the second electrode of the eleventh transistor, the first electrode of the sixth transistor is coupled to the first clock signal line, and the second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor. The gate of the seventh transistor is coupled to the first clock signal line, and the second electrode of the seventh transistor is coupled to the gate of the ninth transistor. The gate of the eighth transistor is coupled to the gate of the thirteenth transistor, the first electrode of the eighth transistor is coupled to the gate of the ninth transistor, and the second electrode of the eighth transistor is coupled to the first voltage line. The first electrode of the ninth transistor is coupled to the first voltage line, and the second electrode of the ninth transistor is coupled to the drive signal output terminal; The first electrode of the tenth transistor is coupled to the drive signal output terminal, and the second electrode of the tenth transistor is coupled to the second voltage line; The gate of the eleventh transistor is coupled to the second voltage line, and the first electrode of the eleventh transistor is coupled to the gate of the fifth transistor. The gate of the twelfth transistor is coupled to the second voltage line, the first electrode of the twelfth transistor is coupled to the second electrode of the first transistor, and the second electrode of the twelfth transistor is electrically connected to the gate of the tenth transistor. The gate of the thirteenth transistor is coupled to the second clock signal line, the first electrode of the thirteenth transistor is coupled to the first voltage line, and the second electrode of the thirteenth transistor is coupled to the gate of the second transistor. The first plate of the first capacitor is coupled to the gate of the sixth transistor, and the second plate of the first capacitor is coupled to the second electrode of the sixth transistor; The first plate of the second capacitor is coupled to the gate of the ninth transistor, and the second plate of the second capacitor is coupled to the first voltage line; The first plate of the third capacitor is coupled to the gate of the fourth transistor, and the second plate of the third capacitor is coupled to the second electrode of the fourth transistor.

20. A display device comprising a display substrate as claimed in any one of claims 1 to 19.

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