A semiconductor structure for calibrating microcell surface potential

Abstract

The application discloses a kind of semiconductor structure for calibrating micro area surface potential, including silicon substrate, the upper side position of the silicon substrate is grown with oxide layer, the upper side position of the oxide layer is provided with a plurality of contact electrode areas respectively, the upper side outer position of a plurality of the contact electrode areas is provided with metal titanium and metal chromium respectively, a plurality of the contact electrode areas are provided with a plurality of finger insertion electrode areas respectively in interval, the upper side outer position of a plurality of the finger insertion electrode areas is provided with a plurality of titanium finger insertion electrode strips and chromium finger insertion electrode strips respectively, the product uses a kind of semiconductor to be matched with two kinds of known work function metal materials, forms interactive design of finger insertion, so that two reference values can be obtained simultaneously when calibrating, so as to directly measure the positive and negative direction of voltage difference between micro area probe and substrate, through the design of micro area finger insertion electrode and large area contact electrode, the probe area is more easily found when experimental test.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor structure technology, specifically relating to a semiconductor structure for calibrating the surface potential of a micro-region. Background Technology

[0002] This semiconductor structure can calibrate the surface potential of a micro-region. It consists of a semiconductor combined with two metal materials with known work functions, namely titanium and chromium, forming an interlocking interactive design. Currently, there is a lack of a semiconductor structure that can experimentally calibrate the surface potential of a micro-region. This results in the inability to obtain two reference values ​​simultaneously during calibration, making it impossible to directly measure the positive and negative directions of the voltage difference between the micro-region probe and the substrate. Furthermore, a microscope is required to observe the probe-placement area. A new semiconductor structure for calibrating the surface potential of a micro-region is needed, which can obtain two reference values ​​during calibration, thereby directly measuring the positive and negative directions of the voltage difference between the micro-region probe and the substrate. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor structure for calibrating the surface potential of a micro-region, thereby solving the problems mentioned in the background art, such as the lack of a semiconductor structure that can experimentally calibrate the surface potential of a micro-region, resulting in the inability to obtain two reference values ​​simultaneously during calibration, the inability to directly measure the positive and negative directions of the voltage difference between the micro-region probe and the substrate, and the need to use a microscope to observe the probe landing area.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a semiconductor structure for calibrating the surface potential of a micro-region, comprising a silicon substrate, an oxide layer grown on the upper side of the silicon substrate, a plurality of contact electrode regions respectively disposed on the upper side of the oxide layer, titanium metal and chromium metal respectively disposed on the upper outer side of the plurality of contact electrode regions, a plurality of finger-insertion electrode regions respectively disposed within the spacing between the plurality of contact electrode regions, a plurality of titanium finger-insertion electrode strips and chromium finger-insertion electrode strips respectively disposed on the upper outer side of the plurality of finger-insertion electrode regions, and gold metal disposed on the upper outer side of the chromium metal.

[0005] Preferably, the oxide layer has a thickness of 300 nm and the finger electrode region has a width of 1 mm.

[0006] Preferably, the size of the contact electrode area is 4mm × 8mm.

[0007] Preferably, the titanium finger electrode strip and the chromium finger electrode strip are made of titanium and chromium materials, respectively. The width of the titanium finger electrode strip is 2 μm, the width of the chromium finger electrode strip is 3 μm, and the gap between the titanium finger electrode strip and the chromium finger electrode strip is alternately designed to be 4 μm and 5 μm.

[0008] Preferably, the thickness of the titanium metal is 45 nm, and the thickness of the chromium metal is 5 nm.

[0009] Preferably, the gold metal is bonded to the chromium metal by vapor deposition, and the thickness of the gold metal is 35 nm.

[0010] Compared with the prior art, the present invention provides a semiconductor structure for calibrating the surface potential of a micro-region, which has the following beneficial effects:

[0011] This product employs a semiconductor combined with two metal materials of known work function to form an interlocking interactive design, allowing two reference values ​​to be obtained simultaneously during calibration. This enables direct measurement of the positive and negative directions of the voltage difference between the micro-probe and the substrate. The design of the micro-interlocking electrode combined with the large-area contact electrode makes the probe area easier to locate during experimental testing. The area where the probe lands can be observed directly with the naked eye without the need for a microscope. Different metals correspond to different interlocking electrode widths, allowing the experimental results to directly determine which metal the measured surface potential corresponds to. The addition of a chromium chelate layer better fixes the gold plating, making its surface more robust and flat. The two different metal surfaces are completely at the same height, thus eliminating the factor of different surface potentials caused by different heights. Furthermore, the modular array design significantly reduces product costs. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the structure of the present invention.

[0013] Figure 2 This is a schematic diagram of the structure of the undeposited gold metal in this invention.

[0014] Figure 3 This is a schematic diagram of the silicon substrate and oxide layer of the present invention.

[0015] In the figure: 1. Silicon substrate; 2. Oxide layer; 3. Titanium metal; 4. Chromium metal; 5. Contact electrode area; 6. Finger electrode area; 7. Titanium finger electrode strip; 8. Chromium finger electrode strip; 9. Gold metal. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] This invention provides, for example Figure 1-3The semiconductor structure shown is for calibrating the surface potential of a micro-region. It includes a silicon substrate 1, an oxide layer 2 grown on the upper side of the silicon substrate 1, multiple contact electrode regions 5 disposed on the upper side of the oxide layer 2, titanium 3 and chromium 4 disposed on the upper outer side of the multiple contact electrode regions 5, multiple finger-insertion electrode regions 6 disposed within the spacing between the multiple contact electrode regions 5, multiple titanium finger-insertion electrode strips 7 and chromium finger-insertion electrode strips 8 disposed on the upper outer side of the multiple finger-insertion electrode regions 6, and gold 9 disposed on the upper outer side of the chromium 4. The oxide layer 2... The thickness is 300nm, the width of the finger electrode region 6 is 1mm, the size of the contact electrode region 5 is 4mm×8mm, the titanium finger electrode strip 7 and the chromium finger electrode strip 8 are made of titanium and chromium materials respectively, the width of the titanium finger electrode strip 7 is 2um, the width of the chromium finger electrode strip 8 is 3um, and the gap between the titanium finger electrode strip 7 and the chromium finger electrode strip 8 is alternately designed to be 4um and 5um, the thickness of the metallic titanium 3 is 45nm, the thickness of the metallic chromium 4 is 5nm, and the metallic gold 9 is connected to the metallic chromium 4 by vapor deposition, and the thickness of the metallic gold 9 is 35nm.

[0018] In this embodiment, a 300 nm thick oxide layer is first grown on a silicon substrate. 4 mm × 8 mm contact electrode regions 5 are alternately deposited using titanium 3 and chromium 4, respectively. A 1 mm gap is formed between the two contact electrode regions 5 to reserve space for the fabrication of finger-insertion electrode regions 6. Within the finger-insertion electrode regions 6, titanium finger-insertion electrode strips 7 and chromium finger-insertion electrode strips 8 with widths of 2 μm and 3 μm, respectively, are fabricated using titanium and chromium. The gap between the titanium finger-insertion electrode strips 7 and chromium finger-insertion electrode strips 8 is alternately designed to be 4 μm and 5 μm. The chromium 4 layer is 5 nm thick for chelation, and the titanium 3 layer is 45 nm thick. A second layer of gold 9, 35 nm thick, is deposited on top of all the chromium layers. The sample is grounded by selecting one or two metal contact electrode regions 5. By applying voltage through the tip of an atomic force microscope or a probe station, the surface potential distribution within the microstructure can be calibrated.

[0019] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A semiconductor structure for calibrating the surface potential of a micro-region, comprising a silicon substrate (1), characterized in that: An oxide layer (2) is grown on the upper side of the silicon substrate (1). Multiple contact electrode regions (5) are respectively disposed on the upper side of the oxide layer (2). Metallic titanium (3) and metallic chromium (4) are respectively disposed on the upper outer side of the multiple contact electrode regions (5). Multiple finger insertion electrode regions (6) are respectively disposed within the spacing of the multiple contact electrode regions (5). Multiple titanium finger insertion electrode strips (7) and chromium finger insertion electrode strips (7) are respectively disposed on the upper outer side of the multiple finger insertion electrode regions (6). The electrode strip (8) has a metal gold (9) disposed on the upper outer side of the metal chromium (4). The contact electrode area (5) is 4mm×8mm in size. The titanium finger electrode strip (7) and the chromium finger electrode strip (8) are made of titanium and chromium materials, respectively. The width of the titanium finger electrode strip (7) is 2um, and the width of the chromium finger electrode strip (8) is 3um. The gap between the titanium finger electrode strip (7) and the chromium finger electrode strip (8) is alternately designed to be 4um and 5um.

2. The semiconductor structure for calibrating the surface potential of a micro-region according to claim 1, characterized in that: The oxide layer (2) has a thickness of 300 nm and the finger electrode region (6) has a width of 1 mm.

3. The semiconductor structure for calibrating the surface potential of a micro-region according to claim 1, characterized in that: The thickness of the titanium (3) is 45 nm, and the thickness of the chromium (4) is 5 nm.

4. The semiconductor structure for calibrating the surface potential of a micro-region according to claim 1, characterized in that: The gold metal (9) is connected to the chromium metal (4) by vapor deposition, and the thickness of the gold metal (9) is 35 nm.

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