A recessed grid enhancement mode GaN HEMT against reverse conducting current and manufacturing method thereof

Abstract

The application provides a recessed grid enhancement mode GaN HEMT structure resisting reverse conduction current, comprising an anode, a cathode and a substrate, a separation layer and a recessed grid enhancement mode GaN HEMT device which are sequentially stacked; wherein the substrate is SiC, and the SiC contains a P-type doped region and an N-type doped region, and the P-type doped region wraps the N-type doped region; the recessed grid enhancement mode GaN HEMT device comprises a first nucleation layer, a channel layer and a barrier layer which are sequentially formed on the separation layer; a first recess is formed on the barrier layer, the first recess penetrates the barrier layer, and the first recess is filled with a gate dielectric layer and a gate metal to form a gate; and a source and a drain are respectively formed on the barrier layer on both sides of the gate; wherein the anode is electrically connected with the P-type doped region, and the anode is electrically connected with the source; the cathode is electrically connected with the N-type doped region, and the cathode is electrically connected with the drain; wherein the N-type doped region covers an area below the drain and extends to an area below the gate; and the reverse conduction current of the device can be inhibited through a PN junction.

Description

Technical Field

[0001] The present invention relates to the field of recessed gate enhancement mode GaN HEMT, and in particular to a recessed gate enhancement mode GaN HEMT resistant to reverse conduction current and a manufacturing method thereof. Background Art

[0002] Recessed-gate enhancement-mode GaN HEMTs have great potential to replace Si-based devices in power device applications due to their advantages such as high breakdown voltage and low on-resistance. In addition to their advantages such as high breakdown voltage and low on-resistance, recessed-gate enhancement-mode GaN HEMTs also make passive devices in power electronic devices more compact and lightweight. Recessed-gate technology involves etching away the barrier layer under the gate during device fabrication. This reduces the two-dimensional electron gas concentration in the entire channel, thereby raising the conduction band bottom below the gate above the Fermi level, thereby enabling recessed-gate enhancement-mode GaN HEMTs to achieve enhanced applications.

[0003] Due to their material properties and conduction mechanism, recessed-gate enhancement-mode GaN HEMTs lack a body diode. Therefore, when they are turned off, their reverse conduction current is higher, resulting in higher turn-off power consumption. There is an urgent need for a recessed-gate enhancement-mode GaN HEMT that can suppress this reverse conduction current. Summary of the Invention

[0004] The present invention provides a recessed gate enhancement type GaN HEMT with anti-reverse conduction current and a manufacturing method thereof, so as to suppress the reverse conduction current of the recessed gate enhancement type GaN HEMT when it is turned off.

[0005] According to a first aspect of the present invention, a recessed gate enhancement mode GaN HEMT structure resistant to reverse conduction current is provided, comprising:

[0006] substrate;

[0007] A P-type doping region and an N-type doping region; wherein the P-type doping region is formed in the substrate and does not contact the substrate; the N-type doping region is formed on a surface layer of a portion of the P-type doping region, and the P-type doping region wraps the N-type doping region;

[0008] a separation layer formed on the substrate and covering the P-type doping region and the N-type doping region;

[0009] A recessed gate enhancement-mode GaN HEMT device is formed on the spacer layer; the recessed gate enhancement-mode GaN HEMT device includes a first nucleation layer, a channel layer, and a barrier layer sequentially formed on the spacer layer; a first groove is formed on the barrier layer, the first groove penetrates the barrier layer, and the first groove is filled with a gate dielectric layer and a gate metal to form a gate; a source and a drain are respectively formed on the barrier layer on both sides of the gate; and a passivation layer is filled in the gap between the source, the gate, and the drain;

[0010] an anode and a cathode, wherein the anode is electrically connected to the P-type doping region and is electrically connected to the source; the cathode is electrically connected to the N-type doping region and is electrically connected to the drain;

[0011] The N-type doped region covers the area below the drain and extends to the area below the gate.

[0012] Optionally, the recessed gate enhancement mode GaN HEMT further includes a field plate structure formed on the top of the gate.

[0013] Optionally, the P-type doping region and the N-type doping region are doped with magnesium ions and silicon ions, respectively.

[0014] Optionally, the doping concentration in the P-type doping region is 1*10 17 ~2*10 17 cm -3 ; The doping concentration in the N-type doping region is 2*10 18 ~6*10 18 cm -3 .

[0015] Optionally, the magnesium ions and silicon ions doped in the P-type doping region and the N-type doping region are activated after selective annealing.

[0016] Optionally, the substrate is a SiC-based substrate.

[0017] Optionally, the material of the separation layer includes aluminum oxide, and the material of the first nucleation layer includes AlN, so the material of the channel layer is GaN, and the material of the barrier layer is AlGaN.

[0018] Optionally, the material of the passivation layer is aluminum oxide.

[0019] According to a second aspect of the present invention, a method for preparing a recessed-gate enhancement-mode GaN HEMT with resistance to reverse conduction current is provided, which is used to manufacture the recessed-gate enhancement-mode GaN HEMT with resistance to reverse conduction current provided by the first aspect and optional solutions of the present invention, the preparation method comprising:

[0020] providing a substrate,

[0021] forming a P-type doping region in the substrate without contacting the substrate, and forming an N-type doping region on a surface layer of a portion of the P-type doping region to form a PN junction;

[0022] forming a separation layer on the substrate, wherein the separation layer covers the P-type doping region and the N-type doping region;

[0023] forming the recessed gate enhancement mode GaN HEMT device on the top of the spacer layer;

[0024] forming an anode and a cathode; wherein the anode is electrically connected to the P-type doped region and is also electrically connected to the source of the recessed gate enhancement mode GaN HEMT device; and the cathode is electrically connected to the N-type doped region and is also electrically connected to the drain of the recessed gate enhancement mode GaN HEMT device;

[0025] The N-type doped region covers the area below the drain and extends to the area below the gate of the recessed gate enhancement mode GaN HEMT device.

[0026] Optionally, forming a P-type doped region in the substrate without contacting the substrate; specifically comprising:

[0027] Performing P-type ion implantation on the first region of the substrate;

[0028] The implanted P-type ions are activated by rapid thermal annealing or laser annealing to form the P-type doping region.

[0029] Optionally, forming an N-type doping region on a surface layer of a portion of the P-type doping region specifically includes:

[0030] Performing N-type ion implantation on the first region of the P-type doping region;

[0031] The implanted N-type ions are activated by rapid thermal annealing or laser annealing to form the N-type doping region.

[0032] Optionally, forming the recessed gate enhancement mode GaN HEMT device on the top of the spacer layer specifically includes:

[0033] forming a first nucleation layer, a channel layer and a barrier layer in sequence on the separation layer;

[0034] forming isolation steps, wherein the isolation steps include first isolation steps located at two ends of the buffer layer along the first direction and second isolation steps located at two ends of the separation layer along the first direction;

[0035] forming a first groove in the barrier layer;

[0036] Depositing source metal and drain metal on the surface of the barrier layer at both sides of the first groove to form a source electrode and a drain electrode respectively;

[0037] After depositing a gate dielectric on the bottom and sidewalls of the first groove, a gate metal is deposited in the first groove to form a gate;

[0038] A passivation layer is filled in the gaps between the source electrode, the gate electrode, and the drain electrode.

[0039] Optionally, forming the isolation step specifically includes:

[0040] Etching the separation layer at both ends along the first direction to form first isolation steps at both ends of the substrate;

[0041] The barrier layer, the channel layer and the first nucleation layer are etched along both ends of the first direction to form second isolation steps at both ends of the separation layer.

[0042] Optionally, manufacturing the anode and cathode specifically includes:

[0043] Depositing a passivation layer on the surfaces of the first isolation step, the second isolation step, and the recessed gate enhancement mode GaN HEMT device;

[0044] forming a plurality of openings in the passivation layer, wherein the plurality of openings respectively penetrate the P-type doping region, the source electrode, the gate electrode, the drain electrode, and the N-type doping region;

[0045] Depositing an electrode metal layer, the electrode metal layer filling the plurality of through holes, wherein the electrode metal layer electrically connected to the P-type doped region constitutes the anode, the electrode metal layer electrically connected to the N-type doped region constitutes the cathode, and the anode is electrically connected to the source; the cathode is electrically connected to the drain.

[0046] Optionally, the method further includes: forming a field plate structure, wherein the field plate structure is the electrode metal layer deposited on and penetrating into the gate opening.

[0047] According to a third aspect of the present invention, a semiconductor device is provided, comprising the recessed gate enhancement mode GaN HEMT with resistance to reverse conduction current provided by the first aspect of the present invention and its optional solutions.

[0048] According to a fourth aspect of the present invention, there is provided an electronic device comprising the semiconductor device provided by the third aspect of the present invention.

[0049] According to a fifth aspect of the present invention, a method for manufacturing a semiconductor device is provided, including the method for manufacturing a recessed gate enhancement mode GaN HEMT resistant to reverse conduction current provided by the second aspect of the present invention and the optional solution.

[0050] According to a sixth aspect of the present invention, a method for preparing an electronic device is provided, comprising the method for preparing the semiconductor device provided in the fifth aspect of the present invention.

[0051] A PN junction formed by the P-type doping region and the N-type doping region in the substrate is used as a body diode of the recessed gate enhancement mode GaN HEMT to suppress a reverse conduction current of the recessed gate enhancement mode GaN HEMT. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0053] Figure 1 This is a schematic diagram of the device structure of the recessed gate enhancement mode GaN HEMT structure in the prior art;

[0054] Figure 2 Schematic diagram of the device structure of a recessed gate enhancement mode GaN HEMT structure with resistance to reverse conduction current provided by an embodiment of the present invention;

[0055] Figure 3 This is a schematic diagram of the process of preparing a recessed gate enhancement mode GaN HEMT with resistance to reverse conduction current provided by an embodiment of the present invention. Figure 1 ;

[0056] Figure 4 Schematic diagram of the device structure at different process stages of the manufacturing method of the recessed gate enhancement mode GaN HEMT with anti-reverse current provided by the embodiment of the present invention Figure 1 ;

[0057] Figure 5 Schematic diagram of the device structure at different process stages of the manufacturing method of the recessed gate enhancement mode GaN HEMT with anti-reverse current provided by the embodiment of the present invention Figure 2 ;

[0058] Figure 6 Schematic diagram of the device structure at different process stages of the manufacturing method of the recessed gate enhancement mode GaN HEMT with anti-reverse current provided by the embodiment of the present invention Figure 3 ;

[0059] Figure 7 Schematic diagram of the device structure at different process stages of the manufacturing method of the recessed gate enhancement mode GaN HEMT with anti-reverse current provided by the embodiment of the present invention Figure 4 ;

[0060] Figure 8 This is a schematic diagram of the process of preparing a recessed gate enhancement mode GaN HEMT with resistance to reverse conduction current provided by an embodiment of the present invention. Figure 2 ;

[0061] Figure 9 Schematic diagram of the device structure at different process stages of the manufacturing method of the recessed gate enhancement mode GaN HEMT with anti-reverse current provided by the embodiment of the present invention Figure 5 ;

[0062] Figure 10 Schematic diagram of the device structure at different process stages of the manufacturing method of the recessed gate enhancement mode GaN HEMT with anti-reverse current provided by the embodiment of the present invention Figure 6 ;

[0063] Figure 11 Schematic diagram of the device structure at different process stages of the manufacturing method of the recessed gate enhancement mode GaN HEMT with anti-reverse current provided by the embodiment of the present invention Figure 7 ;

[0064] Figure 12 Schematic diagram of the device structure at different process stages of the manufacturing method of the recessed gate enhancement mode GaN HEMT with anti-reverse current provided by the embodiment of the present invention Figure 8 ;

[0065] Figure 13 This is a schematic diagram of the process of preparing a recessed gate enhancement mode GaN HEMT with resistance to reverse conduction current provided by an embodiment of the present invention. Figure 3 ;

[0066] Figure 14 Schematic diagram of the device structure at different process stages of the manufacturing method of the recessed gate enhancement mode GaN HEMT with anti-reverse current provided by the embodiment of the present invention Figure 9 ;

[0067] Figure 15 Schematic diagram of the device structure at different process stages of the manufacturing method of the recessed gate enhancement mode GaN HEMT with anti-reverse current provided by the embodiment of the present invention Figure 10 .

[0068] Description of reference numerals:

[0069] 102-substrate;

[0070] 103-P-type doping region;

[0071] 104-N-type doping region;

[0072] 105-separation layer;

[0073] 106-first nucleation layer;

[0074] 107-channel layer;

[0075] 108-barrier layer;

[0076] 109- source;

[0077] 110-drain;

[0078] 111-gate dielectric;

[0079] 112-gate;

[0080] 113-passivation layer;

[0081] 114- anode;

[0082] 115- cathode;

[0083] 116-field plate structure

[0084] 118-First isolation step;

[0085] 119-Second isolation step. DETAILED DESCRIPTION

[0086] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0087] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0088] Before describing the embodiments of the present invention, the design concept of the present invention is briefly described:

[0089] Please refer to Figure 1 Existing recessed-gate enhancement-mode GaN HEMTs consist of a substrate, a buffer layer, and a recessed-gate enhancement-mode GaN HEMT device on the buffer layer. When a turn-on voltage is applied to the drain of the recessed-gate enhancement-mode GaN HEMT device to turn it on, the on-current easily flows from the drain through the recessed-gate enhancement-mode GaN HEMT device and out of the substrate, causing substrate leakage. Furthermore, when the turn-on voltage applied to the drain is removed, a reverse current flows from the source to the drain through the recessed-gate enhancement-mode GaN HEMT device, increasing device losses. In view of these drawbacks of existing recessed-gate enhancement-mode GaN HEMTs, the applicants of the present invention have fabricated an additional PN junction on the buffer layer to suppress substrate leakage when the recessed-gate enhancement-mode GaN HEMT is on and reverse current when it is off.

[0090] Please refer to Figure 2 The embodiment of the present invention provides a recessed gate enhancement mode GaN HEMT structure that is resistant to reverse conduction current, including:

[0091] substrate 102;

[0092] A P-type doping region 103 and an N-type doping region 104; wherein the P-type doping region 103 is formed in the substrate 102 and does not contact the substrate 102; the N-type doping region 104 is formed on a surface layer of a portion of the P-type doping region 103, and the P-type doping region 103 wraps the N-type doping region 104;

[0093] a separation layer 105 formed on the substrate 102 and covering the P-type doping region 103 and the N-type doping region 104;

[0094] A recessed gate enhancement-mode GaN HEMT device is formed on the spacer layer 105; the recessed gate enhancement-mode GaN HEMT device includes a first nucleation layer 106, a channel layer 107, and a barrier layer 108 sequentially formed on the spacer layer 105; a first groove is formed on the barrier layer 108, the first groove penetrating the barrier layer 108, the first groove is filled with a gate dielectric layer 111 and a gate metal 112 to form a gate 112; a source 109 and a drain 110 are respectively formed on the barrier layer 108 on both sides of the gate 112; and a passivation layer 113 is filled in the gap between the source 109, the gate 112, and the drain 110;

[0095] an anode 114 and a cathode 115 , wherein the anode 114 is electrically connected to the P-type doping region 103 and the source 109 ; the cathode 115 is electrically connected to the N-type doping region 104 and the drain 110 ;

[0096] The N-type doped region 104 covers the area below the drain 110 and extends to the area below the gate 112 .

[0097] The principle of suppressing leakage from the substrate 102 when the recess gate enhancement mode GaN HEMT is turned on by using the PN junction is as follows: when a turn-on voltage is applied to the drain 110, if the on-current attempts to flow out of the substrate 102, it will flow from the cathode 115 to the reverse end of the PN junction, thereby being suppressed. In this way, the on-current can only flow from the drain 110 on the recess gate enhancement mode GaN HEMT device to the source, thereby suppressing leakage from the substrate 102 of the recess gate enhancement mode GaN HEMT.

[0098] The principle of suppressing the reverse conduction current of the recess gate enhancement-type GaN HEMT when it is turned off by the PN junction is as follows: when the on-voltage applied to the drain 110 is removed, if the reverse conduction current wants to flow from the source 109 through the recess gate enhancement-type GaN HEMT device to the drain 110, it will be guided by the anode 114 to the positive end of the PN junction, flow through the PN junction and flow out from the cathode 115. In this way, it will not pass through the recess gate enhancement-type GaN HEMT device and increase device losses.

[0099] In addition, the PN junction also has the function of preventing the recessed gate enhancement mode GaN HEMT from experiencing forward breakdown. The specific principle is: when the on-state voltage applied to the drain 110 is too large, the PN junction that originally suppresses the on-state current will undergo reverse breakdown, causing the on-state current to flow through the PN junction and out of the anode 114, thereby preventing the recessed gate enhancement mode GaN HEMT device from experiencing forward breakdown.

[0100] Please refer to Figure 2 As a specific embodiment, the recessed gate enhancement mode GaN HEMT further includes a field plate structure 116 formed on the top of the gate 112 .

[0101] As a specific implementation, the buffer layer is a composition gradient structure, and of course it can also be a superlattice structure, which is not limited here.

[0102] In a specific embodiment, the P-type doping region 103 and the N-type doping region 104 are doped with magnesium ions and silicon ions, respectively. The magnesium ions and silicon ions are selected as the doping ions because they are more easily activated. Of course, other P-type ions and other N-type ions may also be selected as the doping ions. For example, the P-type ions may be Zn, Be, etc., which are not limited here; and the N-type ions may be V, C, etc., which are not limited here.

[0103] As a specific embodiment, the doping concentration in the P-type doping region 103 is 1*10 17 ~2*10 17 cm -3 ; The doping concentration in the N-type doping region 104 is 2*10 18 ~6*10 18 cm -3 Of course, the doping concentration in the P-type doping region 103 is only experimentally preferred data and can be adjusted according to actual needs, and is not limited here; similarly, the doping concentration in the N-type doping region 104 is also only experimentally preferred data and can be adjusted according to actual needs, and is not limited here.

[0104] As a specific implementation manner, the magnesium ions and silicon ions doped in the P-type doping region 103 and the N-type doping region 104 are activated after selective annealing.

[0105] As a specific implementation, the substrate 102 is a SiC-based substrate 102 .

[0106] In a specific embodiment, the material of the spacer layer 105 includes aluminum oxide, and the material of the first nucleation layer 106 includes AlN. Therefore, the material of the channel layer 107 is GaN, and the material of the barrier layer 108 is AlGaN. The function of the spacer layer 105 is to insulate the recessed gate enhancement mode GaN HEMT device from the underlying PN junction. Its material is not limited to aluminum oxide and can also be other insulating materials, such as SiO2, etc., which is not limited here.

[0107] As a specific implementation, the material of the passivation layer 113 is aluminum oxide.

[0108] Please refer to Figure 2 and Figures 3 to 15 The present invention also provides a method for preparing a recessed-gate enhancement-mode GaN HEMT with resistance to reverse conduction current. The method is used to prepare the recessed-gate enhancement-mode GaN HEMT with resistance to reverse conduction current provided by the present invention. The method comprises:

[0109] S1: Please refer to Figure 4 , providing a substrate 102.

[0110] S2: forming a P-type doping region 103 in the substrate 102 without contacting the substrate 102 , and forming an N-type doping region 104 on a surface of a portion of the P-type doping region 103 to form a PN junction.

[0111] S3: Please refer to Figure 7 , forming a separation layer 105 on the substrate 102 , wherein the separation layer 105 covers the P-type doping region 103 and the N-type doping region 104 .

[0112] S4: forming the recessed gate enhancement mode GaN HEMT device on the top of the spacer layer 105 .

[0113] S5: forming an anode 114 and a cathode 115; wherein the anode 114 is electrically connected to the P-type doping region 103, and the anode 114 is also electrically connected to the source 109 of the recessed gate enhancement mode GaN HEMT device; the cathode 115 is electrically connected to the N-type doping region 104, and the cathode 115 is electrically connected to the drain 110 of the recessed gate enhancement mode GaN HEMT device.

[0114] The N-type doped region 104 covers the area below the drain 110 and extends to the area below the gate 112 of the recessed gate enhancement mode GaN HEMT device.

[0115] Please refer to Figure 5 As a specific embodiment, forming a P-type doping region 103 in the substrate 102 without contacting the substrate 102 in S2 specifically includes:

[0116] First, a patterned hard mask is used to cover the substrate 102 except the first region. Then, P-type ions, such as magnesium ions, are implanted into the first region. Then, the implanted P-type ions are activated by rapid thermal annealing or laser annealing to form the P-type doped region 103. Finally, the hard mask is removed using a hydrofluoric acid solution.

[0117] Please refer to Figure 6 As a specific embodiment, forming the N-type doping region 104 on the surface of a portion of the P-type doping region 103 in S2 specifically includes:

[0118] First, a patterned hard mask is formed to cover all areas of the P-type doped region 103 except the first region. Next, N-type ions, such as silicon ions, are implanted into the first region. The implanted N-type ions are then activated by rapid thermal annealing or laser annealing to form the N-type doped region 104. Finally, the hard mask is removed using a hydrofluoric acid solution. The first region of the P-type doped region 103 covers the area below the drain 110 and extends to the area below the gate 112 of the recessed gate enhancement mode GaN HEMT device.

[0119] As a specific implementation, the material of the hard mask is SiN.

[0120] Please refer to Figures 8 to 12 As a specific implementation manner, forming the recessed gate enhancement mode GaN HEMT device on the top of the spacer layer 105 in S4 specifically includes:

[0121] S41: Please refer to Figure 9 , a first nucleation layer 106 , a channel layer 107 and a barrier layer 108 are sequentially formed on the separation layer 105 .

[0122] S42 : forming isolation steps, wherein the isolation steps include a first isolation step 118 located at two ends of the buffer layer along the first direction and a second isolation step 119 located at two ends of the separation layer 105 along the first direction.

[0123] S43 : forming a first groove in the barrier layer 108 .

[0124] S44 : depositing a source electrode 109 metal and a drain electrode 110 metal on the surface of the barrier layer 108 at both sides of the first groove, respectively, to form a source electrode 109 and a drain electrode 110 .

[0125] S45 : depositing a gate dielectric 111 on the bottom and sidewalls of the first groove and then depositing a gate 112 metal in the first groove to form the gate 112 .

[0126] S46 : filling the gaps between the source electrode 109 , the gate electrode 112 , and the drain electrode 110 with a passivation layer 113 .

[0127] Please refer to Figure 10 As a specific implementation, forming the isolation step in S42 specifically includes:

[0128] Etching the separation layer 105 and the PN junction along both ends of the first direction to form first isolation steps 118 at both ends of the buffer layer;

[0129] The barrier layer 108, the channel layer 107, and the first nucleation layer 106 are etched along both ends of the first direction to form second isolation steps 119 at both ends of the separation layer 105. The purpose of step isolation is to prevent a single device from being electrically connected to surrounding devices, so electrical isolation is performed. Of course, in addition to the etching method proposed in the embodiment of the present invention, ion implantation can also be used, which is not limited here.

[0130] Please refer to Figure 11 As a specific embodiment, forming a first recess in the barrier layer 108 in S43 specifically includes: cyclically etching the barrier layer 108 at the gate recess position using oxygen and boron trichloride gases until the barrier layer 108 at the gate recess position is completely etched, thereby forming the first recess. Forming the first recess reduces the 2DEG concentration below the gate 112 and the two-dimensional electron gas concentration throughout the channel, thereby raising the conduction band bottom below the gate 112 above the Fermi level, thereby achieving enhancement-mode applications of recessed-gate enhancement-mode GaN HEMTs.

[0131] Please refer to Figure 11 As a specific embodiment, in S44, source 109 metal and drain 110 metal are respectively deposited on the surface of the barrier layer 108 on both sides of the first groove to form the source 109 and the drain 110, which also specifically includes: depositing source 109 metal and drain 110 metal on the surface of the barrier layer 108 on both sides of the first groove, and performing ohmic contact thermal annealing on the source 109 metal and the drain 110 metal to form the source 109 and the drain 110.

[0132] Please refer to Figure 12 As a specific implementation, the metal material of the gate 112 in S45 and S46 is specifically TiN, and the materials of the gate dielectric 111 and the passivation layer 113 are specifically aluminum oxide, or they can be silicon nitride, which is not limited here.

[0133] Please refer to Figure 13 、 Figure 14 、 Figure 2 As a specific embodiment, forming the anode 114 and the cathode 115 in S5 specifically includes:

[0134] S51: Please refer to Figure 13 A passivation layer 113 is deposited on the surfaces of the first isolation step 118 , the second isolation step 119 , and the recessed gate enhancement mode GaN HEMT device.

[0135] S52: Please refer to Figure 14, a plurality of openings are formed in the passivation layer 113 , and the plurality of openings respectively penetrate the P-type doping region 103 , the source 109 , the gate 112 , the drain 110 and the N-type doping region 104 .

[0136] S53: Depositing an electrode metal layer, wherein the electrode metal layer fills the plurality of through holes, wherein the electrode metal layer electrically connected to the P-type doping region 103 constitutes the anode 114, and the electrode metal layer electrically connected to the N-type doping region 104 constitutes the cathode 115, and the anode 114 is electrically connected to the source 109; the cathode 115 is electrically connected to the drain 110.

[0137] The method for preparing a recessed-gate enhanced-mode GaN HEMT resistant to reverse current provided in an embodiment of the present invention further specifically includes forming a field plate structure 116 , wherein the field plate structure 116 is the electrode metal layer deposited in the opening extending through the gate 112 .

[0138] An embodiment of the present invention further provides a semiconductor device including the recessed gate enhancement mode GaN HEMT structure capable of resisting reverse conduction current.

[0139] An embodiment of the present invention further provides an electronic device, including the electronic device.

[0140] An embodiment of the present invention further provides a method for manufacturing a semiconductor device, including a method for manufacturing the recessed gate enhancement mode GaN HEMT resistant to reverse conduction current.

[0141] An embodiment of the present invention further provides a method for manufacturing an electronic device, and a method for manufacturing the semiconductor device.

[0142] The reverse-current-resistant recessed-gate enhancement-mode GaN HEMT structure provided by the embodiment of the present invention has the following beneficial effects: 1. By forming a PN junction in the substrate 102 , leakage of the substrate 102 is suppressed when the recessed-gate enhancement-mode GaN HEMT is turned on.

[0143] 2. By forming a PN junction in the substrate 102, the reverse conduction current of the recessed gate enhancement mode GaN HEMT is suppressed when the device is turned off, thereby reducing the turn-off loss.

[0144] 3. A PN junction is formed in the substrate 102 to prevent the recessed gate enhancement mode GaN HEMT device from being forward broken down when the on-voltage is too large.

[0145] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A recessed gate enhancement mode GaN HEMT structure resistant to reverse conduction current, characterized in that: include: substrate; forming a P-type doping region and an N-type doping region on a substrate; wherein the P-type doping region is formed in the substrate and does not contact the substrate; and the N-type doping region is formed on a surface layer of a portion of the P-type doping region, and the P-type doping region wraps around the N-type doping region; a separation layer formed on the substrate and covering the P-type doping region and the N-type doping region; A recessed gate enhancement-mode GaN HEMT device is formed on the spacer layer; the recessed gate enhancement-mode GaN HEMT device includes a first nucleation layer, a channel layer, and a barrier layer sequentially formed on the spacer layer; a first groove is formed on the barrier layer, the first groove penetrates the barrier layer, and the first groove is filled with a gate dielectric layer and a gate metal to form a gate; a source and a drain are respectively formed on the barrier layer on both sides of the gate; and a passivation layer is filled in the gap between the source, the gate, and the drain; an anode and a cathode, wherein the anode is electrically connected to the P-type doping region and is electrically connected to the source; the cathode is electrically connected to the N-type doping region and is electrically connected to the drain; The N-type doped region covers the area below the drain and extends to the area below the gate.

2. The recessed gate enhancement mode GaN HEMT with resistance to reverse conduction current according to claim 1, characterized in that: The recessed gate enhancement mode GaN HEMT further includes a field plate structure formed on the top of the gate.

3. The recessed gate enhancement mode GaN HEMT with resistance to reverse conduction current according to claim 1, characterized in that: The P-type doping region and the N-type doping region are doped with magnesium ions and silicon ions, respectively.

4. The recessed gate enhancement mode GaN HEMT with resistance to reverse conduction current according to claim 3, characterized in that: The doping concentration in the P-type doping region is 1*10 17 ~2*10 17 cm -3 ; The doping concentration in the N-type doping region is 2*10 18 ~6*10 18 cm -3 .

5. The recessed gate enhancement mode GaN HEMT with resistance to reverse conduction current according to claim 3, characterized in that: The magnesium ions and silicon ions doped in the P-type doping region and the N-type doping region are activated after selective annealing.

6. The recessed gate enhancement mode GaN HEMT with resistance to reverse conduction current according to claim 1, characterized in that: The substrate is a SiC-based substrate.

7. The recessed gate enhancement mode GaN HEMT with resistance to reverse conduction current according to claim 1, characterized in that: The material of the separation layer includes aluminum oxide, and the material of the first nucleation layer includes AlN. Therefore, the material of the channel layer is GaN, and the material of the barrier layer is AlGaN.

8. The recessed gate enhancement mode GaN HEMT with resistance to reverse conduction current according to claim 2, characterized in that: The material of the passivation layer is aluminum oxide.

9. A method for preparing a recessed gate enhancement mode GaN HEMT with resistance to reverse conduction current, for producing the recessed gate enhancement mode GaN HEMT structure with resistance to reverse conduction current according to any one of 1 to 8, characterized in that: The preparation method comprises: providing a substrate; forming a P-type doping region in the substrate without contacting the substrate, and forming an N-type doping region on a surface layer of a portion of the P-type doping region to form a PN junction; forming a separation layer on the substrate, wherein the separation layer covers the P-type doping region and the N-type doping region; forming the recessed gate enhancement mode GaN HEMT device on the top of the spacer layer; forming an anode and a cathode; wherein the anode is electrically connected to the P-type doped region and is also electrically connected to the source of the recessed gate enhancement mode GaN HEMT device; and the cathode is electrically connected to the N-type doped region and is also electrically connected to the drain of the recessed gate enhancement mode GaN HEMT device; The N-type doped region covers the area below the drain and extends to the area below the gate of the recessed gate enhancement mode GaN HEMT device.

10. The method for preparing a recessed gate enhancement mode GaN HEMT resistant to reverse current according to claim 9, characterized in that: Forming a P-type doped region in the substrate without contacting the substrate; specifically comprising: Performing P-type ion implantation on the first region of the substrate; The implanted P-type ions are activated by rapid thermal annealing or laser annealing to form the P-type doping region.

11. The method for preparing a recessed gate enhancement mode GaN HEMT with resistance to reverse current according to claim 10, characterized in that: Forming an N-type doping region on a surface layer of a portion of the P-type doping region specifically includes: Performing N-type ion implantation on the first region of the P-type doping region; The implanted N-type ions are activated by rapid thermal annealing or laser annealing to form the N-type doping region.

12. The method for preparing a recessed gate enhancement mode GaN HEMT resistant to reverse current according to claim 11, characterized in that: Forming the recessed gate enhancement mode GaN HEMT device on the top of the spacer layer specifically includes: forming a first nucleation layer, a channel layer and a barrier layer in sequence on the separation layer; forming isolation steps, wherein the isolation steps include first isolation steps located at two ends of the buffer layer along the first direction and second isolation steps located at two ends of the separation layer along the first direction; forming a first groove in the barrier layer; Depositing source metal and drain metal on the surface of the barrier layer at both sides of the first groove to form a source electrode and a drain electrode respectively; After depositing a gate dielectric on the bottom and sidewalls of the first groove, a gate metal is deposited in the first groove to form a gate; A passivation layer is filled in the gaps between the source electrode, the gate electrode, and the drain electrode.

13. The method for preparing a recessed gate enhancement mode GaN HEMT resistant to reverse current according to claim 12, characterized in that: The forming of the isolation step specifically includes: Etching the separation layer at both ends along the first direction to form first isolation steps at both ends of the substrate; The barrier layer, the channel layer and the first nucleation layer are etched along both ends of the first direction to form second isolation steps at both ends of the separation layer.

14. The method for preparing a recessed gate enhancement mode GaN HEMT resistant to reverse current according to claim 13, characterized in that: The production of anode and cathode specifically includes: Depositing a passivation layer on the surfaces of the first isolation step, the second isolation step, and the recessed gate enhancement mode GaN HEMT device; forming a plurality of openings in the passivation layer, wherein the plurality of openings respectively penetrate the P-type doping region, the source electrode, the gate electrode, the drain electrode, and the N-type doping region; Depositing an electrode metal layer, the electrode metal layer filling the plurality of openings, wherein the electrode metal layer electrically connected to the P-type doped region constitutes the anode, the electrode metal layer electrically connected to the N-type doped region constitutes the cathode, and the anode is electrically connected to the source; the cathode is electrically connected to the drain.

15. The method for preparing a recessed gate enhancement mode GaN HEMT resistant to reverse current according to claim 14, characterized in that: The method further includes: forming a field plate structure, wherein the field plate structure is the electrode metal layer deposited on and penetrating into the gate opening.

16. A semiconductor device, characterized in that: The recessed gate enhancement mode GaN HEMT structure with resistance to reverse conduction current comprises the structure described in any one of claims 1 to 8.

17. An electronic device comprising the semiconductor device according to claim 16.

18. A method for preparing a semiconductor device, characterized in that: A method for preparing a recessed gate enhancement mode GaN HEMT resistant to reverse conduction current according to any one of claims 9 to 15.

19. A method for manufacturing an electronic device, comprising the method for manufacturing a semiconductor device according to claim 18.

Images