Fin-shaped MOS switch device and its preparation method, chip

Abstract

The present application belongs to the field of semiconductor technology and provides a fin-shaped MOS switch device and its preparation method and chip. The device is formed by forming an N-type drift layer on a semiconductor substrate, forming a connection area on the N-type drift layer, forming a P-type doped layer with a cross-shaped fin structure on both sides of the connection area, forming a gate metal layer on the P-type doped layer, and forming an N-type doped material layer between the fin structures of the P-type doped layer. A first source doped layer and a second source doped layer are formed outside the P-type doped layers on both sides, thereby forming a JFET structure on both sides of the connection area, so that the current flowing out from the drain on the back side of the semiconductor substrate passes through the N-type drift layer and the connection area of ​​the fin area, and reaches the source through the current channel of the JFET structure. The current channel is induced by the gate metal layer on the fin structure to turn on the device, thereby achieving the purpose of taking into account high breakdown voltage, high current density and small device area.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a fin-shaped MOS switch device, a preparation method thereof, and a chip. Background Art

[0002] The breakdown voltage (BV) of a power transistor is a very important parameter. In order to increase the BV of a power transistor while saving chip area, the power transistor is transformed from a planar structure to a vertical structure.

[0003] However, the pursuit of high breakdown voltage, high current density and smaller device area is still the further development direction of power transistors. Summary of the Invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide a fin-shaped MOS switch device and a preparation method and chip thereof, aiming to simultaneously take into account high breakdown voltage, high current density and small device area.

[0005] According to a first aspect of an embodiment of the present application, a fin-shaped MOS switch device is provided. The fin-shaped MOS switch device includes:

[0006] semiconductor substrates;

[0007] An N-type drift layer is provided on the front surface of the semiconductor substrate;

[0008] A first P-type doping layer and a second P-type doping layer are provided on the N-type drift layer, and the first P-type doping layer and the second P-type doping layer are in a cross-shaped fin structure;

[0009] A first gate metal layer and a second gate metal layer are connected to the first P-type doped layer and the second P-type doped layer respectively;

[0010] a connection region, provided between the first P-type doped layer and the second P-type doped layer;

[0011] A first source doping layer and a second source doping layer are respectively arranged on the outer side of the first P-type doping layer and the outer side of the second P-type doping layer;

[0012] a plurality of first N-type doping material layers, filled between the fin-shaped structures of the first P-type doping layer to isolate the connection region from the first source doping layer;

[0013] a plurality of second N-type doping material layers, filled between the fin-shaped structures of the second P-type doping layer to isolate the connection region from the second source doping layer;

[0014] The drain metal layer is arranged on the back side of the semiconductor substrate.

[0015] In one embodiment, the first P-type doping layer includes: a first horizontal doping structure, a first isolation doping structure, and a plurality of first fin-shaped isolation structures;

[0016] The plurality of first fin-shaped isolation structures do not contact each other and are arranged between the first horizontal doping structure and the first isolation doping structure, and the first isolation doping structure contacts the first gate metal layer. The first horizontal doping structure is arranged on the N-type drift layer.

[0017] In one embodiment, the second P-type doping layer includes: a second horizontal doping structure, a second isolation doping structure, and a plurality of second fin-shaped isolation structures;

[0018] The plurality of second fin-shaped isolation structures do not contact each other and are arranged between the second horizontal doping structure and the second isolation doping structure, and the second isolation doping structure contacts the second gate metal layer. The second horizontal doping structure is arranged on the N-type drift layer.

[0019] In one embodiment, the plurality of first fin-shaped isolation structures and the plurality of second fin-shaped isolation structures are arranged in a one-to-one correspondence.

[0020] In one embodiment, the first gate metal layer is disposed perpendicular to the first fin isolation structure, and a width of the first gate metal layer is smaller than a length of the first fin isolation structure.

[0021] In one embodiment, the first source doping layer is disposed on the first horizontal doping structure and contacts the first fin-shaped isolation structures.

[0022] In one embodiment, the second source doping layer is disposed on the second horizontal doping structure and contacts the second fin-shaped isolation structures.

[0023] In one embodiment, the first source doping layer is perpendicular to the first fin isolation structure;

[0024] The second source doping layer is perpendicular to the second fin-shaped isolation structure.

[0025] A second aspect of the present application further provides a method for manufacturing a fin-shaped MOS switch device, the method comprising:

[0026] forming an N-type drift layer on the front surface of the semiconductor substrate;

[0027] forming a first horizontal doping structure and a second horizontal doping structure on the N-type drift layer, and forming a plurality of first fin-shaped isolation structures and a plurality of second fin-shaped isolation structures on the first horizontal doping structure and the second horizontal doping structure, respectively;

[0028] forming a plurality of first N-type doping material layers between the plurality of first fin-shaped isolation structures, and forming a first isolation doping structure on the first fin-shaped isolation structures and the first N-type doping material layers to form a first P-type doping layer of a cross-shaped fin structure;

[0029] forming a plurality of second N-type doping material layers between the plurality of second fin-shaped isolation structures, and forming a second isolation doping structure on the second fin-shaped isolation structure and the second N-type doping material layer to form a second P-type doping layer of a cross-shaped fin structure;

[0030] forming a connection region between the first P-type doping layer and the second P-type doping layer, and forming a first source doping layer and a second source doping layer on the outer sides of the first P-type doping layer and the outer sides of the second P-type doping layer, respectively;

[0031] forming a first gate metal layer on the first isolation doping structure, and forming a second gate metal layer on the second isolation doping structure;

[0032] A drain metal layer is formed on the back side of the semiconductor substrate.

[0033] A third aspect of the embodiments of the present application further provides a chip, in which a fin-shaped MOS switch device as described in any one of the above items is integrated; or a fin-shaped MOS switch device prepared by the preparation method described in the above embodiments is included.

[0034] The beneficial effects of the embodiments of the present application compared with the prior art are: by forming an N-type drift layer on a semiconductor substrate, forming a connection area on the N-type drift layer, forming a P-type doped layer of a fin structure on both sides of the connection area, and sequentially forming a dielectric layer, a work function metal layer and a gate metal layer on the surface of the P-type doped layer, forming a first source doped layer and a second source doped layer on the outside of the P-type doped layers on both sides, so that the current flowing out from the drain on the back side of the semiconductor substrate passes through the N-type drift layer and the connection area of ​​the fin area, and reaches the source through the current channel induced by the first P-type doped layer and the second P-type doped layer structure of the fin structure. The device can be turned on by inducing a current channel by the gate metal layer on the fin structure, thereby achieving the purpose of taking into account high breakdown voltage, high current density and small device area. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a schematic structural diagram of a fin-shaped MOS switch device provided by one embodiment of the present application;

[0036] Figure 2 yes Figure 1 A schematic cross-sectional view of the dashed line A;

[0037] Figure 3 yes Figure 1 A schematic cross-sectional view of the dashed line B;

[0038] Figure 4 It is a flow chart of a method for preparing a fin-shaped MOS switch device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0040] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0041] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means one or more, unless otherwise specifically defined.

[0043] References to "one embodiment," "some embodiments," or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in some other embodiments," "in some other embodiments," "in a specific embodiment," and "in a specific application" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner.

[0044] The battery voltage (BV) of power transistors is a crucial parameter. To increase BV while saving chip area, power transistors have transitioned from a planar to a vertical structure. Since the invention of the fin transistor (FINFET), it has successfully demonstrated the feasibility of CMOS processes at 14nm and even 3-5nm processes.

[0045] In order to take into account high breakdown voltage, high current density and small device area, the embodiment of the present application provides a fin-shaped MOS switch device, combined with Figure 1 、 Figure 2 as well as Figure 3 As shown, the fin-shaped MOS switch device in this embodiment includes: a semiconductor substrate 100, an N-type drift layer 200, a first P-type doped layer 310, a second P-type doped layer 320, a first gate metal layer 710, a second gate metal layer 720, a connection area 830, a first source doped layer 810, a first N-type doped material layer 410, a second N-type doped material layer 420, a second source doped layer 820, and a drain metal layer 850.

[0046] In this embodiment, the N-type drift layer 200 is provided on the front surface of the semiconductor substrate 100, the first P-type doping layer 310 and the second P-type doping layer 320 are provided on the N-type drift layer 200, and the first P-type doping layer 310 and the second P-type doping layer 320 are in a well-shaped fin structure, the connection region 830 is provided between the first P-type doping layer 310 and the second P-type doping layer 320, and a plurality of first N-type doping material layers 410 are filled between the fin structures of the first P-type doping layer 310 to isolate the connection region 830 from the first source doping layer 830. The mixed layer 810 makes the connection area 830, the first source doping layer 810, the first P-type doping layer 310 and the multiple first N-type doping material layers 410 form a first JFET structure, and the multiple second N-type doping material layers 420 are filled between the fin structures of the second P-type doping layer 320 to isolate the connection area 830 and the second source doping layer 820, so that the connection area 830, the second source doping layer 820, the second P-type doping layer 320 and the multiple second N-type doping material layers 420 form a second JFET structure.

[0047] The first gate metal layer 710 and the second gate metal layer 720 are connected to the first P-type doping layer 310 and the second P-type doping layer 320 respectively. The first source doping layer 810 and the second source doping layer 820 are respectively arranged on the outside of the first P-type doping layer 310 and the second P-type doping layer 320. The first source doping layer 810 and the second source doping layer 820 are commonly connected to the source of the fin-shaped MOS switch device. The drain metal layer 850 is arranged on the back side of the semiconductor substrate 100.

[0048] In this embodiment, an N-type drift layer 200 and a connection region 830 are formed on a semiconductor substrate 100, a first P-type doping layer 310 and a second P-type doping layer 320 of a cross-shaped fin structure are formed on both sides of the connection region 830, and a plurality of first N-type doping material layers 410 are formed between the fin structures of the first P-type doping layer 310, a plurality of second N-type doping material layers 420 are formed between the fin structures of the second P-type doping layer 320, a first source doping layer 810 is formed outside the first P-type doping layer 310, and a second source doping layer 810 is formed outside the second P-type doping layer 320. A second source doping layer 820 is formed on the outside of the layer 320, thereby forming a first JFET structure and a first JFET structure on both sides of the connection area 830, so that the current flowing out from the drain on the back side of the semiconductor substrate 100 passes through the N-type drift layer 200 and the connection area 830 of the fin area, and reaches the source through the current channel of the first JFET structure and the first JFET structure. The current channel is induced by the gate metal layer on the fin structure to turn on the device, thereby achieving the purpose of taking into account high breakdown voltage, high current density and smaller device area.

[0049] Combine Figure 2 As shown, the first P-type doping layer 310 includes a first horizontal doping structure 311 , a first isolation doping structure 313 and a plurality of first fin-shaped isolation structures 312 .

[0050] The first fin-shaped isolation structures 312 do not contact each other and are disposed between the first horizontal doping structure 311 and the first isolation doping structure 313 . The first isolation doping structure 313 contacts the first gate metal layer 710 . The first horizontal doping structure 311 is disposed on the N-type drift layer 200 .

[0051] In this embodiment, the first horizontal doping structure 311, the first isolation doping structure 313 and the multiple first fin-shaped isolation structures 312 are all P-type doped semiconductors, wherein the first horizontal doping structure 311 is located between the first N-type doping material layer 410 and the N-type drift layer 200, and is also located between the first fin-shaped isolation structure 312 and the N-type drift layer 200, thereby isolating the first N-type doping material layer 410 from the N-type drift layer 200. The first isolation doping structure 313 is located between the first gate metal layer 710 and the first N-type doping material layer 410, and is located between the first gate metal layer 710 and the first fin-shaped isolation structure 312, thereby isolating the first gate metal layer 710 from the first N-type doping material layer 410.

[0052] Taking the enhancement-type fin-shaped MOS switch device as an example, applying a high voltage to the first gate metal layer 710 can reduce the depletion region of the first JFET structure under the fin gate, thereby turning on the device. If the voltage applied to the first gate metal layer 710 is lower than the turn-off threshold voltage, the depletion region of the first JFET structure under the fin gate can be kept unchanged, thereby turning off the device.

[0053] In practical applications, if the transistor device is a depletion-type normally-on device, a negative voltage needs to be connected to the first gate metal layer 710 to turn off the transistor.

[0054] Combine Figure 3 As shown, the second P-type doping layer 310 includes a second horizontal doping structure 321 , a second isolation doping structure 323 and a plurality of second fin-shaped isolation structures 322 .

[0055] The second fin-shaped isolation structures 322 do not contact each other and are disposed between the second horizontal doping structure 321 and the second isolation doping structure 323 . The second isolation doping structure 323 contacts the second gate metal layer 720 . The second horizontal doping structure 321 is disposed on the N-type drift layer 200 .

[0056] In this embodiment, the second horizontal doping structure 321, the second isolation doping structure 323 and the multiple second fin-shaped isolation structures 322 are all P-type doped semiconductors, wherein the second horizontal doping structure 321 is located between the second N-type doping material layer 420 and the N-type drift layer 200, and is also located between the second fin-shaped isolation structure 322 and the N-type drift layer 200, thereby isolating the second N-type doping material layer 420 from the N-type drift layer 200. The second isolation doping structure 323 is located between the second gate metal layer 720 and the second N-type doping material layer 420, and is located between the second gate metal layer 720 and the second fin-shaped isolation structure 322, thereby isolating the second gate metal layer 720 from the second N-type doping material layer 420.

[0057] Taking the enhancement-type fin-shaped MOS switch device as an example, applying a high voltage to the second gate metal layer 720 can reduce the depletion region of the second JFET structure under the fin gate, thereby turning on the device. If the voltage applied to the second gate metal layer 720 is lower than the turn-off threshold voltage, the depletion region of the second JFET structure under the fin gate can be kept unchanged, thereby turning off the device.

[0058] In practical applications, if the transistor device is a depletion-type normally-on device, a negative voltage needs to be connected to the second gate metal layer 720 to turn off the transistor.

[0059] In one embodiment, the first horizontal doping structure 311 and the first isolation doping structure 313 are arranged in parallel.

[0060] Combine Figure 2 As shown, the first N-type doping material layer 610 is filled between the fin structures of the first P-type doping layer 310 to isolate the connection region 830 and the first source doping layer 810 . At the same time, multiple first fin isolation structures 312 and multiple first N-type doping material layers 410 are alternately arranged.

[0061] In one embodiment, the second horizontal doping structure 321 and the second isolation doping structure 323 are arranged in parallel.

[0062] Combine Figure 3 As shown, the second N-type doping material layer 320 is filled between the fin structures of the second P-type doping layer 320 to isolate the connection area 830 and the second source doping layer 820 , and multiple second fin isolation structures 322 and multiple second N-type doping material layers 420 are alternately arranged.

[0063] Specifically, multiple first fin-shaped isolation structures 312 are arranged on the first horizontal doped structure 311 and contact the connection region 830 and the first source doped layer 810, and are used to provide multiple current channels between the connection region 830 and the first source doped layer 810 when the device is turned on. Multiple second fin-shaped isolation structures 322 are arranged on the second horizontal doped structure 321 and contact the connection region 830 and the second source doped layer 820, and are used to provide multiple current channels between the connection region 830 and the second source doped layer 810 when the device is turned on.

[0064] In one embodiment, the first P-type doped layer 310 and the second P-type doped layer 320 are both made of P-type semiconductor materials, such as P-type silicon carbide, P-type silicon, or P-type gallium nitride.

[0065] In one embodiment, the semiconductor substrate 100 may be silicon carbide, silicon, or gallium nitride.

[0066] In one embodiment, combined Figure 1 As shown, the plurality of first fin-shaped isolation structures 312 and the plurality of second fin-shaped isolation structures 322 are arranged in a one-to-one correspondence.

[0067] Specifically, the plurality of first fin-shaped isolation structures 312 and the plurality of second fin-shaped isolation structures 322 are combined Figure 1 As shown, Figure 1 The dotted arrow in the figure represents the current path. After the first gate metal layer 710 and the second gate metal layer 720 on the fin structure induce a current channel, the current flows out from the drain on the back side of the semiconductor substrate 100, passes through the N-type drift layer 200 and the connection area 830 of the fin area, and reaches the source through the first P-type doped layer 310 and the second P-type doped layer 320 of the fin structure, achieving the purpose of taking into account high breakdown voltage, high current density and small device area.

[0068] In one embodiment, the device's withstand voltage can be increased by designing the thickness of the wafer, thereby cooperating with the switching of the fin-shaped MOS switch device and increasing the width of the device, such as Figure 1 The dotted arrow portion in FIG. achieves high current density and high breakdown voltage within the same chip area. Compared to conventional device designs, although the connection region 830 is added, as process evolution allows for the introduction of more high aspect ratio technologies, the fin-shaped MOS switch device in this embodiment has significant development potential.

[0069] In one embodiment, the connection region 830 can be integrally formed with the N-type drift layer 200. For example, the connection region 830 is also an N-type semiconductor. The central protruding structure is retained by etching both sides of the N-type drift layer 200, and the protruding structure is used as the connection region 830. Then, a first P-type doped layer 310 and a second P-type doped layer 320 are formed on both sides of the connection region 830.

[0070] In one embodiment, the concentration of the P-type doping ions in the first fin isolation structure 312 and the second fin isolation structure 322 is lower than the concentration of the P-type doping ions in the first horizontal doping structure 311 and the second horizontal doping structure 321 .

[0071] In one embodiment, the first gate metal layer 710 is disposed perpendicular to the first fin isolation structure 312 , and the width of the first gate metal layer 710 is smaller than the length of the first fin isolation structure 312 .

[0072] In one embodiment, the second gate metal layer 720 is disposed perpendicular to the second fin isolation structure 322 , and the width of the second gate metal layer 720 is smaller than the length of the second fin isolation structure 322 .

[0073] In one embodiment, the first source doping layer 810 is disposed on the first horizontal doping structure 311 and contacts the plurality of first fin isolation structures 312 .

[0074] In this embodiment, the first source doping layer 810 and the multiple first fin isolation structures 312 are all arranged on the first horizontal doping structure 311 , and the sum of the width of the first source doping layer 810 and the length of the first fin isolation structure 312 is equal to the length of the first horizontal doping structure 311 .

[0075] In one embodiment, the second source doping layer 820 is disposed on the second horizontal doping structure 321 and is in contact with the plurality of second fin-shaped isolation structures 322 .

[0076] In this embodiment, the second source doping layer 820 and the plurality of second fin isolation structures 322 are both disposed on the second horizontal doping structure 321 , and the sum of the width of the second source doping layer 820 and the length of the second fin isolation structure 322 is equal to the length of the second horizontal doping structure 321 .

[0077] In one embodiment, the first source doping layer 810 and the plurality of first fin isolation structures 312 are vertically arranged.

[0078] In one embodiment, the second source doping layer 820 is disposed perpendicular to the plurality of second fin isolation structures 322 .

[0079] In one embodiment, the first source doping layer 810 and the second source doping layer 820 are N-type semiconductors.

[0080] In one embodiment, the P-type semiconductor may be P-type silicon carbide, P-type silicon, or P-type gallium nitride, and the N-type semiconductor may be N-type silicon carbide, N-type silicon, or N-type gallium nitride.

[0081] The present application also provides a method for preparing a fin-shaped MOS switch device, see Figure 1 As shown, the preparation method in this embodiment includes steps S10 to S70.

[0082] The following combination Figure 1 、 Figure 2 as well as Figure 3 Steps S10 to S70 will be described.

[0083] Combine Figure 1 As shown, in step S10 , an N-type drift layer 200 is formed on the front surface of the semiconductor substrate 100 .

[0084] The N-type drift layer 200 is formed on the front surface of the semiconductor substrate 100 , which is an N-type semiconductor.

[0085] In one embodiment, the semiconductor substrate 100 may be silicon carbide, silicon, or gallium nitride.

[0086] In step S20 , a first horizontal doping structure 311 and a second horizontal doping structure 321 are formed on the N-type drift layer 200 , and a plurality of first fin isolation structures 321 and a plurality of second fin isolation structures 322 are formed on the first horizontal doping structure 311 and the second horizontal doping structure 321 , respectively.

[0087] In step S30 , a plurality of first N-type doping material layers 410 are formed between the plurality of first fin isolation structures 321 , and a first isolation doping structure 313 is formed on the first fin isolation structure 321 and the first N-type doping material layer 410 to form a first P-type doping layer 310 of a cross-shaped fin structure.

[0088] In this embodiment, the first P-type doping layer 310 of the cross-shaped fin structure is composed of the first horizontal doping structure 311, the first isolation doping structure 313 and the multiple first fin isolation structures 312, and the first N-type doping material layer 410 is filled between the fin structures of the first P-type doping layer 310.

[0089] In one embodiment, the first horizontal doping structure 311, the first isolation doping structure 313 and the multiple first fin-shaped isolation structures 312 are all P-type doped semiconductors, wherein the first horizontal doping structure 311 is located between the first N-type doping material layer 410 and the N-type drift layer 200, and is also located between the first fin-shaped isolation structure 312 and the N-type drift layer 200, thereby isolating the first N-type doping material layer 410 and the N-type drift layer 200.

[0090] In step S40 , a plurality of second N-type doping material layers 420 are formed between the plurality of second fin isolation structures 322 , and a second isolation doping structure 323 is formed on the second fin isolation structure 322 and the second N-type doping material layer 420 to form a second P-type doping layer 320 of a cross-shaped fin structure.

[0091] In this embodiment, a second P-type doping layer 320 of a cross-shaped fin structure is formed by a second horizontal doping structure 321, a second isolation doping structure 323 and a plurality of second fin-shaped isolation structures 322. The plurality of second fin-shaped isolation structures 322 do not contact each other and are arranged between the second horizontal doping structure 321 and the second isolation doping structure 323, and the second isolation doping structure 323 is in contact with the second gate metal layer 720. The second horizontal doping structure 321 is arranged on the N-type drift layer 200, and the second N-type doping material layer 320 is filled between the fin structures of the second P-type doping layer 320.

[0092] In one embodiment, the second horizontal doping structure 321, the second isolation doping structure 323 and the multiple second fin-shaped isolation structures 322 are all P-type doped semiconductors, wherein the second horizontal doping structure 321 is located between the second N-type doping material layer 420 and the N-type drift layer 200, and is also located between the second fin-shaped isolation structure 322 and the N-type drift layer 200, thereby isolating the second N-type doping material layer 420 and the N-type drift layer 200.

[0093] In step S50 , a connection region 830 is formed between the first P-type doping layer 310 and the second P-type doping layer 320 , and a first P-type doping layer 310 and a second P-type doping layer 320 are formed outside the first P-type doping layer 310 and outside the second P-type doping layer 320 , respectively.

[0094] In one embodiment, both sides of the N-type drift layer 200 may be etched to retain a central protruding structure, with the protruding structure serving as the connection region 830 , and then a first P-type doped layer 310 and a second P-type doped layer 320 may be formed on both sides of the connection region 830 .

[0095] In step S60 , a first gate metal layer 710 is formed on the first isolation doping structure 313 , and a second gate metal layer 720 is formed on the second isolation doping structure 323 .

[0096] In step S70 , a drain metal layer 850 is formed on the back surface of the semiconductor substrate 100 .

[0097] In one embodiment, the first source doping layer 810 and the second source doping layer 820 are connected to the source electrode of the device through a metal wire.

[0098] An embodiment of the present application further provides a chip, in which the fin-shaped MOS switch device as described in any of the above embodiments is integrated.

[0099] In one embodiment, the chip integrates a fin-shaped MOS switch device manufactured by the manufacturing method described in the above embodiment.

[0100] In this embodiment, the chip includes a chip substrate, on which one or more fin-shaped MOS switch devices are arranged. The fin-shaped MOS switch device can be prepared by the preparation method in any of the above embodiments, or the fin-shaped MOS switch device in any of the above embodiments can be arranged on the chip substrate.

[0101] In a specific application embodiment, other related semiconductor devices may be integrated on the chip substrate to form an integrated circuit together with the fin-shaped MOS switch device.

[0102] In a specific application embodiment, the chip may be a switch chip or a driver chip.

[0103] The beneficial effects of the embodiments of the present application compared with the prior art are: by forming an N-type drift layer on a semiconductor substrate, forming a connection area on the N-type drift layer, forming a P-type doped layer with a cross-shaped fin structure on both sides of the connection area, and forming a gate metal layer on the P-type doped layer, and forming an N-type doped material layer between the fin structures of the P-type doped layer, forming a first source doped layer and a second source doped layer on the outside of the P-type doped layers on both sides, thereby forming a JFET structure on both sides of the connection area, so that the current flowing out from the drain on the back side of the semiconductor substrate passes through the N-type drift layer and the connection area of ​​the fin area, and reaches the source through the current channel of the JFET structure. The current channel is induced by the gate metal layer on the fin structure to turn on the device, thereby achieving the purpose of taking into account high breakdown voltage, high current density and small device area.

[0104] Those skilled in the art will clearly understand that for the sake of convenience and brevity in description, only the division of the above-mentioned doping regions is used as an example. In actual applications, the above-mentioned functional areas can be allocated to different doping regions as needed, that is, the internal structure of the device can be divided into different doping regions to complete all or part of the functions described above.

[0105] The doping regions in the embodiment can be integrated into one functional region, or each doping region can exist physically separately, or two or more doping regions can be integrated into one functional region. The above-mentioned integrated functional regions can be implemented by using the same doping ion or by using multiple doping ions. In addition, the specific names of the doping regions are only for the convenience of distinguishing each other and are not used to limit the scope of protection of this application. The specific working process of the doping region in the preparation method of the above-mentioned device can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0106] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A fin-shaped MOS switch device, characterized in that: The fin-shaped MOS switch device comprises: semiconductor substrates; An N-type drift layer is provided on the front surface of the semiconductor substrate; A first P-type doping layer and a second P-type doping layer are provided on the N-type drift layer, and the first P-type doping layer and the second P-type doping layer are in a cross-shaped fin structure; A first gate metal layer and a second gate metal layer are connected to the first P-type doped layer and the second P-type doped layer respectively; a connection region, provided between the first P-type doped layer and the second P-type doped layer; A first source doping layer and a second source doping layer are respectively arranged on the outer side of the first P-type doping layer and the outer side of the second P-type doping layer; a plurality of first N-type doping material layers, filled between the fin-shaped structures of the first P-type doping layer to isolate the connection region from the first source doping layer; a plurality of second N-type doping material layers, filled between the fin-shaped structures of the second P-type doping layer to isolate the connection region from the second source doping layer; The drain metal layer is arranged on the back side of the semiconductor substrate.

2. The fin-shaped MOS switch device according to claim 1, wherein: The first P-type doping layer includes: a first horizontal doping structure, a first isolation doping structure and a plurality of first fin-shaped isolation structures; The plurality of first fin-shaped isolation structures do not contact each other and are arranged between the first horizontal doping structure and the first isolation doping structure, and the first isolation doping structure contacts the first gate metal layer. The first horizontal doping structure is arranged on the N-type drift layer.

3. The fin-shaped MOS switch device according to claim 2, wherein: The second P-type doping layer includes: a second horizontal doping structure, a second isolation doping structure and a plurality of second fin-shaped isolation structures; The plurality of second fin-shaped isolation structures do not contact each other and are arranged between the second horizontal doping structure and the second isolation doping structure, and the second isolation doping structure contacts the second gate metal layer. The second horizontal doping structure is arranged on the N-type drift layer.

4. The fin-shaped MOS switch device according to claim 3, wherein: The plurality of first fin-shaped isolation structures and the plurality of second fin-shaped isolation structures are arranged in a one-to-one correspondence.

5. The fin-shaped MOS switch device according to claim 3 or 4, wherein: The first gate metal layer is disposed perpendicular to the first fin isolation structure, and a width of the first gate metal layer is smaller than a length of the first fin isolation structure.

6. The fin-shaped MOS switch device according to claim 3 or 4, characterized in that: The first source doping layer is disposed on the first horizontal doping structure and is in contact with the first fin-shaped isolation structures.

7. The fin-shaped MOS switch device according to claim 3 or 4, wherein: The second source doping layer is disposed on the second horizontal doping structure and contacts the second fin-shaped isolation structures.

8. The fin MOS switch device according to claim 7, wherein: The first source doping layer is perpendicular to the first fin isolation structure; The second source doping layer is perpendicular to the second fin-shaped isolation structure.

9. A method for preparing a fin-shaped MOS switch device, characterized in that: The preparation method comprises: forming an N-type drift layer on the front surface of the semiconductor substrate; forming a first horizontal doping structure and a second horizontal doping structure on the N-type drift layer, and forming a plurality of first fin-shaped isolation structures and a plurality of second fin-shaped isolation structures on the first horizontal doping structure and the second horizontal doping structure, respectively; forming a plurality of first N-type doping material layers between the plurality of first fin-shaped isolation structures, and forming a first isolation doping structure on the first fin-shaped isolation structures and the first N-type doping material layers to form a first P-type doping layer of a cross-shaped fin structure; forming a plurality of second N-type doping material layers between the plurality of second fin-shaped isolation structures, and forming a second isolation doping structure on the second fin-shaped isolation structure and the second N-type doping material layer to form a second P-type doping layer of a cross-shaped fin structure; forming a connection region between the first P-type doping layer and the second P-type doping layer, and forming a first source doping layer and a second source doping layer on the outer sides of the first P-type doping layer and the outer sides of the second P-type doping layer, respectively; forming a first gate metal layer on the first isolation doping structure, and forming a second gate metal layer on the second isolation doping structure; A drain metal layer is formed on the back side of the semiconductor substrate.

10. A chip, characterized in that: The chip integrates the fin-shaped MOS switch device according to any one of claims 1 to 8; or includes a fin-shaped MOS switch device prepared by the preparation method according to claim 9.

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