A power MOSFET device with improved output capacitance

Abstract

The present invention relates to power semiconductor technology, and in particular to a power MOSFET device with improved output capacitance, comprising a drain metal, a heavily doped first conductivity type semiconductor substrate, a lightly doped second conductivity type semiconductor epitaxial layer, a lightly doped first conductivity type semiconductor buried layer, a heavily doped first conductivity type semiconductor vertical sinker, a gate dielectric layer, a gate polysilicon electrode, a second conductivity type semiconductor body region, a first conductivity type semiconductor drift region, a heavily doped first conductivity type semiconductor source region, a heavily doped second conductivity type semiconductor ohmic contact region, an insulating dielectric layer, and a source metal. The power MOSFET device structure with improved output capacitance provided by the present invention further widens the depletion region of the PN junction between the drain and source by introducing a buried layer structure below the semiconductor body region to assist in the depletion epitaxial layer, thereby reducing the junction capacitance between the drain and source, thereby improving the output capacitance of the device.

Description

Technical Field

[0001] The present invention relates to power semiconductor technology, and in particular to a power MOSFET device with improved output capacitance. Background Art

[0002] Power semiconductor devices, also known as power electronic devices, are devices capable of handling high currents and high voltages and are essential components in modern electronic systems. Power MOSFETs offer advantages such as high input impedance, low conduction and switching losses, and high reliability, making them commonly used as electronic switches in power management applications.

[0003] Power MOSFET devices are divided into lateral power MOSFET devices and vertical power MOSFET devices based on the direction of the current path when conducting. Lateral power MOSFET devices and vertical power MOSFET devices each have advantages and disadvantages. Lateral power MOSFET devices have low gate-drain capacitance but high on-resistance, resulting in a wider cell width, lower current density, and poor overcurrent capability. Vertical power MOSFET devices have low on-resistance and better overcurrent capability, but significant gate parasitics (especially high gate-drain capacitance), resulting in low switching speeds and high drive power consumption. To address these issues, TI proposed the NexFET, which uses heavily doped vertical sinkers to change the carrier movement path of lateral power MOSFET devices to a vertical one. This helps reduce the size of the cell and improves the device's overcurrent capability, while also maintaining low gate-drain capacitance.

[0004] The heavily doped vertical sinker structure effectively addresses the current density and current capability limitations of lateral power MOSFETs, as well as the gate parasitics issues of vertical power MOSFETs. However, this results in a larger area for the PN junction capacitance between the drain and source within the device, leading to larger internal drain-source capacitance, which in turn increases the device's output capacitance and reduces output efficiency. Therefore, improving output capacitance is one of the current challenges in the design of power MOSFETs with heavily doped vertical sinkers. Summary of the Invention

[0005] In view of the above problems, the present invention proposes a power MOSFET device with improved output capacitance.

[0006] In order to achieve the above-mentioned purpose of the invention, the technical solution of the present invention is as follows:

[0007] A power MOSFET device with improved output capacitance includes a drain metal 1, a heavily doped first conductivity type semiconductor substrate 2, a lightly doped second conductivity type semiconductor epitaxial layer 3, a lightly doped first conductivity type semiconductor buried layer 4, a heavily doped first conductivity type semiconductor vertical sinker 5, a gate dielectric layer 6, a gate polysilicon electrode 7, a second conductivity type semiconductor body region 8, a first conductivity type semiconductor drift region 9, a heavily doped first conductivity type semiconductor source region 10, a heavily doped second conductivity type semiconductor ohmic contact region 12, an insulating dielectric layer 11, and a source metal 13.

[0008] The heavily doped first conductive type semiconductor substrate 2 is located above the drain metal 1, the lightly doped second conductive type semiconductor epitaxial layer 3 is located above the heavily doped first conductive type semiconductor substrate 2, the second conductive type semiconductor body region 8 is located in the upper left of the lightly doped second conductive type semiconductor epitaxial layer 3, the heavily doped first conductive type semiconductor vertical sinker 5 is located in the right side of the lightly doped second conductive type semiconductor epitaxial layer 3, the lightly doped first conductive type semiconductor buried layer 4 is located directly below the second conductive type semiconductor body region 8 in the lightly doped second conductive type semiconductor epitaxial layer 3 and is in direct contact with the second conductive type semiconductor body region 8, and its width is greater than the second conductive type semiconductor body region 8; the first conductive type semiconductor drift region 9 is located in the upper part of the lightly doped second conductive type semiconductor epitaxial layer 3, and its two sides are in direct contact with the heavily doped first conductive type semiconductor vertical sinker 5 and the second conductive type semiconductor body region 8; the heavily doped first conductive type semiconductor vertical sinker 5 extends into the lightly doped second conductive type semiconductor epitaxial layer 3 to the heavily doped first conductivity type semiconductor substrate 2, connecting the first conductivity type semiconductor drift region 9 and the heavily doped first conductivity type semiconductor substrate 2; the upper left inside of the second conductivity type semiconductor body region 8 is provided with a heavily doped first conductivity type semiconductor source region 10 and a heavily doped second conductivity type semiconductor ohmic contact region 12; the left side of the heavily doped first conductivity type semiconductor source region 10 is in contact with the source metal 13, and the upper side of the heavily doped second conductivity type semiconductor ohmic contact region 12 is in contact with the source metal 13; the upper surface of the second conductivity type semiconductor epitaxial layer 3 is covered with an insulating dielectric layer 11, and the insulating dielectric layer 11 surrounds the gate polysilicon electrode 7; the gate polysilicon electrode 7 is isolated from the second conductivity type semiconductor body region 8 by the gate dielectric layer 6; the source metal 13 is located on the upper surface of the insulating dielectric layer 11 and completely covers the area where the first conductivity type semiconductor drift region 9 is located; the source metal 13 extends into the semiconductor material through the contact hole, and its depth is deeper than the heavily doped first conductivity type semiconductor source region 10.

[0009] The present invention also provides a second power MOSFET device with improved output capacitance, comprising a drain metal 1, a heavily doped first conductivity type semiconductor substrate 2, a lightly doped second conductivity type semiconductor epitaxial layer 3, a lightly doped first conductivity type semiconductor buried layer 4, a heavily doped first conductivity type semiconductor vertical sinker 5, a gate dielectric layer 6, a gate polysilicon electrode 7, a second conductivity type semiconductor body region 8, a first conductivity type semiconductor drift region 9, a heavily doped first conductivity type semiconductor source region 10, a heavily doped second conductivity type semiconductor ohmic contact region 12, an insulating dielectric layer 11, a source metal 13, and a second conductivity type semiconductor buried layer 14;

[0010] The heavily doped first conductive type semiconductor substrate 2 is located above the drain metal 1, the lightly doped second conductive type semiconductor epitaxial layer 3 is located above the heavily doped first conductive type semiconductor substrate 2, the second conductive type semiconductor body region 8 is located in the upper left of the lightly doped second conductive type semiconductor epitaxial layer 3, the heavily doped first conductive type semiconductor vertical sinker 5 is located in the right of the lightly doped second conductive type semiconductor epitaxial layer 3, the lightly doped first conductive type semiconductor buried layer 4 is located below the second conductive type semiconductor body region 8 in the lightly doped second conductive type semiconductor epitaxial layer 3, a second conductive type semiconductor buried layer 14 is provided between the lightly doped first conductive type semiconductor buried layer 4 and the second conductive type semiconductor body region 8, the width of the second conductive type semiconductor body region 8 is less than or equal to the width of the second conductive type semiconductor buried layer 14, and the width of the second conductive type semiconductor buried layer 14 is less than or equal to the width of the lightly doped first conductive type semiconductor buried layer 4;

[0011] The first conductive type semiconductor drift region 9 is located in the upper part of the lightly doped second conductive type semiconductor epitaxial layer 3, and its two sides are in direct contact with the heavily doped first conductive type semiconductor vertical sinker 5 and the second conductive type semiconductor body region 8; the heavily doped first conductive type semiconductor vertical sinker 5 extends into the lightly doped second conductive type semiconductor epitaxial layer 3 to the heavily doped first conductive type semiconductor substrate 2, connecting the first conductive type semiconductor drift region 9 and the heavily doped first conductive type semiconductor substrate 2; the second conductive type semiconductor body region 8 has a heavily doped first conductive type semiconductor source region 10 and a heavily doped second conductive type semiconductor ohmic contact region 12 in the upper left corner; the heavily doped The left side of the first conductive type semiconductor source region 10 is in contact with the source metal 13, and the heavily doped second conductive type semiconductor ohmic contact region 12 is in contact with the source metal 13 above; the upper surface of the second conductive type semiconductor epitaxial layer 3 is covered with an insulating dielectric layer 11, and the insulating dielectric layer 11 surrounds the gate polysilicon electrode 7; the gate polysilicon electrode 7 is isolated from the second conductive type semiconductor body region 8 by the gate dielectric layer 6; the source metal 13 is located on the upper surface of the insulating dielectric layer 11 and completely covers the area where the first conductive type semiconductor drift region 9 is located; the source metal 13 extends into the semiconductor material through the contact hole, and its depth is deeper than the heavily doped first conductive type semiconductor source region 10.

[0012] As a preferred embodiment, the doping concentration of the heavily doped nanostructured ... -3 The doping concentration of the first conductive type semiconductor drift region 9 is in the range of 1e17 cm -3 -3e17 cm -3 The doping concentration range of the lightly doped first conductivity type semiconductor buried layer 4 is 2e16 cm -3 -5e16 cm -3 The doping concentration of the lightly doped second conductivity type semiconductor epitaxial layer 3 is less than 1e17 cm -3 .

[0013] As a preferred embodiment, the first conductive type semiconductor is an N-type semiconductor, and the second conductive type semiconductor is a P-type semiconductor; or the first conductive type semiconductor is a P-type semiconductor, and the second conductive type semiconductor is an N-type semiconductor.

[0014] As a preferred embodiment, the semiconductor material is silicon or silicon carbide.

[0015] The beneficial effects of the present invention are as follows: compared to the traditional power MOSFET device with a heavily doped vertical sinker, the power MOSFET device structure provided by the present invention improves the output capacitance by introducing a buried layer structure below the semiconductor body region to assist in depleting the epitaxial layer. When the device is subjected to voltage, the PN junction composed of the heavily doped substrate, the heavily doped vertical sinker and the lightly doped epitaxial layer is reverse biased to withstand the withstand voltage, forming a part of the depletion region. The buried layer located below the semiconductor body region can assist in depleting the lightly doped epitaxial layer, and its depletion region is connected to the depletion region of the former, so that the depletion region is further widened, and then the junction capacitance between the drain and source inside the device is reduced, thereby improving the output capacitance of the device. The structure of the present invention reduces the output capacitance of the device on the basis of ensuring the original basic electrical performance of the device without affecting the static electrical parameters of the device, thereby effectively improving the output efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 1 is a schematic structural diagram of a power MOSFET device with improved output capacitance according to embodiment 1 of the present invention;

[0017] Figure 2 This is a schematic diagram of the depletion region and drain-source capacitance of a traditional power MOSFET device with a heavily doped vertical sinker;

[0018] Figure 3 Schematic diagram of the depletion region and drain-source capacitance of a power MOSFET device with improved output capacitance according to embodiment 1 of the present invention;

[0019] Figure 4 This is a depletion region simulation diagram of a power MOSFET device with improved output capacitance according to embodiment 1 of the present invention;

[0020] Figure 5 This is a comparison diagram of the output capacitance of a power MOSFET device with improved output capacitance according to Example 1 of the present invention and a conventional power MOSFET device with a heavily doped vertical sinker;

[0021] Figure 6 1 is a schematic structural diagram of a power MOSFET device with improved output capacitance according to embodiment 2 of the present invention;

[0022] Figures 7 to 13 This is a key process step in the manufacturing process of a power MOSFET device with improved output capacitance according to embodiment 1 of the present invention.

[0023] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0024] 1 is the drain metal, 2 is the heavily doped first conductivity type semiconductor substrate, 3 is the lightly doped second conductivity type semiconductor epitaxial layer, 4 is the lightly doped first conductivity type semiconductor buried layer, 5 is the heavily doped first conductivity type semiconductor vertical sinker, 6 is the gate dielectric layer, 7 is the gate polysilicon electrode, 8 is the second conductivity type semiconductor body region, 9 is the first conductivity type semiconductor drift region, 10 is the heavily doped first conductivity type semiconductor source region, 12 is the heavily doped second conductivity type semiconductor ohmic contact region, 11 is the insulating dielectric layer, 13 is the source metal, and 14 is the second conductivity type semiconductor buried layer.

[0025] Figure 2 In the figure, the dotted line represents the depletion region boundary, C1 represents the depletion layer capacitance of the PN junction composed of the lightly doped epitaxial layer and the drift region, C2 represents the depletion layer capacitance of the PN junction composed of the lightly doped epitaxial layer and the heavily doped vertical sinker, C3 represents the depletion layer capacitance of the PN junction composed of the lightly doped epitaxial layer and the heavily doped substrate, S represents the source, and D represents the drain.

[0026] Figure 4 In the figure, the white line indicates the depletion region boundary. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] Example 1

[0029] like Figure 1 As shown, this embodiment provides a power MOSFET device with improved output capacitance, including a drain metal 1, a heavily doped first conductivity type semiconductor substrate 2, a lightly doped second conductivity type semiconductor epitaxial layer 3, a lightly doped first conductivity type semiconductor buried layer 4, a heavily doped first conductivity type semiconductor vertical sinker 5, a gate dielectric layer 6, a gate polysilicon electrode 7, a second conductivity type semiconductor body region 8, a first conductivity type semiconductor drift region 9, a heavily doped first conductivity type semiconductor source region 10, a heavily doped second conductivity type semiconductor ohmic contact region 12, an insulating dielectric layer 11, and a source metal 13;

[0030] The heavily doped first conductive type semiconductor substrate 2 is located above the drain metal 1, the lightly doped second conductive type semiconductor epitaxial layer 3 is located above the heavily doped first conductive type semiconductor substrate 2, the second conductive type semiconductor body region 8 is located in the upper left of the lightly doped second conductive type semiconductor epitaxial layer 3, the heavily doped first conductive type semiconductor vertical sinker 5 is located in the right side of the lightly doped second conductive type semiconductor epitaxial layer 3, the lightly doped first conductive type semiconductor buried layer 4 is located directly below the second conductive type semiconductor body region 8 in the lightly doped second conductive type semiconductor epitaxial layer 3 and is in direct contact with the second conductive type semiconductor body region 8, and its width is greater than the second conductive type semiconductor body region 8; the first conductive type semiconductor drift region 9 is located in the upper part of the lightly doped second conductive type semiconductor epitaxial layer 3, and its two sides are in direct contact with the heavily doped first conductive type semiconductor vertical sinker 5 and the second conductive type semiconductor body region 8; the heavily doped first conductive type semiconductor vertical sinker 5 extends into the lightly doped second conductive type semiconductor epitaxial layer 3 to the heavily doped first conductivity type semiconductor substrate 2, connecting the first conductivity type semiconductor drift region 9 and the heavily doped first conductivity type semiconductor substrate 2; the upper left inside of the second conductivity type semiconductor body region 8 is provided with a heavily doped first conductivity type semiconductor source region 10 and a heavily doped second conductivity type semiconductor ohmic contact region 12; the left side of the heavily doped first conductivity type semiconductor source region 10 is in contact with the source metal 13, and the upper side of the heavily doped second conductivity type semiconductor ohmic contact region 12 is in contact with the source metal 13; the upper surface of the second conductivity type semiconductor epitaxial layer 3 is covered with an insulating dielectric layer 11, and the insulating dielectric layer 11 surrounds the gate polysilicon electrode 7; the gate polysilicon electrode 7 is isolated from the second conductivity type semiconductor body region 8 by the gate dielectric layer 6; the source metal 13 is located on the upper surface of the insulating dielectric layer 11 and completely covers the area where the first conductivity type semiconductor drift region 9 is located; the source metal 13 extends into the semiconductor material through the contact hole, and its depth is deeper than the heavily doped first conductivity type semiconductor source region 10.

[0031] The doping concentration of the heavily doped -3 The doping concentration of the first conductive type semiconductor drift region 9 is in the range of 1e17 cm -3 -3e17 cm -3 The doping concentration range of the lightly doped first conductivity type semiconductor buried layer 4 is 2e16 cm -3 -5e16cm -3 The doping concentration of the lightly doped second conductivity type semiconductor epitaxial layer 3 is less than 1e17 cm -3 .

[0032] The working principle of the present invention is described below using the first embodiment as an example:

[0033] When the device is subjected to voltage, the traditional power MOSFET device with heavily doped vertical sinker only has the first depletion region of the PN junction composed of the heavily doped substrate, heavily doped vertical sinker, drift region and lightly doped epitaxial layer, such as Figure 2 As shown, the dotted line represents the depletion region boundary. In addition, Figure 2 It also points out the drain-source capacitance structure inside the device, the drain-source capacitance C ds The following relationships exist with these capacitors:

[0034] C ds = C1+C2+C3 (1)

[0035] In the formula, C1 represents the depletion layer capacitance of the PN junction formed by the lightly doped epitaxial layer and the drift region; C2 represents the depletion layer capacitance of the PN junction formed by the lightly doped epitaxial layer and the heavily doped vertical sinker; and C3 represents the depletion layer capacitance of the PN junction formed by the lightly doped epitaxial layer and the heavily doped substrate. Clearly, the drain-source capacitance of a conventional power MOSFET device with a heavily doped vertical sinker is composed of these three components in parallel.

[0036] The present invention provides a power MOSFET device structure with improved output capacitance, wherein a lightly doped first conductive type semiconductor buried layer 4 is introduced below the second conductive type semiconductor body region 8 to form a second depletion region, and the second depletion region is connected to the first depletion region, so that the depletion region is further widened. Figure 3 As shown. Since the depletion layer capacitance of the PN junction can be approximated as an ordinary parallel plate capacitor, the depletion layer capacitance and the depletion region width have the following relationship:

[0037]

[0038] Where C d Represents the depletion layer capacitance per unit area of ​​PN junction; ε s represents the dielectric constant of the semiconductor; x d Refers to the width of the PN junction depletion region.

[0039] Therefore, the depletion region is further widened, reducing the junction capacitance between the drain and source within the device, thereby improving the device output capacitance. It is worth noting that the doping concentration of the lightly doped first conductivity type semiconductor buried layer 4 should not be too high, otherwise the PN junction formed by the second conductivity type semiconductor body region 8 and the lightly doped first conductivity type semiconductor buried layer 4 will break down prematurely, causing the device to malfunction. In addition, the width of the lightly doped first conductive type semiconductor buried layer 4 also needs to be designed according to the specific parameters of the device. If the width is too large, when the lightly doped first conductive type semiconductor buried layer 4 diffuses to the heavily doped vertical sinker, that is, when it is in direct contact with the vertical sinker, the potential of the lightly doped first conductive type semiconductor buried layer 4 will become the drain potential. At this time, the PN junction formed by the second conductive type semiconductor body region 8 and the lightly doped first conductive type semiconductor buried layer 4 will break down prematurely, causing the device to malfunction. If the width is too small, the distance between the lightly doped first conductive type semiconductor buried layer 4 and the heavily doped first conductive type semiconductor vertical sinker 5 is large, and the effect on the depletion region of the PN junction formed by the lightly doped second conductive type semiconductor epitaxial layer and the heavily doped first conductive type semiconductor vertical sinker will be weakened, and the depletion region cannot be effectively widened. The structure of the present invention reduces the output capacitance of the device and effectively improves the output efficiency without affecting the static electrical parameters of the device while ensuring the original basic electrical performance of the device.

[0040] Figure 5 This is a comparison diagram of the output capacitance of a power MOSFET device with improved output capacitance in Example 1 of the present invention and a traditional power MOSFET device with a heavily doped vertical sinker. Compared with the output capacitance of the traditional structure, the output capacitance of the new structure is smaller, and it is more obvious when the external drain voltage is small. As the external drain voltage increases, the gap between the two will narrow.

[0041] like Figures 7 to 13 As shown, the key process steps in the manufacturing process of a power MOSFET device with improved output capacitance provided by this embodiment are as follows:

[0042] 1. Epitaxially grow a portion of lightly doped second conductivity type semiconductor epitaxial layer 3 on heavily doped first conductivity type semiconductor substrate 2, ion implant lightly doped first conductivity type semiconductor buried layer 4 and anneal. Figure 7 As shown;

[0043] 2. Continue epitaxial growth of a lightly doped second conductivity type semiconductor epitaxial layer 3, such as Figure 8 As shown;

[0044] 3. Etch a trench in the lightly doped second conductivity type semiconductor epitaxial layer 3 and deposit a heavily doped first conductivity type semiconductor vertical sinker 5, as shown in FIG. Figure 9 As shown;

[0045] 4. Thermal oxidation growth gate dielectric layer 6, deposit gate polysilicon electrode 7 and etch, as shown in FIG. Figure 10 As shown;

[0046] 5. Ion implantation into the second conductive type semiconductor body region 8, the first conductive type semiconductor drift region 9 and the heavily doped first conductive type semiconductor source region 10 and then push the junction, as shown in FIG. Figure 11 As shown;

[0047] 6. Deposit an insulating dielectric layer 11, etch contact holes, ion implant heavily dope the second conductive type semiconductor ohmic contact region 12 and push the junction, and deposit the source metal 13, as shown in FIG. Figure 12 As shown;

[0048] 7. Thin the substrate and form drain metal 1 on the back, such as Figure 13 shown.

[0049] Example 2

[0050] like Figure 6 As shown, this embodiment provides a power MOSFET device with improved output capacitance, including a drain metal 1, a heavily doped first conductivity type semiconductor substrate 2, a lightly doped second conductivity type semiconductor epitaxial layer 3, a lightly doped first conductivity type semiconductor buried layer 4, a heavily doped first conductivity type semiconductor vertical sinker 5, a gate dielectric layer 6, a gate polysilicon electrode 7, a second conductivity type semiconductor body region 8, a first conductivity type semiconductor drift region 9, a heavily doped first conductivity type semiconductor source region 10, a heavily doped second conductivity type semiconductor ohmic contact region 12, an insulating dielectric layer 11, a source metal 13, and a second conductivity type semiconductor buried layer 14;

[0051] The heavily doped first conductive type semiconductor substrate 2 is located above the drain metal 1, the lightly doped second conductive type semiconductor epitaxial layer 3 is located above the heavily doped first conductive type semiconductor substrate 2, the second conductive type semiconductor body region 8 is located in the upper left of the lightly doped second conductive type semiconductor epitaxial layer 3, the heavily doped first conductive type semiconductor vertical sinker 5 is located in the right of the lightly doped second conductive type semiconductor epitaxial layer 3, the lightly doped first conductive type semiconductor buried layer 4 is located below the second conductive type semiconductor body region 8 in the lightly doped second conductive type semiconductor epitaxial layer 3, a second conductive type semiconductor buried layer 14 is provided between the lightly doped first conductive type semiconductor buried layer 4 and the second conductive type semiconductor body region 8, the width of the second conductive type semiconductor body region 8 is less than or equal to the width of the second conductive type semiconductor buried layer 14, and the width of the second conductive type semiconductor buried layer 14 is less than or equal to the width of the lightly doped first conductive type semiconductor buried layer 4;

[0052] The first conductive type semiconductor drift region 9 is located in the upper part of the lightly doped second conductive type semiconductor epitaxial layer 3, and its two sides are in direct contact with the heavily doped first conductive type semiconductor vertical sinker 5 and the second conductive type semiconductor body region 8; the heavily doped first conductive type semiconductor vertical sinker 5 extends into the lightly doped second conductive type semiconductor epitaxial layer 3 to the heavily doped first conductive type semiconductor substrate 2, connecting the first conductive type semiconductor drift region 9 and the heavily doped first conductive type semiconductor substrate 2; the second conductive type semiconductor body region 8 has a heavily doped first conductive type semiconductor source region 10 and a heavily doped second conductive type semiconductor ohmic contact region 12 in the upper left corner; the heavily doped The left side of the first conductive type semiconductor source region 10 is in contact with the source metal 13, and the heavily doped second conductive type semiconductor ohmic contact region 12 is in contact with the source metal 13 above; the upper surface of the second conductive type semiconductor epitaxial layer 3 is covered with an insulating dielectric layer 11, and the insulating dielectric layer 11 surrounds the gate polysilicon electrode 7; the gate polysilicon electrode 7 is isolated from the second conductive type semiconductor body region 8 by the gate dielectric layer 6; the source metal 13 is located on the upper surface of the insulating dielectric layer 11 and completely covers the area where the first conductive type semiconductor drift region 9 is located; the source metal 13 extends into the semiconductor material through the contact hole, and its depth is deeper than the heavily doped first conductive type semiconductor source region 10.

[0053] The doping concentration of the heavily doped -3 The doping concentration of the first conductive type semiconductor drift region 9 is in the range of 1e17 cm -3 -3e17 cm -3 The doping concentration range of the lightly doped first conductivity type semiconductor buried layer 4 is 2e16 cm -3 -5e16cm -3 The doping concentration of the lightly doped second conductivity type semiconductor epitaxial layer 3 is less than 1e17 cm -3 .

[0054] The advantage of this embodiment is that, under the action of the lightly doped first-conductivity-type semiconductor buried layer 4, the depletion region will expand into the second-conductivity-type semiconductor body region 8. If the depletion region expands too much, the effective channel length of the device will be reduced. When the drain-source voltage is large, punch-through will occur between the source and the drain, resulting in soft breakdown. Because the second-conductivity-type semiconductor buried layer 14 and the lightly doped first-conductivity-type semiconductor buried layer 4 have different doping types, the expansion of the depletion region can be controlled by changing the doping concentration of the buried layer 14, effectively preventing the excessive expansion of the depletion region caused by the lightly doped first-conductivity-type semiconductor buried layer 4, thereby suppressing the soft breakdown phenomenon.

[0055] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A power MOSFET device with improved output capacitance, characterized in that: The invention comprises a drain metal (1), a heavily doped first conductive type semiconductor substrate (2), a lightly doped second conductive type semiconductor epitaxial layer (3), a lightly doped first conductive type semiconductor buried layer (4), a heavily doped first conductive type semiconductor vertical sinker (5), a gate dielectric layer (6), a gate polysilicon electrode (7), a second conductive type semiconductor body region (8), a first conductive type semiconductor drift region (9), a heavily doped first conductive type semiconductor source region (10), a heavily doped second conductive type semiconductor ohmic contact region (12), an insulating dielectric layer (11), and a source metal (13); The heavily doped first conductive type semiconductor substrate (2) is located above the drain metal (1), the lightly doped second conductive type semiconductor epitaxial layer (3) is located above the heavily doped first conductive type semiconductor substrate (2), the second conductive type semiconductor body region (8) is located in the upper left of the lightly doped second conductive type semiconductor epitaxial layer (3), the heavily doped first conductive type semiconductor vertical sinker (5) is located in the right of the lightly doped second conductive type semiconductor epitaxial layer (3), the lightly doped first conductive type semiconductor buried layer (4) is located in the lightly doped second conductive type semiconductor epitaxial layer The first conductive type semiconductor drift region (9) is located directly below the second conductive type semiconductor body region (8) in the lightly doped second conductive type semiconductor epitaxial layer (3) and is in direct contact with the second conductive type semiconductor body region (8), and its width is greater than the second conductive type semiconductor body region (8); the first conductive type semiconductor drift region (9) is located in the upper part of the lightly doped second conductive type semiconductor epitaxial layer (3), and its two sides are in direct contact with the heavily doped first conductive type semiconductor vertical sinker (5) and the second conductive type semiconductor body region (8); the heavily doped first conductive type semiconductor vertical sinker (5) extends into the lightly doped second conductive type semiconductor epitaxial layer (3) to A heavily doped first conductive type semiconductor substrate (2) is provided, connecting a first conductive type semiconductor drift region (9) and the heavily doped first conductive type semiconductor substrate (2); a heavily doped first conductive type semiconductor source region (10) and a heavily doped second conductive type semiconductor ohmic contact region (12) are provided at the upper left of the second conductive type semiconductor body region (8); the left side of the heavily doped first conductive type semiconductor source region (10) is in contact with a source metal (13), and the upper side of the heavily doped second conductive type semiconductor ohmic contact region (12) is in contact with the source metal (13) The upper surface of the second conductive type semiconductor epitaxial layer (3) is covered with an insulating dielectric layer (11), and the insulating dielectric layer (11) surrounds the gate polysilicon electrode (7); the gate polysilicon electrode (7) is isolated from the second conductive type semiconductor body region (8) by the gate dielectric layer (6); the source metal (13) is located on the upper surface of the insulating dielectric layer (11) and completely covers the area where the first conductive type semiconductor drift region (9) is located; the source metal (13) extends into the semiconductor material through a contact hole, and its depth is deeper than the heavily doped first conductive type semiconductor source region (10).

2. A power MOSFET device with improved output capacitance, characterized in that: The invention comprises a drain metal (1), a heavily doped first conductive type semiconductor substrate (2), a lightly doped second conductive type semiconductor epitaxial layer (3), a lightly doped first conductive type semiconductor buried layer (4), a heavily doped first conductive type semiconductor vertical sinker (5), a gate dielectric layer (6), a gate polysilicon electrode (7), a second conductive type semiconductor body region (8), a first conductive type semiconductor drift region (9), a heavily doped first conductive type semiconductor source region (10), a heavily doped second conductive type semiconductor ohmic contact region (12), an insulating dielectric layer (11), a source metal (13), and a second conductive type semiconductor buried layer (14); The heavily doped first conductive type semiconductor substrate (2) is located above the drain metal (1), the lightly doped second conductive type semiconductor epitaxial layer (3) is located above the heavily doped first conductive type semiconductor substrate (2), the second conductive type semiconductor body region (8) is located in the upper left of the lightly doped second conductive type semiconductor epitaxial layer (3), the heavily doped first conductive type semiconductor vertical sinker (5) is located in the right of the lightly doped second conductive type semiconductor epitaxial layer (3), the lightly doped first conductive type semiconductor buried layer (4) is located below the second conductive type semiconductor body region (8) in the lightly doped second conductive type semiconductor epitaxial layer (3), a second conductive type semiconductor buried layer (14) is provided between the lightly doped first conductive type semiconductor buried layer (4) and the second conductive type semiconductor body region (8), the width of the second conductive type semiconductor body region (8) is less than or equal to the width of the second conductive type semiconductor buried layer (14), and the width of the second conductive type semiconductor buried layer (14) is less than or equal to the width of the lightly doped first conductive type semiconductor buried layer (4); The first conductive type semiconductor drift region (9) is located at the upper part of the lightly doped second conductive type semiconductor epitaxial layer (3), and its two sides are in direct contact with the heavily doped first conductive type semiconductor vertical sinker (5) and the second conductive type semiconductor body region (8); the heavily doped first conductive type semiconductor vertical sinker (5) extends into the lightly doped second conductive type semiconductor epitaxial layer (3) to the heavily doped first conductive type semiconductor substrate (2), connecting the first conductive type semiconductor drift region (9) and the heavily doped first conductive type semiconductor substrate (2); the second conductive type semiconductor body region (8) has a heavily doped first conductive type semiconductor source region (10) and a heavily doped second conductive type semiconductor ohmic contact region (12) in the upper left corner; ... heavily doped first conductive type semiconductor source region (10) and the heavily doped second conductive type semiconductor ohmic contact region (12) in the upper left corner; the heavily doped first conductive type semiconductor vertical sinker (5) extends into the lightly doped second conductive type semiconductor epitaxial layer (3) to the heavily doped first conductive type semiconductor substrate (2), connecting the first conductive type semiconductor drift region (9) and the heavily doped first conductive type semiconductor substrate (2); the heavily doped first conductive type semiconductor source region (10) and the heavily doped second conductive type semiconductor ohmic contact region (12) The left side of the second conductive type semiconductor source region (10) is in contact with the source metal (13), and the upper portion of the heavily doped second conductive type semiconductor ohmic contact region (12) is in contact with the source metal (13); the upper surface of the second conductive type semiconductor epitaxial layer (3) is covered with an insulating dielectric layer (11), and the insulating dielectric layer (11) surrounds the gate polysilicon electrode (7); the gate polysilicon electrode (7) and the second conductive type semiconductor body region (8) are isolated by the gate dielectric layer (6); the source metal (13) is located on the upper surface of the insulating dielectric layer (11) and completely covers the area where the first conductive type semiconductor drift region (9) is located; the source metal (13) extends into the semiconductor material through a contact hole, and its depth is deeper than that of the heavily doped first conductive type semiconductor source region (10).

3. A power MOSFET device with improved output capacitance according to claim 1 or 2, characterized in that: Heavily doped with a doping concentration greater than 1e19 cm -3 The doping concentration of the first conductive type semiconductor drift region (9) is in the range of 1e17 cm -3 -3e17 cm -3 The doping concentration of the lightly doped first conductive type semiconductor buried layer (4) is in the range of 2e16 cm -3 -5e16 cm -3 The doping concentration of the lightly doped second conductivity type semiconductor epitaxial layer (3) is less than 1e17 cm -3 .

4. A power MOSFET device with improved output capacitance according to claim 1 or 2, characterized in that: The first conductive type semiconductor is an N-type semiconductor, and the second conductive type semiconductor is a P-type semiconductor; or the first conductive type semiconductor is a P-type semiconductor, and the second conductive type semiconductor is an N-type semiconductor.

5. A power MOSFET device with improved output capacitance according to claim 1 or 2, characterized in that: The semiconductor material is silicon or silicon carbide.

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