Gain and Noise Programmable Comparator Based on Floating Amplifier and Control Method

Abstract

The present invention belongs to the technical field of integrated circuits, and particularly relates to a gain and noise programmable comparator based on a floating amplifier and a control method. Among them, a gain and noise programmable comparator based on a floating amplifier includes a pre-preamplifier and a latch; the pre-preamplifier adopts a preamplifier based on a floating power supply; the latch adopts an SA dynamic latch, and the SA dynamic latch has a latch structure with positive feedback latch. Through two circuit modules, namely, a preamplifier based on a floating power supply and an SA dynamic latch, the comparator of the present invention can operate in multiple modes, and different power consumption and low-noise performance of the comparator can be realized respectively in different operating modes.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a comparator and a control method thereof. Background Art

[0002] As one of the important modules in all analog-to-digital converters (ADCs), for realizing high-speed, high-precision, and low-power ADCs, the selection of the comparator structure is crucial. In fact, a comparator is a one-bit ADC. According to the power consumption performance of the comparator, the comparator can be divided into a static comparator and a dynamic comparator. The dynamic comparator has no static current, while the static comparator has a static current. Therefore, compared with the static comparator, the dynamic comparator has lower power consumption. In addition, the dynamic comparator has a faster comparison speed. Therefore, in the design of high-performance and low-power ADCs, designers prefer to use dynamic comparators.

[0003] A dynamic comparator is usually composed of a preamplifier and a latch. Amplification and positive feedback are the basic working principles of the dynamic comparator. First, the preamplifier amplifies the input signal. Since the input signals are different and there is a voltage difference, the leakage currents of the preamplifier are different, and the discharge speeds of the output nodes of the preamplifier are also different, triggering the latch to conduct, and the comparator enters the positive feedback stage. Through positive feedback, the potentials of the two output nodes are respectively pulled to the power supply potential and the ground potential. As an important part of the analog-to-digital converter (ADC), the optimization of the structure and performance of the comparator is very important and has high research significance in high-precision and low-power ADCs.

[0004] However, the offset and input noise of the existing dynamic comparators are relatively large, seriously restricting the performance of the ADC. Summary of the Invention

[0005] Aiming at the technical problem that the input noise of the existing dynamic comparators is relatively large, seriously restricting the performance of the ADC, the present invention aims to provide a gain and noise programmable comparator based on a floating amplifier and a control method thereof.

[0006] A gain and noise programmable comparator based on a floating amplifier includes a preamplifier and a latch;

[0007] The preamplifier adopts a preamplifier based on a floating power supply. The input side of the preamplifier is respectively connected to two voltage input terminals, a common-mode voltage input terminal, a pair of two-phase non-overlapping clock signals, and a pair of two-phase non-overlapping programming control signals. The output side of the preamplifier has a pair of preamplifier output signals;

[0008] The latch adopts an SA dynamic latch, the SA dynamic latch has a latch structure with positive feedback latch, the input end side of the SA dynamic latch is respectively connected to a pair of the preamplifier output signals, and the output end side of the SA dynamic latch has a pair of latch output signals as the output signals of the comparator;

[0009] A pair of the clock signals are respectively a clock signal CLK and a clock signal CLKB, the clock signal CLK and the clock signal CLKB are a pair of mutually inverted clock signals, and the clock signal CLKB is also connected to the input end side of the SA dynamic latch.

[0010] As a preferred solution, the preamplifier includes transistors M1, M2, M3, M4, M5 and M6, capacitors C X1 , C X2 and C RES0 , CMOS transmission gates I1 and I2, switches S1 and S2. Among them, M5, M6, C RES0 , I1 and I2 form a group of working mode components;

[0011] The source electrode of M1 is connected to the source electrode of M2 and is connected to the output end of I1. The drain electrode of M1 is connected to the drain electrode of M3. The drain electrode of M2 is connected to the drain electrode of M4. The common terminal between the drain electrode of M1 and the drain electrode of M3 and the common terminal between the drain electrode of M2 and the drain electrode of M4 are respectively used as a pair of the preamplifier output signals and are respectively connected to the upper plates of C X1 , C X2 . The upper plates of C X1 , C X2 are respectively connected to the common mode voltage input terminal through S1 and S2. The lower plates of C X1 , C X2 are respectively connected to the ground potential. The source electrode of M3 is connected to the source electrode of M4 and is connected to the output end of I2. The gate electrode of M1 is connected to the gate electrode of M3 and is connected to one of the voltage input terminals. The gate electrode of M2 is connected to the gate electrode of M4 and is connected to the other voltage input terminal;

[0012] The drain electrode of M5 is respectively connected to the input end of I1 and the upper plate of C RES0 . The drain electrode of M6 is respectively connected to the input end of I2 and the lower plate of C RES0 . The source electrode of M5 is connected to the power supply potential. The source electrode of M6 is connected to the ground potential. The gate electrode of M5 is connected to the clock signal CLK. The gate electrode of M6 is connected to the clock signal CLKB. The positive control terminal and the negative control terminal of I1 and I2 are controlled by at least one of a pair of clock signals and a pair of the programming control signals;

[0013] The number of groups of the working mode components is the same as the number of working modes of the comparator. When there are at least two groups of the working mode components, the adjacent other group of the working mode components includes corresponding M7, M8, C RES1 , I3 and I4, and the drain of M5 is further connected to the output terminal of I3, and the drain of M6 is further connected to the output terminal of I4. The adjacent two groups of the working mode components are connected in sequence in this way to form multiple groups of working mode components connected in sequence.

[0014] As a preferred solution, the working mode of the comparator is three, the number of groups of the working mode components is three, and the adjacent other group of the working mode components includes corresponding M9, M10, C RES2 , I5 and I6;

[0015] The positive control terminals of I1 and I2 are connected to the clock signal CLK, and the negative control terminals of I1 and I2 are connected to the clock signal CLKB;

[0016] The preamplifier further includes AND gates A1, A2, A3 and A4. Defining the programming control signals as V1 and V2, then the clock signal CLK and V1 are respectively connected to the negative control terminals of I3 and I4 after passing through A1, and the clock signal CLKB and V1 are respectively connected to the positive control terminals of I3 and I4 after passing through A2. The clock signal CLK and V2 are respectively connected to the negative control terminals of I5 and I6 after passing through A3, and the clock signal CLKB and V2 are respectively connected to the positive control terminals of I5 and I6 after passing through A4.

[0017] As a preferred solution, the CMOS transmission gate includes transistors M22 and M23;

[0018] The drain of M22 is connected to the drain of M23 and serves as the input terminal of the CMOS transmission gate. The source of M22 is connected to the source of M23 and serves as the output terminal of the CMOS transmission gate. The gate of M22 serves as the positive control terminal of the CMOS transmission gate, and the gate of M23 serves as the negative control terminal of the CMOS transmission gate.

[0019] As a preferred solution, the SA dynamic latch includes transistors M11, M12, M13, M14, M15, M16, M17, M18, M19, M20 and M21;

[0020] The gates of M11 and M12 are respectively connected to a pair of the pre - amplifier output signals. The sources of M11 and M12 are connected to each other and then connected to the drain of M21. The source of M21 is connected to the power supply potential. The drain of M11 is respectively connected to the source of M13 and the drain of M15. The drain of M12 is respectively connected to the source of M14 and the drain of M16. The gates of M13, M17, the drain of M14 and the drain of M18 are connected to each other and serve as the output signal of one of the comparators. The gates of M14, M18, the drain of M13 and the drain of M17 are connected to each other and serve as the output signal of the other comparator, thus forming a latch structure with positive - feedback latch.

[0021] The sources of M15, M16, M17, M18, M19 and M20 are all connected to the ground potential. The gates of M15, M16, M19, M20 and M21 are respectively connected to the clock signal CLKB and are controlled to conduct or turn off by the clock signal CLKB. When the clock signal CLKB is at a low level, the SA dynamic latch performs normal comparison work. Due to the latch structure with positive - feedback latch, the output signals of the comparators are respectively pulled to the power supply and the ground potential, and the comparison results are stored by the SA dynamic latch.

[0022] A control method for a gain - and - noise programmable comparator based on a floating amplifier, comprising:

[0023] Controlling both V1 and V2 to be at a low level, then the comparator operates in a first operating mode, and the first operating mode serves as the normal operating mode;

[0024] Controlling V1 to be at a high level and V2 to be at a low level, then the comparator operates in a second operating mode. The second operating mode has higher power consumption and lower noise than the first operating mode, so the second operating mode serves as a medium - power - consumption low - noise mode;

[0025] Controlling both V1 and V2 to be at a high level, then the comparator operates in a third operating mode. The third operating mode has higher power consumption and lower noise than the second operating mode, so the third operating mode serves as a high - power - consumption ultra - low - noise mode;

[0026] Controlling the clock signal CLK to be at a low level and the clock signal CLKB to be at a high level, then the comparator operates in a reset state;

[0027] Controlling the clock signal CLK to be at a high level and the clock signal CLKB to be at a low level, then the comparator operates in a comparison state.

[0028] The positive and progressive effects of the present invention are as follows: The present invention adopts a gain and noise programmable comparator and control method based on a floating amplifier. Through two circuit modules, namely a pre-amplifier based on a floating power supply and an SA dynamic latch, the comparator can operate in multiple modes. In different operating modes, different power consumption and low-noise performance of the comparator can be achieved respectively, and various performance indicators of the comparator such as resolution, equivalent input noise, and linearity are comprehensively considered, realizing a comparator with programmable gain and noise. According to different application requirements, the operating mode of the comparator can be flexibly adjusted. The present invention has broad application prospects in low-noise analog-to-digital converters. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is an overall block diagram of the present invention;

[0030] Figure 2 is a system block diagram of the present invention;

[0031] Figure 3 is a circuit diagram of a pre-amplifier based on a floating power supply of the present invention;

[0032] Figure 4 is a circuit diagram of an SA dynamic latch of the present invention;

[0033] Figure 5 is a circuit diagram of a CMOS transmission gate of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] In order to make the technical means, creative features, achieved purposes and effects of the present invention easy to understand, the present invention will be further described below with reference to specific drawings.

[0035] Refer to Figure 1 , a gain and noise programmable comparator based on a floating amplifier. The comparator 1 (Comparator) includes two voltage input terminals 2 (V I+ , V I- ), a common-mode voltage input terminal 3 (V cm ), a pair of two-phase non-overlapping clock signals 4 (CLK, CLKB), a pair of two-phase non-overlapping programming control signals 5 (V1, V2) and a pair of output signals 6 (D O+ , D O- ).

[0036] Refer to Figure 2 , the comparator 1 includes a first-stage pre-amplifier 7 (Pre_Amp) based on a floating power supply and a second-stage SA dynamic latch 8 (SA-Latch). The SA dynamic latch 8 has a latch structure with positive feedback latch.

[0037] On the input side of the preamplifier 7, two voltage inputs 2, a common-mode voltage input 3, a pair of two-phase non-overlapping clock signals 4, and a pair of two-phase non-overlapping programming control signals 5 are respectively connected. On the output side of the preamplifier 7, there is a pair of preamplifier output signals 9 (V X+ , V X- ) which are connected to the input of the SA dynamic latch 8 of the second stage. Moreover, the inverted clock signal CLKB of the clock signal CLK is also connected to the input side of the SA dynamic latch 8. On the output side of the SA dynamic latch 8, there is a pair of latch output signals which serve as a pair of output signals 6 of the comparator 1.

[0038] In the present invention, through two circuit modules, namely the preamplifier 7 and the SA dynamic latch 8 based on a floating power supply, the comparator can operate in multiple modes. The clock signals CLK and CLKB control two operating states of the comparator 1, namely the reset state or the comparison state, and a pair of programming control signals V1 and V2 control the operating mode of the comparator 1 to be in normal operating mode, medium power consumption and low noise mode, or high power consumption and ultra-low noise mode, etc., enabling the comparator to achieve different power consumption and noise performances in different operating modes. And various performance indicators of the comparator such as resolution, equivalent input noise, and linearity are comprehensively considered, realizing a comparator with programmable gain and noise, which can flexibly adjust the operating mode of the comparator according to different application requirements.

[0039] In some embodiments, referring to Figure 3 , the preamplifier 7 includes transistors M1, M2, M3, M4, M5, and M6, capacitors C X1 , C X2 , and C RES0 , CMOS transmission gates I1 and I2, switches S1 and S2. Among them, M5, M6, C RES0 , I1, and I2 form a group of operating mode components.

[0040] The source of M1 is connected to the source of M2 and is connected to the output terminal (OUT) of I1. The drain of M1 is connected to the drain of M3, the drain of M2 is connected to the drain of M4. The common terminal between the drain of M1 and the drain of M3 serves as V X- of the preamplifier output signal 9. The common terminal between the drain of M1 and the drain of M3 is connected to the upper plate of C X1 . The common terminal between the drain of M2 and the drain of M4 serves as V X+ of the preamplifier output signal 9. The common terminal between the drain of M2 and the drain of M4 is connected to the upper plate of C X2 . The upper plate of C X1 is connected to V cm through S1. The upper plate of C X2 is connected to Vcm is connected to C X1 The lower plate of is connected to the ground potential, C X2 The lower plate of is connected to the ground potential. The source of M3 is connected to the source of M4 and connected to the output terminal (OUT) of I2. The gate of M1 is connected to the gate of M3 and to the V of voltage input terminal 2 I+ is connected, the gate of M2 is connected to the gate of M4 and to the V of voltage input terminal 2 I- is connected.

[0041] The connection method of a single working mode component is as follows: The drain of M5 is respectively connected to the input terminal (IN) of I1 and the upper plate of C RES0 The upper plate of is connected. The drain of M6 is respectively connected to the input terminal (IN) of I2 and the lower plate of C RES0 The lower plate of is connected. The source of M5 is connected to the power supply potential, the source of M6 is connected to the ground potential, the gate of M5 is connected to the clock signal CLK, the gate of M6 is connected to the clock signal CLKB, and the positive control terminal and negative control terminal of I1 and I2 are respectively controlled by at least one of a pair of clock signals 4 and a pair of programming control signals 5. As Figure 3 shown, the positive control terminal (VN) of I1 is connected to the clock signal CLK, the negative control terminal (VP) of I1 is connected to the clock signal CLKB, the positive control terminal (VN) of I2 is connected to the clock signal CLK, and the negative control terminal (VP) of I2 is connected to the clock signal CLKB.

[0042] The number of groups of working mode components is the same as the number of working modes of comparator 1. When there are at least two groups of working mode components, the connection methods of the respective components in each group of working mode components are the same. For example, an adjacent group of working mode components includes corresponding M7, M8, C RES1 , I3 and I4, then the drain of M7 is respectively connected to the input terminal (IN) of I3 and the upper plate of C RES1 The upper plate of is connected. The drain of M8 is respectively connected to the input terminal (IN) of I4 and the lower plate of C RES1 The lower plate of is connected. The source of M7 is connected to the power supply potential, the source of M8 is connected to the ground potential, the gate of M7 is connected to the clock signal CLK, the gate of M8 is connected to the clock signal CLKB, and the positive control terminal and negative control terminal of I3 and I4 are respectively controlled by at least one of a pair of clock signals 4 and a pair of programming control signals 5. As Figure 3 shown, the positive control terminal and negative control terminal of I3 and I4 are jointly controlled via the clock signal CLK, the clock signal CLKB, V1, AND gates A1 and A2. That is, the clock signal CLK and V1 are respectively connected to the negative control terminal (VP) of I3 and the negative control terminal (VP) of I4 after passing through A1, and the clock signal CLKB and V1 are respectively connected to the positive control terminal (VN) of I3 and the positive control terminal (VN) of I4 after passing through A2.

[0043] The connection relationship between two adjacent groups of working mode components is established as follows: The drain of M5 is also connected to the output terminal (OUT) of I3, and the drain of M6 is also connected to the output terminal (OUT) of I4.

[0044] Through the design of multiple groups of working mode components, the present invention realizes the design of multiple working modes. For example, if two working modes are designed, only two groups of the above-connected working mode components need to be established. When designing three or more working modes, multiple groups of the above-connected working mode components can be established by analogy.

[0045] In some embodiments, referring to Figure 3 , the working mode of comparator 1 of the present invention is preferably three, so the number of groups of working mode components is designed as three, and the adjacent other group of working mode components includes corresponding M9, M10, C RES2 , I5 and I6. The preamplifier 7 further includes AND gates A1, A2, A3 and A4.

[0046] The control connection manner of a pair of clock signals 4 and a pair of programming control signals 5 to three groups of working mode components is as follows:

[0047] The positive control terminal (VN) of I1 is connected to the clock signal CLK, the positive control terminal (VN) of I2 is connected to the clock signal CLK, the negative control terminal (VP) of I1 is connected to the clock signal CLKB, and the negative control terminal (VP) of I2 is connected to the clock signal CLKB.

[0048] After passing through A1, the clock signal CLK and V1 are respectively connected to the negative control terminal (VP) of I3 and the negative control terminal (VP) of I4. After passing through A2, the clock signal CLKB and V1 are respectively connected to the positive control terminal (VN) of I3 and the positive control terminal (VN) of I4.

[0049] After passing through A3, the clock signal CLK and V2 are respectively connected to the negative control terminal (VP) of I5 and the negative control terminal (VP) of I6. After passing through A4, the clock signal CLKB and V2 are respectively connected to the positive control terminal (VN) of I5 and the positive control terminal (VN) of I6.

[0050] In some embodiments, referring to Figure 5 , the CMOS transmission gate TG of the present invention adopts the following design structure:

[0051] The CMOS transmission gate includes transistors M22 and M23. The drain of M22 is connected to the drain of M23 and serves as the input terminal (IN) of the CMOS transmission gate. The source of M22 is connected to the source of M23 and serves as the output terminal (OUT) of the CMOS transmission gate. The gate of M22 serves as the positive control terminal (VN) of the CMOS transmission gate, and the gate of M23 serves as the negative control terminal (VP) of the CMOS transmission gate.

[0052] In some embodiments, referring to Figure 3 , transistors M1, M2, M5, M7, M9, and M22 are preferably N-channel insulated gate bipolar transistors, and transistors M3, M4, M6, M8, M10, and M23 are preferably P-channel insulated gate bipolar transistors. If the above transistors are designed conversely, only minor adjustments to the entire circuit are required.

[0053] In some embodiments, referring to Figure 4 , the SA dynamic latch 8 includes transistors M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, and M21.

[0054] The gate of M11 is connected to the V X+ of the preamplifier output signal 9, the gate of M12 is connected to the V X- of the preamplifier output signal 9. The source of M11 is connected to the source of M12 and is connected to the drain of M21. The source of M21 is connected to the power supply potential. The drain of M11 is respectively connected to the source of M13 and the drain of M15. The drain of M12 is respectively connected to the source of M14 and the drain of M16. The gates of M13, M17, the drain of M14, and the drain of M18 are connected together and serve as the output signal D O+ of the comparator 1, and the gates of M14, M18, the drain of M13, and the drain of M17 are connected together and serve as the output signal D O- of the comparator 1, thus forming a latch structure with positive feedback latch.

[0055] The sources of M15, M16, M17, M18, M19, and M20 are all connected to the ground potential. The gates of M15, M16, M19, M20, and M21 are respectively connected to the clock signal CLKB. The conduction or cutoff of M15, M16, M19, M20, and M21 is controlled by the clock signal CLKB. When the clock signal CLKB is at a low level, the SA dynamic latch 8 performs normal comparison operations. Due to the latch structure with positive feedback latch, the output signals of the comparator 1 are respectively pulled to the power supply and the ground potential, and the comparison results are stored by the SA dynamic latch 8.

[0056] In some embodiments, referring to Figure 4, the transistors M11, M12, M13, M14, and M21 are preferably N-channel insulated-gate bipolar transistors, and the transistors M15, M16, M17, M18, M19, and M20 are preferably P-channel insulated-gate bipolar transistors. If the above transistors are designed conversely, only minor adjustments to the entire circuit are required.

[0057] In some embodiments, referring to Figures 1 to 4 , the present invention also provides a control method for a gain and noise programmable comparator 1 based on a floating amplifier, including:

[0058] Controlling both V1 and V2 to be low levels, then the comparator 1 operates in the first operating mode, and the first operating mode serves as the normal operating mode; controlling V1 to be high level and V2 to be low level, then the comparator 1 operates in the second operating mode, and the second operating mode has higher power consumption and lower noise than the first operating mode, so that the second operating mode serves as the medium power consumption and low noise mode; controlling both V1 and V2 to be high levels, then the comparator 1 operates in the third operating mode, and the third operating mode has higher power consumption and lower noise than the second operating mode, so that the third operating mode serves as the high power consumption and ultra-low noise mode.

[0059] Controlling the clock signal CLK to be low level and the clock signal CLKB to be high level, then the comparator 1 operates in the reset state; controlling the clock signal CLK to be high level and the clock signal CLKB to be low level, then the comparator 1 operates in the comparison state.

[0060] Under the action of a pair of two-phase non-overlapping clock signals 4 (CLK, CLKB) and a pair of two-phase non-overlapping programming control signals 5 (V1, V2), the comparator 1 of the present invention has three operating modes, namely the normal operating mode, the medium power consumption and low noise mode, and the high power consumption and ultra-low noise mode, and the comparator 1 has two states, namely the reset state and the comparison state.

[0061] The working principle of the comparator 1 of the present invention to achieve multiple operating modes is as follows:

[0062] 1) The first operating mode: When the programming control signals V1 and V2 are both low levels, the CMOS transmission gates I3, I4, I5, and I6 are all turned off. At this time, only the capacitor C RES0 serves as a floating power supply to supply power to the pre-amplifier 7 of the first stage.

[0063] When the clock signal CLK is low level and the clock signal CLKB is high level, the comparator 1 operates in the reset state, and vice versa in the normal comparison state.

[0064] (11) In the reset state, the transistors M5 and M6 are turned on, and the capacitor C RES0is pre-charged to the power supply potential, CMOS transmission gates I1 and I2 are turned off, and switches S1 and S2 are turned on, resulting in the output terminals V X+ and V X- of the pre-amplifier 7 in the first stage being reset to the common-mode level V cm , and the circuit in the first stage does not work at this time. Also, since M19 and M20 are turned on, the output signals (D O+ , D O- ) are at the ground potential, causing M17 and M18 to be cut off. At the same time, M15 and M16 are turned on, and the drain voltages of M15 and M16 are pulled to the ground potential.

[0065] (12) In the normal comparison state, transistors M5 and M6 are cut off, CMOS transmission gates I1 and I2 are turned on, and capacitor C RES0 starts to discharge. The switches S1 and S2 in the pre-amplifier 7 in the first stage are closed. Under the action of the input signals V I+ , V I- ) corresponding to the voltage input terminals (V i+ and V i- ), M1, M2, M3, and M4 are turned on. And due to the voltage difference between the voltage input terminals (V I+ , V I- ), the leakage currents on both sides are different, resulting in different falling speeds of the pre-amplifier output signals 9 (V X+ , V X- ) of the pre-amplifier 7 in the first stage. Taking the falling speed of the V X- potential being greater than the falling speed of the V X+ potential (i.e., V I+ >V I- ) as an example for explanation. In the SA dynamic latch 8 in the second stage, the gate potential of M12 (i.e., the V X- potential) drops quickly. Therefore, M12 reaches the conduction condition earlier than M11. The source potential of M14 rises first, and the source potential of M13 rises later, causing M14 to conduct earlier than M13. Once D O+ rises to the potential that causes M17 to conduct, due to positive feedback latching, D O+ is pulled to the ground potential, and D O- is pulled to the power supply potential. Therefore, the comparator output signal 6 (D O+ , D O- ) outputs the correct comparison result.

[0066] In summary, when V I+ >V I- , the comparator 1 outputs D O- >D O+ , and the comparison result is correct. Conversely, when V I- >V I+ , the working analysis process of the comparator 1 is the same as the above by the same token.

[0067] (13) Since the programming control signals V1 and V2 are both at low level at this time, the CMOS transmission gates I3, I4, I5 and I6 are all turned off, and only the capacitor C RES0 acts as a floating power supply to supply power to the preamplifier 7 of the first stage. The overall dynamic operating current of the circuit is the minimum current among the three operating modes, so the dynamic power consumption is the lowest. At the same time, since the value of the equivalent input noise is inversely proportional to the value of the capacitor C RES and the higher its value, the smaller the noise. Also, because the value of C RES is equal to the value of C RES0 , the noise in the first operating mode is at a normal level. Therefore, the first operating mode is considered the normal operating mode.

[0068] 2) Second operating mode: When the programming control signal V1 is at high level and V2 is at low level, the CMOS transmission gates I5 and I6 are both turned off. At this time, the capacitors C RES0 and C RES1 act as a floating power supply to supply power to the preamplifier 7 of the first stage.

[0069] When the clock signal CLK is at low level and the clock signal CLKB is at high level, the comparator 1 operates in the reset state, and vice versa in the normal comparison state.

[0070] (21) In the reset state, the transistors M5, M6, M7 and M8 are turned on, the capacitors C RES0 and C RES1 are pre-charged to the power supply potential, the CMOS transmission gates I1, I2, I3 and I4 are turned off, the switches S1 and S2 are turned on, resulting in the output terminals V X+ and V X- of the preamplifier 7 of the first stage being reset to the common-mode level V cm . At this time, the circuit of the first stage does not work. Also, since M19 and M20 are turned on, the output signals (D O+ , D O- ) are at ground potential, causing M17 and M18 to be cut off. At the same time, M15 and M16 are turned on, and the drain voltages of M15 and M16 are pulled to ground potential.

[0071] (22) In the normal comparison state, the working analysis process of the comparator 1 is the same as that in (12) of the first operating mode.

[0072] (23) Since the programming control signal V1 is at high level and V2 is at low level at this time, the transmission gates I5 and I6 are both turned off, and the capacitors C RES0 and C RES1 act as a floating power supply to supply power to the preamplifier 7 of the first stage. At the same time, since the value of the equivalent input noise is inversely proportional to the value of the capacitor C RESis inversely proportional to the value. The higher the value, the smaller the noise. Also, since the value of C at this time RES is equal to C RES0 plus C RES1 , comparator 1 operates in a low-power mode at this time. Therefore, the second operating mode is considered a medium-power low-noise mode.

[0073] 3) Third operating mode: When both the programming control signals V1 and V2 are high, capacitor C RES0 , C RES1 and C RES2 serve as a floating power supply to power the preamplifier 7 of the first stage.

[0074] When the clock signal CLK is low and the clock signal CLKB is high, comparator 1 operates in a reset state; otherwise, it is in a normal comparison state.

[0075] (31) In the reset state, transistors M5, M6, M7, M8, M9, and M10 are conducting, capacitors C RES0 , C RES1 and C RES2 are pre-charged to the power supply potential, CMOS transmission gates I1, I2, I3, I4, I5, and I6 are turned off, switches S1 and S2 are conducting, causing the output terminals V X+ and V X- of the preamplifier 7 of the first stage to be reset to the common-mode level V cm . At this time, the circuit of the first stage does not work. Also, since M19 and M20 are conducting, the output signals (D O+ , D O- ) are at ground potential, causing M17 and M18 to be cut off, and at the same time M15 and M16 are conducting, and the drain voltages of M15 and M16 are pulled to ground potential.

[0076] (32) In the normal comparison state, the working analysis process of comparator 1 is the same as in (12) of the first operating mode.

[0077] (33) Since the programming control signals V1 and V2 are both high at this time, capacitors C RES0 , C RES1 and C RES2 serve as a floating power supply to power the preamplifier 7 of the first stage. At the same time, since the value of the equivalent input noise is inversely proportional to the value of capacitor C RES , the higher the value, the smaller the noise. Also, since the value of C RES is equal to the sum of C RES0 , C RES1 and C RES2 , comparator 1 operates in an ultra-low-power mode at this time. Therefore, the third operating mode is considered a high-power ultra-low-noise mode.

[0078] In summary, the comparator 1 of the present invention has two operating states: a reset state and a comparison state. When the clock signal CLK is at a low level and the clock signal CLKB is at a high level, it is in the reset state; otherwise, it is in the comparison state.

[0079] Meanwhile, the programming control signals V1 and V2 are used to control the operating mode of the comparator 1. When both programming control signals V1 and V2 are at a low level, the comparator 1 operates in the normal operating mode. In the preamplifier 7, only the capacitor C RES0 powers the preamplifier 7. When the programming control signal V1 is at a high level and V2 is at a low level, the comparator 1 operates in the medium-power and low-noise mode. In the first-stage preamplifier 7, the capacitors C RES0 and C RES1 serve as a floating power supply to power the first-stage preamplifier 7, reducing the equivalent input noise of the comparator 1. However, as a compromise, a certain amount of power consumption is sacrificed. When both programming control signals V1 and V2 are at a high level, the comparator 1 operates in the high-power and ultra-low-noise mode. In the first-stage preamplifier 7, the capacitors C RES0 、C RES1 and C RES2 jointly serve as a floating power supply to power the first-stage preamplifier 7, minimizing the power consumption of the comparator 1. In the ADC design, the operating mode of the comparator can be flexibly adjusted according to different design requirements, enabling it to operate in the normal operating mode, the medium-power and low-noise mode, and the high-power and ultra-low-noise mode respectively.

[0080] In addition, the present invention adopts a circuit structure of the preamplifier 7 based on a floating power supply, significantly reducing the overall power consumption of the comparator 1 compared with traditional dynamic latch comparators.

[0081] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and the descriptions in the specification only illustrate the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of the present invention claimed is defined by the appended claims and their equivalents.

Claims

1. A gain and noise programmable comparator based on a floating amplifier, comprising a preamplifier and a latch; Characterized in that, The preamplifier adopts a preamplifier based on a floating power supply. The input side of the preamplifier is respectively connected to two voltage input terminals, a common-mode voltage input terminal, a pair of two-phase non-overlapping clock signals, and a pair of two-phase non-overlapping programming control signals. The output side of the preamplifier has a pair of preamplifier output signals; The latch adopts an SA dynamic latch. The SA dynamic latch has a latch structure with positive feedback latching. The input side of the SA dynamic latch is respectively connected to a pair of the preamplifier output signals. The output side of the SA dynamic latch has a pair of latch output signals as the output signals of the comparator; A pair of the clock signals are respectively a clock signal CLK and a clock signal CLKB. The clock signal CLK and the clock signal CLKB are a pair of mutually inverted clock signals. The clock signal CLKB is also connected to the input side of the SA dynamic latch; The preamplifier includes transistors M1, M2, M3, M4, M5 and M6, and capacitors C X1 , C X2 and C RES0 , CMOS transmission gates I1 and I2, and switches S1 and S2. Among them, M5, M6, C RES0 , I1 and I2 form a set of operating mode components; The source of M1 is connected to the source of M2 and to the output terminal of I1. The drain of M1 is connected to the drain of M3, and the drain of M2 is connected to the drain of M4. The common terminal between the drain of M1 and the drain of M3, and the common terminal between the drain of M2 and the drain of M4 are respectively used as a pair of the preamplifier output signals and are respectively connected to C X1 , C X2 's upper plate. The upper plates of C X1 , C X2 are respectively connected to the common-mode voltage input terminal through S1 and S2. The lower plates of C X1 , C X2 are respectively connected to the ground potential. The source of M3 is connected to the source of M4 and to the output terminal of I2. The gate of M1 is connected to the gate of M3 and is connected to one of the voltage input terminals. The gate of M2 is connected to the gate of M4 and is connected to the other voltage input terminal; The drain of M5 is respectively connected to the input end of I1 and the upper plate of C RES0 The drain of M6 is respectively connected to the input end of I2 and the lower plate of C RES0 The source of M5 is connected to the power supply potential, the source of M6 is connected to the ground potential, the gate of M5 is connected to the clock signal CLK, the gate of M6 is connected to the clock signal CLKB, and the positive control end and negative control end of I1 and I2 are controlled by at least one of a pair of clock signals and a pair of the programming control signals; The number of groups of the working mode components is the same as the number of working modes of the comparator. When there are at least two groups of the working mode components, the adjacent other group of the working mode components includes corresponding M7, M8, C RES1 , I3 and I4, and the drain of M5 is further connected to the output end of I3, and the drain of M6 is further connected to the output end of I4. The adjacent two groups of the working mode components are connected in sequence in this way to form multiple groups of working mode components connected in sequence.

2. The gain and noise programmable comparator based on a floating amplifier according to claim 1, Characterized in that, The comparator has three operating modes, and the number of groups of the operating mode components is three. Another adjacent group of the operating mode components includes corresponding M9, M10, C RES2 , I5, and I6; The positive control terminals of I1 and I2 are connected to the clock signal CLK, and the negative control terminals of I1 and I2 are connected to the clock signal CLKB; The preamplifier further includes AND gates A1, A2, A3, and A4. Defining a pair of the programming control signals as V1 and V2, then the clock signal CLK and V1 are respectively connected to the negative control terminals of I3 and I4 after passing through A1, and the clock signal CLKB and V1 are respectively connected to the positive control terminals of I3 and I4 after passing through A2. The clock signal CLK and V2 are respectively connected to the negative control terminals of I5 and I6 after passing through A3, and the clock signal CLKB and V2 are respectively connected to the positive control terminals of I5 and I6 after passing through A4.

3. The gain and noise programmable comparator based on a floating amplifier according to claim 2, Characterized in that, The transistors M1, M2, M5, M7, and M9 are N-channel insulated gate bipolar transistors, and the transistors M3, M4, M6, M8, and M10 are P-channel insulated gate bipolar transistors.

4. The gain and noise programmable comparator based on a floating amplifier according to claim 1, Characterized in that, The CMOS transmission gate includes transistors M22 and M23; The drain of M22 is connected to the drain of M23 and serves as the input terminal of the CMOS transmission gate. The source of M22 is connected to the source of M23 and serves as the output terminal of the CMOS transmission gate. The gate of M22 serves as the positive control terminal of the CMOS transmission gate, and the gate of M23 serves as the negative control terminal of the CMOS transmission gate.

5. The gain and noise programmable comparator based on a floating amplifier according to claim 4, Characterized in that, The transistor M22 is an N-channel insulated gate bipolar transistor, and the transistor M23 is a P-channel insulated gate bipolar transistor.

6. The gain and noise programmable comparator based on a floating amplifier as claimed in claim 1 or 2, characterized in that, the SA dynamic latch includes transistors M11, M12, M13, M14, M15, M16, M17, M18, M19, M20 and M21; the gates of M11 and M12 are respectively connected to a pair of the pre-amplifier output signals, the sources of M11 and M12 are connected to each other and connected to the drain of M21, the source of M21 is connected to the power supply potential, the drain of M11 is respectively connected to the sources of M13 and M15, the drain of M12 is respectively connected to the sources of M14 and M16, the gates of M13, M17, the drain of M14 and the drain of M18 are connected to each other and serve as an output signal of one of the comparators, the gates of M14, M18, the drain of M13 and the drain of M17 are connected to each other and serve as an output signal of the other comparator, thereby forming a latch structure with positive feedback latch; the sources of M15, M16, M17, M18, M19 and M20 are all connected to the ground potential, and the gates of M15, M16, M19, M20 and M21 are respectively connected to the clock signal CLKB.

7. The gain and noise programmable comparator based on a floating amplifier as claimed in claim 6, characterized in that, the transistors M11, M12, M13, M14 and M21 are N-channel insulated gate bipolar transistors, and the transistors M15, M16, M17, M18, M19, M20 are P-channel insulated gate bipolar transistors.

8. A control method for the gain and noise programmable comparator based on a floating amplifier as claimed in claim 2, characterized in that, it includes: controlling both V1 and V2 to be low levels, then the comparator operates in a first operating mode, and the first operating mode serves as a normal operating mode; controlling V1 to be a high level and V2 to be a low level, then the comparator operates in a second operating mode, and the second operating mode has higher power consumption and lower noise than the first operating mode, so that the second operating mode serves as a medium power consumption and low noise mode; controlling both V1 and V2 to be high levels, then the comparator operates in a third operating mode, and the third operating mode has higher power consumption and lower noise than the second operating mode, so that the third operating mode serves as a high power consumption and ultra-low noise mode.

9. The control method for the gain and noise programmable comparator based on a floating amplifier as claimed in claim 8, characterized in that, controlling the clock signal CLK to be a low level and the clock signal CLKB to be a high level, then the comparator operates in a reset state; controlling the clock signal CLK to be a high level and the clock signal CLKB to be a low level, then the comparator operates in a comparison state.

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