Display panel and display device

Abstract

This application discloses a display panel and a display device. The display panel includes: a display area and a non-display area; a switching area located in the non-display area; a substrate, a first insulating layer, and a first metal layer, the first metal layer being located between the first insulating layer and the substrate; the first insulating layer includes a first via located in the switching area, the first via exposing at least a portion of the first metal layer; a second insulating layer located between the first metal layer and the substrate, and in contact with the first metal layer; within the switching area, along the thickness direction of the display panel, the distance from the side of the second insulating layer away from the substrate to the side of the substrate near the second insulating layer is D1; ​​within the display area, along the thickness direction of the display panel, the distance from the side of the second insulating layer away from the substrate to the side of the substrate near the second insulating layer is D2; wherein, D1 > D2 > 0. This application enables smoother electrical connections at the first via.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] When a display device includes touch functionality, if an embedded design is used, the light-emitting device layer is typically encapsulated first, and touch signal lines are placed on the side of the encapsulation layer facing away from the substrate. The touch signal lines extend into the non-display area and are routed through vias to the area below the encapsulation layer. During the manufacturing of the display panel, transfer holes are provided at the transfer points of the touch signal lines. When encapsulating the display panel, encapsulation material can easily enter these transfer holes, affecting the electrical connection quality between the subsequent touch signal lines and the underlying film layer at the transfer hole. Summary of the Invention

[0003] This application provides a display panel and display device that enable smoother electrical connections at signal line switching points.

[0004] In a first aspect, a display panel is provided, comprising: a display area and a non-display area; a switching area located in the non-display area; a substrate, a first insulating layer, and a first metal layer, the first metal layer being located between the first insulating layer and the substrate; the first insulating layer including a first via located in the switching area, the first via exposing at least a portion of the first metal layer; a second insulating layer located between the first metal layer and the substrate, and in contact with the first metal layer; within the switching area, along the thickness direction of the display panel, the distance from the side surface of the second insulating layer away from the substrate to the side surface of the substrate near the second insulating layer is D1; ​​within the display area, along the thickness direction of the display panel, the distance from the side surface of the second insulating layer away from the substrate to the side surface of the substrate near the second insulating layer is D2; wherein, D1 > D2 > 0.

[0005] Secondly, based on the same inventive concept, a display device is also provided, including the display panel of the first aspect of this application.

[0006] In the display panel and display device provided in this application embodiment, a first via located in the first insulating layer is disposed in the switching area and exposes the first metal layer for electrical connection of signal lines requiring switching. The second insulating layer located on the side of the first metal layer closest to the substrate has a distance D1 from its surface away from the substrate to the surface of the substrate closest to the second insulating layer. This distance is greater in the switching area than in the display area. Therefore, when fabricating the encapsulation layer, the portion of the first metal layer located in the first via is closer to the mask of the encapsulation layer than the portion located in the display area. Consequently, the material of the encapsulation layer is less likely to enter the first via, allowing the first metal layer to be more fully exposed in the first via, thereby improving the electrical connection quality between the signal lines and the first metal layer. Attached Figure Description

[0007] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of the structure of a display panel according to an embodiment of this application.

[0009] Figure 2 for Figure 1 A cross-sectional view of the display panel DD section in an embodiment of this application.

[0010] Figure 3 for Figure 1 Another cross-sectional view of the DD section of the display panel in the embodiment of this application.

[0011] Figure 4 This is a schematic diagram of the pixel circuit of the display panel according to an embodiment of this application.

[0012] Figure 5 for Figure 1 Another cross-sectional view of the DD section of the display panel in the embodiment of this application.

[0013] Figure 6 for Figure 1 Another cross-sectional view of the DD section of the display panel in the embodiment of this application.

[0014] Figure 7 for Figure 1 Another cross-sectional view of the DD section of the display panel in the embodiment of this application.

[0015] Figure 8 for Figure 1Another cross-sectional view of the DD section of the display panel in the embodiment of this application.

[0016] Figure 9 This is a schematic diagram of the routing of the first bonding line of the display panel in an embodiment of this application.

[0017] Figure 10 for Figure 1 A cross-sectional view of the EE section of the display panel in an embodiment of this application.

[0018] Figure 11 for Figure 1 A cross-sectional view of the FF section of the display panel in an embodiment of this application.

[0019] Figure 12 for Figure 1 Another cross-sectional view of the FF section of the display panel in the embodiment of this application.

[0020] Figure 13 for Figure 1 Another cross-sectional view of the FF section of the display panel in the embodiment of this application.

[0021] Figure 14 for Figure 1 Another cross-sectional view of the EE section of the display panel in the embodiment of this application.

[0022] Figure 15 This is a schematic diagram of the routing of the second bonding line of the display panel in an embodiment of this application.

[0023] Figure 16 This is a top view of the touch layer of the display panel in an embodiment of this application.

[0024] Figure 17 for Figure 1 Another cross-sectional view of the EE section of the display panel in the embodiment of this application.

[0025] Figure 18 This is a schematic diagram of the structure of a display device according to an embodiment of this application.

[0026] Figure label:

[0027] 01. Display panel; 02. Display device;

[0028] 1. Substrate;

[0029] 2. First insulating layer; 21. First via;

[0030] 3. First metal layer; 31. First bonding line;

[0031] 4. Second insulating layer; 41. Second via;

[0032] 5. First metal pad;

[0033] 61. Thin-film transistor; 611. First transistor electrode; 62. Capacitor; 621. First capacitor electrode; 63. First signal line; 64. Light-emitting device; 641. First device electrode;

[0034] 7. Second metal layer; 71. Second bonding line;

[0035] 8. Touch layer; 81. Touch signal line;

[0036] AA, Display area; NA, Non-display area; H, Cable switching area; B, Bending area. Detailed Implementation

[0037] The features and exemplary embodiments of various aspects of this application will now be described in detail. Numerous specific details are set forth in the following detailed description in order to provide a comprehensive understanding of this application. However, it will be apparent to those skilled in the art that this application can be implemented without some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this application by illustrating examples thereof.

[0038] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The embodiments will now be described in detail with reference to the accompanying drawings.

[0039] Relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0040] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0041] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0042] It should be understood that in the embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0043] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0044] The applicant discovered that in current display devices, touch signal lines are typically routed in non-display areas of the display panel. For example, when a touch layer is incorporated into the display device, it is generally located on the side of the light-emitting device layer facing away from the substrate. The chip used to process touch signals is usually located in the lower bezel area on the side of the light-emitting device layer facing the substrate. The touch signal line needs to cross the bend area of ​​the lower bezel area to connect with the pads corresponding to the chip pins. Therefore, the touch signal line needs to be routed in the non-display area of ​​the display panel to enhance its resistance to bending in the bend area. Vias are usually provided at the route change point of the touch signal line so that the touch signal line on the side of the light-emitting device layer can be electrically connected to the corresponding connection signal line on the other side of the light-emitting device layer. The connection signal line then connects to the chip to conduct the touch signal. During the manufacturing process of the display panel, it needs to be encapsulated, i.e., a packaging layer needs to be prepared. Generally, chemical vapor deposition (CVD) is used to prepare the packaging layer. During the fabrication process, the CVD mask will block the vias used for line switching. However, there are gaps between the mask and the underlying film layer. The material of the encapsulation layer may enter the via through the gap, thereby affecting the electrical connection between the subsequent touch signal line and the corresponding connection signal line at the via, and thus affecting the signal conduction of the touch signal line.

[0045] Based on the above analysis, the applicant proposes a display panel comprising a first insulating layer, a first metal layer, a second insulating layer, and a substrate, stacked sequentially. The first insulating layer has a first via located in a switching region, exposing the first metal layer for switching first connection signal lines. The distance from the surface of the second insulating layer away from (away from) the substrate to the surface of the substrate closer to the second insulating layer is such that the corresponding distance D1 of the second insulating layer in the switching region is greater than the corresponding distance D2 of the second insulating layer in the display region, resulting in the first insulating layer in the switching region being higher than the first insulating layer in the display region. During the fabrication of the encapsulation layer, the first via located in the switching region is closer to the CVD mask, making it more difficult for the encapsulation layer material to enter the first via, thereby improving the electrical connection quality between the first connection signal line and the first metal layer in the first via.

[0046] Figure 1 This is a schematic diagram of the structure of a display panel according to an embodiment of this application. Figure 2 for Figure 1 A cross-sectional view of the display panel DD section in an embodiment of this application.

[0047] Please see Figure 1 and Figure 2 This application provides a display panel, including: a display area AA and a non-display area NA; a switching area H located in the non-display area NA; a substrate 1, a first insulating layer 2, and a first metal layer 3, the first metal layer 3 being located between the first insulating layer 2 and the substrate 1; the first insulating layer 2 including a first via 21 located in the switching area H, the first via 21 exposing at least a portion of the first metal layer 3; a second insulating layer 4 located between the first metal layer 3 and the substrate 1, and in contact with the first metal layer 3; within the switching area H, along the thickness direction of the display panel, the distance from the side surface of the second insulating layer 4 away from the substrate 1 to the side surface of the substrate 1 near the second insulating layer 4 is D1; ​​within the display area AA, along the thickness direction of the display panel, the distance from the side surface of the second insulating layer 4 away from the substrate 1 to the side surface of the substrate 1 near the second insulating layer 4 is D2; wherein, D1 > D2 > 0.

[0048] In this embodiment of the application, the display panel has a display area AA for displaying light emission. A non-display area NA at least partially surrounds the display area AA. A switching area H is located within the non-display area NA and is used for switching the first connection signal line. The first connection signal line is electrically connected to a second connection signal line in the switching area H. Exemplarily, the first connection signal line can be a touch signal line of the touch layer, and the second connection signal line can be electrically connected to a pad corresponding to a chip pin, so that touch signals are transmitted via the first and second signal lines.

[0049] The substrate 1 should cover the display area AA and the non-display area NA, serving as a carrier for other film layers of the display panel. The substrate 1 can be formed from polymer materials such as glass, polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyaryl compounds (PAR), or glass fiber reinforced plastic (FRP). The substrate 1 can be transparent, translucent, or opaque. In the embodiments of this application, the substrate 1 can also be a flexible substrate, formed from a thin polymer, such as polyimide.

[0050] The first insulating layer 2 is located on the side of the first metal layer 3 facing away from the substrate 1. Except at vias, it can be used for insulation between the first metal layer 3 and the metal film layer on the other side of the first insulating layer 2. The first via 21 located in the line switching area H exposes the first metal layer 3, allowing the first connection signal line to be electrically connected to the first metal layer 3 at the first via, thereby realizing the line switching of the first connection signal line. The second insulating layer 4 is located between the first metal layer 3 and the substrate 1, and can be used for insulation between the first metal layer 3 and the metal film layer on the other side of the second insulating layer 4. The first insulating layer 2, the first metal layer 3, and the second insulating layer 4 are all partially located in the display area AA and partially located in the line switching area H.

[0051] Along the thickness direction of the display panel, within the display area AA and the non-display area NA, the distance between the side of the second insulating layer 4 away from the substrate 1 and the side of the substrate 1 closer to the second insulating layer 4 varies. The distance D1 corresponding to the display area AA and the distance D2 corresponding to the switching area H satisfy D1 > D2 > 0. Therefore, the second insulating layer 4 in the switching area H is farther from the substrate 1 than the second insulating layer 4 in the display area AA. Since the first metal layer 3 is in contact with the second insulating layer 4, and the first insulating layer 2 is located on the side of the first metal layer 3 away from the second insulating layer 4, the first insulating layer 2 in the switching area H is farther from the substrate 1 than the first insulating layer 2 in the display area AA. When the encapsulation layer is fabricated on the side of the first insulating layer 2 away from the substrate 1, the first insulating layer 2 located in the switching area H is closer to the mask than the first insulating layer 2 located in the display area AA. That is, the first via 21 located in the first insulating layer 2 is closer to the mask. Therefore, the material of the encapsulation layer is less likely to enter the first via 21 through the gap between the mask and the first insulating layer 2, thereby improving the quality of the electrical connection between the first connection signal line and the first metal layer 3, and making the signal transmission of the first connection signal line smoother.

[0052] It should be noted that the first connection signal line that is switched in the switching area H should be capable of switching between different layers of the display panel. For example, the first connection signal line for switching can be a touch signal line of the touch layer or a feedback signal line of the light sensor. The second connection signal line, located on another layer of the display panel corresponding to the first connection signal line, can be disposed on the first metal layer 3 or between the first metal layer 3 and the substrate 1. If disposed between the first metal layer 3 and the substrate 1, it needs to be electrically connected to the first metal layer 3. The second connection signal line is electrically connected to the first connection signal line to achieve signal transmission. For example, the second connection signal line can be electrically connected to the touch chip to transmit touch signals.

[0053] Furthermore, the second insulating layer 4 can be in direct contact with the substrate 1, and other film layers can also be provided between the second insulating layer 4 and the substrate 1. For example, a planarization layer, other metal layers, and insulating layers can be provided between the second insulating layer 4 and the substrate 1.

[0054] Figure 3 for Figure 1 Another cross-sectional view of the DD section of the display panel in the embodiment of this application.

[0055] Further, please refer to Figure 3 The display panel in this embodiment of the application also includes a first metal pad 5 located in the line switching area H, and the first metal pad 5 is disposed between the second insulating layer 4 and the substrate 1.

[0056] A first metal layer 3 pad located in the line-changing area H is disposed between the second insulating layer 4 and the substrate 1. Compared to the display area AA, the first metal pad 5 can move the second insulating layer 4 in the line-changing area H away from the substrate 1, increasing the distance D1 from the side of the second insulating layer 4 away from the substrate 1 to the side of the substrate 1 closer to the second insulating layer 4, making D1 > D2. During the fabrication of the encapsulation layer, the first via 21 located in the first insulating layer 2 can be placed closer to the mask, reducing the possibility of encapsulation layer material entering the first via 21, improving the quality of the electrical connection between the first connection signal line and the first metal layer 3, and making the signal transmission of the first connection signal line smoother.

[0057] Figure 4 This is a schematic diagram of the pixel circuit of the display panel according to an embodiment of this application. Figure 5 for Figure 1 Another cross-sectional view of the DD section of the display panel in the embodiment of this application. Figure 6 for Figure 1 Another cross-sectional view of the DD section of the display panel in the embodiment of this application. Figure 7 for Figure 1Another cross-sectional view of the DD section of the display panel in the embodiment of this application.

[0058] Further, please refer to Figures 4 to 7 The display area AA includes multiple thin-film transistors 61, capacitors 62, and a first signal line 63; the thin-film transistors 61 include first transistor electrodes 611, and the capacitors 62 include first capacitor electrodes 621; the first transistor electrodes 611, the first capacitor electrodes 621, and the first signal line 63 are all disposed in different layers; the first signal line 63 is located in the first metal layer 3; the first metal pad 5 is disposed in the same layer as at least one of the first transistor electrodes 611 and the first capacitor electrodes 621.

[0059] The thin-film transistors 61, capacitor 62, and first signal line 63 in display area AA can be used to form the pixel circuit of the display panel to control the light-emitting device 64 of the display panel to emit light. For ease of explanation, this application embodiment uses a pixel circuit including seven thin-film transistors 61 and one capacitor 62 (7T1C pixel circuit) as an example. The pixel circuit of this application embodiment can also take other forms, such as 7T2C, 8T1C, 8T2C, 9T1C, and 9T2C pixel circuits, etc.

[0060] In this design, thin-film transistor M1 can be a driving transistor, thin-film transistor M2 can be a threshold compensation transistor, thin-film transistor M3 can be a data writing transistor, thin-film transistor M4 can be a first reset transistor, thin-film transistor M5 can be a second reset transistor, thin-film transistor M6 can be a first light-emitting control transistor, and thin-film transistor M7 can be a second light-emitting control transistor; capacitor Cst can be a storage capacitor; signal line S1 can be a first scan signal line, signal line S2 can be a second scan signal line, signal line Verf can be a reference voltage signal line, signal line Emit can be a light-emitting control signal line, signal line Vdata can be a data signal line, signal line PVDD can be a first power supply signal line, and signal line PVEE can be a second power supply signal line. Thin-film transistors M4 and M5 can be connected to different reference (reset) voltage signal lines; each thin-film transistor can be selected as a P-type or N-type transistor according to design requirements. Figure 4 The illustration will only use P-type transistors as an example.

[0061] In this embodiment, the first signal line 63 can be the first power signal line PVDD, the capacitor 62 can be the storage capacitor Cst, and the thin film transistor 61 can be the first light-emitting control transistor M6 or the second light-emitting control transistor M7.

[0062] Exemplarily, the first transistor electrode 611 of the thin-film transistor 61 can be either the gate or the drain. The first capacitor electrode 621 of the capacitor 62 can be any electrode of the capacitor 62. The first signal line 63 can be a positive power supply line. The first transistor electrode 611, the first capacitor electrode 621, and the first signal line 63 are disposed on different layers. Generally, along the thickness direction of the display panel, the first transistor electrode 611 and the first capacitor electrode 621 can be located between the first signal line 63 and the substrate 1. Therefore, the first signal line 63 is located on the first metal layer 3, and the first metal pad 5 is disposed on the same layer as at least one of the first transistor electrode 611 and the first capacitor electrode 621. The portion of the first metal layer 3 exposed by the first via 21 and the first signal line 63 can be fabricated simultaneously, which facilitates the fabrication of the portion of the first metal layer 3 exposed by the first via 21 and does not significantly increase the thickness of the display surface in this embodiment. Alternatively, the first metal pad 5 and the first transistor electrode 611 can be fabricated simultaneously, and / or the first metal pad 5 and the first capacitor electrode 621 can be fabricated simultaneously. This facilitates the fabrication of the first metal pad 5 and ensures that the distance from the first via 21 of the first insulating layer 2 to the substrate 1 is greater than the distance from the first insulating layer 2 to the substrate 1 in the display area AA. The number of first metal pads 5 should be at least one, and each first metal pad 5 is disposed in the same layer as one of the first transistor electrode 611 and the first capacitor electrode 621.

[0063] Further reading Figures 5 to 7 In the thickness direction of the display panel, the first metal pad 5 and the first via 21 at least partially overlap.

[0064] In this embodiment, the first metal pad 5 is used to ensure that the distance from the first via 21 of the first insulating layer 2 to the substrate 1 is greater than the distance from the first insulating layer 2 to the substrate 1 in the display area AA. Since the first metal pad 5 at least partially overlaps with the first via 21, the area of ​​the first insulating layer 2 located in the switching area H that overlaps with the first metal pad 5 can satisfy the requirement that the distance to the substrate 1 is greater than the distance from the first insulating layer 2 to the substrate 1 in the display area AA. This reduces the risk of encapsulation layer material entering the first via 21, thereby improving the electrical connection quality at the first via 21. For example, when the first via 21 is a central hole, the first pad can also be a circular pad; in the plane where the substrate 1 is located, the orthographic projection of the first via 21 lies within the orthographic projection of the first pad.

[0065] Figure 8 for Figure 1 Another cross-sectional view of the DD section of the display panel in the embodiment of this application.

[0066] Further, please refer to Figure 8In the thickness direction of the display panel, at least a portion of the first metal pad 5 does not overlap with the first via 21.

[0067] Since at least a portion of the first metal pad 5 does not overlap with the first via 21, the distance from the first insulating layer 2 located in the switching area H and outside the first via 21 to the substrate 1 is greater than the distance from the first insulating layer 2 located in the display area AA to the substrate 1. Conversely, the distance from the first insulating layer 2 located at the first via 21 to the substrate 1 can be greater than or equal to the distance from the first insulating layer 2 located in the display area AA to the substrate 1. For example, when the first via 21 is a circular hole, the first pad can be an annular pad; on the plane of the substrate 1, the orthographic projection of the first pad surrounds the orthographic projection of the first via 21.

[0068] Further reading Figure 8 In the line-changing area H, along the thickness direction of the display panel, the distance from the side surface of the substrate 1 away from the first metal pad 5 covered by the second insulating layer 4 to the side surface of the substrate 1 near the second insulating layer 4 is D11; in the line-changing area H, along the thickness direction of the display panel, the distance from the side surface of the substrate 1 away from the first metal pad 5 covered by the second insulating layer 4 to the side surface of the substrate 1 near the second insulating layer 4 is D12; where D11 > D12 > 0.

[0069] Along the thickness direction of the display panel, in the non-display area, the distance between the side of the second insulating layer 4 away from the substrate 1 and the side of the substrate 1 closer to the second insulating layer 4 varies. The distance D11 corresponding to the location covering the first metal pad 5 and the distance D12 corresponding to the location not covering the first metal pad 5 satisfy D11 > D12 > 0. Therefore, the second insulating layer 4 covering the first metal pad 5 is farther away from the substrate 1 than the second insulating layer 4 not covering the first metal pad 5. Since the first metal layer 3 is in contact with the second insulating layer 4, and the first insulating layer 2 is located on the side of the first metal layer 3 away from the second insulating layer 4, the first insulating layer 2 covering the first metal pad 5 is farther away from the substrate 1 than the first insulating layer 2 not covering the first metal pad 5. Considering that the orthographic projection of the first pad surrounds the orthographic projection of the first via 21 in the plane of the substrate 1, the portion of the first insulating layer 2 covering the first metal pad 5 can also prevent the encapsulation layer material from entering the first via 21, improving the electrical connection quality between the first via 21 and the signal line before the line change.

[0070] Figure 9 This is a schematic diagram of the routing of the first bonding line of the display panel in an embodiment of this application.

[0071] Further, please refer to Figure 9The non-display area NA also includes a bending area B, and the line-changing area H is located between the bending area B and the display area AA; the first metal layer 3 includes a first bonding line 31, at least a portion of which is located in the bending area B; the first via 21 exposes at least a portion of the first bonding line 31.

[0072] The display panel of this embodiment can be electrically connected to a circuit board with a chip via bonding. To increase the proportion of the display area AA, the bonded area and the circuit board with the chip can be bent to the side of the substrate 1 away from the first metal layer 3. In this embodiment, the bending area B of the non-display area NA can be bent. After the circuit board with the chip is bonded to the display panel of this embodiment, the bending area B can be bent so that the circuit board with the chip is bent to the side of the substrate 1 away from the first metal layer 3, thereby increasing the proportion of the display area AA. At least a portion of the first bonding line 31 of the first metal layer 3 is located in the bending area B and is used as a second connection signal line. When the first connection signal line is changed, the first connection signal line can be electrically connected to the first bonding line 31 through the first via 21 to achieve the purpose of changing the line. Optionally, after the display panel of this embodiment is bonded, the first bonding line 31 can be bent together with the bending area B.

[0073] Figure 10 for Figure 1 A cross-sectional view of the EE section of the display panel in an embodiment of this application.

[0074] Further, please refer to Figure 10 The display panel of this application embodiment further includes: a second metal layer 7, located between the second insulating layer 4 and the substrate 1; the second insulating layer 4 is provided with a second via 41 located in the non-display area NA, the second via 41 exposing the second metal layer 7; at the second via 41, the first metal layer 3 is electrically connected to the second metal layer 7.

[0075] The second metal layer 7 is exposed at the second via 41, allowing the first metal layer 3 to be electrically connected to the second metal layer 7 at the second via 41. The second connection signal line can be located on the second metal layer 7. In this case, the first connection signal line is electrically connected to the third metal layer 3, and the second connection signal line located on the second metal layer 7 is also electrically connected to the third metal layer 3, thus achieving an indirect electrical connection between the first and second connection signal lines. Because the first and second connection signal lines are connected indirectly, the space along the thickness direction between the first metal layer 3 and the substrate 1 can be utilized more fully, thereby reducing the space occupied by the non-display area NA and increasing the proportion of the display area AA.

[0076] Further reading Figure 10 The second via 41 is located outside the switching area H.

[0077] When it is difficult to set the second via 41 in the switching area H, the second via 41 can be set outside the switching area H. Considering that the first metal layer 3 and the second metal layer 7 are electrically connected at the second via 41, a signal line can be set in the first metal layer 3, and the signal line extends from the first via 21 to the second via 41 to simplify the complexity of the first metal layer 3.

[0078] Figure 11 for Figure 1 A cross-sectional view of the FF section of the display panel in an embodiment of this application. Figure 12 for Figure 1 Another cross-sectional view of the FF section of the display panel in the embodiment of this application. Figure 13 for Figure 1 Another cross-sectional view of the FF section of the display panel in the embodiment of this application.

[0079] Further, please refer to Figures 11 to 13 The display area AA includes multiple light-emitting devices 64, thin-film transistors 61, capacitors 62, and a first signal line 63; the thin-film transistor 61 includes a first transistor electrode 611, the capacitor 62 includes a first capacitor electrode 621, and the light-emitting device 64 includes a first device electrode 641; the first device electrode 641, the first transistor electrode 611, the first capacitor electrode 621, and the first signal line 63 are all disposed in different layers; the first device electrode 641 is located in the first metal layer 3; the first metal pad 5 is disposed in the same layer as at least one of the first signal line 63, the first transistor electrode 611, and the first capacitor electrode 621; the first signal line 63 is located in the second metal layer 7.

[0080] The thin-film transistor 61, capacitor 62, and first signal line 63 located in the display area AA can be used to form the pixel circuit of the display panel to control the light-emitting device 64 located in the display area AA to emit light. Exemplarily, the light-emitting device 64 can be an organic light-emitting diode (OLED), and the first device electrode 641 can be the anode of the light-emitting device 64. The first transistor electrode 611 of the thin-film transistor 61 can be the gate or drain. The first capacitor electrode 621 of the capacitor 62 can be any electrode of the capacitor 62. The first signal line 63 can be a positive power supply line. The first device electrode 641, the first transistor electrode 611, the first capacitor electrode 621, and the first signal line 63 are disposed on different layers. Generally, along the thickness direction of the display panel, the first transistor electrode 611, the first capacitor electrode 621, and the first signal line 63 are located between the first device electrode 641 and the substrate 1. Therefore, the first device electrode 641 is disposed on the first metal layer 3, and the first metal pad 5 is disposed on the same layer as at least one of the first signal line 63, the first transistor electrode 611, and the first capacitor electrode 621. The first metal layer 3 and the first device electrode 641 exposed in the first via 21 can be fabricated simultaneously, which facilitates the fabrication of the first metal layer 3 exposed in the first via 21 and does not significantly increase the thickness of the display surface in this embodiment. Alternatively, the first metal pad 5 and the first device electrode 641 can be fabricated simultaneously, and / or the first metal pad 5 and the first transistor electrode 611 can be fabricated simultaneously, and / or the first metal pad 5 and the first capacitor electrode 621 can be fabricated simultaneously, which facilitates the fabrication of the first metal pad 5 and ensures that the distance from the first via 21 of the first insulating layer 2 to the substrate 1 is greater than the distance from the first insulating layer 2 to the substrate 1 in the display area AA. The number of first metal pads 5 should be at least one, and each first metal pad 5 is disposed in the same layer as one of the first signal line 63, the first transistor electrode 611, and the first capacitor electrode 621.

[0081] Figure 14 for Figure 1 Another cross-sectional view of the EE section of the display panel in the embodiment of this application.

[0082] Further, please refer to Figure 14 The first metal pad 5 is located in the second metal layer 7.

[0083] When the first metal pad 5 is disposed on the same layer as one of the first signal line 63, the first transistor electrode 611, and the first capacitor electrode 621, the first metal pad 5 is located in the second metal layer 7. During the fabrication of the second metal layer 7, the second metal layer 7 and the first metal pad 5 located at the second via 41, as well as one of the first signal line 63, the first transistor electrode 611, and the first capacitor electrode 621, can be fabricated simultaneously. Therefore, the fabrication process of the embodiments of this application can be simplified, while making fuller use of the space in different areas of the second metal layer 7.

[0084] Figure 15 This is a schematic diagram of the routing of the second bonding line of the display panel in an embodiment of this application.

[0085] Further, please refer to Figure 15 The non-display area NA also includes a bending area B, and a line-changing area H is located between the bending area B and the display area AA; the second via 41 is located between the line-changing area H and the bending area B; the second metal layer 7 includes a second bonding line 71, at least a portion of which is located in the bending area B; the second via 41 exposes at least a portion of the second bonding line 71.

[0086] At least a portion of the second bonding line 71 of the second metal layer 7 is located in the bending area B and is used as a second connection signal line. When the first connection signal line is replaced, the first connection signal line can be electrically connected to the first metal layer 3 through the first via 21, and the first metal layer 3 can be electrically connected to the second bonding line 71 through the second via 41 to achieve the purpose of replacement. After the display panel of this embodiment is bonded, the second bonding line 71 bends together with the bending area B.

[0087] Figure 16 This is a top view of the touch layer of the display panel in an embodiment of this application. Figure 17 for Figure 1 Another cross-sectional view of the EE section of the display panel in the embodiment of this application.

[0088] Further, please refer to Figure 16 and Figure 17 The display panel in this embodiment further includes a touch layer 8, which includes touch signal lines 81; the touch signal lines 81 are electrically connected to the first metal layer 3 through a first via 21.

[0089] In the display panel of this application embodiment, touch functionality is achieved by providing a touch layer 8. For ease of explanation, this application embodiment uses mutual capacitance as an example for the touch layer 8, but the touch layer 8 can also use self-capacitance. The touch signal line 81 of the touch layer 8 is used to conduct touch signals. When a touch operation is performed, the capacitance between the touch electrodes at the corresponding touch position in the touch layer 8 changes, thus changing the electrical signal generated by the touch signal line 81 electrically connected to the touch electrodes, forming a touch signal. The touch signal line 81 leads the touch signal out to the non-display area. In this application embodiment, after the display panel is bonded with a circuit board containing a chip, the chip can identify the touch position based on the touch signal. The touch signal line 81 serves as a first connection signal line and is electrically connected to the first metal layer 3 at the first via 21, that is, electrically connected to the corresponding first bonding line 31 located in the first metal layer 3, realizing the switching of the touch signal line 81. The first bonding line 31 serves as a second connection signal line. Touch signals can be transmitted to the bending area B via the corresponding first bonding line 31 located in the first metal layer 3, and transmitted to the chip through the bonding connection between the display panel and the circuit board with the chip.

[0090] Figure 18 This is a schematic diagram of the structure of a display device according to an embodiment of this application.

[0091] Please see Figure 18 This application also provides a display device 02, including the display panel 01 of the previous embodiment. The display device provided in this application can be any product or component with practical functions, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0092] In summary, this application provides a display panel and display device in which a first via located in a first insulating layer is disposed in a switching area and exposes a first metal layer for electrical connection of signal lines requiring switching. The second insulating layer located on the side of the first metal layer closest to the substrate has a distance D1 from its surface furthest from the substrate to the surface of the substrate closest to the second insulating layer. This distance is greater in the switching area than in the display area. Therefore, during the fabrication of the encapsulation layer, the portion of the first metal layer located in the first via is closer to the mask of the encapsulation layer than the portion located in the display area. Consequently, the material of the encapsulation layer is less likely to enter the first via, allowing the first metal layer to be more fully exposed in the first via, thereby improving the electrical connection quality between the signal lines and the first metal layer.

[0093] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, include: Display area and non-display area; A line-changing area, located in the non-display area; The substrate, a first insulating layer, and a first metal layer are provided, wherein the first metal layer is located between the first insulating layer and the substrate; the first insulating layer includes a first via located in the switching region, the first via exposing at least a portion of the first metal layer. A second insulating layer is located between the first metal layer and the substrate, and the second insulating layer is in contact with the first metal layer. Within the switching area, along the thickness direction of the display panel, the distance from the side surface of the second insulating layer away from the substrate to the side surface of the substrate near the second insulating layer is D1; ​​within the display area, along the thickness direction of the display panel, the distance from the side surface of the second insulating layer away from the substrate to the side surface of the substrate near the second insulating layer is D2; where D1 > D2 > 0. The display panel further includes a first metal pad located in the switching area, the first metal pad being disposed between the second insulating layer and the substrate. The display area includes multiple light-emitting devices, thin-film transistors, capacitors, and a first signal line; the thin-film transistor includes a first transistor electrode, the capacitor includes a first capacitor electrode, and the light-emitting device includes a first device electrode; the first device electrode, the first transistor electrode, the first capacitor electrode, and the first signal line are all disposed in different layers; The display panel further includes: a second metal layer located between the second insulating layer and the substrate; the second insulating layer has a second via located in the non-display area, the second via exposing the second metal layer; at the second via, the first metal layer is electrically connected to the second metal layer; The first signal line is located in the first metal layer; the first metal pad is disposed in the same layer as at least one of the first transistor electrode and the first capacitor electrode; Alternatively, the first device electrode is located in the first metal layer; the first metal pad is disposed in the same layer as at least one of the first signal line, the first transistor electrode, and the first capacitor electrode; and the first signal line is located in the second metal layer.

2. The display panel according to claim 1, characterized in that, The non-display area also includes a bend area, and the line-changing area is located between the bend area and the display area; The first metal layer includes a first bonding line, at least a portion of which is located in the bending region; The first via exposes at least a portion of the first bonding line.

3. The display panel according to claim 1, characterized in that, The second via is located outside the switching area.

4. The display panel according to claim 1, characterized in that, The first metal pad is located in the second metal layer.

5. The display panel according to claim 1, characterized in that, The non-display area also includes a bending area, and the line-changing area is located between the bending area and the display area; the second via is located between the line-changing area and the bending area; The second metal layer includes a second bonding line, at least a portion of which is located in the bending region; The second via exposes at least a portion of the second bonding line.

6. The display panel according to claim 1, characterized in that, In the thickness direction of the display panel, the first metal pad at least partially overlaps with the first via.

7. The display panel according to claim 1, characterized in that, In the thickness direction of the display panel, at least a portion of the first metal pad does not overlap with the first via.

8. The display panel according to claim 7, characterized in that, Within the switching area, along the thickness direction of the display panel, the distance from the side surface of the substrate away from the first metal pad where the second insulating layer covers the substrate to the side surface of the substrate near the second insulating layer is D11; within the switching area, along the thickness direction of the display panel, the distance from the side surface of the substrate away from the first metal pad where the second insulating layer does not cover the substrate to the side surface of the substrate near the second insulating layer is D12; wherein, D11 > D12 > 0.

9. The display panel according to claim 1, characterized in that, Also includes: A touch layer, the touch layer including touch signal lines; in the first via, the touch signal lines are electrically connected to the first metal layer.

10. The display panel according to claim 9, characterized in that, At least a portion of the touch signal lines are located in the non-display area.

11. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 10.

Images