Memristor and method for manufacturing the same

Abstract

The application relates to the field of semiconductor devices, in particular to a memristor and a preparation method thereof. The memristor provided by the application adopts a structure of an upper one-dimensional nano array, a memristor medium layer and a lower one-dimensional nano array, the effective working area of the memristor is limited in the intersection area between the upper one-dimensional nano array and the lower one-dimensional nano array, and the memristor with a fixed number and a uniformly distributed conductive filament is realized; the working area of a single memristor formed by the intersection area is defined to the nanometer level, so that the conductive filament formed during the working of the single memristor realizes single and same-root growth and breaking, the randomness introduced by the growth of the conductive filament is reduced, the position, the number and the diameter of the growth of the conductive filament are limited, and then the uniformly distributed and stably working conductive filament is obtained, the uniformity and the stability of the memristor are improved, and the preparation and the application in the future large-scale storage array or the neuromorphic computing are facilitated.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, in particular to a memristor and a preparation method thereof. BACKGROUND

[0002] With the explosive growth of data, information processing and integrated circuit chips have higher requirements for storage capacity. In the past few decades, the complementary metal oxide semiconductor technology has been greatly improved. However, as the feature size is less than 10 nanometers, the current advanced semiconductor technology is facing double pressure of manufacturing and power consumption. In order to continue the rapid development of the integrated circuit industry, more and more new semiconductor device architectures are proposed. One of the important semiconductor devices is the memristor.

[0003] The memristor is a nonlinear passive two-terminal element, and its resistance value depends on the historical input current or voltage, which has a memory characteristic. The non-volatile memristor can still maintain a high resistance state and a low resistance state for a long time after removing the external voltage, while the volatile memristor spontaneously returns to the high resistance state from the low resistance state in milliseconds. The volatile memristor has superior performance, including high on-off ratio, low power consumption, fast switching speed and high durability, and is often used as a threshold switch selector to suppress the bypass leakage current in a large-scale high-density memory array. In addition, the leaky-integrate-fire behavior of the volatile memristor under the external pulse stimulation can also simulate the behavior of neurons, and is further applied to neuromorphic networks and storage-computing integration. SUMMARY

[0004] To solve the problems of discrete work voltage and high and low resistance state of the memristor, the present application provides a memristor, comprising:

[0005] a substrate;

[0006] a lower one-dimensional nanometer array located on the surface of the substrate, the lower one-dimensional nanometer array being a plurality of inert nanowires, or the lower one-dimensional nanometer array being a plurality of active metal nanowires;

[0007] a lower metal electrode located at both ends of the lower one-dimensional nanometer array and on the surface of the substrate;

[0008] a memristor dielectric layer located on the surface of the lower one-dimensional nanometer array;

[0009] an upper one-dimensional nanometer array located on the surface of the memristor dielectric layer, the upper one-dimensional nanometer array being a plurality of active metal nanowires, or the upper one-dimensional nanometer array being a plurality of inert nanowires;

[0010] The upper one-dimensional nanometer array and the lower one-dimensional nanometer array are arranged in cross, so that each intersection of the upper one-dimensional nanometer array and the lower one-dimensional nanometer array forms at most one conductive filament in the memristor medium layer;

[0011] The upper metal electrode is located at two ends of the upper one-dimensional nanometer array.

[0012] Optionally, the active metal nanowire material is silver nanowire or copper nanowire, and the inert nanowire is one of carbon nanotube, gold nanowire or platinum nanowire.

[0013] Optionally, the silver nanowire has a diameter less than 20 nanometers.

[0014] Optionally, the carbon nanotube has a diameter less than 10 nanometers.

[0015] Optionally, the conductive filament has a diameter less than 20 nanometers.

[0016] Optionally, the lower metal electrode and the upper metal electrode are one of metal titanium, chromium, gold, platinum and copper.

[0017] Optionally, the memristor medium layer material is three-dimensional bulk material or two-dimensional layered material; the three-dimensional bulk material includes oxide and semiconductor material; the oxide is one of silicon dioxide, hafnium dioxide, titanium dioxide, aluminum oxide, zinc oxide and copper peroxide, and the semiconductor material is silicon or germanium; the two-dimensional layered material is one of hexagonal boron nitride, tungsten diselenide, molybdenum disulfide, molybdenum ditelluride, molybdenum selenide, stannous sulfide and stannous selenide.

[0018] The application further provides a preparation method of the memristor, comprising:

[0019] providing a substrate;

[0020] preparing a lower one-dimensional nanometer array on the surface of the substrate, the lower one-dimensional nanometer array being a plurality of inert nanowires, or the lower one-dimensional nanometer array being a plurality of active metal nanowires;

[0021] preparing a lower metal electrode at two ends of the lower one-dimensional nanometer array and on the surface of the substrate;

[0022] preparing a memristor medium layer on the surface of the lower one-dimensional nanometer array;

[0023] preparing an upper one-dimensional nanometer array on the surface of the memristor medium layer, the upper one-dimensional nanometer array being a plurality of active metal nanowires, or the upper one-dimensional nanometer array being a plurality of inert nanowires, and the upper one-dimensional nanometer array and the lower one-dimensional nanometer array being arranged in cross, so that each intersection of the upper one-dimensional nanometer array and the lower one-dimensional nanometer array forms at most one conductive filament in the memristor medium layer.

[0024] Preparation of the upper metal electrode at both ends of the upper one-dimensional nanometer array.

[0025] Optionally, the lower one-dimensional nanometer array and the upper one-dimensional nanometer array are prepared by a transfer method.

[0026] Optionally, the memristor is a silver nanowire-aluminum oxide-carbon nanotube structure.

[0027] In summary, the advantages and beneficial effects of the present application are:

[0028] The present application provides a memristor and a preparation method thereof, the memristor provided by the present application adopts the structure of an upper one-dimensional nanometer array and a lower one-dimensional nanometer array, the upper one-dimensional nanometer array of the memristor is connected to an upper metal electrode, and the lower one-dimensional nanometer array is connected to a lower metal electrode, so that the effective working area of the memristor is limited to the intersection area between the upper one-dimensional nanometer array and the lower one-dimensional nanometer array, and a memristor with a fixed number and a uniform distribution of conductive filaments is realized.

[0029] The working area of a single memristor formed in the intersection area between the upper one-dimensional nanometer array and the lower one-dimensional nanometer array is defined to the nanometer level, and due to the ultra-small size, the conductive filaments formed during the working of the single memristor realize single and same-root growth and breaking, which reduces the randomness introduced by the growth of the conductive filaments, thereby limiting the position, number and diameter of the growth of the conductive filaments, and further obtaining uniformly distributed and stably working conductive filaments, improving the uniformity and stability of the memristor, and facilitating the preparation and application in large-scale storage arrays or neuromorphic computing in the future.

[0030] By limiting the diameter of the conductive filaments, the induction of high current flow to the lateral growth of the filaments is suppressed, the volatility of the memristor is enhanced, the memory window of the volatile memristor is reduced, and the application in logic devices and neuromorphic artificial neurons in the future is facilitated; the limitation of the diameter of the conductive filaments also indirectly defines the on-state current of the semiconductor device, so that the semiconductor device can complete the volatile work of the memristor without increasing additional current limiting devices.

[0031] The memristor has multiple conductive filaments with the same morphology during working, and the competitive and synergistic relationship of these conductive filaments has more stable performance compared with traditional memristors, and also has a higher working current compared with an ultra-small single memristor. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 It is a schematic diagram of a traditional array of memristors;

[0033] Figure 2Schematic diagram of an array of conductive filaments of a conventional memristor;

[0034] Figure 3 Flow chart of a method for manufacturing a memristor according to an embodiment of the present application;

[0035] Figures 4A-4E Schematic diagram of a cross-sectional structure of a manufacturing process of a memristor according to an embodiment of the present application;

[0036] Figure 5 Schematic diagram of a structure of a conductive filament of a memristor according to an embodiment of the present application;

[0037] Figure 6 Current-voltage characteristic curves of the 5th and 20th turn-on and turn-off voltages of a memristor according to an embodiment of the present application;

[0038] Figure 7 Current-voltage characteristic curves of the 5th and 20th turn-on and turn-off voltages of a memristor according to the prior art. DETAILED DESCRIPTION

[0039] Reference should be made to Figure 1 The array of conventional memristors includes three layers, a middle memristor dielectric layer and two electrode layers on the upper and lower surfaces of the memristor dielectric layer, one of which is an active metal electrode layer. Based on the conductive filament mechanism, the active metal electrode layer not only serves as a transmission terminal for carriers, but also needs to provide ions, which migrate to the memristor dielectric layer, thereby forming a conductive filament.

[0040] Reference should be made to Figure 2 Silver, as a common active metal electrode layer, is oxidized into silver ions under the action of an applied electric field, which enter the middle memristor dielectric layer and move towards the other electrode layer of the memristor. The silver ions are reduced to metal silver atoms by obtaining electrons during the movement, and the accumulation of metal silver atoms in the memristor dielectric layer along the direction of the electric field forms a conductive filament that can conduct electricity.

[0041] However, due to the random distribution of silver atoms in the memristor dielectric layer, the growth position, connection path and diameter of the conductive filament all have randomness, and the distribution of the working voltage and high and low resistance states of the memristor also has discrete problems, which greatly challenges the stability and durability of the semiconductor device, and also seriously hinders the large-scale integration of the memristor in the actual cross array.

[0042] In addition, the volatile characteristic of the memristor is related to the diameter of the conductive filament, and a higher current will induce further lateral growth of the conductive filament, and a conductive filament with a diameter that is too large cannot spontaneously dissolve and break, and the device must be reset to destroy the conductive filament in a Joule heating manner, and the volatile characteristic of the device will also change to non-volatile. In order to effectively guarantee the volatile characteristic of the memristor, an additional resistance needs to be connected in series in actual work to limit the current in the memristor, so as to inhibit the excessive growth of the conductive filament, and the circuit design of the memristor and the large-scale integrated application introduces additional costs.

[0043] For the convenience of those skilled in the art, the present application will be further described in detail below in combination with specific embodiments.

[0044] The embodiment of the present application provides a memristor, as shown in the drawings, comprising: Figure 4E

[0045] a substrate 100;

[0046] a lower one-dimensional nano array 200 located on the surface of the substrate 100, the lower one-dimensional nano array 200 being a plurality of inert nanowires, or the lower one-dimensional nano array 200 being a plurality of active metal nanowires;

[0047] a lower metal electrode 300 located at both ends of the lower one-dimensional nano array 200 and on the surface of the substrate 100;

[0048] a memristor dielectric layer 400 located on the surface of the lower one-dimensional nano array 200;

[0049] an upper one-dimensional nano array 500 located on the surface of the memristor dielectric layer 400, the upper one-dimensional nano array 500 being a plurality of active metal nanowires, or the upper one-dimensional nano array 500 being a plurality of inert nanowires, and the upper one-dimensional nano array 500 and the lower one-dimensional nano array 200 are arranged in cross, so that each intersection point of the upper one-dimensional nano array 500 and the lower one-dimensional nano array 200 forms at most one conductive filament in the memristor dielectric layer 400;

[0050] an upper metal electrode 600 located at both ends of the upper one-dimensional nano array 500.

[0051] In the embodiment of the present application, the substrate 100 is a silicon substrate. In other embodiments, the substrate is a silicon carbide substrate, a sapphire substrate or other suitable substrate.

[0052] ​The lower layer one-dimensional nano array 200 includes a plurality of inert nanowires, the inert nanowires are one of carbon nanotubes, gold nanowires or platinum nanowires; the upper layer one-dimensional nano array 500 includes a plurality of active metal nanowires, the active metal nanowire material is silver nanowire or copper nanowire, or the lower layer one-dimensional nano array 200 includes a plurality of active metal nanowires, the active metal nanowire material is silver nanowire or copper nanowire; the upper layer one-dimensional nano array 500 includes a plurality of inert nanowires, the inert nanowires are one of carbon nanotubes, gold nanowires or platinum nanowires.

[0053] The conductive filament formed by the inert nanowires is not easy to spontaneously dissolve and break, so that the memory characteristic of the memristor is stronger, that is, the non-volatility of the memristor is enhanced; the conductive filament formed by the active metal nanowires is easy to spontaneously dissolve and break, so that the memory characteristic of the memristor is weaker, that is, the volatility of the memristor is enhanced.

[0054] Through the selection of the inert nanowires and the active metal nanowires, the memristor has the volatility and the non-volatility, so that the memristor has a relatively wide application in the selector and the memory.

[0055] In the embodiment of the application, the lower layer one-dimensional nano array 200 is a plurality of carbon nanotubes, and the upper layer one-dimensional nano array 500 is a plurality of silver nanowires.

[0056] The diameter of the carbon nanotube can be less than 10 nanometers and can reach the order of magnitude of 1 nanometer, the diameter of the carbon nanotube is smaller than the diameter of other inert nanowires, which is beneficial to further limit the growth range of the diameter of the conductive filament, at the same time, the carbon nanotube is only used for connecting the conductive filament to form a conductive path, without introducing metal atoms to diffuse in the medium layer, so as to avoid interfering with the growth form of the conductive filament, which is helpful to the repeated growth and breakage of the conductive filament and enhances the stability of the device; as the active metal nanowire, silver is more likely to diffuse, the conductive filament is more likely to spontaneously dissolve and break, and the device volatility is enhanced.

[0057] The intersection area between the upper layer one-dimensional nano array 500 and the lower layer one-dimensional nano array 200 forms the working area of a single memristor, so that the working area of the single memristor is defined to the order of nanometers, the conductive filament formed by the single memristor during working realizes single and same root growth and breakage, the randomness introduced by the growth of the conductive filament is reduced, so as to limit the position, quantity and diameter of the growth of the conductive filament, and then the uniformly distributed and stably working conductive filament is obtained, the uniformity and stability of the memristor are improved, and the preparation and application in the large-scale storage array or the neuromorphic computing in the future are facilitated.

[0058] In the embodiment of the application, the memristor medium layer 400 is an oxide or a two-dimensional layered material.

[0059] The oxide is one of silicon dioxide, hafnium dioxide, titanium dioxide, aluminum oxide, zinc oxide, and copper peroxide.

[0060] The two-dimensional layered material is one of hexagonal boron nitride, tungsten diselenide, molybdenum disulfide, molybdenum ditelluride, molybdenum selenide, stannous selenide, and stannous sulfide.

[0061] When the memristor medium layer 400 is an oxide, the oxide provides oxygen vacancies, so that metal atoms can be oxidized, diffused and reduced in the medium layer, so that the conductive filaments can grow, dissolve and break, ensuring the normal work of the memristor.

[0062] In the embodiment of the application, the memristor medium layer 400 is aluminum oxide, and the thickness of the aluminum oxide is 5 nm.

[0063] In other embodiments, the memristor medium layer is a two-dimensional layered material.

[0064] When the memristor medium layer is a two-dimensional layered material, the two-dimensional layered material provides defects, and the activation energy of the metal atoms entering the defect site of the medium layer is smaller, the defect of the medium layer induces the direction and morphology of the growth of the conductive filaments between the lower one-dimensional nanometer array and the upper one-dimensional nanometer array, ensuring the normal work of the memristor.

[0065] Since the thickness of the two-dimensional layered material can reach the atomic level, the size of the semiconductor device is further miniaturized in the longitudinal direction, the growth distance of the conductive filaments is shortened, the working voltage of the semiconductor device is reduced, the switching speed of the semiconductor device is improved, and an atomic-level high-performance memristor is realized.

[0066] In the embodiment of the application, the lower metal electrode 300 is a whole piece of metal, and the material of the lower metal electrode 300 is one of titanium, chromium, gold, platinum, copper or other conductive materials.

[0067] In the embodiment of the application, the upper metal electrode 600 is a whole piece of metal, and the material of the upper metal electrode 600 is one of titanium, chromium, gold, platinum, copper or other conductive materials.

[0068] The upper one-dimensional nanometer array 500 in the memristor is connected to the upper metal electrode 600, and the lower one-dimensional nanometer array 200 is also connected to the lower metal electrode 300, so that the effective working area of the memristor is limited to the intersection area between the upper one-dimensional nanometer array 500 and the lower one-dimensional nanometer array 200, and a memristor with a fixed number and a uniform distribution of conductive filaments is realized.

[0069] In the embodiment of the application, the diameter of the silver nanowire is less than 20 nanometers.

[0070] In the embodiment of the present application, the diameter of the carbon nanotube is less than 10 nanometers.

[0071] In the embodiment of the present application, the diameter of the conductive filament is less than 20 nanometers and greater than the diameter of one active metal atom.

[0072] By limiting the diameters of the upper one-dimensional nanometer array and the lower one-dimensional nanometer array, the diameter of the conductive filament is limited, the induction of high current to the lateral growth of the conductive filament is inhibited, and the volatility of the memristor is enhanced; the limitation of the diameter of the conductive filament also indirectly defines the on-state current of the semiconductor device, so that the additional current limiting device is not needed for the semiconductor device to complete the volatile work of the memristor.

[0073] The present application also provides a preparation method of a memristor, please refer to Figure 3 , comprising:

[0074] Step S10, providing a substrate;

[0075] Step S20, preparing a lower one-dimensional nanometer array on the surface of the substrate, the lower one-dimensional nanometer array is a plurality of inert nanowires, or the lower one-dimensional nanometer array is a plurality of active metal nanowires;

[0076] Step S30, preparing a lower metal electrode at both ends of the lower one-dimensional nanometer array and on the surface of the substrate;

[0077] Step S40, preparing a memristor dielectric layer on the surface of the lower one-dimensional nanometer array;

[0078] Step S50, preparing an upper one-dimensional nanometer array on the surface of the memristor dielectric layer, the upper one-dimensional nanometer array is a plurality of active metal nanowires, or the upper one-dimensional nanometer array is a plurality of inert nanowires, the upper one-dimensional nanometer array and the lower one-dimensional nanometer array are arranged in cross, so that each intersection point of the upper one-dimensional nanometer array and the lower one-dimensional nanometer array forms at most one conductive filament in the memristor dielectric layer;

[0079] Step S60, preparing an upper metal electrode at both ends of the upper one-dimensional nanometer array.

[0080] Specifically, step S10 is performed to provide a substrate 100.

[0081] In the embodiment of the present application, the substrate 100 is a silicon substrate.

[0082] In other embodiments, the substrate is a silicon carbide substrate, a sapphire substrate or other suitable substrate.

[0083] Step S20 is performed, please refer to Figure 4APreparation of a lower one-dimensional nano array 200 on the surface of the substrate 100, the lower one-dimensional nano array 200 is a plurality of inert nanowires, or the lower one-dimensional nano array is a plurality of active metal nanowires.

[0084] In the embodiment of the present application, the lower one-dimensional nano array 200 is prepared by a transfer method.

[0085] Step S30 is performed, please refer to Figure 4B Preparation of a lower metal electrode 300 on both ends of the lower one-dimensional nano array 200 and on the surface of the substrate 100.

[0086] In the embodiment of the present application, the lower metal electrode 300 is first formed by laser direct writing, and then by metal thermal evaporation.

[0087] In other embodiments, the lower metal electrode 300 can be first formed by photolithography or electron beam exposure, and then by magnetron sputtering or electron beam evaporation.

[0088] Step S40 is performed, please refer to Figure 4C Preparation of a memristor dielectric layer 400 on the surface of the lower one-dimensional nano array 200.

[0089] In the embodiment of the present application, the memristor dielectric layer 400 is prepared by an atomic layer deposition method.

[0090] In other embodiments, the memristor dielectric layer is prepared by a material transfer method.

[0091] Step S50 is performed, please refer to Figure 4D Preparation of an upper one-dimensional nano array 500 on the surface of the memristor dielectric layer 400, the upper one-dimensional nano array 500 is a plurality of active metal nanowires, or the upper one-dimensional nano array is a plurality of inert nanowires, the upper one-dimensional nano array and the lower one-dimensional nano array are arranged in a cross manner, so that each intersection point of the upper one-dimensional nano array 500 and the lower one-dimensional nano array 200 forms at most one conductive filament in the memristor dielectric layer 400.

[0092] The plurality of inert nanowires are carbon nanotubes, gold nanowires or platinum nanowires.

[0093] In the embodiment of the present application, the inert nanowires are carbon nanotubes, which are uniformly distributed and parallel to each other, and the diameter of the carbon nanotubes is less than 10 nanometers.

[0094] The active metal nanowire material is silver nanowire or copper nanowire.

[0095] In the embodiment of the present application, the active metal nanowire is silver nanowire, the silver nanowire is uniformly distributed and parallel to each other, and the diameter of the silver nanowire is less than 20 nanometers.

[0096] In the embodiment of the present application, the upper layer one-dimensional nanometer array 500 is prepared by a transfer method.

[0097] In the embodiment of the present application, the lower layer one-dimensional nanometer array 200 and the upper layer one-dimensional nanometer array 500 are perpendicular to each other.

[0098] The step S60 is performed, please refer to Figure 4E The upper layer metal electrode 600 is prepared at both ends of the upper layer one-dimensional nanometer array 500.

[0099] In the embodiment of the present application, the lower layer metal electrode 300 is first formed by laser direct writing and then formed by metal thermal evaporation.

[0100] In other embodiments, the upper layer metal electrode 600 can be first formed by photolithography or electron beam exposure, and then formed by magnetron sputtering or electron beam evaporation.

[0101] In the embodiment of the present application, when the memristor works, a voltage is applied to the upper layer metal electrode 600, the lower layer metal electrode 300 is grounded, a forward scanning voltage is applied, the upper layer one-dimensional nanometer array 500 provides metal ions, the provided metal ions diffuse into the memristor dielectric layer 400 to form a conductive filament, and the conductive filament spontaneously dissolves and breaks under a negative scanning voltage.

[0102] In the embodiment of the present application, a voltage is applied to the upper layer metal electrode 600 of the memristor, the lower layer metal electrode 300 is grounded, and the working area of a single memristor formed in the intersection area between the upper layer one-dimensional nanometer array 500 and the lower layer one-dimensional nanometer array 200.

[0103] Please refer to Figure 5 The metal ions in the upper layer one-dimensional nanometer material diffuse into the memristor dielectric layer 400, a single memristor works, a conductive filament is formed to realize single and same-root growth and breaking, the randomness introduced by the growth of the conductive filament is reduced, the position, number and diameter of the growth of the conductive filament are limited, and then a uniformly distributed and stable conductive filament is obtained, the uniformity and stability of the memristor are improved, and the preparation and application in a large-scale storage array or a neuromorphic computing in the future are facilitated.

[0104] In the embodiment of the present application, under a forward scanning voltage, metal atoms in the active metal nanowire in the upper layer one-dimensional nanometer array 500 accumulate along the path of the electric field direction, a conductive filament is formed in the memristor dielectric layer 400, the conductive filament connects the upper layer one-dimensional nanometer array 500 and the lower layer one-dimensional nanometer array 200, and the memristor is converted from a high resistance state to a low resistance state.

[0105] In other embodiments, under a forward scanning voltage, metal atoms in the active metal nanowire in the lower one-dimensional nanowire array are accumulated along the path of the metal atoms in the direction of the electric field, forming a conductive filament in the memristor dielectric layer, which connects the upper one-dimensional nanowire array and the lower one-dimensional nanowire array, so that the memristor is converted from a high resistance state to a low resistance state.

[0106] The growth diameter of the conductive filament is in a range between the diameter of the active metal nanowire and the diameter of the inert nanowire.

[0107] In embodiments of the present application, the growth diameter of the conductive filament is in a range of less than 10 nanometers.

[0108] The growth diameter of the conductive filament of a conventional memristor is in a range of 10 nanometers to 200 nanometers, and the present application limits the diameters of the inert nanowire and the active metal nanowire, so that the growth diameter of the conductive filament is in a range of less than 10 nanometers, thereby realizing the range limitation of the growth diameter of the conductive filament. By limiting the diameter of the conductive filament, the induction of high current flow to the lateral growth of the filament is inhibited, the volatility of the memristor is enhanced, the memory window of the volatile memristor is reduced, and the application of the memristor in future logic devices and neuromorphic artificial neurons is facilitated; the limitation of the diameter of the conductive filament also indirectly defines the on-state current of the semiconductor device, so that the semiconductor device can complete the volatile work of the memristor without adding an additional current limiting device.

[0109] In embodiments of the present application, under a negative scanning voltage, the conductive filament in the memristor dielectric layer 400 spontaneously dissolves and breaks, and the device is converted from a low resistance state to a high resistance state.

[0110] In embodiments of the present application, after the conductive filament in the memristor dielectric layer 400 dissolves and breaks, the residual metal atoms provide a preferential path for the formation of the conductive filament when the power is turned on next time.

[0111] In embodiments of the present application, when the active metal nanowire of the memristor is a silver nanowire, the memristor dielectric layer is aluminum oxide, and the inert nanowire is a carbon nanotube, the vertical structure of a single memristor formed is a silver nanowire-aluminum oxide-carbon nanotube; the silver nanowire leads out a test pin from the upper metal electrode, and the carbon nanotube leads out a test pin from the lower metal electrode, and a direct current voltage is scanned on the vertical structure to obtain the volatile resistance change characteristics of the device.

[0112] When the memristor is forward scanned from 0V to 1V, the initial state of the memristor is a high resistance state, at this time, the conductive filament in the single memristor is not formed, with the increase of the voltage, the silver ions continuously diffuse into the aluminum oxide in the memristor dielectric layer, the silver ions are reduced to silver atoms by electrons, until a plurality of silver atoms are accumulated to form a conductive filament, at this time, the electrons are transmitted by the thermionic emission and tunneling mechanism, the memristor is turned on, the memristor is switched from the high resistance state to the low resistance state, and the conductive filament grows in the vertical direction and then grows in the horizontal direction, and the diameter of the conductive filament gradually increases.

[0113] When the memristor is negative scanned from 1V to 0V, the initial state of the memristor is a low resistance state, at this time, the conductive filament has been formed, with the decrease of the voltage, the silver atoms in the conductive filament and the aluminum oxide in the interface of the memristor dielectric layer can cause the silver atoms to be oxidized to silver ions, and the conductive filament is gradually dissolved, until the conductive filament is broken, at this time, the memristor is turned off, and the memristor is switched from the low resistance state to the high resistance state; the process from the beginning of the dissolution of the conductive filament to the complete breakage of the conductive filament causes the existence of a hysteresis window of the direct current characteristic of the memristor, that is, the memory characteristic.

[0114] Please refer to Figure 6 Through multiple scanning tests, the opening voltage and the closing voltage data of the fifth and the twentieth times of the memristor provided by the application can be obtained, the position offset of the voltage is small, and it is indicated that the opening voltage and the closing voltage of the memristor are well coincident.

[0115] Please refer to Figure 7 The opening voltage and the closing voltage data of the fifth and the twentieth times of the traditional memristor are provided, and it is found that the position of the voltage is greatly offset, and it is indicated that the opening voltage and the closing voltage of the memristor cannot be well coincident.

[0116] It is found through experiments that the volatility of the memristor provided by the application is enhanced compared with the volatility of the traditional memristor; and when the voltage is negative scanned, the memristor provided by the application can be turned off earlier, while the traditional memristor is turned off when the voltage is close to zero, and the memristor provided by the application has more stable performance compared with the traditional memristor.

[0117] When the memristor works, a plurality of conductive filaments with the same shape are generated, and the competitive and synergistic relationship of the conductive filaments has more stable performance compared with the traditional memristor, and also has a higher working current compared with a single memristor with an ultra-small size.

[0118] Finally, it is stated that any modification or equivalent replacement of part or all of the technical features of the technical solutions relying on the method and the embodiments of the application, the essence of which does not deviate from the corresponding technical solutions of the application, belongs to the patent range of the device array and the embodiments of the application.

Claims

1. A memristor, characterized in that, include: Substrate; A lower one-dimensional nanoarray located on the surface of a substrate, wherein the lower one-dimensional nanoarray is composed of multiple inert nanowires or multiple active metal nanowires. Lower metal electrodes located at both ends of the lower one-dimensional nanoarray and on the substrate surface; Memristor dielectric layer located on the surface of the lower one-dimensional nanoarray; The upper one-dimensional nanoarray located on the surface of the memristor dielectric layer is either a multi-active metal nanowire or a multi-inert nanowire. The upper one-dimensional nanoarray and the lower one-dimensional nanoarray are arranged in an interleaved manner, such that each intersection of the upper one-dimensional nanoarray and the lower one-dimensional nanoarray forms at most one conductive filament in the memristor dielectric layer, and the diameter of the conductive filament is less than 20 nanometers. Upper metal electrodes located at both ends of the upper one-dimensional nanoarray; Wherein, when the lower one-dimensional nanoarray is composed of multiple inert nanowires, the upper one-dimensional nanoarray is composed of multiple active metal nanowires; when the lower one-dimensional nanoarray is composed of multiple active metal nanowires, the upper one-dimensional nanoarray is composed of multiple inert nanowires, wherein the inert nanowires are one of carbon nanotubes, gold nanowires, or platinum nanowires.

2. A memristor as described in claim 1, characterized in that, The active metal nanowire material is either silver nanowire or copper nanowire.

3. A memristor as described in claim 2, characterized in that, The diameter of the silver nanowires is less than 20 nanometers.

4. A memristor as described in claim 1, characterized in that, The diameter of the carbon nanotubes is less than 10 nanometers.

5. A memristor as described in claim 1, characterized in that, The lower and upper metal electrodes are made of one of the following metals: titanium, chromium, gold, platinum, and copper.

6. A memristor as described in claim 1, characterized in that, The memristor dielectric layer material is an oxide or a two-dimensional layered material; the oxide is one of silicon dioxide, hafnium dioxide, titanium dioxide, aluminum oxide, zinc oxide, and copper peroxide; the two-dimensional layered material is one of hexagonal boron nitride, tungsten diselenide, molybdenum disulfide, molybdenum ditelluride, molybdenum selenide, tin sulfide, and tin selenide.

7. A method for fabricating a memristor, characterized in that, include: Provide substrate; A lower-layer one-dimensional nanoarray is prepared on the surface of the substrate. The lower-layer one-dimensional nanoarray is composed of multiple inert nanowires or multiple active metal nanowires. Lower metal electrodes are fabricated at both ends of the lower one-dimensional nanoarray and on the substrate surface; A memristor dielectric layer is fabricated on the surface of the lower one-dimensional nanoarray. An upper one-dimensional nanoarray is fabricated on the surface of the memristor dielectric layer. The upper one-dimensional nanoarray is composed of multiple active metal nanowires or multiple inert nanowires. The upper one-dimensional nanoarray and the lower one-dimensional nanoarray are arranged in an interleaved manner, such that each intersection of the upper one-dimensional nanoarray and the lower one-dimensional nanoarray forms at most one conductive filament within the memristor dielectric layer. The diameter of the conductive filament is less than 20 nanometers. Upper metal electrodes are fabricated at both ends of the upper one-dimensional nanoarray; Wherein, when the lower one-dimensional nanoarray is composed of multiple inert nanowires, the upper one-dimensional nanoarray is composed of multiple active metal nanowires; when the lower one-dimensional nanoarray is composed of multiple active metal nanowires, the upper one-dimensional nanoarray is composed of multiple inert nanowires, wherein the inert nanowires are one of carbon nanotubes, gold nanowires, or platinum nanowires.

8. The method for fabricating a memristor as described in claim 7, characterized in that, The lower and upper one-dimensional nanoarrays are prepared by a transfer method.

9. The method for fabricating a memristor as described in claim 7, characterized in that, The memristor has a silver nanowire-alumina-carbon nanotube structure.

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