Conformal oxidation for wraparound gate nanosheet input / output devices

Abstract

Horizontal gate all around devices and methods of fabricating the same are described. The hGAA devices include an oxide layer on a semiconductor material that is between a source region and a drain region of the device. The methods include radical plasma oxidation (RPO) of a semiconductor material layer between a source region and a drain region of an electronic device.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to methods for filling substrate features. More specifically, embodiments of this disclosure relate to methods for forming high-quality I / O oxides. Background Technology

[0002] Transistors are critical components in most integrated circuits. Since the drive current and resulting speed of a transistor are proportional to its gate width, faster transistors typically require larger gate widths. Therefore, a trade-off must be made between transistor size and speed, and "fin field-effect transistors" (finFETs) have been developed to resolve this conflicting goal of maximizing drive current and minimizing transistor size. FinFETs are characterized by fin-shaped channel regions, which can significantly increase transistor size without substantially increasing the transistor's footprint, and are now used in many integrated circuits. However, finFETs have their own drawbacks.

[0003] As the feature size of transistor devices continues to shrink to achieve greater circuit density and higher performance, there is a need for improved transistor device structures to improve electrostatic coupling and reduce negative impacts such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, FinFET structures, and horizontal all-around gate (hGAA) structures. The hGAA device structure includes several lattice-matched channels suspended in a stacked configuration and connected via source / drain regions. The hGAA structure provides good electrostatic control and is widely applicable to complementary metal-oxide-semiconductor (CMOS) wafer fabrication.

[0004] Conventional I / O oxide processes result in the immediate regeneration of poor-quality native oxides after ex-situ pre-cleaning, low-density ALD-type oxide deposition, linear reduction in the space between nanosheets, limited downstream integration (i.e., multi-threshold voltage (multi-Vt)), and require additional post-processing to densify the ALD film, which increases cost and complexity. Summary of the Invention

[0005] One or more embodiments of this disclosure relate to a method for forming a semiconductor device. The method includes the steps of: pre-cleaning a plurality of semiconductor material layers to remove native oxides and / or residues; and forming an oxide layer on the plurality of semiconductor material layers.

[0006] Another embodiment of this disclosure relates to a horizontally all-around gate device. The processing device includes an oxide layer surrounding a plurality of horizontal semiconductor material layers between a source region and a drain region.

[0007] Other embodiments of this disclosure relate to a non-transitory computer-readable medium including instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform the following operations: pre-cleaning multiple semiconductor material layers to remove native oxides and / or residues; and forming oxide layers on the multiple semiconductor material layers using free radical plasma oxidation. Attached Figure Description

[0008] Therefore, the above-described features of this disclosure can be understood in detail by referring to embodiments that are briefly outlined above, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only show typical embodiments of this disclosure and should not be considered as limiting the scope, as other equivalent embodiments are permissible.

[0009] Figure 1 Plotting the process flow of a method according to one or more embodiments;

[0010] Figures 2A to 2F A cross-sectional view of an electronic device according to one or more embodiments is shown;

[0011] Figures 3A to 3G A cross-sectional view of an electronic device according to one or more embodiments is shown; and

[0012] Figure 4 Illustrations of clustering tools according to one or more implementations. Detailed Implementation

[0013] Before describing several exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the setup or processing described in the following specification. This disclosure can have other embodiments and can be implemented or performed in various ways.

[0014] As used in this specification and the appended claims, the term "substrate" refers to a surface, or a portion of a surface, on which the process is performed. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, reference to a substrate may refer only to a portion of a substrate. Furthermore, reference to deposition on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0015] As used herein, "substrate" refers to any substrate or material surface formed on a substrate, on which a film treatment is performed during a manufacturing process. For example, depending on the application, substrate surfaces on which treatment can be performed may include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials (such as metals, metal nitrides, metal alloys, and other conductive materials). Substrates may include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to grind, etch, reduce, oxidize, hydroxylate (or generate or graft target chemical moieties to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to performing film treatments directly on the surface of the substrate itself, any of the film treatment steps disclosed herein (disclosed in more detail below) may also be performed on an underlayer formed on the substrate, and the term "substrate surface" is intended to include such an underlayer as referred to herein. Therefore, for example, when a film / layer or part of a film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface contains will depend on the film to be deposited and the specific chemicals used.

[0016] As used in this specification and the accompanying claims, the terms “precursor,” “reactant,” “reactive gas,” etc., are used interchangeably to refer to any gaseous species that can react with the substrate surface.

[0017] A transistor is a circuit component or element typically formed on a semiconductor device. Depending on the circuit design, transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, wires, or other components. Typically, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions comprise doped regions of a substrate and exhibit a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric that is interposed between the gate electrode and the channel region in the substrate.

[0018] As used herein, the term "field-effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement-mode field-effect transistors typically exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by an electric field in the device, generated by the voltage difference between the body and the gate. The three terminals of an FET are: source (S), through which charge carriers enter the channel; drain (D), through which charge carriers leave the channel; and gate (G), the gate terminal used to regulate the channel conductivity. Typically, the current entering the channel at the source (S) is denoted as I.S The current entering the channel at the drain (D) is denoted as I. D The drain-to-source voltage is denoted as V. DS By applying a voltage to the gate (G), the current (i.e., I) entering the channel at the drain can be controlled. D ).

[0019] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate whose voltage determines the device's conductivity. This ability to change conductivity by applying a voltage is used to amplify or switch electronic signals. A MOSFET is based on the regulation of charge concentration using a metal-oxide-semiconductor (MOS) capacitor between a host electrode and a gate electrode, which is located above the host and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a highly doped region separated by the host region. These regions can be p-type or n-type, but they are of the same type and opposite to the type of the host region. A "+" sign following the doping type indicates that the source and drain (different from the host) are highly doped.

[0020] If the MOSFET is an n-channel or nMOS FET, the source and drain are in the n+ region, and the main body is the p region. If the MOSFET is a p-channel or pMOS FET, the source and drain are in the p+ region, and the main body is the n region. The source is called this because it is the origin of charge carriers flowing through the channel (electrons for an n-channel and holes for a p-channel); similarly, the drain is where charge carriers leave the channel.

[0021] As used herein, the term "FinFET" refers to a MOSFET transistor built on a substrate, where the gate is located on two or three sides of the channel, forming a dual-gate or triple-gate structure. Because the channel region forms "fins" on the substrate, the common name for FinFET devices is FinFET. FinFET devices feature fast switching times and high current densities.

[0022] As used herein, the term "gate all-around (GAA)" is used to refer to an electronic device (e.g., a transistor) in which gate material surrounds all sides of a channel region. The channel region of a GAA transistor may include nanowires or nanoslabs, rod-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has multiple vertically spaced horizontal nanowires or horizontal rods, thereby making the GAA transistor a stacked horizontal gate all-around (hGAA) transistor.

[0023] As used herein, the term "nanowire" refers to a device with nanoscale (10⁻⁶) characteristics. -9 Nanowires are nanostructures with a diameter of (meters). A nanowire can also be defined as a length-to-width ratio greater than 1000. Alternatively, a nanowire can be defined as a structure with a thickness or diameter limited to tens of nanometers or less and an unlimited length. Nanowires are used in transistors and some laser applications, and in one or more embodiments, are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in transistors of logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices.

[0024] Conventional I / O oxide processes result in immediate regrowth of poor-quality native oxides after ex-situ pre-cleaning, low-density ALD-type oxide deposition, linear reduction in nanosheet-to-nanosheet space deposition, limited downstream integration (i.e., multi-threshold voltage (multi-Vt)), and the need for additional post-processing to densify the ALD film, increasing cost and complexity. Therefore, one or more embodiments advantageously provide an integrable and selective pre-cleaning process that removes poor-quality native oxides and inhibits regrowth, eliminating the q-time between pre-cleaning and I / O oxide formation. In one or more embodiments, the oxides are advantageously dense, thus eliminating the need for a post-processing densification step. In one or more embodiments, silicon nanosheets (NS) are advantageously consumed during growth, generating more NS-NS space and promoting downstream integration margin (i.e., multi-threshold voltage (multi-Vt)). Some embodiments advantageously reduce the dielectric constant, k-value, of the gate and internal spacers by partially oxidizing the surface.

[0025] One or more embodiments of this disclosure are described with reference to the accompanying drawings. In one or more embodiments, a gate-all-around transistor is fabricated using a standard process flow. In one or more embodiments, after removing the dummy gate, an integrated (in-situ) pre-cleaning is performed to remove the dummy gate oxide. This is followed by conformal oxidation and spacer treatment without disrupting the vacuum.

[0026] Figure 1 A process flow diagram is illustrated for a method 100 for forming a semiconductor device according to some embodiments of this disclosure. The following refers to... Figures 2A to 2F To describe method 100, Figures 2A to 2F The manufacturing stages of a semiconductor structure according to some embodiments of this disclosure are described. Figures 2A to 2F This is a cross-sectional view of an electronic device (e.g., hGAA) according to one or more embodiments. Method 100 may be part of a multi-step manufacturing process for a semiconductor device. Therefore, method 100 can be performed in any suitable processing chamber coupled to a clustering tool. The clustering tool may include processing chambers for manufacturing semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber for manufacturing semiconductor devices.

[0027] Method 100 involves providing a substrate 200 having a top surface 202 (e.g., ...). Figure 2A(As illustrated) and thus begin operation 102. In some embodiments, substrate 200 may be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate in which the entire substrate is made of semiconductor material. A bulk semiconductor substrate may comprise any suitable semiconductor material and / or a combination of semiconductor materials used to form the semiconductor structure. For example, the semiconductor layer may comprise one or more materials, such as crystalline silicon (e.g., Si). <100> or Si <111> The semiconductor material may include silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 200 comprises a semiconductor material such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 200 comprises one or more of the following: silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although some examples of materials that can form a substrate have been described herein, any material that can serve as the basis for passive and active devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) falls within the spirit and scope of this disclosure.

[0028] In some embodiments, the semiconductor material may be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, any suitable process, such as ion implantation, may be used to dope the substrate. As used herein, the term "n-type" refers to a semiconductor generated during manufacturing by doping an intrinsic semiconductor with an electron donor element. The term n-type derives from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of a well (or hole). In contrast to an n-type semiconductor, a p-type semiconductor has a hole concentration greater than an electron concentration. In a p-type semiconductor, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopant, or combinations thereof. In some embodiments, to prevent parasitic bottom devices from conducting, the substrate may be doped to provide a high dose of dopant at a first location on the surface of the substrate 200. For example, in some embodiments, the surface of the substrate may have about 1018 atoms / cm 3 To about 10 19 atoms / cm 3 The dopant density.

[0029] At least one superlattice structure 204 is formed on the top surface 202 of the substrate 200 (e.g., Figure 2A (As depicted). The superlattice structure 204 includes a plurality of sacrificial layers 224 and corresponding plurality of channel layers 226 arranged alternately in multiple stacked pairs. In some embodiments, the plurality of stacked layers comprises a silicon (Si) group and a silicon-germanium (SiGe) group. In some embodiments, the plurality of sacrificial layers 224 and corresponding plurality of channel layers 226 may contain any number of lattice-matching material pairs suitable for forming the superlattice structure 204. In some embodiments, the plurality of sacrificial layers 224 and corresponding plurality of channel layers 226 comprise about 2 to about 50 pairs of lattice-matching materials.

[0030] Typically, parasitic devices will be present at the bottom of the superlattice structure 204. In some embodiments, as discussed above, dopants implanted in the substrate are used to suppress the conduction of parasitic devices. In some embodiments, the substrate 200 is etched such that the bottom portion of the superlattice structure 204 includes an unremoved substrate portion, thereby allowing said substrate portion to serve as a bottom release layer of the superlattice structure 204.

[0031] In one or more embodiments, the thicknesses of the sacrificial layer 224 and the channel layer 226 are in the range of about 2 nm to about 50 nm, about 3 nm to about 20 nm, or about 2 nm to about 15 nm in some embodiments. In some embodiments, the average thickness of the sacrificial layer 224 is within 0.5 to 2 times the average thickness of the channel layer 226.

[0032] In some embodiments, dielectric material 246 is deposited on substrate 200 using a conventional chemical vapor deposition method. In some embodiments, dielectric material 246 is recessed below the top surface 202 of substrate 200, such that substrate 200 forms the bottom portion of superlattice structure 204.

[0033] Please see Figure 2B In some embodiments, an alternative gate structure (e.g., dummy gate structure 208) is formed over and adjacent to the superlattice structure 204. The dummy gate structure 208 defines the channel region of the transistor device. The dummy gate structure 208 can be formed using any suitable conventional deposition and patterning process known in the art.

[0034] In some embodiments, sidewall spacers 210 are formed along the outer sidewall of the virtual gate structure 208. In some embodiments, the sidewall spacers 210 comprise suitable insulating materials known in the art, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc. In some embodiments, the sidewall spacers 210 are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0035] In some embodiments, embedded source regions 232 and drain regions 234 are formed in the source trench and drain trench, respectively. In some embodiments, the source region 232 is formed near a first end of the superlattice structure 204, and the drain region 234 is formed near a opposite second end of the superlattice structure. Figure 2C In the illustrated embodiment, one of the source region 232 or the drain region 234 is shown at the front of the superlattice structure 204. The other end of the superlattice structure 204 has the other of the source region 232 or the drain region 234. In some embodiments, the source region 232 and / or the drain region 234 are formed of any suitable semiconductor material, such as, but not limited to, silicon, germanium, silicon-germanium, etc. In some embodiments, any suitable deposition process, such as epitaxial deposition, can be used to form the source region 232 and the drain region 234.

[0036] In some embodiments, an inter-layer dielectric (ILD) layer 220 is deposited over a substrate 200 including source / drain regions 232, 234, a dummy gate structure 208, and sidewall spacers 210. The ILD layer 220 can be deposited using conventional chemical vapor deposition methods (e.g., plasma-enhanced chemical vapor deposition and low-pressure chemical vapor deposition). In one or more embodiments, the ILD layer 220 is formed from any suitable dielectric material, such as, but not limited to, undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride. In one or more embodiments, the ILD layer 220 is then polished back using conventional chemical mechanical planarization methods to expose the top of the dummy gate structure 208. In some embodiments, the ILD layer 220 is polished to expose the top of the dummy gate structure 208 and the top of the sidewall spacers 210.

[0037] like Figure 2DAs shown, in operation 104, the dummy gate structure 208 is removed to expose the channel region 214 of the superlattice structure 204. During the removal of the dummy gate structure 208, the ILD layer 220 protects the source / drain regions 232, 234. The dummy gate structure 208 can be removed using any conventional etching method, such as plasma dry etching or wet etching. In some embodiments, the dummy gate structure 208 comprises polysilicon and is removed by a selective etching process. In some embodiments, the dummy gate structure 208 comprises polysilicon, and the superlattice structure 204 comprises alternating layers of silicon (Si) and silicon-germanium (SiGe).

[0038] like Figure 2E As shown, in operation 106, the channel layer 226 between the sacrificial layers 224 in the superlattice structure 204 is selectively etched. For example, when the superlattice structure 204 is composed of silicon (Si) layers and silicon germanium (SiGe) layers, the silicon germanium (SiGe) is selectively etched to form the channel nanowires 240. Any well-known etchant can be used to remove the channel layer 226, such as silicon germanium (SiG), which is selective for the layers of the sacrificial layer 224, and the etchant etches the layers of the channel layer 226 at a significantly higher rate than it etches the layers of the sacrificial layer 224. In some embodiments, selective dry etching or wet etching processes can be used. In some embodiments, when the sacrificial layer 224 is silicon (Si) and the channel layer 226 is silicon germanium (SiGe), a wet etchant can be used to selectively remove the silicon germanium layers. The wet etchant can be, for example, but not limited to, aqueous carboxylic acid / nitric acid / HF solutions and aqueous citric acid / nitric acid / HF solutions. Removing the channel layer 226 leaves a gap 228 between the sacrificial layers 224. The gap 228 between the sacrificial layers 224 has a thickness of about 3 nm to about 20 nm. The remaining sacrificial layers 224 form a vertical array of channel nanowires 240, which are coupled to source / drain regions 232, 234. The channel nanowires 240 travel parallel to the top surface 202 of the substrate 200 and are aligned with each other to form a single row of channel nanowires 240. The formation of the source region 232 and the drain region 234 and the optional lateral etch stop layer advantageously provide self-alignment and structural integrity in the formation of the channel structure.

[0039] like Figure 2F and Figures 3A to 3B As shown, in operation 108, the device undergoes in-situ pre-cleaning to remove any oxides on the gate. Pre-cleaning removes native oxides present on the surface of the gate. The pre-cleaning process may include a dry etching process, a wet etching process, or a combination of both.

[0040] In such implementations, the dry etching process may include conventional plasma etching or remote plasma-assisted dry etching processes, such as SiCoNi available from Applied Materials, Inc., Santa Clara, California. TM Etching process. In SiCoNi TM During the etching process, the device is exposed to H2, NF3, and / or NH3 plasma species, such as plasma-excited hydrogen and fluorine species. For example, in some embodiments, the device may be simultaneously exposed to H2, NF3, and NH3 plasmas. This can be achieved on SiCoNi... TM SiCoNi was carried out in the pre-cleaned chamber TM Etching process, SiCoNi TM The pre-cleaning chamber can be integrated into one of a variety of multiprocessing platforms, including those from Applied. of Dual ACP, GT and Platform. Wet etching processes may include hydrofluoric acid (HF) lasting processes, i.e., HF etching of the surface in a so-called "HF last" process to leave a hydrogen-terminated surface. Alternatively, any other liquid-based pre-epitaxial pre-cleaning process may be used. In some embodiments, the process includes sublimation etching to remove native oxides. Etching processes may be plasma-based or thermal-based. Plasma processes may be any suitable plasma (e.g., conductively coupled plasma, inductively coupled plasma, microwave plasma).

[0041] Please see Figure 3A and Figure 3B The inner spacer 210 may contain different materials. In some embodiments, the inner spacer 210b located between two adjacent nanosheet sacrificial layers 224 may contain silicon nitride (SiN). In other embodiments, the inner space 210a located on the top surface of the nanosheet semiconductor layer 224 may contain a low-k material different from the inner spacer 210b.

[0042] Please see Figure 2F and Figures 3C to 3D In operation 110, an oxide layer 250 is formed on the sacrificial layer 224. In one or more embodiments, the oxide layer 250 is formed by radical plasma oxidation (RPO) in an atmosphere of hydrogen (H2) and oxygen (O2) at ambient pressure, at a temperature ranging from about 700°C to about 900°C. The oxide layer 250 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the oxide layer 250 comprises silicon oxide (SiO2). x ). Figure 3DThis is a schematic diagram illustrating how the oxide layer 250 is grown on the sacrificial layer 224. In one or more embodiments, the oxide layer 250 is conformally grown (or formed) on the surface of the sacrificial layer 224. Because the sacrificial layer 224 is directly oxidized, the oxide layer 250 is dense. Oxidation consumes the sacrificial layer 224 (e.g., silicon (Si)) nanosheets, ensuring more space (e.g., distance, width) between the nanosheets of the sacrificial layer 224, thereby promoting downstream integration window (i.e., multi-threshold voltage (Vt)). In one or more embodiments, the sacrificial layer 224 comprises silicon (Si), and the oxide layer 250 comprises silicon oxide (SiO2). x ), and silicon dioxide (SiO) x The ratio of oxide to silicon (Si) is approximately 3:1. In some embodiments, the oxide layer 250 has an oxide layer thickness t. O Furthermore, the sacrificial layer 224 has a semiconductor material layer thickness t S Furthermore, the ratio of oxide layer thickness to semiconductor material layer thickness is 3:1.

[0043] In addition to oxidizing the sacrificial layer 224, operation 112 also partially oxidizes the spacer 210, thereby reducing the dielectric constant, k-value, of the spacer 210.

[0044] In one or more embodiments, operation 114 of method 100 represents one or more post-oxidation processing operations. The one or more post-oxidation processing operations can be any process known to those skilled in the art for completing hGAA devices. See also Figures 3E to 3G In some embodiments, a high-k dielectric 252 is formed on the oxide layer 250. The high-k dielectric 252 can be any suitable high-k dielectric material deposited using any suitable deposition technique known to those skilled in the art. In some embodiments, the high-k dielectric 252 comprises hafnium oxide. In some embodiments, a conductive material 254, such as titanium nitride (TiN), tungsten (W), cobalt (Co), or aluminum (Al), is deposited on the high-k dielectric 252. Any suitable deposition process (e.g., but not limited to atomic layer deposition (ALD)) can be used to form the conductive material 254 to ensure the formation of a layer with a uniform thickness around each sacrificial layer 224.

[0045] In some embodiments, a gate electrode 256 is formed on a substrate 200 and surrounding a conductive material 254. The gate electrode 256 can be formed from any suitable gate electrode material known in the art. The gate electrode material 256 is deposited using any suitable deposition process such as atomic layer deposition (ALD) to ensure that the gate electrode 256 is formed around and between the respective sacrificial layers 224.

[0046] According to embodiments of this disclosure, the resulting device formed using the methods described herein is a horizontal all-around gate (hGAA) device. Some embodiments of this disclosure relate to a horizontal all-around gate device comprising an RPO oxide layer 250 surrounding a sacrificial layer 224 as a nanowire or nano-slab in a channel between a source region and a drain region.

[0047] One or more embodiments of this disclosure relate to a method of forming a semiconductor device. In one or more embodiments, the method of forming a semiconductor device includes the steps of: selectively etching a superlattice structure comprising a plurality of semiconductor material layers and corresponding plurality of release layers arranged in a plurality of stacked pairs to remove each of the semiconductor material layers or each of the release layers to form a plurality of voids in the superlattice structure and the plurality of semiconductor material layers extending between a source region and a drain region; and oxidizing the plurality of semiconductor material layers to form an oxidized semiconductor material layer.

[0048] Additional implementations of this disclosure relate to, for example... Figure 4 The processing tool 300 shown is used to form a GAA device and is used in the methods described herein. Various multi-processing platforms can be used, including those from Applied... of Dual ACP, GT and The platform also has other processing systems. Please see [link / reference]. Figure 4 The clustering tool 300 includes at least one central transfer station 314 having multiple sides. A robot 316 is disposed within the central transfer station 314 and configured to move robot blades and wafers to each of the multiple sides.

[0049] Typically, clustering tools are modular systems comprising multiple chambers performing various functions, including substrate centering and orientation, degassing, annealing, deposition, and / or etching. According to one or more embodiments, a clustering tool includes at least a first chamber and a central transfer chamber. The central transfer chamber houses a robot that can transfer substrates between processing chambers and a loading-locking chamber. The transfer chamber is typically maintained under vacuum conditions and provides an intermediate stage for transferring substrates from one chamber to another, and / or to a loading-locking chamber located at the front end of the clustering tool. However, the actual arrangement and combination of chambers can be varied to perform specific steps of the processes described herein. Other processing chambers that can be used include, but are not limited to, circulating layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, thermal treatment (such as RTP), plasma nitriding, degassing, orientation, hydroxylation, and other substrate processes. By performing the process in a chamber on a cluster tool, surface contamination of the substrate by atmospheric impurities can be avoided without the need for oxidation before depositing subsequent films.

[0050] Please see Figure 4 The cluster tool 300 includes multiple processing chambers 308, 310, and 312, also referred to as processing stations, connected to a central transfer station. Each processing chamber provides an independent processing area isolated from adjacent processing stations. The processing chambers can be any suitable chamber, including but not limited to: pre-cleaning chambers, deposition chambers, annealing chambers, etching chambers, selective etching chambers, etc. The specific arrangement of the processing chambers and components may vary depending on the cluster tool and should not be considered as limiting the scope of this disclosure.

[0051] In some embodiments, the clustering tool 300 includes an isotropic etching chamber for selectively etching / trimming the sacrificial layer 224. In some embodiments, the isotropic etching chamber comprises one or more fluorine-based dry etching chambers. In some embodiments, the clustering tool 300 includes a pre-cleaning chamber connected to a central transport station.

[0052] exist Figure 4 In the illustrated embodiment, the factory interface 318 is connected to the front side of the cluster tool 300. The factory interface 318 includes a chamber 302 for loading and unloading on the front side 319 of the factory interface 318.

[0053] The size and shape of the loading chamber and unloading chamber 302 can be varied, for example, depending on the substrate to be processed in the clustering tool 300. In the illustrated embodiment, the dimensions of the loading chamber and unloading chamber 302 are set to hold a wafer cassette in which multiple wafers are disposed.

[0054] Robot 304 is located within factory interface 318 and can move between loading and unloading chambers 302. Robot 304 can transfer wafers from cassettes in loading chamber 302 to loading locking chamber 320 via factory interface 318. Robot 304 can also transfer wafers from loading locking chamber 320 to unloading chamber 302 via factory interface 318.

[0055] In some embodiments, robot 316 is a multi-armed robot capable of moving more than one wafer at a time independently. Robot 316 is configured to move wafers between chambers surrounding transfer chamber 314. Each wafer is mounted on a wafer transport blade located remotely to the first robotic mechanism.

[0056] The system controller 357 communicates with the robot 316 and the multiple processing chambers 308, 310, and 312. The system controller 357 can be any suitable component that controls the processing chambers and the robot. For example, the system controller 357 can be a computer including a central processing unit (CPU) 392, a memory 394, input / output 396, suitable circuitry 398, and storage.

[0057] Typically, the process can be stored as a software routine in the memory of system controller 357, which, when executed by a processor, causes the processing chamber to perform the process of this disclosure. The software routine can also be stored and / or executed by a remote second processor (not shown) located in processor-controlled hardware. Some or all of the methods of this disclosure can also be executed in hardware. Thus, the process can be implemented as software and executed using a computer system, implemented as hardware (e.g., an application-specific integrated circuit or other type of hardware implementation), or implemented as a combination of software and hardware. When executed by a processor, the software routine transforms a general-purpose computer into a dedicated computer (controller) that controls the operation of the processing chamber.

[0058] In some embodiments, the system controller 357 is configured to control the deposition of oxide layer 250 on sacrificial layer 224 and spacer 210.

[0059] In one or more embodiments, a processing tool includes: a central transport station including a robot configured to move a wafer; a plurality of processing stations connected to the central transport station and providing processing areas separated from processing areas of adjacent processing stations, the plurality of processing stations including: a deposition chamber, a plasma chamber, a hardening chamber, and an etching chamber; and a controller connected to the central transport station and the plurality of processing stations, the controller being configured to initiate the robot to move the wafer between the processing stations and to control the processes occurring in each processing station.

[0060] Throughout this specification, references to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, phrases appearing in various places throughout this specification, such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment," do not necessarily refer to the same embodiment of this disclosure. Furthermore, in one or more embodiments, specific features, structures, materials, or characteristics can be combined in any manner.

[0061] While the disclosure herein has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of this disclosure. Those skilled in the art will recognize that various modifications and variations can be made to the methods and apparatus of this disclosure without departing from the spirit and scope of this disclosure. Therefore, this disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a semiconductor device, comprising the following steps: A superlattice structure comprising multiple first layers and corresponding multiple second layers arranged in multiple stacked pairs is selectively etched to remove each of the second layers, thereby forming multiple voids in the superlattice structure. The multiple first layers extend between source and drain regions, and each of the multiple first layers is made of silicon oxide (SiO₂). x Internal spacers separate the spacers; Pre-clean the multiple first layers and silicon oxide (SiO2) x Internal spacers are used to remove native oxides and / or residues; and An oxide layer is conformally formed on the plurality of first layers, and through the plurality of first layers and the silicon oxide (SiO) x Radical plasma oxidation (RPO) of the internal spacer to oxidize the silicon oxide (SiO2) x The internal spacer is converted into a low-k dielectric internal spacer, and the radical plasma oxidation occurs at a temperature ranging from 700 °C to 900 °C in an atmosphere of hydrogen (H2) and oxygen (O2) under ambient pressure. The method described herein is performed in a processing chamber without disrupting the vacuum.

2. The method of claim 1, further comprising the steps of: forming the source region and the drain region, wherein the source region is adjacent to a first end of the superlattice structure and the drain region is adjacent to a second opposite end of the superlattice structure.

3. The method of claim 1, further comprising the step of: forming the superlattice structure on the top surface of the substrate.

4. The method of claim 1, wherein the semiconductor device comprises a horizontally wrapped gate device.

5. The method of claim 1, wherein the first layer comprises silicon (Si) and the second layer comprises silicon germanium (SiGe).

6. The method of claim 5, wherein selectively etching the superlattice structure comprises the step of: etching the silicon-germanium (SiGe) second layer and leaving the silicon (Si) first layer.

7. The method of claim 5, wherein the oxide layer comprises silicon oxide (SiO2). x ).

8. The method of claim 1, wherein the thickness of the first layer and the second layer is each from 3 nm to 20 nm.

9. The method of claim 1, further comprising the following steps: A high-k dielectric layer is formed on the oxide layer; and A conductive layer is formed on the high-k dielectric layer.

10. The method of claim 9, wherein the high-k dielectric layer comprises hafnium oxide, and the conductive layer comprises one or more of the following: titanium nitride (TiN), tungsten (W), cobalt (Co), and aluminum (Al).

11. A non-transitory computer-readable medium having instructions stored on the non-transitory computer-readable medium, which, when executed, cause the formation of a semiconductor device, the method comprising the steps of: A superlattice structure comprising multiple first layers and corresponding multiple second layers arranged in multiple stacked pairs is selectively etched to remove each of the second layers, thereby forming multiple voids in the superlattice structure. The multiple first layers extend between source and drain regions, and each of the multiple first layers is made of silicon oxide (SiO₂). x Internal spacers separate the spacers; Pre-clean the plurality of first layers and the silicon oxide (SiO2). x Internal spacers are used to remove native oxides and / or residues; and An oxide layer is conformally formed on the plurality of first layers, and the plurality of first layers and the silicon oxide (SiO) are used. x The free radical plasma oxidation of the internal spacer of the silicon oxide (SiO) x The internal spacer is converted into a low-k dielectric internal spacer, and the free radical plasma oxidation occurs at a temperature ranging from 700 °C to 900 °C in an atmosphere of hydrogen (H2) and oxygen (O2) under ambient pressure. The oxide layer has an oxide layer thickness, and the first layer has a first layer thickness, wherein the ratio of the oxide layer thickness to the first layer thickness is 3:

1. The method described herein is performed in a processing chamber without disrupting the vacuum.

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