Method for improving hardware fault response time of new energy vehicle driver using cpld

Abstract

The application relates to a method for improving the hardware fault response time of a new energy automobile driver by using a CPLD, and relates to the technical field of new energy automobile drivers, and is used for solving the technical problem that the existing new energy automobile driver cannot deal with emergency conditions in time. In the method for improving the hardware fault response time of the new energy automobile driver by using the CPLD, a CPLD is added to achieve timely processing of hardware faults, and when the protection strategy is upgraded and optimized, the hardware circuit only needs to be modified, and the internal program only needs to be modified; the CPLD is a single device, so when the failure is calculated, the CPLD can be regarded as a whole, the failure rate of the hardware circuit is reduced, and the stability of the whole circuit is improved; the state machine in the CPLD can quickly respond to the fault, the spi slave protocol in the internal CPLD and the register for communication can control and operate the CPLD through the protocol.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of new energy vehicle drive, and particularly relates to a method for improving hardware fault response time of new energy vehicle drive by using CPLD. BACKGROUND

[0002] With the rise of the new energy vehicle market, higher requirements are put forward for the safety of new energy vehicles. High voltage, high power and large torque can bring better experience to the driver, but at the same time, risks are also introduced, so the safety of motor control is particularly important. Since high voltage acts on the motor, torque output is on the motor, in order to ensure safety during driving, some function safety related protection needs to be carried out on the control of the motor.

[0003] At present, the key hardware faults of motor control of new energy vehicles on the market are usually detected and handled by using MCU external interrupt pins in cooperation with externally built logic circuits. However, the existing technology directly detects and handles by using MCU, which mainly uses MCU external interrupt pins in cooperation with some logic circuits. When a certain index is out of limit, a high or low level is generated to trigger an interrupt, at which time the MCU can perform some processing in the interrupt service function. Such design has the following shortcomings:

[0004] (1) The logic circuit built by discrete components increases the number of electronic devices used, thereby increasing the risk of circuit failure;

[0005] (2) Using MCU to handle emergency situations may have a certain delay, because the CPU in MCU works in series, and only after the tasks with higher priority are handled, the emergency situation can be handled;

[0006] (3) The existing method cannot monitor the PWM sent by MCU;

[0007] (4) The later upgrade and optimization of this design requires simultaneous adjustment of hardware and software, which will increase the development cycle. SUMMARY

[0008] The purpose of the present application is to provide a method for improving the hardware fault response time of new energy vehicle drive by using CPLD, which solves the technical problem that the new energy vehicle drive in the prior art cannot handle emergency situations in time; in addition, it can also make hardware level fault diagnosis for the control system.

[0009] To achieve the above purpose, the present application adopts the following technical scheme:

[0010] A method for improving the hardware fault response time of new energy vehicle drive by using CPLD, comprising the following steps:

[0011] The CPLD loads a user program and performs initialization operation on the internal registers and IOs of the CPLD first, and then performs reset operation if a reset signal is monitored; when it is detected that the esr0 is high, it is indicated that the MCU has been initialized successfully, and the state machine in the CPLD starts to run;

[0012] The whole system starts to run in parallel from the power-on of the CPLD, and the state of the whole system is determined by detecting the state of each IO; when an overvoltage or overcurrent signal occurs, the PWM is clamped in the first time, and the corresponding fault is uploaded to the MCU;

[0013] The CPLD is internally designed with a finite state machine, which can quickly respond to changes in external actions, and through the judgment of the state machine, the output can be executed in the specified state;

[0014] The CPLD is internally designed with the protocol of the SPI slave, which can enable the SPI master to access and modify the state in the CPLD through the standard SPI protocol; and the CPLD is abstracted as a register by using the internal logic resources of the CPLD, and the host can read and write the specific register through the SPI protocol and the corresponding address.

[0015] The CPLD includes a state module, an error module, a drive module, a pwm&asc module, an SPI module, and a system module, and is connected through defined signals; the key current and voltage hardware signals on the circuit are fed back to the internal modules through the IO pins, and the signals are processed and judged by the internal sub-modules and a certain reaction is made, and the running state in the CPLD is fed back to the MCU, facilitating the monitoring and positioning of the fault by the MCU;

[0016] The state module is a frequency divider, which outputs a 25kHz square wave, and the MCU judges whether the CPLD works normally by detecting the square wave signal;

[0017] The error module filters and latches the overcurrent and overvoltage signals, and can also clear the latched fault signals;

[0018] The drive module is used for processing the input and output signals of the drive chip;

[0019] The pwm&asc module sets the pwm dead time protection, and clamps the PWM when a fault is detected;

[0020] The SPI module is the implementation of the slave protocol and is used for read and write operation of the CPLD register.

[0021] The system module is used for jump of the state machine, and the sub-module resets the processing of the err_rest signal.

[0022] Specifically, the cpld is used for bridging between the mcu and the driving module, and the overvoltage and overcurrent fault signals are directly input into the cpld, so that the pwm wave is blocked and the action of the asc is performed in a very short time after the fault occurs, and the loss caused by the fault is minimized.

[0023] Compared with the prior art, the method for improving the hardware fault response time of the new energy automobile driver by using the cpld has the following advantages:

[0024] In the method for improving the hardware fault response time of the new energy automobile driver by using the cpld provided by the application, the cpld is added to achieve timely processing of hardware faults, and the hardware circuit does not need to be adjusted when the protection strategy is upgraded and optimized, but only needs to be modified internally; the cpld is a separate device, so when the failure is calculated, the cpld can be regarded as a whole, thereby reducing the failure rate of the hardware circuit and effectively improving the stability of the entire circuit; in other words, in the present application, a state machine is designed inside the cpld, which can quickly respond to faults and also feedback the state to the mcu; and the spi slave protocol and the register for communication are designed inside the cpld, the spi master can control and operate the cpld through the protocol, and also feedback the internal state to the mcu. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 The flowchart of the method for improving the hardware fault response time of the new energy automobile driver by using the cpld provided by the embodiment of the application is shown in the figure.

[0026] Figure 2 The structure diagram of the cpld in the method for improving the hardware fault response time of the new energy automobile driver by using the cpld provided by the embodiment of the application is shown in the figure.

[0027] Figure 3 The function framework diagram of the method for improving the hardware fault response time of the new energy automobile driver by using the cpld provided by the embodiment of the application is shown in the figure. DETAILED DESCRIPTION

[0028] It needs to be supplemented here that the cpld refers to complex programmable logic device, the mcu refers to micro control unit, the asc refers to active short circuit, the ota refers to over-the-air technology, the state machine refers to state register and combination logic circuit, which can be transferred according to the control signal in the pre-set state, and it is the control center of coordinating the action of related signals and completing specific operation.

[0029] For the convenience of understanding, the method for improving the hardware fault response time of a new energy vehicle driver using a cpld provided by the embodiment of the application is described in detail below in combination with the drawings of the specification.

[0030] The embodiment of the application provides a method for improving the hardware fault response time of a new energy vehicle driver using a cpld, as shown in the figure, comprising the following steps: Figure 1

[0031] The cpld is powered on to load a user program and perform initialization operation on the registers and IO in the cpld first, and then if a reset signal is monitored, the reset operation is performed, and when it is detected that esr0 is high, it indicates that the mcu has been successfully initialized, and the state machine in the cpld starts to run;

[0032] The whole system starts to run in parallel from the power-on in the cpld, the state of the whole system is judged by detecting the state of each IO, and when the overvoltage or overcurrent signal occurs, the pwm is clamped in the first time, and the response fault is uploaded to the mcu;

[0033] In order to better monitor the internal state of the cpld, a finite state machine is designed in the cpld, which can quickly respond to the change of external action, and through the judgment of the state machine, the output can be executed in the specified state;

[0034] Since the mcu and the cpld IO are limited, the use of IO interaction is very wasteful of resources, therefore, the protocol of spi slave is designed in the cpld, which can enable the spi master to access and modify the internal state of the cpld through the standard spi protocol, and the internal logic resource of the cpld is used to abstract the internal cpld as a register (in table 1), and the host can read and write the specific register through the spi protocol and the corresponding address.

[0035] Table 1: self-defined register in cpld

[0036]

[0037]

[0038] ​Compared with existing technologies, the method for improving the hardware fault response time of new energy vehicle drive systems using CPLD as described in this embodiment of the invention has the following advantages:

[0039] The method for improving the hardware fault response time of a new energy vehicle driver using a CPLD provided in this embodiment of the invention achieves timely handling of hardware faults by adding a CPLD. Furthermore, when upgrading and optimizing the protection strategy, no hardware circuit adjustments are required; only the internal program needs to be modified. Since the CPLD is a separate device, it can be considered as a whole when calculating failures, thereby reducing the failure rate of the hardware circuit and effectively improving the overall stability of the circuit. In other words, in this application, a state machine is designed inside the CPLD, enabling rapid response to faults and feedback of the state to the MCU. Additionally, the CPLD incorporates an SPI slave protocol and registers for communication, allowing the SPI master to control the CPLD via the protocol and also feed back its internal state to the MCU.

[0040] Among them, such as Figure 2 As shown, the above CPLD includes: state module, error module, drive module, PWM & ASC module, SPI module, and system module, which are connected through defined signals. The key current and voltage hardware signals on the circuit are fed back to each module through IO pins. The internal sub-modules process and judge the signals and make certain responses. At the same time, the internal running status of the CPLD is fed back to the MCU, which facilitates the MCU's monitoring and location of faults. In other words, each function is abstracted into a functional module, which facilitates the sorting of internal logic and subsequent optimization and upgrades.

[0041] The state module is a frequency divider that outputs a 25kHz square wave. The MCU detects this square wave signal to determine whether the CPLD is working properly. The error module filters and latches overcurrent and overvoltage signals, and can also clear latched fault signals. The drive module is used to process the input and output signals of the driver chip. The PWM & ASC module sets PWM dead time protection and blocks the signal when a fault is detected. The SPI module implements the slave protocol and is used for reading and writing CPLD registers. The system module is used for state machine transitions and the processing of the err_rest signal in the submodule reset.

[0042] Specifically, such as Figure 3 As shown, the MCU and the driver module are bridged using CPLD, and overvoltage and overcurrent fault signals are also directly fed into CPLD to block the PWM wave and execute ASC within a very short period of time after the fault occurs, thereby minimizing the losses caused by the fault.

[0043] To sum up, the method for improving the hardware fault response time of a new energy vehicle driver using a CPLD provided by the embodiment of the application mainly has the following advantages:

[0044] I. The use of independent devices CPLD reduces the use of discrete devices resistance and capacitance, diodes, transistors and comparators, simplifies circuit design, reduces the failure points of hardware circuit, and improves the stability of hardware circuit;

[0045] II. The code written by the CPLD is downloaded and formed into a hardware circuit inside the CPLD after compilation. The processing of logical relationships is completely parallel, without the operations of CPU instruction fetching, decoding and instruction execution. The time consumed is only the delay of the resistance and capacitance on the hardware circuit. Therefore, compared with MCU processing, the CPLD has higher real-time performance;

[0046] III. The PWM output by the MCU is detected by the CPLD and output to the execution end. The effectiveness of the PWM can be monitored inside the CPLD. When an exception occurs, the output of the PWM can be stopped quickly;

[0047] IV. The adjustment of the hardware scheme is the most wasteful development cycle. According to the needs of customers, when the functional safety strategy changes, the hardware scheme needs to be adjusted. The use of discrete devices will cause the change of the circuit board, while the use of CPLD can not change the circuit board, and directly modify the CPLD firmware. With the development of the Internet of Things, future controllers will be integrated with OTA. The CPLD can leave a firmware upgrade interface and modify the firmware inside the CPLD remotely through the OTA technology, so as to facilitate the timely repair of product safety hazards.

[0048] The above is only a specific embodiment of the application, but the protection scope of the application is not limited thereto. Any skilled person in the art can easily think of changes or replacements within the technical range disclosed by the application, which should be covered within the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims.

Claims

1. A method for improving the hardware fault response time of a new energy vehicle driver using a cpld, characterized by, It comprises the following steps: The cpld is powered on to load user program and initialize the registers and IOs inside the cpld, and then if the reset signal is monitored, the reset operation is performed, when the esr0 is detected as high, it indicates that the mcu has been initialized successfully, and the state machine inside the cpld starts to run; The whole system starts to run in parallel from the power-on, the state of the whole system is determined by detecting the state of each IO, when the overvoltage or overcurrent signal occurs, the pwm is blocked in the first time, and the response fault is uploaded to the mcu; The cpld is designed with a finite state machine, which can quickly respond to the changes of external actions, and through the judgment of the state machine, the output can be executed in the specified state; The cpld is designed with spi slave protocol, which can enable the spi master to access and modify the state inside the cpld through the standard spi protocol; and the cpld is abstracted as a register by using the logic resources inside the cpld, and the host can read and write the specific register through the spi protocol and the corresponding address.

2. The method of claim 1, wherein, The cpld comprises a state module, an error module, a drive module, a pwm&asc module, a spi module, and a system module, and is connected through defined signals, the key current and voltage hardware signals on the circuit are fed back to the internal modules through the IO pins, the signals are processed and judged by the internal sub-modules and a certain reaction is made, and the running state inside the cpld is fed back to the mcu, which is convenient for the mcu to monitor and locate the fault; The state module is a frequency divider, which outputs a 25khz square wave, and the mcu detects the square wave signal to determine whether the cpld is working normally; The error module filters and latches the overcurrent and overvoltage signals, and can also clear the latched fault signals; The drive module is used to process the input and output signals of the drive chip; The pwm&asc module sets the pwm dead time protection, and detects the fault to block the wave; The spi module is the implementation of the slave protocol, and is used for reading and writing the cpld register; The system module is used for state machine jumping and reset err_rest signal processing.

3. The method of claim 1 or 2, wherein, The cpld is used to bridge between the mcu and the drive module, and the overvoltage and overcurrent fault signals are directly entered into the cpld, so that the pwm wave can be blocked and the asc action can be executed in a very short time after the fault occurs, and the loss caused by the fault can be minimized.

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