Method for sizing power switch transistor and system therefor

Abstract

This invention provides a method for setting the size of a power switching transistor. A first load current acquisition step acquires a first load current of a first logic circuit. A second load current acquisition step acquires a second load current of a second logic circuit. A voltage drop limit calculation step calculates a voltage drop limit based on a speed ratio value, the first load current, and the second load current. A reference supply current calculation step calculates a reference supply current based on the voltage drop limit. A simulated supply current calculation step calculates a simulated supply current based on the reference supply current, the voltage drop limit, and the line voltage value. A size setting step compares the first load current and the simulated supply current to calculate size parameters, and sets the size of the power switching transistor based on the size parameters. This maintains a high response speed for the logic circuit.

Description

Technical Field

[0001] This invention relates to a method and system for setting the size of a power switching transistor, and more particularly to a method for setting the size of a power switching transistor using the load current of a logic circuit, while the logic circuit configuring the power switching transistor still maintains high-speed transmission. Background Technology

[0002] In recent years, with the increasing number of electronic circuit devices integrating semiconductor materials, the demand for low-power consumption technologies has also been increasing. One such low-power consumption technology is the configuration of multi-threshold CMOS (MTCMOS) in logic circuits. MTCMOS is an effective power switching control technology that reduces leakage current and power consumption of logic circuits while maintaining the required speed performance by appropriately alternating high-threshold and low-threshold transistors.

[0003] However, many MTCMOS gates used as logic gates are frequently overloaded, significantly impacting the speed of logic circuits. The main reason for the slowdown in overloaded logic gates is the large voltage drop at the drain-source terminals, which leads to a decrease in the gate-source voltage (Vgs). An effective way to address this issue is to configure the minimum MTCMOS size to match the load (i.e., the logic circuit).

[0004] In view of this, the public eagerly anticipates and has a system for setting the size of power switching transistors that can meet the speed requirements of logic circuits. This is also the goal and direction that relevant businesses must strive to develop and break through. Summary of the Invention

[0005] Therefore, the purpose of this invention is to provide a method and system for setting the size of a power switching transistor, which uses the load current of a logic circuit to calculate the size of the power switching transistor and ensures that the logic circuit can maintain high-speed transmission.

[0006] According to an embodiment of the present invention, a method for setting the size of a power switching transistor is provided, comprising a first load current acquisition step, a second load current acquisition step, a voltage drop limit calculation step, a reference supply current calculation step, an analog supply current calculation step, and a size setting step. The first load current acquisition step drives an arithmetic processing unit to acquire a first load current of a first logic circuit. The first logic circuit is connected to a power supply voltage via at least one power switching transistor and at least one power line to generate the first load current, and the at least one power line has at least one voltage value. The second load current acquisition step drives the arithmetic processing unit to acquire a second load current of a second logic circuit. The second logic circuit is connected to the power supply voltage to generate the second load current. The voltage drop limit calculation step drives the arithmetic processing unit to set a speed ratio value and store the speed ratio value in a storage unit. The arithmetic processing unit performs a voltage calculation program on the speed ratio value, the first load current, and the second load current to calculate a voltage drop limit between the at least one power switching transistor and the first logic circuit. The reference supply current calculation step drives the arithmetic processing unit to calculate a reference supply current of the at least one power switching transistor based on the voltage drop limit. The simulated supply current calculation step drives the arithmetic processing unit to perform a current calculation program on the reference supply current, the limiting voltage drop, and the aforementioned at least one line voltage value to calculate a simulated supply current for the aforementioned at least one power switching transistor. The sizing step drives the arithmetic processing unit to compare the first load current with the simulated supply current to calculate a sizing parameter, and then sets a sizing for the aforementioned at least one power switching transistor based on the sizing parameter. The voltage calculation program includes a speed ratio value, a first load current, a second load current, a supply voltage, a threshold voltage, and a voltage across the aforementioned at least one power line and the first logic circuit. The speed ratio value is denoted as S, and the first load current is denoted as... The second load current is expressed as The power supply voltage is expressed as The critical voltage is expressed as The terminal voltage is expressed as And it meets the following formula:

[0007]

[0008] In addition, the processing unit can limit the voltage drop based on the difference between the speed ratio limit terminal voltage and the power supply voltage.

[0009] The current calculation program includes the simulated supply current, the reference supply current, the limiting voltage drop, and at least one of the aforementioned line voltage values. The simulated supply current is expressed as... The reference supply current is expressed as The voltage drop limit is expressed as The aforementioned voltage value of at least one line is expressed as: And it meets the following formula:

[0010]

[0011] Therefore, the power switch transistor size setting method of the present invention sets a speed ratio value according to its own speed requirements, and calculates a limiting voltage drop by comparing a first logic circuit equipped with a power switch transistor and a second logic circuit directly connected to the power supply voltage based on the speed ratio value, thereby setting the size of the power switch transistor that can meet the speed ratio value, and ensuring that various logic circuits still maintain high-speed transmission.

[0012] Other embodiments of the aforementioned implementation are as follows: The structure of the aforementioned first logic circuit may be the same as the structure of the second logic circuit.

[0013] Other embodiments of the aforementioned implementation are as follows: The aforementioned first logic circuit may include multiple transistors, and the first load current acquisition step may connect the power supply voltage to a first power domain and a second power domain of the first logic circuit through the aforementioned at least one power switch transistor and the aforementioned at least one power line, so that the transistors in the first logic circuit operate in a saturation region and generate a first load current.

[0014] Other embodiments of the aforementioned implementation are as follows: The aforementioned second logic circuit includes a plurality of transistors, and the second load current acquisition step can connect another power supply voltage to a first power supply domain and a second power supply domain of the second logic circuit, so that the transistors in the second logic circuit operate in a saturation region and generate a second load current.

[0015] Other embodiments of the aforementioned implementation are as follows: The aforementioned reference supply current calculation step may include a preset sub-step and a calculation sub-step. The preset sub-step drives the arithmetic processing unit to preset the limiting voltage drop to a drain-source voltage of the aforementioned at least one power switching transistor, causing the aforementioned at least one power switching transistor to operate in a linear region. The calculation sub-step drives the arithmetic processing unit to calculate the reference supply current based on the drain-source voltage.

[0016] Other embodiments of the aforementioned implementation are as follows: the aforementioned at least one power switching transistor may be a multi-threshold CMOS (MTCMOS).

[0017] According to another embodiment of the present invention, a power switching transistor sizing system is provided, comprising a power supply voltage, at least one power switching transistor, at least one power line, a first logic circuit, a second logic circuit, a storage unit, and an arithmetic processing unit. The at least one power switching transistor is electrically connected to the power supply voltage. The at least one power line is electrically connected to the at least one power switching transistor and has at least one line voltage value. The first logic circuit is electrically connected to the at least one power line and generates a first load current. The second logic circuit is electrically connected to the power supply voltage and generates a second load current. The storage unit is used to access the at least one line voltage value, a voltage calculation program, and a current calculation program. The arithmetic processing unit is signal-connected to the storage unit and configured to implement a first load current acquisition step, a second load current acquisition step, a voltage drop limit calculation step, a reference supply current calculation step, an analog supply current calculation step, and a sizing step. Specifically, the first load current acquisition step acquires the first load current. The second load current acquisition step acquires the second load current. The voltage drop limiting calculation step sets a speed ratio value and stores it in a storage unit. Then, a voltage calculation program is performed on the speed ratio value, the first load current, and the second load current to calculate a limiting voltage drop between the at least one power switching transistor and the first logic circuit. The reference supply current calculation step calculates a reference supply current for the at least one power switching transistor based on the limiting voltage drop. The analog supply current calculation step performs a current calculation program on the reference supply current, the limiting voltage drop, and the voltage value of the at least one power line to calculate an analog supply current for the at least one power switching transistor. The size setting step compares the first load current and the analog supply current to calculate a size parameter, and then sets a size for the at least one power switching transistor based on the size parameter. The voltage calculation program includes the speed ratio value, the first load current, the second load current, the supply voltage, a threshold voltage, and the voltage at one end between the at least one power line and the first logic circuit. The speed ratio value is denoted as S, and the first load current is denoted as... The second load current is expressed as The power supply voltage is expressed as The critical voltage is expressed as The terminal voltage is expressed as And it meets the following formula:

[0018]

[0019] In addition, the processing unit can limit the voltage drop based on the difference between the speed ratio limit terminal voltage and the power supply voltage.

[0020] The current calculation program includes the simulated supply current, the reference supply current, the limiting voltage drop, and at least one of the aforementioned line voltage values. The simulated supply current is expressed as... The reference supply current is expressed as The voltage drop limit is expressed as The aforementioned voltage value of at least one line is expressed as: And it meets the following formula:

[0021]

[0022] Therefore, the power switch transistor size setting system of the present invention uses the arithmetic processing unit to obtain the load current under different load conditions to calculate the limiting voltage drop, and sets the size of the power switch transistor that can meet the speed ratio value, while ensuring that various logic circuits still maintain high-speed transmission.

[0023] Other embodiments of the aforementioned implementation are as follows: The structure of the aforementioned first logic circuit may be the same as the structure of the second logic circuit.

[0024] Other embodiments of the aforementioned implementation are as follows: The aforementioned first logic circuit may include multiple transistors, and the first load current acquisition step connects the power supply voltage to a first power domain and a second power domain of the first logic circuit through the aforementioned at least one power switching transistor and the aforementioned at least one power line, so that the transistors in the first logic circuit operate in a saturation region and generate a first load current.

[0025] Other embodiments of the aforementioned implementation are as follows: The aforementioned second logic circuit may include multiple transistors, and the second load current acquisition step connects another power supply voltage to a first power supply domain and a second power supply domain of the second logic circuit, so that the transistors in the second logic circuit operate in a saturation region and generate a second load current.

[0026] Other embodiments of the aforementioned implementation are as follows: The aforementioned reference supply current calculation step may include a preset sub-step and a calculation sub-step. The preset sub-step drives the arithmetic processing unit to preset the limiting voltage drop to a drain-source voltage of the aforementioned at least one power switching transistor, causing the aforementioned at least one power switching transistor to operate in a linear region. The calculation sub-step drives the arithmetic processing unit to calculate the reference supply current based on the drain-source voltage.

[0027] Other embodiments of the aforementioned implementation are as follows: the aforementioned at least one power switching transistor may be a multi-threshold CMOS (MTCMOS). Attached Figure Description

[0028] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the accompanying drawings are described below:

[0029] Figure 1A flowchart illustrating a method for setting the size of a power switching transistor according to a first embodiment of the present invention is shown.

[0030] Figure 2 Show Figure 1 A schematic diagram of the first logic circuit, power switching transistor, and power line in the first load current acquisition step of the method for setting the size of the power switching transistor.

[0031] Figure 3 Show Figure 1 A schematic diagram of the second logic circuit in the second load current acquisition step of the method for setting the size of the power switching transistor; and

[0032] Figure 4 A schematic diagram of a power switch transistor size setting system according to a second embodiment of the present invention is shown.

[0033] Explanation of reference numerals in the attached figures:

[0034] 100: Method for setting the size of power switching transistors

[0035] 110: First load current

[0036] 120: Second load current

[0037] 130: Speed ​​Proportion Value

[0038] 140: Limit voltage drop

[0039] 150: Reference supply current

[0040] 160: Simulated supply current

[0041] 170: Dimensions

[0042] 200: Power Switch Transistor Size Setting System

[0043] 260: Storage unit

[0044] 261: Line voltage value

[0045] 262: Voltage Calculation Program

[0046] 263: Current Calculation Program

[0047] 264: Transistor Parameters

[0048] 270: Processing Unit

[0049] S02: Steps for obtaining the first load current

[0050] S04: Steps for obtaining the second load current

[0051] S06: Steps for Calculating Voltage Drop Limitation

[0052] S08: Steps for calculating the reference supply current

[0053] S081: Preset Sub-step

[0054] S082: Operator Steps

[0055] S10: Simulated Supply Current Calculation Steps

[0056] S12: Size Setting Steps

[0057] LC1,240: First logic circuit

[0058] LC2,250: Second Logic Circuit

[0059] VDD,VSS,210: Power supply voltage

[0060] Isupply: Supply current

[0061] ENb: Inverting enable signal

[0062] EN: Enable signal

[0063] VMTH, VMTL: Terminal voltage

[0064] VMTHz0: First power domain

[0065] VMTLz0: Second power domain

[0066] Q1, Q2, 220: Power switching transistors

[0067] M1, M2, 230: Power cord Detailed Implementation

[0068] Several embodiments of the present invention will now be described with reference to the accompanying drawings. For clarity, many practical details will be set forth in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential. Furthermore, for the sake of simplicity in the drawings, some conventionally used structures and elements will be shown in a simple schematic manner; and repeated elements may be denoted by the same reference numerals.

[0069] Furthermore, in this document, when a component (or unit or module, etc.) is "connected / linked" to another component, it can mean that the component is directly connected / linked to the other component, or it can mean that the component is indirectly connected / linked to the other component, that is, there is another component between the component and the other component. Only when it is explicitly stated that a component is "directly connected / linked" to another component does it indicate that there is no other component between the component and the other component. The terms "first," "second," and "third" are only used to describe different components and do not limit the components themselves; therefore, "first component" can also be referred to as "second component." Moreover, the combinations of components / units / circuits in this document are not combinations generally known, conventional, or prior art in this field. Whether the component / unit / circuit itself is prior art cannot be used to determine whether its combination relationship is easily accomplished by a person skilled in the art.

[0070] Please see Figure 1 This illustrates a flowchart of a method 100 for setting the size of a power switching transistor according to a first embodiment of the present invention. Figure 1 As shown, the power switch transistor size setting method 100 includes a first load current acquisition step S02, a second load current acquisition step S04, a voltage drop limit calculation step S06, a reference supply current calculation step S08, an analog supply current calculation step S10, and a size setting step S12.

[0071] In the first load current acquisition step S02, an arithmetic processing unit acquires a first load current 110 of a first logic circuit, wherein the first logic circuit is connected to a power supply voltage via at least one power switching transistor and at least one power supply line to generate the first load current 110. Furthermore, the aforementioned at least one power supply line has at least one voltage value, which is stored in a memory cell.

[0072] In the second load current acquisition step S04, the driving arithmetic processing unit acquires a second load current 120 from a second logic circuit, wherein the second logic circuit is connected to the power supply voltage to generate the second load current 120.

[0073] In step S06, the arithmetic processing unit sets a speed ratio value 130 and stores the speed ratio value 130 in the storage unit. The arithmetic processing unit performs a voltage calculation program on the speed ratio value 130, the first load current 110, and the second load current 120 to calculate a limiting voltage drop 140 between the aforementioned at least one power switching transistor and the first logic circuit.

[0074] The reference supply current calculation step S08 drives the arithmetic processing unit to calculate a reference supply current 150 for the aforementioned at least one power switch transistor based on the limiting voltage drop 140.

[0075] The simulated supply current calculation step S10 drives the arithmetic processing unit to perform a current calculation program on the reference supply current 150, the limiting voltage drop 140 and the aforementioned at least one line voltage value, so as to calculate an simulated supply current 160 of the aforementioned at least one power switch transistor.

[0076] In the size setting step S12, the driving arithmetic processing unit compares the first load current 110 with the analog supply current 160 to calculate a size parameter 170, and then sets a size of the aforementioned at least one power switch transistor according to the size parameter 170.

[0077] In this way, users can set the speed ratio value 130 according to the speed requirements of the first logic circuit for different specifications, and calculate the size parameter 170 using the power switching transistor size setting method 100 of the present invention, and configure a power switching transistor of appropriate size for the first logic circuit, thereby minimizing area loss and standby power consumption. The following paragraphs will describe in detail the operation mechanism of the power switching transistor size setting method 100 of the present invention with reference to the accompanying drawings.

[0078] Please refer to the following: Figure 1 , Figure 2 and Figure 3 ,in Figure 2 Show Figure 1 A schematic diagram of the first logic circuit LC1, power switching transistors Q1 and Q2, and power lines M1 and M2 in the first load current acquisition step S02 of the power switching transistor size setting method 100; and Figure 3 Show Figure 1 This is a schematic diagram of the second logic circuit LC2 in the second load current acquisition step S04 of the power switch transistor size setting method 100. It should be noted that the structure of the first logic circuit LC1 in this embodiment is the same as the structure of the second logic circuit LC2; that is, the first logic circuit LC1 and the second logic circuit LC2 are the same logic circuit. In other words... Figure 3 The second logic circuit LC2 is Figure 2 Internal circuit diagram of the first logic circuit LC1.

[0079] like Figure 2 As shown, in the first load current acquisition step S02, a power supply voltage VDD is connected to a first power domain VMTHz0 of the first logic circuit LC1 via a power switching transistor Q1 and a power line M1, so that the transistors in the first logic circuit LC1 (i.e., the corresponding...) Figure 3The transistor in the second logic circuit LC2 operates in the saturation region and generates a first load current 110. Furthermore, the first load current acquisition step S02 also connects another power supply voltage VSS to a second power domain VMTLz0 of the first logic circuit LC1 via another power switching transistor Q2 and another power line M2, causing the aforementioned transistor to similarly operate in the saturation region and generate another first load current (not otherwise labeled). Generally, the power supply in a logic circuit can be divided into multiple independent blocks, called power domains. The first power domain VMTHz0 of this invention is the high-voltage power domain in the first logic circuit LC1; conversely, the second power domain VMTLz0 is the low-voltage power domain in the first logic circuit LC1.

[0080] In addition, in this embodiment, power switching transistors Q1 and Q2 can both be multi-threshold CMOS (MTCMOS). Specifically, power switching transistor Q1 is a PMOS transistor, and power switching transistor Q2 is an NMOS transistor. The gate of power switching transistor Q1 is electrically connected to an inverting enable signal ENb, which controls the switching of power switching transistor Q1. The drain of power switching transistor Q1 is electrically connected to the power supply voltage VDD. The voltage between the source of power switching transistor Q1 and power line M1 is denoted as VMTH. Similarly, the gate of power switching transistor Q2 is electrically connected to an enable signal EN, which controls the switching of power switching transistor Q2. The drain of power switching transistor Q2 is electrically connected to the power supply voltage VSS. The voltage between the source of power switching transistor Q2 and power line M2 is denoted as VMTL, where power lines M1 and M2 are made of the same wire and have the same line voltage value.

[0081] like Figure 3 As shown, the second logic circuit LC2 is a 23-stage ring oscillator, which consists of 23 inverters connected in series. In this embodiment, the second logic circuit LC2 includes a NAND gate and 22 inverters. The fan-out of the second logic circuit LC2 is 3, and each inverter in the second logic circuit LC2 may contain multiple transistors (not shown separately). Specifically, the second load current acquisition step S04 connects the power supply voltage VDD to a first power supply domain (i.e., the high-voltage power supply domain connected to the source terminal of each inverter) and a second power supply domain (i.e., the low-voltage power supply domain connected to the source terminal of each inverter) of the second logic circuit LC2, causing the transistors in the second logic circuit LC2 to operate in the saturation region and generate a second load current 120.

[0082] The response speed of the first logic circuit LC1 connected to the power switch transistor Q1 will be slower than the response speed of the second logic circuit LC2 without any power switch connected. This is because the first load current I10 is greater than the supply current Isuppli flowing through the power switch transistor Q1 (e.g., ...). Figure 2 When the power supply range is longer (i.e., the power line M1 is longer), the charging time of the first logic circuit LC1 will increase. The resistance of the power line M1 must be considered if the power supply range is longer. Specifically, this invention aims to ensure that the response speed of the first logic circuit LC1 is only slightly lower than that of the second logic circuit LC2. Therefore, the arithmetic processing unit can set a speed ratio value 130, and the voltage drop caused by the power line M1 can be limited by the speed ratio value 130 to maintain the high response speed of the power switching transistor Q1.

[0083] In the voltage drop limiting calculation step S06, the voltage calculation program may include a speed ratio value 130, a first load current 110, a second load current 120, a power supply voltage VDD, a critical voltage of the power switching transistor Q1, and the terminal voltage between the power line M1 and the first logic circuit LC1 (i.e., the voltage value of the first power domain VMTHz0). The speed ratio value 130 is represented by S, and the first load current 110 is represented by... The second load current of 120 is expressed as The power supply voltage VDD is represented as The critical voltage of the power switching transistor Q1 is expressed as: The terminal voltage between power line M1 and the first logic circuit LC1 is expressed as: And it conforms to the following formula (1):

[0084] (1).

[0085] In detail, since the transistors in the first logic circuit LC1 and the second logic circuit LC2 both operate in the saturation region, the first load current 110 and the second load current 120 both belong to the saturation region currents. The first load current 110 conforms to the following equation (2) according to the existing saturation region formula, and the second load current 120 conforms to the following equation (3) according to the existing saturation region formula:

[0086] (2);

[0087] (3).

[0088] Where K is a process transconductance parameter, which cancels out in equation (1). Furthermore, the terminal voltage between power line M1 and the first logic circuit LC1 conforms to the following equation (4):

[0089] (4).

[0090] in, Here is a resistance value for power line M1. Generally, when the load (not shown) connected to the back end of the first logic circuit LC1 is the same, the first load current 110 of the first logic circuit LC1 is inversely proportional to the charging time of the corresponding load. This invention defines a speed parameter corresponding to the first logic circuit LC1 that is proportional to the charging time, therefore the aforementioned speed parameter is inversely proportional to the first load current 110. Next, in equation (1), the arithmetic processing unit limits the difference between the terminal voltage between power line M1 and the first logic circuit LC1 and the power supply voltage VDD to a limit voltage drop 140 based on the speed ratio value 130.

[0091] For example, in this embodiment, the power supply voltage VDD is equal to 1.1 volts ( The threshold voltage of the power switching transistor Q1 is 0.25 volts. The speed ratio value 130 is set to 5%. The processing unit substitutes the above parameters into equation (1) to deduce that the terminal voltage between the power supply line M1 and the first logic circuit LC1 can only be less than the power supply voltage VDD by 21 millivolts. This 21 millivolts is the limit voltage drop of 140. In other embodiments, the user can set the speed ratio value according to the speed requirements of the first logic circuit corresponding to different specifications, and the present invention is not limited thereto.

[0092] Furthermore, the reference supply current calculation step S08 of the present invention may include a preset sub-step S081 and a calculation sub-step S082. The preset sub-step S081 drives the arithmetic processing unit to preset the limiting voltage drop 140 to a drain-source voltage of the power switching transistor Q1, causing the power switching transistor Q1 to operate in a linear region. The calculation sub-step S082 drives the arithmetic processing unit to calculate the reference supply current 150 based on the drain-source voltage of the power switching transistor Q1. Further, the supply current Isupply of the power switching transistor Q1 is in the linear region because the power supply voltage VDD minus the terminal voltage VMTH between the source terminal of the power switching transistor Q1 and the power line M1 will be less than the power supply voltage VDD minus the critical voltage of the power switching transistor Q1. If the length of power line M1 is very short and the resistance of power line M1 is negligible, the processing unit sets the limiting voltage drop of 140 (i.e., 21 millivolts) as the drain-source voltage of power switching transistor Q1, and substitutes the limiting voltage drop of 140 into the existing linear region formula, which satisfies the following equation (5):

[0093] (5).

[0094] The reference supply current is 150. It limits the voltage drop to 140 ( =21 mV), It is the gate-source voltage of the power switching transistor Q1. =VDD-VSS=1.1-0=1.1V), is the linear region carrier mobility, W is the channel width of power switching transistor Q1 (W=3.6μm), and L is the channel length of power switching transistor Q1 (L=0.08 μm). It is the unit capacitance of the gate oxide layer. It is the threshold voltage of the power switching transistor Q1. =0.25 V), where the carrier mobility in the linear region is... Compared with the unit capacitance of the gate oxide layer These parameters are determined by the transistor's manufacturing process. The processing unit substitutes these parameters into equation (5) to calculate the reference supply current, 150, which equals 20 microamperes. =20 μA). This reference supply current of 150 represents that, with the drain current of the power switching transistor Q1 being 20 microamps, the response speed of the first logic circuit LC1 will be less than 5% relative to the response speed of the second logic circuit LC2.

[0095] On the other hand, if the power supply range between the power switching transistor Q1 and the first logic circuit LC1 is far, then it is necessary to consider the resistance value of the power line M1 and calculate the voltage across the power line M1. In the analog supply current calculation step S10, the arithmetic processing unit performs a current calculation program on the reference supply current 150, the limiting voltage drop 140, and the line voltage value across the power line M1 to calculate the analog supply current 160 of the power switching transistor Q1.

[0096] Furthermore, the current calculation program can include an analog supply current of 160, a reference supply current of 150, a limiting voltage drop of 140, and the line voltage across power line M1. The analog supply current of 160 is expressed as... The reference supply current of 150 is expressed as The voltage drop limit of 140 is expressed as The line voltage across power line M1 is expressed as: And it conforms to the following formula (6):

[0097] (6).

[0098] in, , =0.5mA, =20 ohm (line length is 100 μm), =21mV, =20μA. The processing unit substitutes the above parameters into equation (6) to calculate the simulated supply current 160 ( =20 0.52381).

[0099] Continuing with the size setting step S12, the arithmetic processing unit compares the first load current 110 with the analog supply current 160 to calculate the size parameter 170, and then sets the size of the power switch transistor Q1 according to the size parameter 170. Specifically, the arithmetic processing unit divides the first load current 110 by the analog supply current 160 to generate the size parameter 170, and then multiplies the size parameter 170 by the channel length and channel width of the power switch transistor Q1 to calculate the size of the power switch transistor Q1, which conforms to the following equations (7) and (8):

[0100] (7);

[0101] (8).

[0102] in, The size parameter is 170. The first load current is 110. The analog supply current is 160 Ω, and the length of the power switching transistor Q1 is expressed as follows: The width dimension of the power switching transistor Q1 is expressed as follows: L is the channel length of power switching transistor Q1, and W is the channel width of power switching transistor Q1.

[0103] Table 1 below lists the dimensional parameters 170 of the present invention, corresponding to the line length and resistance value of different power lines M1 (i.e., different power supply ranges) and the first load current 110 of different first logic circuits LC1. It should be noted that Table 1 mainly addresses the case where the speed ratio 130 is 5%, and the present invention is not limited thereto.

[0104]

[0105] In Table 1 above, when the length of power line M1 is 10 μm and the first load current 110 is 840 μA, the user can configure the corresponding size parameter 170. =48) to set the size of the power switching transistor Q1, and so on. In this way, the user can use the power switching transistor size setting method 100 of the present invention to set the size of the power switching transistor Q1 that can meet the speed ratio value 130, and ensure that various logic circuits still maintain high-speed transmission.

[0106] Please refer to the following: Figures 1 to 4 ,in Figure 4 A schematic diagram of a power switch transistor sizing system 200 according to a second embodiment of the present invention is shown. Figure 4 As shown, the power switching transistor sizing system 200 includes a power supply voltage 210, a power switching transistor 220, a power line 230, a first logic circuit 240, a second logic circuit 250, a storage unit 260, and an arithmetic processing unit 270. The power switching transistor 220 is electrically connected to the power supply voltage 210. The power line 230 is electrically connected to the power switching transistor 220 and has a line voltage value 261. The first logic circuit 240 is electrically connected to the power line 230 and generates a first load current 110. The second logic circuit 250 is electrically connected to the power supply voltage 210 and generates a second load current 120, wherein the structure of the first logic circuit 240 is the same as the structure of the second logic circuit 250. The storage unit 260 is used to store the line voltage value 261, a voltage calculation program 262, a current calculation program 263, and transistor parameters 264 of the power switching transistor 220. The arithmetic processing unit 270 is signal-connected to the storage unit 260. Furthermore, the arithmetic processing unit 270 acquires the peak currents of the first load current 110 and the second load current 120, and configures them to implement the power switch transistor sizing method 100. The arithmetic processing unit 270 may be a digital signal processor (DSP), a microprocessor (MPU), a central processing unit (CPU), or other electronic processor, but the present invention is not limited thereto.

[0107] In this way, the power switch transistor size setting system 200 of the present invention uses the arithmetic processing unit 270 to calculate the limiting voltage drop 140 based on the first load current 110 and the second load current 120, and sets the size of the power switch transistor 220 that can meet the speed ratio value 130, and ensures that the first logic circuit 240 connected to the power switch transistor 220 still maintains high-speed transmission.

[0108] In summary, the present invention has the following advantages: First, it avoids configuring excessively large power switching transistors in logic circuits, thereby reducing circuit costs. Second, it ensures that logic circuits equipped with power switching transistors still have high-speed transmission capabilities. Third, it reduces the layout time for users regarding the size configuration of power switching transistors during product development, thereby accelerating the development process.

[0109] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A method for setting the size of a power switching transistor, characterized in that, Includes the following steps: A first load current acquisition step involves driving an arithmetic processing unit to acquire a first load current of a first logic circuit. The first logic circuit is connected to a power supply voltage via at least one power switching transistor and at least one power line to generate the first load current, and the at least one power line has at least one line voltage value. A second load current acquisition step involves driving the arithmetic processing unit to acquire a second load current of a second logic circuit, wherein the second logic circuit is connected to the power supply voltage to generate the second load current. A voltage drop limiting calculation step involves driving the arithmetic processing unit to set a speed ratio value and storing the speed ratio value in a storage unit. The arithmetic processing unit performs a voltage calculation program on the speed ratio value, the first load current, and the second load current to calculate a voltage drop limiting between the at least one power switching transistor and the first logic circuit. A reference supply current calculation step drives the arithmetic processing unit to calculate a reference supply current of the at least one power switching transistor based on the limiting voltage drop; A simulated supply current calculation step drives the arithmetic processing unit to perform a current calculation program on the reference supply current, the limiting voltage drop, and the at least one line voltage value to calculate a simulated supply current of the at least one power switching transistor. as well as A size setting step involves driving the arithmetic processing unit to compare the first load current with the analog supply current to calculate a size parameter, and then setting a size of the at least one power switching transistor based on the size parameter. The voltage calculation program includes the speed ratio value, the first load current, the second load current, the power supply voltage, a threshold voltage, and the voltage at one end between the at least one power supply line and the first logic circuit. The speed ratio value is denoted as S, and the first load current is denoted as... The second load current is expressed as The power supply voltage is expressed as The critical voltage is expressed as The voltage at this terminal is expressed as And it meets the following formula: The processing unit limits the voltage drop limit based on the speed ratio value, which is the difference between the terminal voltage and the power supply voltage. The current calculation program includes the simulated supply current, the reference supply current, the limiting voltage drop, and the at least one-wire voltage value. The simulated supply current is expressed as follows: The reference supply current is expressed as The voltage drop limit is expressed as The voltage value of at least one line is expressed as And it meets the following formula:

2. The method for setting the size of a power switching transistor as described in claim 1, characterized in that, The structure of the first logic circuit is the same as that of the second logic circuit.

3. The method for setting the size of a power switching transistor as described in claim 1, characterized in that, The first logic circuit includes multiple transistors, and the first load current acquisition step includes: The power supply voltage is connected to a first power domain and a second power domain of the first logic circuit through the at least one power switching transistor and the at least one power line, so that the transistors operate in a saturation region and generate the first load current.

4. The method for setting the size of a power switching transistor as described in claim 1, characterized in that, The second logic circuit includes multiple transistors, and the second load current acquisition step includes: Connect another power supply voltage to a first power supply domain and a second power supply domain of the second logic circuit, causing the transistors to operate in a saturation region and generate the second load current.

5. The method for setting the size of a power switching transistor as described in claim 1, characterized in that, The steps for calculating the reference supply current include: A preset sub-step drives the arithmetic processing unit to preset the limiting voltage drop to a drain-source voltage of the at least one power switching transistor, causing the at least one power switching transistor to operate in a linear region; and One step of the deduction operator drives the arithmetic processing unit to calculate the reference supply current based on the drain-source voltage.

6. The method for setting the size of a power switching transistor as described in claim 1, characterized in that, The at least one power switching transistor is a multi-critical voltage complementary metal-oxide-semiconductor.

7. A size setting system for a power switching transistor, characterized in that, Include: One power supply voltage; At least one power switching transistor is electrically connected to the power supply voltage; At least one power line is electrically connected to the at least one power switching transistor and has at least one line voltage value; A first logic circuit is electrically connected to the at least one power supply line and generates a first load current. A second logic circuit is electrically connected to the power supply voltage and generates a second load current; A storage unit for storing and accessing the at least one voltage value, a voltage calculation program, and a current calculation program; and An arithmetic processing unit, signal-connected to the storage unit, is configured to perform operations including the following steps: A first load current acquisition step is performed to acquire the first load current. A second load current acquisition step is performed to acquire the second load current. A voltage drop limiting calculation step involves setting a speed ratio value and storing the speed ratio value in the storage unit, and then performing the voltage calculation program on the speed ratio value, the first load current, and the second load current to calculate a voltage drop limiting between the at least one power switching transistor and the first logic circuit. A reference supply current calculation step is to calculate a reference supply current for the at least one power switching transistor based on the limiting voltage drop; A simulated supply current calculation step involves performing the current calculation program on the reference supply current, the limiting voltage drop, and the at least one line voltage value to calculate a simulated supply current for the at least one power switching transistor. and A size setting step involves comparing the first load current with the simulated supply current to calculate a size parameter, and then setting a size of the at least one power switching transistor based on the size parameter. The voltage calculation program includes the speed ratio value, the first load current, the second load current, the power supply voltage, a threshold voltage, and the voltage at one end between the at least one power supply line and the first logic circuit. The speed ratio value is denoted as S, and the first load current is denoted as... The second load current is expressed as The power supply voltage is expressed as The critical voltage is expressed as The voltage at this terminal is expressed as And it meets the following formula: The processing unit limits the voltage drop limit based on the speed ratio value, which is the difference between the terminal voltage and the power supply voltage. The current calculation program includes the simulated supply current, the reference supply current, the limiting voltage drop, and the at least one-wire voltage value. The simulated supply current is expressed as follows: The reference supply current is expressed as The voltage drop limit is expressed as The voltage value of at least one line is expressed as And it meets the following formula:

8. The power switching transistor size setting system as described in claim 7, characterized in that, The structure of the first logic circuit is the same as that of the second logic circuit.

9. The power switching transistor size setting system as described in claim 7, characterized in that, The first logic circuit includes multiple transistors, and the first load current acquisition step includes: By connecting the power supply voltage to a first power domain and a second power domain of the first logic circuit through the at least one power switching transistor and the at least one power line, the transistors are made to operate in a saturation region and generate the first load current.

10. The power switching transistor size setting system as described in claim 7, characterized in that, The second logic circuit includes multiple transistors, and the second load current acquisition step includes: Connect another power supply voltage to a first power supply domain and a second power supply domain of the second logic circuit, causing the transistors to operate in a saturation region and generate the second load current.

11. The power switching transistor size setting system as described in claim 7, characterized in that, The steps for calculating the reference supply current include: A preset sub-step drives the arithmetic processing unit to preset the limiting voltage drop to a drain-source voltage of the at least one power switching transistor, causing the at least one power switching transistor to operate in a linear region; and One step of the deduction operator drives the arithmetic processing unit to calculate the reference supply current based on the drain-source voltage.

12. The power switch transistor size setting system as described in claim 7, characterized in that, The at least one power switching transistor is a multi-critical voltage complementary metal-oxide-semiconductor.

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