A 1 / 4 rate PAM4 clock and data recovery circuit based on three-way phase detection and majority voting

Abstract

The present invention discloses a quarter-rate four-level pulse amplitude modulation (PAM4) clock and data recovery circuit based on three-way phase detection and majority voting, which relates to the field of high-speed communications. The circuit comprises three quarter-rate phase detectors and a majority voter, which identify and determine the phase difference between three thermometer codes and a multiphase clock, reducing phase jitter caused by discrete zero crossings and improving the rate of the PAM4 clock and data recovery circuit. A quadrature voltage-controlled oscillator and a phase interpolator dynamically adjust the output frequency of the quadrature voltage-controlled oscillator to provide a sampling multiphase clock for the quarter-rate phase detector. Three 1:4 multiplexers and a pulse generator use a four-phase pulse signal with a 25% duty cycle as an enable signal to reconstruct four retimed quarter-rate NRZ signals into a single full-rate NRZ signal. The PAM4 clock and data recovery circuit proposed in the present invention has the advantages of high speed, high efficiency, low jitter, and high precision, and has broad application prospects in the field of communication transceivers.

Description

Technical Field

[0001] The present invention belongs to the field of high-speed communications, and in particular relates to a 1 / 4 rate PAM4 clock and data recovery circuit based on three-way phase detection and majority voting. Background Art

[0002] Over the next five to ten years, the communications industry will face a major conflict between the demand for high-speed transmission of massive amounts of data and the increasingly scarce electromagnetic spectrum resources. Due to the high speed and low bit error rate requirements of next-generation communications systems, traditional non-return-to-zero (NRZ) modulation systems are limited by circuit bandwidth at fixed process nodes, making it difficult to meet the increasing transmission rates expected in the future. However, higher-order modulation methods can achieve transmission rates many times that of NRZ modulation within the same bandwidth. Among these, four-level pulse amplitude modulation (PAM4) is one of the most promising high-order modulation methods and represents a key step towards high-speed transmission.

[0003] As communication speeds continue to increase, data jitter and phase deviation between the clock and data significantly increase the phase and amplitude jitter of the demodulated data, reducing the eye opening of the demodulated data. Therefore, it is crucial to introduce a clock and data recovery (CDR) circuit to reduce data jitter. A PAM4 receiver uses a threshold decision block and a limiting amplifier to generate three-way thermometer codes (i.e., NRZ codes with only four code patterns: 111, 110, 100, and 000). Because PAM4 signals have four levels and 12 transition patterns, and the zero-crossing locations of these transition patterns vary, including central zeros and discrete zeros, this can cause phase jitter on the CDR input signal. Furthermore, when the thermometer code is generated through limiting, the symbol periods of the three thermometer codes may be inconsistent. Therefore, how to handle the phase jitter of the input signals to the CDR circuit and the inconsistent symbol periods of the three input signals becomes a major challenge in clock and data recovery for PAM4 receivers. As data rates continue to increase, some traditional circuit structures have difficulty meeting the high-speed bandwidth requirements of PAM4 receiver clock and data recovery circuits. Therefore, it is crucial to propose a clock and data recovery circuit architecture suitable for high-speed receivers.

[0004] Patent CN112737570A proposes a clock and data recovery circuit for PAM4 signals using a software phase-locked loop (PLL). This circuit performs software-based statistics on signal quality, but its implementation is difficult and complex, making it unsuitable for large-scale integrated applications. Our research group's previous patent application (publication number: CN113644909A) proposed a single-channel phase detection circuit. This circuit uses a waveform filter to select four of the twelve PAM4 signal waveform transitions that cross both the center zero point and the center threshold. This ensures phase detection density while avoiding phase jitter caused by discrete zero points.

[0005] Currently, the market still lacks monolithic, low-cost, high-speed and efficient PAM4 receivers and clock and data recovery circuits. Summary of the Invention

[0006] Because non-return-to-zero modulation communication systems are limited by the circuit bandwidth of fixed process nodes and are unable to meet the gradually increasing transmission rates in the future, PAM4 modulation receivers are gradually emerging. To achieve clock and data recovery in ultra-high-speed PAM4 receivers, the present invention proposes a 1 / 4-rate PAM4 clock and data recovery circuit based on three-way phase detection and majority voting based on SiGe BiCMOS technology. The present invention uses an LC orthogonal oscillator and a phase interpolator to recover the multi-phase clock, and uses three 1 / 4-rate phase detectors to phase-detect the three-way thermometer code respectively. The majority voter determines the three-way phase difference information, alleviating the bandwidth limitations of traditional phase detectors and reducing phase jitter caused by inconsistent zero-crossing points in the PAM4 signal transition mode. The 1:4 multiplexer splices the retimed 1 / 4-rate data into a full-rate thermometer code, reducing the complexity of the 1 / 4-rate data transmission path. The circuit proposed in this invention solves the clock and data recovery problem of ultra-high-speed communication receivers and is expected to be applied to future 100G / 200G / 400G communication nodes. See the following description for details:

[0007] A 1 / 4 rate PAM4 clock and data recovery circuit based on three-way phase detection and majority voting includes:

[0008] Three quarter-rate phase detectors identify the phase difference between the three thermometer codes and the multiphase clock. The use of quarter-rate phase detectors overcomes the bandwidth limitations of traditional full-rate phase detectors on clock and data recovery circuits, playing a crucial role in increasing the speed of PAM4 clock and data recovery circuits.

[0009] A majority voter determines the phase detection results of the three thermometer codes. Due to the inconsistent output waveform periods of the limiting amplifiers and phase jitter caused by discrete zero crossings, the phase detection results of the three thermometer codes may differ. Therefore, the majority voter is used to determine the phase difference between the PAM4 signal and the recovered clock based on the "majority wins" principle.

[0010] a voltage-to-current converter for converting the voltage pulse reflecting the phase difference into a charge and discharge current;

[0011] A loop filter charges and discharges the capacitor with a pulse current reflecting the phase difference, converting the current signal into a control voltage signal that varies with the phase difference and reducing the ripple of the voltage signal;

[0012] A quadrature voltage-controlled oscillator (VCO) uses a control voltage output by the loop filter to change the capacitance of the variable capacitor in the oscillator, thereby dynamically adjusting the output frequency of the VCO. The quadrature oscillator uses a parallel coupling structure and outputs a four-phase clock with a phase difference of 90°.

[0013] A phase interpolator takes a four-phase clock with a phase difference of 90° output by the orthogonal oscillator as the signal input and outputs an eight-phase clock with a phase difference of 45° to provide the sampling clock for the 1 / 4 rate phase detector;

[0014] A pulse generator uses clocks of different phases to perform logic AND and output a four-phase pulse signal with a duty cycle of 25%;

[0015] Three 1:4 multiplexers use a pulse signal with a duty cycle of 25% as an enable signal to re-splice the four retimed 1 / 4 rate NRZ signals into one full rate NRZ signal.

[0016] The beneficial effects of the technical solution provided by the present invention are:

[0017] The quarter-rate phase detector designed in this invention performs phase detection on three thermometer codes, significantly alleviating the bandwidth limitations of conventional phase detectors and significantly improving the processing rate of the PAM4 clock and data recovery circuit. The thermometer code, sampled by the D-type flip-flop in the phase detector, can be directly used as retimed quarter-rate data, simplifying the circuit structure. The three-way phase detection results are determined by a majority voter to determine the phase difference between the PAM4 signal and the recovered clock. This reduces phase jitter introduced by discrete zero crossings and addresses the phase deviation fluctuation of the three-way thermometer code caused by the limiting amplifier.

[0018] 2. The quadrature voltage-controlled oscillator designed in this invention uses two NMOS cross-coupled voltage-controlled oscillators in parallel and reverse-coupled to generate a four-phase clock with a 90° phase difference. This clock, through an analog phase interpolator, outputs an eight-phase clock with a 45° phase difference, providing the sampling clock for the quarter-rate phase detector. Compared to methods that generate an eight-phase clock with a 45° phase difference by reverse-coupling four voltage-controlled oscillators or digitally implemented phase interpolators, this invention offers a higher level of integration and a simpler circuit structure.

[0019] 3. The pulse generator and 1:4 multiplexer designed in this invention jointly concatenate the quarter-rate sampled data into a full-rate NRZ thermometer code. Conventional quarter-rate PAM4 CDRs use four decoders to decode the quarter-rate thermometer code, significantly increasing receiver power consumption and complicating the data path. However, the PAM4 clock and data recovery circuit designed in this invention incorporates a multiplexer. The retimed quarter-rate data is then concatenated into the full-rate code before being input into the decoder. This avoids the need for additional decoder modules, reduces receiver power consumption, and significantly reduces receiver complexity.

[0020] In summary, the present invention designs a quarter-rate PAM4 clock and data recovery circuit for high-speed PAM4 receivers. Based on a standard BiCMOS process, the circuit has a simple structure and high integration, and holds great promise for applications in communications, including high-speed PAM4 transceivers and clock and data recovery circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 : Block diagram of a high-speed PAM4 receiver and its clock and data recovery circuit;

[0022] Figure 2 :1 / 4 rate phase detector circuit diagram;

[0023] Figure 3 : Majority voter circuit diagram;

[0024] Figure 4 : Voltage-to-current converter circuit schematic;

[0025] Figure 5 : Schematic diagram of quadrature voltage controlled oscillator circuit;

[0026] Figure 6 : Phase interpolator circuit schematic;

[0027] Figure 7 : Schematic diagram of pulse generator circuit;

[0028] Figure 8 : 1:4 multiplexer circuit schematic;

[0029] Figure 9 : 100Gb / s PAM4 clock and data recovery circuit outputs full-rate data eye diagram. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention are described in further detail below.

[0031] Example 1

[0032] The embodiment of the present invention proposes a 1 / 4 rate PAM4 clock and data recovery circuit based on three-way phase detection and majority voting, see Figure 1 , the circuit includes:

[0033] Three quarter-rate phase detectors identify the phase difference between the three thermometer codes and the multiphase clock. The use of quarter-rate phase detectors overcomes the bandwidth limitations of traditional full-rate phase detectors on clock and data recovery circuits, playing a crucial role in increasing the speed of PAM4 clock and data recovery circuits.

[0034] A majority voter determines the phase detection results of the three thermometer codes. Due to the inconsistent output waveform periods of the limiting amplifiers and phase jitter caused by discrete zero crossings, the phase detection results of the three thermometer codes may differ. Therefore, the majority voter is used to determine the phase difference between the PAM4 signal and the recovered clock based on the "majority wins" principle.

[0035] a voltage-to-current converter for converting the voltage pulse reflecting the phase difference into a charge and discharge current;

[0036] A loop filter charges and discharges the capacitor with a pulse current reflecting the phase difference, converting the current signal into a control voltage signal that varies with the phase difference and reducing the ripple of the voltage signal;

[0037] A quadrature voltage-controlled oscillator (VCO) uses a control voltage output by the loop filter to change the capacitance of the variable capacitor in the oscillator, thereby dynamically adjusting the output frequency of the VCO. The quadrature oscillator uses a parallel coupling structure and outputs a four-phase clock with a phase difference of 90°.

[0038] A phase interpolator takes a four-phase clock with a phase difference of 90° output by the orthogonal oscillator as the signal input and outputs an eight-phase clock with a phase difference of 45° to provide the sampling clock for the 1 / 4 rate phase detector;

[0039] A pulse generator uses clocks of different phases to perform logic AND and output a four-phase pulse signal with a duty cycle of 25%;

[0040] Three 1:4 multiplexers use a pulse signal with a duty cycle of 25% as an enable signal to re-splice the four retimed 1 / 4 rate NRZ signals into one full rate NRZ signal.

[0041] Example 2

[0042] Figure 1This is a block diagram of a high-speed PAM4 receiver with clock and data recovery circuitry. The transimpedance amplifier in the PAM4 receiver converts the high-speed PAM4 current signal into a PAM4 voltage signal. Three threshold decisions and a limiting amplifier then convert the PAM4 voltage signal into three thermometer codes, which serve as the input signals for the high-speed PAM4 clock and data recovery circuitry of the present invention. The core circuitry of the PAM4 clock and data recovery circuit designed in this invention includes a quarter-rate phase detector, a majority voter, a voltage-to-current converter, a loop filter, a quadrature voltage-controlled oscillator, a phase interpolator, a pulse generator, and a 1:4 multiplexer. The output signal is a retimed full-rate thermometer code. The PAM4 receiver's decoder decodes the retimed thermometer code signal output by the PAM4 clock and data recovery circuit into two NRZ signals.

[0043] Figure 2 This is a quarter-rate phase detector circuit. It takes as input the full-rate NRZ code and the multiphase clock recovered by the PAM4 clock and data recovery circuit, and detects the phase lead / lag between them. The quarter-rate phase detector's multiphase sampling clock has phases of 0°, 90°, 135°, 180°, and 270°, driving a D flip-flop to sample the full-rate thermometer code, producing sampled data D0, D1, E0, D2, and D3, respectively. D1 and E0, and E0 and D2, are XORed, and the outputs are the phase lead / lag information X and Y between the data and clock edges. Because the phase detector detects data edges at 135° phase, after the PAM4 clock and data recovery circuit are locked, the clock edges at phases of 0°, 90°, 180°, and 270° are aligned with their respective "centers of the data," preventing data metastable states from being sampled. Therefore, D0, D1, D2, and D3 are also the retimed 1 / 4 rate data signals. The three 1 / 4 rate phase detectors respectively detect the phase of the three thermometer codes of the PAM4 receiver and obtain the phase difference information between the three thermometers and the multiphase recovered clock.

[0044] Figure 3 This is the circuit diagram of a majority voter. Three quarter-rate phase detectors detect the phase of the three thermometer codes in the PAM4 receiver, determining the phase difference between the three thermometer codes and the recovered polyphase clock. After the high-speed PAM4 signal passes through three thresholds, the output pulse widths of the three signals are inconsistent. This phenomenon is exacerbated by amplification through three limiting amplifiers. Furthermore, the 12 transition modes of the PAM4 signal have inconsistent zero-crossing locations, resulting in discrete zero-crossings that can cause input signal jitter and phase deviation fluctuations. Therefore, a majority voter circuit is introduced to determine the phase difference between the three signals, using the "majority wins" principle. The implementation is P = A·B + B·C + C·A.

[0045] Figure 4The voltage-current converter circuit schematic is shown in Figure 2. The majority voter outputs the phase difference information between the three-way thermometer code and the recovered multiphase clock, that is, the phase difference information between the PAM4 signal and the recovered clock. UP With V DOWN They are respectively the charging and discharging signals of the loop filter from the voltage-current converter. M4 and M5 form a current mirror to convert V UP The controlled current information is converted to V DOWN The same side charges the loop filter and outputs the control terminal voltage of the voltage-controlled oscillator.

[0046] Figure 5 This is the circuit schematic of a quadrature voltage-controlled oscillator. The resonator of the voltage-controlled oscillator unit is composed of an inductor and a variable capacitor. The NMOS cross-coupled negative resistance structure provides energy compensation for the voltage-controlled oscillator. The control voltage output by the voltage-to-current converter and loop filter serves as the common terminal of the two variable capacitors. The clock and data recovery circuit adjusts the voltage-controlled oscillator control voltage based on the phase difference information obtained by the phase detector, thereby adjusting the variable capacitor value to adjust the frequency of the voltage-controlled oscillator's output clock. M0, M3, M4, and M7 are parallel current-injection MOS transistors. The two voltage-controlled oscillator units are reverse-coupled through four current-injection transistors to form a quadrature voltage-controlled oscillator, outputting a four-phase recovered clock with a 90° phase difference.

[0047] Figure 6 The analog phase interpolator used in this invention adopts a current mode logic structure, which linearly superimposes two clock signals through a shared resistor. The tail currents of the two input branches are αI SS With (1-α)I SS By varying the value of α, or the tail current coefficients of the two circuits, the offset of the interpolated phase of the output clock signal can be controlled. When α is 0.5, the output clock signal phase is interpolated at the center between the two input clock signal phases. For example, if the two input clock signal phases are 0° and 90°, respectively, the output clock signal phase is 45°.

[0048] Figure 7 The pulse generator circuit diagram is shown in Figure 1. The input of the pulse generator is two clock signals with a phase difference of 90°. The circuit structure is a two-input NOR gate, which is The output pulse signal has a pulse width of 1 / 4 of the period, i.e., a duty cycle of 25%. The PAM4 clock and data recovery circuit designed in this invention has four pulse generators, and the pulse widths of the four generated pulse signals completely cover the 1 / 4 rate signal period. The output signal of the pulse generator serves as the enable signal for the 1:4 multiplexer.

[0049] Figure 8The schematic diagram of the 1:4 multiplexer circuit. S0, S1, S2 and S3 are the output signals of the pulse generator, which serve as the enable signal for selecting data in the multiplexer. D0, D1, D2 and D3 are the 1 / 4 rate data signals sampled by the five D flip-flops in the 1 / 4 rate phase detector, and are alternately selected by the enable signal. The enable signal is obtained through the logic operation of the multi-phase clock signal, and the 1 / 4 rate data is also sampled and output by the multi-phase clock, so the edge of the 1 / 4 rate data is aligned with the edge of the enable signal. The enable signal is selected by the high level, and the final output is D out The PAM4 clock and data recovery circuit has three 1:4 multiplexers, corresponding to the three-way thermometer code of the PAM4 receiver.

[0050] According to the above circuit structure, based on the IHP 130nm BiCMOS process, the present invention simulates and optimizes the PAM4 clock and data recovery circuit. Figure 9 This example recovers the full-rate data eye diagram for a 100Gb / s PAM4 clock and data recovery circuit. When the input signal is a 100Gb / s PAM4 signal, the three thermometer codes used as input signals for the PAM4 clock and data recovery circuit are 50Gb / s NRZ signals. In the PAM4 clock and data recovery circuit, a quadrature voltage-controlled oscillator recovers a 12.5G multiphase clock signal and retimes the input data. The retimed 1 / 4-rate data is multiplexed through a 1:4 multiplexer to produce the full-rate thermometer code recovered by the PAM4 clock and data recovery circuit. Using an IHP BiCMOS 130nm process with a 3.3V power supply, the core circuit consumes 896.91mW, of which the three phase detectors consume a total of 513.87mW. As shown in the figure, the differential eye swing reaches 1.9V, with a peak-to-peak phase jitter of only 1.35ps and a peak-to-peak amplitude jitter of 33.18mV.

[0051] In summary, the PAM4 clock and data recovery circuit designed in the present invention can be used in ultra-high-speed PAM4 receivers and has the advantages of low jitter, large swing, and high stability.

[0052] Unless otherwise specified, the embodiments of the present invention do not limit the models of the components. Any component that can perform the above functions may be used.

[0053] Those skilled in the art will understand that the accompanying drawings are only a schematic diagram of a preferred embodiment, and the serial numbers of the embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0054] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A 1 / 4 rate PAM4 clock and data recovery circuit based on three-way phase detection and majority voting, characterized in that: The circuit comprises: Three quarter-rate phase detectors identify the phase difference between the three thermometer codes and the multiphase clock. This eliminates the bandwidth limitations of traditional full-rate phase detectors on clock and data recovery circuits, playing a crucial role in increasing the speed of PAM4 clock and data recovery circuits. A majority voter determines the phase detection results of the three thermometer codes. Due to the inconsistent output waveform periods of the limiting amplifiers and phase jitter caused by discrete zero crossings, the phase detection results of the three thermometer codes may differ. Therefore, based on the "majority wins" principle, the majority voter is used to determine the phase difference between the PAM4 signal and the recovered clock. a voltage-to-current converter for converting the voltage pulse reflecting the phase difference into a charge and discharge current; A loop filter charges and discharges the capacitor with a pulse current reflecting the phase difference, converting the current signal into a control voltage signal that varies with the phase difference and reducing the ripple of the voltage signal; A quadrature voltage-controlled oscillator (VCO). The control voltage output by the loop filter changes the capacitance of the variable capacitor in the oscillator, thereby dynamically adjusting the output frequency of the VCO. The quadrature oscillator uses a parallel coupling structure and outputs a four-phase clock with a phase difference of 90°. A phase interpolator takes a four-phase clock with a phase difference of 90° output by the orthogonal oscillator as the signal input and outputs an eight-phase clock with a phase difference of 45° to provide the sampling clock for the 1 / 4 rate phase detector; A pulse generator uses clocks of different phases to perform logic AND and output a four-phase pulse signal with a duty cycle of 25%; Three 1:4 multiplexers use a pulse signal with a duty cycle of 25% as an enable signal to re-splice the four retimed 1 / 4 rate NRZ signals into one full rate NRZ signal.

2. The 1 / 4 rate PAM4 clock and data recovery circuit based on three-way phase detection and majority voting according to claim 1, characterized in that: The 1 / 4 rate phase detector identifies the phase advance / lag information between the thermometer code and the multi-phase clock. The phases of the multi-phase sampling clock are 0°, 90°, 135°, 180°, and 270°, respectively driving a D flip-flop to sample the full-rate thermometer code, obtaining sampled data D0, D1, E0, D2, and D3, respectively. D1 and E0 and E0 and D2 are XORed, and phase advance / lag information X and Y between the data edge and the clock edge are output. D0, D1, D2, and D3 are also the retimed 1 / 4 rate data signals. Three 1 / 4 rate phase detectors respectively perform phase detection on the three thermometer codes of the PAM4 receiver to obtain phase difference information between the three thermometer codes and the multi-phase recovered clock.

3. The 1 / 4 rate PAM4 clock and data recovery circuit based on three-way phase detection and majority voting according to claim 1, characterized in that: The majority voter determines the phase difference information of the three signals using the implementation method of P=A·B+B·C+C·A. This solves the problem of inconsistent pulse widths of the three high-speed PAM4 signals after they pass through the three-way threshold judgment and limiting amplifier. It also alleviates the impact of input signal jitter and phase deviation fluctuation caused by the 12 types of transitions in the PAM4 signal.

4. The 1 / 4 rate PAM4 clock and data recovery circuit based on three-way phase detection and majority voting according to claim 1, characterized in that: The orthogonal voltage-controlled oscillator is composed of two voltage-controlled oscillator units reversely coupled through four current injection tubes, and outputs a four-phase recovered clock with a phase difference of 90°; the phase interpolator adopts a current-mode logic structure, linearly superimposes two clock signals through a shared resistor, and outputs an eight-phase clock with a phase difference of 45°, providing a sampling clock for the 1 / 4 rate phase detector.

5. The 1 / 4 rate PAM4 clock and data recovery circuit based on three-way phase detection and majority voting according to claim 1, characterized in that: The input of the pulse generator is two clock signals with a phase difference of 90°, and the circuit structure is a two-input NOR gate, that is, A pulse signal with a duty cycle of 25% is output as an enable signal for a 1:4 multiplexer. The 1:4 multiplexer is selected by a high level of the enable signal to recombine four channels of 1 / 4 rate data into one channel of full rate data. The pulse generator and the 1:4 multiplexer not only avoid an increase in the number of decoder modules and reduce receiver power consumption, but also greatly simplify the system complexity.

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