An adaptively regulated injection-locked frequency divider

Abstract

The application relates to the technical field of integrated circuit design, and provides an adaptive injection-locked frequency divider, which directly injects a differential sine signal by using parallel double MOS tubes, and specifically comprises a frequency divider body, an injection strength detection module, a direct current bias point selection module and a power supply device which are electrically connected. The injection-locked frequency divider firstly connects a pair of differential sine signals output by a voltage-controlled oscillator to the input end of the injection strength detection module, and obtains a direct current voltage through the injection strength detection module; then according to the direct current voltage and a corresponding reference voltage, the strength of the connected differential sine signal is judged by using a preset number of comparators, and a corresponding direct current bias voltage is obtained through a digital logic gate; finally, the obtained direct current bias voltage is injected to the frequency divider body, and a frequency division signal is output, so that the adaptive adjustment of the direct current bias point according to the injection strength is realized, and the frequency division range is effectively widened.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to an adaptively adjustable injection-locked frequency divider. Background Technology

[0002] With the rapid development of technology, modern integrated circuits are inevitably evolving towards system-on-a-chip (SoC). As the requirements for information acquisition, transmission, and processing become increasingly stringent, high-frequency, low-power design has become a necessary requirement for circuit design in various communication systems. In modern communication systems, phase-locked loop (PLL) systems capable of precise phase modulation are mostly used to obtain stable local oscillator signals.

[0003] A phase-locked loop (PLL) system mainly includes a voltage-controlled oscillator (VCO) and a frequency divider. Since the frequency divider is often used as the first-stage load of the VCO in the system to obtain a frequency-divided output, it is a key circuit in a wireless communication system.

[0004] Currently, frequency dividers are mainly classified into three categories based on their working principle: current-mode logic dividers, regenerative dividers, and injection-locked dividers. Current-mode logic dividers are a traditional flip-flop structure divider with a wide operating range, primarily suitable for lower-frequency divider designs. Regenerative dividers use a mixing principle to achieve frequency down-conversion; their core is the mixing circuit. They represent another implementation method for millimeter-wave frequency dividers. Although regenerative dividers operate at higher frequencies than current-mode logic dividers, they consume more DC power, have a narrower frequency locking range, and require more complex mixing circuit design. Injection-locked dividers operate at high frequencies with low power consumption. Furthermore, due to their inherent suppression properties, they exhibit good phase noise characteristics, thus providing high-quality output signals and are widely used in millimeter-wave phase-locked loop circuits. However, the biggest drawback of injection-locked dividers is their very limited frequency division range, restricting them to narrowband operation.

[0005] Due to the limitations of current integrated circuit technology and the complexity of circuit design, current-mode logic dividers and regenerative dividers are not suitable for the design requirements of millimeter-wave ultra-high-speed dividers. Since most wireless applications at present are narrowband systems, injection-locked dividers can still effectively complete frequency division within specific frequency bands. Therefore, how to broaden the frequency division range of injection-locked dividers will inevitably become a key research direction for future high-speed dividers, so as to be more widely used in wireless communication systems that require high frequency and low power consumption. Summary of the Invention

[0006] To overcome the shortcomings of existing technologies and address the narrow frequency division range of current injection-locked frequency dividers, this application provides an adaptively adjustable injection-locked frequency divider that uses a relatively simple method to automatically adjust the bias voltage of the injection node according to the injection intensity, thereby widening the frequency division range.

[0007] To achieve the above objectives, this application provides an adaptive injection-locked frequency divider, which employs parallel dual MOS transistors to directly inject differential signals, specifically including: a frequency divider body, an injection intensity detection module, and a DC bias point selection module.

[0008] The injection intensity detection module is used to acquire the differential signal amplitude injected by the parallel dual MOS transistors; and to obtain a DC voltage based on the differential signal amplitude.

[0009] The DC bias point selection module is electrically connected to the output terminal of the injection intensity detection module, and is used to obtain a reference voltage based on the differential signal amplitude and the DC voltage; and to output a preset number of digital signals using a preset number of comparators based on the DC voltage and the reference voltage; and to determine the DC bias voltage using digital logic gates based on the preset number of digital signals.

[0010] The frequency divider body is electrically connected to the output terminal of the DC bias point selection module, and is used to adjust the DC bias voltage of the gate of the parallel dual MOS transistor according to the DC bias voltage, and output the frequency division signal.

[0011] Furthermore, the DC voltage is linearly correlated with the amplitude of the differential signal.

[0012] Furthermore, the specific method for obtaining the reference voltage based on the differential signal amplitude and the DC voltage is as follows:

[0013] Based on the differential signal amplitude and the DC voltage, the linear correlation coefficient between the differential signal amplitude and the DC voltage is obtained through simulation.

[0014] The reference voltage is obtained based on the linear correlation coefficient and the amplitude of the differential signal.

[0015] Furthermore, the preset number of comparators is set according to the preset number of automatic adjustment segments.

[0016] Furthermore, the preset number of automatic adjustment segments is four, and the number of comparators is three.

[0017] Furthermore, the frequency divider body includes a parallel dual MOS transistor and an LC resonant network. The parallel dual MOS transistor is used to inject differential signals. The LC resonant network includes an AC coupling unit, an inductor, and a capacitor, which are connected in parallel.

[0018] Furthermore, the AC coupling unit adopts a cross-coupling circuit consisting of two MOS transistors, two capacitors, and two resistors, with the sources of both MOS transistors grounded.

[0019] Furthermore, the injection-locked frequency divider also includes a power supply device for providing power support to the frequency divider body, the injection intensity detection module, and the DC bias point selection module.

[0020] Furthermore, the injection intensity detection module, the DC bias point selection module, and the power supply device are integrated into the frequency divider body.

[0021] Secondly, this application also provides an adaptive adjustment method for an injection-locked frequency divider, specifically including:

[0022] Obtain the amplitude of the differential signal injected by the parallel dual MOS transistors.

[0023] The DC voltage is obtained based on the amplitude of the differential signal.

[0024] Based on the differential signal amplitude and the DC voltage, the corresponding reference voltage is obtained through simulation.

[0025] Based on the DC voltage and the reference voltage, a preset number of digital signals are output using a preset number of comparators.

[0026] Based on the preset number of digital signals, the DC bias voltage is selected through digital logic gates.

[0027] Based on the DC bias voltage, the DC bias voltage of the gates of the parallel dual MOS transistors is adjusted, and a frequency division signal is output.

[0028] This application provides an adaptive injection-locked frequency divider. The injection-locked frequency divider uses parallel dual MOS transistors to directly inject differential sinusoidal signals. Specifically, it includes a frequency divider body, an injection intensity detection module, a DC bias point selection module, and a power supply unit, all electrically connected. The injection-locked frequency divider first connects a pair of differential sinusoidal signals output from a voltage-controlled oscillator to the input of the intensity detection module, obtaining a DC voltage through the module. Then, based on the DC voltage and a corresponding reference voltage, a preset number of comparators are used to determine the intensity of the input differential sinusoidal signal. A corresponding DC bias voltage is then obtained through digital logic gates. Finally, the obtained DC bias voltage is applied to the frequency divider body to output a divided frequency signal, thereby achieving adaptive adjustment of the DC bias point according to the injection intensity and effectively widening the frequency division range. Attached Figure Description

[0029] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A schematic diagram of an adaptively adjustable injection-locked frequency divider structure provided in an embodiment of this application;

[0031] Figure 2 This is a schematic diagram of the injection intensity detection module structure provided in an embodiment of this application;

[0032] Figure 3 This is a schematic diagram of the DC bias point selection module structure provided in an embodiment of this application;

[0033] Figure 4 This is a schematic flowchart of a method for obtaining the reference voltage VREF provided in an embodiment of this application;

[0034] Figure 5 This is a schematic diagram of the frequency divider body structure provided in the embodiments of this application;

[0035] Figure 6 This is a schematic diagram showing the comparison of frequency division ranges under two different scenarios provided in the embodiments of this application;

[0036] Figure 7 This is a schematic flowchart of an adaptive adjustment method for an injection-locked frequency divider provided in an embodiment of this application. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be described completely and clearly below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0038] To facilitate understanding of the technical solutions of the embodiments of this application, some concepts involved in the embodiments of this application will be explained below.

[0039] When crosstalk exists between a freely oscillating oscillator and a clock operating at a different frequency, especially when their frequencies are close, the resonant frequency of the freely oscillating oscillator will be affected by the clock. When the crosstalk is small, spurious signals will appear around the oscillator's resonant frequency. When the crosstalk is large, the oscillator's resonant frequency will change or even become the same as the clock frequency causing the crosstalk. This phenomenon is called oscillator injection lock-in, and the clock signal causing the crosstalk is called the injection signal. If the injection signal is set near the higher harmonics of the oscillator's oscillation frequency, the injection lock-in phenomenon can be used to pull the oscillator's oscillation frequency to 1 / N, which is called an injection-locked N-divider. However, since the higher the power of the injection signal, the easier it is for frequency pulling to occur. As the harmonic order increases, the power decreases, and the probability of frequency pulling also decreases. Therefore, second harmonic injection produces the best frequency locking and pulling effect. Thus, the oscillator's resonant frequency is usually designed to be near half the frequency of the injection signal, thereby achieving a frequency division of the injection signal by half.

[0040] Frequency dividers are used to reduce the frequency of the oscillator output signal and are a key unit in a phase-locked loop (PLL) system. In practical applications, frequency dividers are usually multi-stage, forming a frequency divider chain, with the operating frequency of each stage decreasing sequentially. The input signal of the first-stage frequency divider is the output signal of the oscillator in the PLL system, which has the highest operating frequency in the entire circuit. Therefore, the injection-locked frequency divider proposed in this application is applied to the first stage of the entire frequency divider chain, which can ensure the stable operation of subsequent frequency divider circuits with a large frequency locking range.

[0041] Frequency lock-in range refers to the range of input signal frequencies that an injection-locked frequency divider can divide. It reflects the divider's bandwidth performance and is the most important indicator of an injection-locked frequency divider. In millimeter-wave fully digital phase-locked loops, the output signal frequency of the numerically controlled oscillator (CNC) is relatively high, so frequency division is necessary. Therefore, the injection-locked frequency divider must operate at a high frequency, and its frequency lock-in range must cover the CNC oscillator's output frequency. This requires the injection-locked frequency divider to have a wide frequency lock-in range.

[0042] refer to Figure 1The first aspect of this application provides an adaptive injection-locked frequency divider. This injection-locked frequency divider uses parallel dual MOS transistors to directly inject differential signals and specifically includes: a frequency divider body, an injection intensity detection module, a DC bias point selection module, and a power supply device. In this application embodiment, the injection intensity detection module, DC bias point selection module, and power supply device are all integrated on the frequency divider body, thereby reducing chip size, saving space, and increasing versatility. Of course, the above modules can also be set separately according to actual needs and integrated on the same chip to form an injection-locked frequency divider device. Regardless of the combination method, as long as the electrical connection between the modules can be realized and the information exchange between the modules can be completed, it is acceptable.

[0043] Specifically, the power supply unit provides power to the frequency divider body, the injection intensity detection module, and the DC bias point selection module. In this embodiment, an external power supply is used because it is low-cost, easy to install, and convenient to operate. Of course, other power supply methods can also be selected, as long as the power supply unit can provide a power source for the injection-locked frequency divider.

[0044] refer to Figure 2 This is a schematic diagram of the injection intensity detection module structure provided in an embodiment of this application. In this embodiment, the injection intensity detection (Power Detector, PD) module is used to acquire the differential signal amplitude injected by the parallel dual MOSFETs; and to obtain the DC voltage VPD based on the differential signal amplitude. Figure 1 It can be seen that when a pair of differential sinusoidal input signals are injected into VIN_P and VIN_N, after being processed by the PD module, a DC voltage VPD can be directly output. The DC voltage VPD has an approximately linear relationship with the amplitude of the injected differential signals VIN_N and VIN_P, that is, VPD increases as the amplitude of VIN_N and VIN_P increases, and vice versa.

[0045] refer to Figure 3 This is a schematic diagram of the DC bias point selection module structure provided in an embodiment of this application. In this embodiment, the DC bias point selection module is electrically connected to the output terminal of the injection intensity detection module, and is used to obtain the reference voltage VREF based on the amplitudes of the differential signals VIN_N and VIN_P and the DC voltage VPD; and to output a preset number of digital signals using a preset number of comparators based on the DC voltage VPD and the reference voltage VREF; and to determine the DC bias voltage using digital logic gates based on the preset number of digital signals.

[0046] For details, please refer to Figure 4 In this embodiment of the application, the reference voltage VREF is obtained using the following method:

[0047] Step S11: Based on the amplitudes of the differential signals VIN_N and VIN_P and the DC voltage VPD, obtain the linear correlation coefficient k between the amplitudes of the differential signals VIN_N and VIN_P and the DC voltage VPD through simulation;

[0048] Step S12: Obtain the reference voltage VREF based on the linear correlation coefficient k and the amplitudes of the differential signals VIN_N and VIN_P.

[0049] More specifically, the number of comparators is set according to the number of automatic adjustment segments. In this embodiment, the number of automatic adjustment segments is set to four, therefore the number of comparators is set to three. It should be noted that the number of automatic adjustment segments is set according to specific circumstances and is not limited to four segments. For example, in practical applications, if the system power supply voltage is 1.2V, then according to the actual situation, it is only necessary to set the number of segments to three, that is, the injected signal amplitude is in three intervals: 0-0.4, 0.4-0.8, and 0.8-1.2. In this case, two comparators need to be set at the injected signal amplitude values ​​of 0.4 and 0.8.

[0050] Therefore, in this embodiment of the application, the working process of the DC bias point selection module can be simply summarized as follows: based on the three sets of VPD values ​​and the corresponding three sets of VREF values, three comparators are used to output three sets of corresponding digital signals, and then digital logic gates are used to select the magnitude of the DC bias voltage applied to the gates of the two injection transistors for the three sets of digital signals.

[0051] refer to Figure 5 This is a schematic diagram of the frequency divider body structure provided in an embodiment of this application. In this implementation, the frequency divider body is electrically connected to the output terminal of the DC bias point selection module, which is used to adjust the DC bias voltage of the gates of the parallel dual MOS transistors according to the DC bias voltage and output the frequency division signal.

[0052] As shown in the figure, in this embodiment of the application, the frequency divider body includes parallel dual MOS transistors and an LC resonant network. The parallel dual MOS transistors are injection transistors used to receive differential signals, specifically composed of M3 and M4 connected in parallel, with the two sides of M4 being the frequency division signal output terminals. The LC resonant network includes an AC coupling unit, two inductors L and one capacitor C3, and the AC coupling unit, inductors and capacitor are connected in parallel.

[0053] More specifically, the AC coupling unit employs a cross-coupling circuit consisting of two cross-connected MOSFETs M1 and M2, two capacitors C1, and two resistors R1. The sources of both MOSFETs M1 and M2 are grounded. The two capacitors C1 and two resistors R1 form AC coupling, allowing the gate voltages of M1 and M2 to be manually set, thereby changing the negative resistance provided by the AC coupling unit. Capacitor C2 and resistor R2 in the diagram also form AC coupling, which can be used to change the DC bias voltage.

[0054] It should be noted that the frequency division range of the frequency divider is mainly related to the injection intensity and the quality factor Q of the resonant network. The greater the injection intensity, the wider the frequency division range will be. However, the embodiments of this application mainly consider the injection intensity factor, which is mainly manifested in the following aspects: Figure 5 The amplitude of the sinusoidal signal inputs VIN_N and VIN_P.

[0055] In summary, in this embodiment, the same naming point is the same point throughout the injection-locked frequency divider, specifically manifested as all modules being short-circuited together by metal wires. In actual operation, the injection-locked frequency divider provided in this embodiment first inputs a pair of differential sinusoidal signals output from the voltage-controlled oscillator (VCO) to VIN_P and VIN_N. The DC voltage VPD is obtained through the injection intensity detection module. Then, based on the DC voltage VPD and the corresponding reference voltage VREF, three comparators are used to determine the intensity of the input VIN_P and VIN_N. The corresponding VDC_P and VDC_N are then obtained through digital logic gates. Finally, the obtained VDC_P and VDC_N are injected into the frequency divider body, outputting a divided frequency signal, thereby achieving adaptive adjustment of the DC bias point according to the injection intensity.

[0056] Therefore, the core of this application's embodiment lies in automatically adjusting the DC bias points of M3 and M4 based on the injection intensity. For example, when the injection intensity is low, i.e., the input signal amplitude is small, the DC bias point of the N transistor can be automatically increased, making it easier for the N transistor to conduct, thereby obtaining a better injection effect and improving the frequency division range.

[0057] The second aspect of this application provides an adaptive adjustment method for an injection-locked frequency divider, which guides the operation of an adaptively adjusted injection-locked frequency divider provided in the first aspect of this application. For details not disclosed in the adaptive adjustment method for an injection-locked frequency divider provided in the second aspect of this application, please refer to the adaptively adjusted injection-locked frequency divider provided in the first aspect of this application.

[0058] See Figure 6 In this embodiment of the application, the adaptive adjustment method of the injection-locked frequency divider specifically includes the following steps:

[0059] Step S21: Obtain the amplitude of the differential signal injected by the parallel dual MOS transistors.

[0060] Step S22: Obtain the DC voltage VPD based on the differential signal amplitude.

[0061] Step S23: Based on the differential signal amplitude and DC voltage VPD, obtain the corresponding reference voltage VREF through simulation.

[0062] Step S24: Based on the DC voltage VPD and the reference voltage VREF, a preset number of digital signals are output using a preset number of comparators.

[0063] Step S25: Select the DC bias voltage using digital logic gates based on a preset number of digital signals.

[0064] Step S26: Adjust the DC bias voltage of the gate of the parallel dual MOS transistors according to the DC bias voltage, and output a frequency division signal to realize the adaptive adjustment of the DC bias voltage of the parallel dual MOS transistors.

[0065] The following will describe in detail an adaptive injection-locked frequency divider provided in the embodiments of this application through specific examples.

[0066] In this specific embodiment, a four-segment automatic adjustment is adopted. The system power supply voltage is 1.2V, the injection lock divider voltage is 0.9V, VPD is the output of the PD module, and VREF1, VREF2, and VREF3 are the values ​​of VPD when the injected signal amplitude is equal to 0.3, 0.6, and 0.9, respectively. It should be emphasized that VPD increases with the increase of the injected signal amplitude, but it is not equal to the injected signal amplitude. The two are only approximately linearly related. The injection intensity can be determined by three comparators, and then the DC bias voltage applied to the gates of the two injection transistors is selected by digital logic gates. In specific embodiments of this application, the specific parameters are as follows: injected signal amplitude 0-0.3, VDC_P = 0.2, VDC_N = 1.2; injected signal amplitude 0.3-0.6, VDC_P = 0.3, VDC_N = 1.15; injected signal amplitude 0.6-0.9, VDC_P = 0.4, VDC_N = 1.1; injected signal amplitude 0.9-1.2, VDC_P = 0.6, VDC_N = 1.05.

[0067] Through the above-mentioned automatic adjustment method, the following can be obtained: Figure 7The diagram shows the frequency division range, where the horizontal axis represents the input frequency in GHz, and the vertical axis represents the injection intensity in mV. In the diagram, the gray line represents the frequency division range obtained by maintaining a fixed bias voltage under maximum injection conditions; the black line represents the frequency division range after automatically adjusting the bias voltage, which is the frequency division range of the specific embodiment of this application. As can be seen from the diagram, the specific embodiment of this application can achieve a frequency division range of 19GHz-35GHz, which is larger than the frequency division range using a fixed bias voltage in the prior art, effectively widening the frequency division range.

[0068] Furthermore, the technical solution of the specific embodiment of this application is compared with the performance indicators of seven existing technical solutions, as shown in Table 1. The frequency division range of the specific embodiment of this application is 19G-35G, and the frequency division range percentage reaches 59.3%, which is much higher than the frequency division range percentage of the other seven existing technologies, further illustrating the advantage of the specific embodiment of this application in widening the frequency division range.

[0069] Table 1. List of comprehensive performance indicators under different technical solutions

[0070]

[0071] This application provides an adaptive injection-locked frequency divider, which uses parallel dual MOS transistors to directly inject differential signals and includes: a frequency divider body, an injection intensity detection module, and a DC bias point selection module.

[0072] The injection intensity detection module is used to acquire the differential signal amplitude injected by the parallel dual MOS transistors; and to obtain a DC voltage based on the differential signal amplitude.

[0073] The DC bias point selection module is electrically connected to the output terminal of the injection intensity detection module, and is used to obtain a reference voltage based on the differential signal amplitude and the DC voltage; and to output a preset number of digital signals using a preset number of comparators based on the DC voltage and the reference voltage; and to determine the DC bias voltage using digital logic gates based on the preset number of digital signals.

[0074] The frequency divider body is electrically connected to the output terminal of the DC bias point selection module, and is used to adjust the DC bias voltage of the gate of the parallel dual MOS transistor according to the DC bias voltage, and output the frequency division signal.

[0075] As can be seen from the above technical solution, this application provides an adaptive injection-locked frequency divider. This injection-locked frequency divider uses parallel dual MOS transistors to directly inject differential sinusoidal signals. Specifically, it includes a frequency divider body, an injection intensity detection module, a DC bias point selection module, and a power supply unit, all electrically connected. The injection-locked frequency divider first connects a pair of differential sinusoidal signals output from a voltage-controlled oscillator to the input terminal of the intensity detection module, and obtains a DC voltage through the injection intensity detection module. Then, based on the DC voltage and the corresponding reference voltage, a preset number of comparators are used to determine the intensity of the input differential sinusoidal signal. The corresponding DC bias voltage is then obtained through digital logic gates. Finally, the obtained DC bias voltage is applied to the frequency divider body to output a divided frequency signal, thereby achieving adaptive adjustment of the DC bias point according to the injection intensity, effectively widening the frequency division range.

[0076] The present application has been described in detail above with reference to specific embodiments and exemplary examples, enabling those skilled in the art to understand or implement the present application. However, these descriptions should not be construed as limiting the present application. Those skilled in the art will understand that various equivalent substitutions, modifications, or improvements can be made to the technical solutions and implementation methods of the present application without departing from the spirit and scope of the present application, and all such modifications and improvements fall within the scope of the present application. The scope of protection of the present application is determined by the appended claims.

Claims

1. An adaptive injection-locked frequency divider, employing parallel dual MOS transistors to directly inject differential signals, characterized in that, include: Frequency divider body, injection intensity detection module and DC bias point selection module; The injection intensity detection module is used to obtain the amplitude of the differential signal injected by the parallel dual MOS transistors; And, the DC voltage is obtained based on the amplitude of the differential signal; The DC bias point selection module is electrically connected to the output terminal of the injection intensity detection module, and is used to obtain a reference voltage based on the differential signal amplitude and the DC voltage. Furthermore, based on the DC voltage and the reference voltage, a preset number of digital signals are output using a preset number of comparators; Furthermore, based on the preset number of digital signals, a DC bias voltage is determined using digital logic gates; The frequency divider body is electrically connected to the output terminal of the DC bias point selection module, and is used to adjust the DC bias voltage of the gate of the parallel dual MOS transistor according to the DC bias voltage, and output the frequency division signal.

2. The adaptively adjustable injection-locked frequency divider according to claim 1, characterized in that, The DC voltage is linearly related to the amplitude of the differential signal.

3. The adaptively adjustable injection-locked frequency divider according to claim 2, characterized in that, The specific method for obtaining the reference voltage based on the differential signal amplitude and the DC voltage is as follows: Based on the differential signal amplitude and the DC voltage, the linear correlation coefficient between the differential signal amplitude and the DC voltage is obtained through simulation. The reference voltage is obtained based on the linear correlation coefficient and the amplitude of the differential signal.

4. The adaptively adjustable injection-locked frequency divider according to claim 1, characterized in that, The preset number of comparators is set according to the preset number of automatic adjustment segments.

5. The adaptively adjustable injection-locked frequency divider according to claim 4, characterized in that, The preset number of automatic adjustment segments is four, and the number of comparators is three.

6. The adaptively adjustable injection-locked frequency divider according to claim 1, characterized in that, The frequency divider body includes a parallel dual MOS transistor and an LC resonant network. The parallel dual MOS transistor is used to inject differential signals. The LC resonant network includes an AC coupling unit, an inductor, and a capacitor, which are connected in parallel.

7. An adaptively adjustable injection-locked frequency divider according to claim 6, characterized in that, The AC coupling unit employs a cross-coupling circuit consisting of two MOS transistors, two capacitors, and two resistors, with the sources of both MOS transistors grounded.

8. The adaptively adjustable injection-locked frequency divider according to claim 1, characterized in that, The injection-locked frequency divider also includes a power supply device for providing power support to the frequency divider body, the injection intensity detection module, and the DC bias point selection module.

9. An adaptively adjustable injection-locked frequency divider according to claim 8, characterized in that, The injection intensity detection module, the DC bias point selection module, and the power supply device are integrated on the frequency divider body.

10. An adaptive adjustment method for an injection-locked frequency divider, characterized in that, The adaptive adjustment method is applied to an adaptively adjusted injection-locked frequency divider according to any one of claims 1-9, comprising: Obtain the amplitude of the differential signal injected by the parallel dual MOS transistors; The DC voltage is obtained based on the amplitude of the differential signal; Based on the differential signal amplitude and the DC voltage, the corresponding reference voltage is obtained through simulation. Using a preset number of comparators, a preset number of digital signals are output based on the DC voltage and the reference voltage; Based on the preset number of digital signals, a DC bias voltage is selected using digital logic gates; Based on the DC bias voltage, the DC bias voltage of the gates of the parallel dual MOS transistors is adjusted, and a frequency division signal is output.

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