High gain low power comparator with output mismatch self-calibration
By designing an output offset self-calibration unit, the limitations of traditional comparators in terms of gain and power consumption are solved, realizing a high-gain, low-power comparator, reducing offset error and improving operation speed, which is suitable for high-precision analog-to-digital converter design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING MXTRONICS CORP
- Filing Date
- 2023-02-21
- Publication Date
- 2026-05-29
AI Technical Summary
Traditional comparators have limitations in improving gain and reducing power consumption, especially due to the reduced operation speed caused by offset error and increased circuit load. Furthermore, existing offset storage technology struggles to balance the conflicting requirements of circuit stability and preamplifier gain.
An output offset self-calibration unit is adopted, which realizes the storage and calibration of offset error through the matching of switches, capacitors and NMOS transistors, avoiding the introduction of additional coupling capacitors. A multi-stage preamplifier cascade structure is designed, and a matching output offset self-calibration unit is designed at the output of each preamplifier stage.
The comparator gain was increased without increasing power consumption, offset error was reduced, chip area and circuit complexity were saved, and the high switching speed and flexibility of the comparator were maintained.
Smart Images
Figure CN116260464B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of mixed-signal integrated circuit technology, and more particularly to a high-gain, low-power comparator and analog-to-digital converter with output offset self-calibration. Background Technology
[0002] With the continuous development of semiconductor processing technology, integrated circuits have entered the "post-Moore's Law era," and device performance has been greatly improved. The performance of mixed-signal integrated circuits has also been continuously upgraded. As the core module of analog-to-digital converter circuits, the comparator's comparison accuracy is limited by offset error, which in turn restricts the development of analog-to-digital converters.
[0003] like Figure 1 and Figure 2 As shown, traditional comparators typically employ a preamplifier cascaded latch structure. The high gain of the preamplifier reduces the influence of the inherent offset of the latch. Input offset storage and output offset storage techniques are then used, with the preamplifier offset stored through coupling capacitors. Offset calibration is achieved at different operating phases. However, the introduction of coupling capacitors increases the circuit load and reduces the comparator's operating speed.
[0004] Input offset storage technology typically requires a large coupling capacitance value, high circuit closed-loop stability, and is susceptible to clock feedthrough effects. Output offset storage technology stores the amplified offset error. To ensure that the preamplifier output is not saturated, its gain cannot be too high, but this also limits the preamplifier's ability to suppress the inherent offset of the latch. Summary of the Invention
[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and propose a high-gain, low-power comparator with self-calibrating output offset. This comparator improves the comparator gain without significantly increasing power consumption, effectively reduces comparator offset error, saves chip area, and meets the design requirements of high-precision, low-power analog-to-digital converters.
[0006] The technical solution adopted in this invention is as follows:
[0007] A high-gain, low-power comparator with output offset self-calibration includes a sampling switch, a preamplifier, an output offset self-calibration unit, and an output dynamic latch.
[0008] The comparator's operating phase is divided into the sampling common-mode signal phase and the sampling input signal operation phase. In the sampling common-mode signal phase, the sampling switch samples the common-mode signal VCM and transmits it to the input of the preamplifier. At this time, the preamplifier amplifies the offset error signal and transmits the amplified result to the output offset self-calibration unit and the output dynamic latch. The output offset self-calibration unit completes the offset error storage, and the output dynamic latch outputs a reset.
[0009] During the phase operation of the sampled input signal, the sampling switch samples the differential input signals VINP and VINN and transmits them to the input of the preamplifier. At this time, the preamplifier amplifies the differential input signal and transmits the amplified result to the output offset self-calibration unit and the output dynamic latch. The output offset self-calibration unit completes the offset error self-calibration, and the output dynamic latch updates the output result.
[0010] Furthermore, the sampling switches are differential structures, including input signal sampling switches SW1 and SW2, and common-mode signal sampling switches SW3, SW4 and SW11; respectively referred to as the first switch SW1, the second switch SW2, the third switch SW3, the fourth switch SW4 and the eleventh switch SW11;
[0011] The first terminal of the first switch SW1 is connected to the positive input signal VINP, and the second terminal of the first switch SW1 is simultaneously connected to the positive input terminal of the preamplifier, the first terminal of the third switch SW3, and the second terminal of the eleventh switch SW11; the first terminal of the second switch SW2 is connected to the negative input signal VINN, and the second terminal of the second switch SW2 is simultaneously connected to the negative input terminal of the preamplifier, the first terminal of the fourth switch SW4, and the first terminal of the eleventh switch SW11; the second terminals of the third switch SW3 and the fourth switch SW4 are simultaneously connected to the common-mode signal VCM.
[0012] Furthermore, the common-mode signal sampling switches SW3, SW4, and SW11 operate in non-overlapping clock phases with the input signal sampling switches SW1 and SW2.
[0013] Furthermore, the output offset self-calibration unit includes a first offset storage capacitor C1, a fifth switch SW5, a sixth switch SW6, a ninth switch SW9, a ninth NMOS transistor M9, a second offset storage capacitor C2, a seventh switch SW7, an eighth switch SW8, a tenth switch SW10, and a tenth NMOS transistor M10.
[0014] The first terminal of the first offset storage capacitor C1 is connected to GND, and the second terminal is simultaneously connected to the gate of the ninth NMOS transistor M9 and the first terminal of the sixth switch SW6; the substrate and source of the ninth NMOS transistor M9 are both connected to GND, and the drain is simultaneously connected to the negative output terminal of the preamplifier and the first terminal of the fifth switch SW5; the second terminal of the fifth switch SW5 is simultaneously connected to the second terminal of the sixth switch SW6 and the first terminal of the ninth switch SW9; the second terminal of the ninth switch SW9 is connected to VDD; the first terminal of the second offset storage capacitor C2 is connected to GND, and the second terminal is simultaneously connected to the gate of the tenth NMOS transistor M10 and the first terminal of the eighth switch SW8; the substrate and source of the tenth NMOS transistor M10 are both connected to GND, and the drain is connected to the positive output terminal of the preamplifier and the first terminal of the seventh switch SW7; the second terminal of the seventh switch SW7 is simultaneously connected to the second terminal of the eighth switch SW8 and the first terminal of the tenth switch SW10; the second terminal of the tenth switch SW10 is connected to VDD.
[0015] Furthermore, the fifth switch SW5, the sixth switch SW6, the seventh switch SW7 and the eighth switch SW8 operate in the same phase as the common-mode signal sampling switches SW3, SW4 and SW5, and the comparator offset error is stored during the enable period.
[0016] Switches 9 and 10 operate in opposite phases that do not overlap with the common-mode signal sampling switches SW3, SW4 and SW5, ensuring rapid storage of output offset errors and improving the comparator signal setup speed.
[0017] Furthermore, the output dynamic latch includes a reset switch SW12 and a latch LATCH, and the reset switch SW12 is referred to as the twelfth switch SW12.
[0018] The first terminal of the twelfth switch SW12 is simultaneously connected to the positive output terminal of the preamplifier, the drain of the tenth NMOS transistor M10, the first terminal of the seventh switch SW7, and the VN terminal of the latch LATCH; the second terminal of the twelfth switch SW12 is simultaneously connected to the negative output terminal of the preamplifier, the drain of the ninth NMOS transistor M9, the first terminal of the fifth switch SW5, and the VP terminal of the latch LATCH; the output terminal of the latch LATCH is connected to DOUT.
[0019] Furthermore, the twelfth switch SW12 is reset and cleared during the initial pulse phase of the sampled common-mode signal.
[0020] Furthermore, the preamplifier can be designed as a comparator structure with multiple cascaded preamplifiers, and a matching output offset self-calibration unit can be designed at the output of each preamplifier stage.
[0021] Furthermore, the comparator includes a sampled common-mode signal phase and a sampled input signal operation phase, and the clocks of the two phases are non-overlapping clocks;
[0022] When the comparator is operating in sampling the phase of the common-mode signal, the third switch SW3, the fourth switch SW4, and the eleventh switch SW11 are closed first, and the positive and negative input terminals of the preamplifier are shorted and connected to the common-mode signal VCM.
[0023] The twelfth switch SW12 is reset during the initial pulse phase of the common-mode signal sampling, resetting the positive and negative output terminals of the preamplifier and simultaneously resetting the latch LATCH.
[0024] The sixth switch SW6 and the eighth switch SW8 close earlier than the fifth switch SW5 and the seventh switch SW7 after the twelfth switch SW12 is reset. The offset storage capacitors C1 and C2 realize offset error charging calculation during the closing of the fifth switch SW5, the sixth switch SW6, the seventh switch SW7 and the eighth switch SW8.
[0025] Subsequently, the sixth switch SW6 and the eighth switch SW8 are disconnected before the fifth switch SW5 and the seventh switch SW7, thus completing the accurate storage of the comparator offset error.
[0026] Furthermore, when the comparator operates in the sampling input signal operation phase, the first switch SW1 and the second switch SW2 are closed. The positive input signal VINP is connected to the positive input terminal of the preamplifier through the first switch SW1, and the negative input signal VINN is connected to the negative input terminal of the preamplifier through the second switch SW2. At this time, the preamplifier amplifies the difference between the positive input signal VINP and the negative input signal VINN. The offset error at the negative output terminal of the preamplifier is discharged through the path formed by the offset storage capacitor C1 and the NMOS transistor M9 connected to it. The offset error at the positive output terminal of the preamplifier is discharged through the path formed by the offset storage capacitor C2 and the NMOS transistor M10 connected to it, thus realizing output offset self-calibration. At this time, the differential output signal of the preamplifier is then processed by the latch LATCH operation to obtain the comparison result DOUT corresponding to the differential input signal VINP-VINN of the comparator.
[0027] Furthermore, when the comparator operates in the sampling input signal operation phase, the ninth switch SW9 and the tenth switch SW10 are in the closed state, transmitting the power supply signal VDD to the first terminal of the ninth switch SW9 and the tenth switch SW10, thereby accelerating the establishment speed of the offset voltage of the offset storage capacitors C1 and C2.
[0028] Compared with the prior art, the present invention has the following obvious advantages:
[0029] (1) In addition to the traditional comparator structure, the present invention adopts an output offset self-calibration unit, which realizes the storage and calibration of offset error through the matching of switches, capacitors and NMOS transistors, thereby reducing the comparator offset error.
[0030] (2) Since the present invention uses an output offset self-calibration unit circuit, no additional coupling capacitor is required. While ensuring the comparator switching speed, the comparator can maintain a high gain, which greatly reduces the impact of comparator offset error, and also reduces the power consumption, area and implementation complexity of the circuit.
[0031] (3) The output offset self-calibration unit used in this invention can be designed with a comparator structure of multi-stage preamplifier cascade according to system requirements, and a matching output offset self-calibration unit is designed at the output end of each preamplifier stage, which has strong technical portability.
[0032] (4) The present invention can design matching timing signals according to the requirements of different analog-to-digital converter architectures, and has a large design space. Attached Figure Description
[0033] Figure 1 This is a schematic diagram of a traditional comparator topology;
[0034] Figure 2 This is a schematic diagram of an existing comparator topology that uses input offset storage technology and output offset storage technology.
[0035] Figure 3 This is a schematic diagram of the output offset self-calibrating high-gain low-power comparator topology of the present invention;
[0036] Figure 4 This is a schematic diagram of the operating timing of the comparator of the present invention;
[0037] Figure 5 This is a schematic diagram of the comparator sampling common-mode signal phase circuit of the present invention;
[0038] Figure 6 This invention provides a schematic diagram of the phase calculation circuit for sampling the input signal of the comparator. Detailed Implementation
[0039] The present invention proposes a high-gain, low-power comparator with self-calibrating output offset, which is described in detail below with reference to the accompanying drawings and embodiments.
[0040] This invention proposes a high-gain, low-power comparator with self-calibrated output offset, such as... Figure 3 As shown, the feature is that it includes a sampling switch 100, a preamplifier 200, an output offset self-calibration unit 300, and an output dynamic latch 400. The specific circuit structure and connection relationship of each part are described below.
[0041] The sampling switch 100 is a differential structure, including input signal sampling switches SW1 and SW2 and common-mode signal sampling switches SW3, SW4 and SW11. The first terminal of the first switch SW1 is connected to the positive input signal VINP, and the second terminal is connected to the positive input terminal of the preamplifier 200, the first terminal of the third switch SW3 and the second terminal of the eleventh switch SW11. The first terminal of the second switch SW2 is connected to the negative input signal VINN, and the second terminal is connected to the negative input terminal of the preamplifier 200, the first terminal of the fourth switch SW4 and the first terminal of the eleventh switch SW11. The second terminals of the third switch SW3 and the fourth switch SW4 are connected to the common-mode signal VCM.
[0042] The preamplifier 200 adopts a fully differential structure, with differential input and differential output terminals.
[0043] The output offset self-calibration unit 300 consists of a first offset storage capacitor C1, a fifth switch SW5, a sixth switch SW6, a ninth switch SW9, a ninth NMOS transistor M9, a second offset storage capacitor C2, a seventh switch SW7, an eighth switch SW8, a tenth switch SW10, and a tenth NMOS transistor M10. The first terminal of the first offset storage capacitor C1 is connected to GND, and the second terminal is connected to both the gate of the ninth NMOS transistor M9 and the first terminal of the sixth switch SW6. The substrate and source of the ninth NMOS transistor M9 are both connected to GND, and the drain is connected to both the negative output terminal of the preamplifier 200 and the first terminal of the fifth switch SW5. The second terminal of switch SW5 is simultaneously connected to the second terminal of the sixth switch SW6 and the first terminal of the ninth switch SW9; the second terminal of the ninth switch SW9 is connected to VDD; the first terminal of the second offset storage capacitor C2 is connected to GND, and the second terminal is simultaneously connected to the gate of the tenth NMOS transistor M10 and the first terminal of the eighth switch SW8; the substrate and source of the tenth NMOS transistor M10 are both connected to GND, and the drain is connected to the positive output terminal of the preamplifier 200 and the first terminal of the seventh switch SW7; the second terminal of the seventh switch SW7 is simultaneously connected to the second terminal of the eighth switch SW8 and the first terminal of the tenth switch SW10; the second terminal of the tenth switch SW10 is connected to VDD.
[0044] The output dynamic latch 400 includes a reset switch SW12 and a latch LATCH. The first terminal of the twelfth switch SW12 is connected to the positive output terminal of the preamplifier 200, the drain of the tenth NMOS transistor M10, the first terminal of the seventh switch SW7, and the VN terminal of the latch LATCH. The second terminal of the twelfth switch SW12 is connected to the negative output terminal of the preamplifier 200, the drain of the ninth NMOS transistor M9, the first terminal of the fifth switch SW5, and the VP terminal of the latch LATCH. The output terminal of the latch LATCH is connected to DOUT.
[0045] The timing sequence of the comparator in this invention is as follows: Figure 4 As shown, it mainly includes the sampling common-mode signal phase and the sampling input signal operation phase, wherein the clocks of the two phases are non-overlapping clocks.
[0046] Specifically, the circuit diagram of the comparator when sampling the phase of the common-mode signal is as follows: Figure 5 As shown, the third switch SW3, the fourth switch SW4, and the eleventh switch SW11 are closed first, shorting the positive and negative input terminals of the preamplifier 200 and connecting them to the common-mode signal VCM; the twelfth switch SW12 is reset during the initial pulse phase of the sampled common-mode signal, resetting the positive and negative output terminals of the preamplifier 200 and simultaneously resetting the latch LATCH; the sixth switch SW6 and the eighth switch SW8 are closed before the fifth switch SW5 and the seventh switch SW7 after the twelfth switch SW12 is reset, and the offset storage capacitors C1 and C2 perform offset error charging calculations during the closing of the fifth switch SW5, the sixth switch SW6, the seventh switch SW7, and the eighth switch SW8; subsequently, the sixth switch SW6 and the eighth switch SW8 are opened before the fifth switch SW5 and the seventh switch SW7, completing the accurate storage of the comparator offset error.
[0047] The circuit diagram of the comparator when sampling the input signal and calculating the phase is shown below. Figure 6 As shown, when the first switch SW1 and the second switch SW2 are closed, the positive input signal VINP is connected to the positive input terminal of the preamplifier 200 through the first switch SW1, and the negative input signal VINN is connected to the negative input terminal of the preamplifier 200 through the second switch SW2. At this time, the preamplifier 200 amplifies the difference between the positive input signal VINP and the negative input signal VINN. The offset error at the negative output terminal of the preamplifier 200 is discharged through the path formed by the offset storage capacitor C1 and the NMOS transistor M9 connected to it, and the offset error at the positive output terminal of the preamplifier 200 is discharged through the path formed by the offset storage capacitor C2 and the NMOS transistor M10 connected to it, thus realizing output offset self-calibration. At this time, the differential output signal of the preamplifier 200 is then processed by the latch LATCH operation to obtain the comparison result DOUT corresponding to the differential input signal VINP-VINN of the comparator.
[0048] Furthermore, when the comparator operates in the sampling input signal operation phase, the ninth switch SW9 and the tenth switch SW10 are in the closed state, transmitting the power supply signal VDD to the first terminals of the ninth switch SW9 and the tenth switch SW10, effectively accelerating the offset voltage establishment speed of the offset storage capacitors C1 and C2.
[0049] The contents not described in detail in this specification are common knowledge to those skilled in the art. Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications or variations within the scope of the appended claims.
Claims
1. A high-gain, low-power comparator with self-calibrating output offset, characterized in that: It includes a sampling switch (100), a preamplifier (200), an output offset self-calibration unit (300), and an output dynamic latch (400). The comparator's operating phase is divided into the sampling common-mode signal phase and the sampling input signal operation phase. In the sampling common-mode signal phase, the sampling switch (100) samples the common-mode signal VCM and transmits it to the input of the preamplifier (200). At this time, the preamplifier (200) amplifies the offset error signal and transmits the amplified result to the output offset self-calibration unit (300) and the output dynamic latch (400). The output offset self-calibration unit (300) completes the offset error storage, and the output dynamic latch (400) outputs a reset. During the sampling input signal operation phase, the sampling switch (100) samples the differential input signals VINP and VINN and transmits them to the input terminal of the preamplifier (200). At this time, the preamplifier (200) amplifies the differential input signal and transmits the amplified result to the output offset self-calibration unit (300) and the output dynamic latch (400). The output offset self-calibration unit (300) completes the offset error self-calibration, and the output dynamic latch (400) updates the output result. The output offset self-calibration unit (300) includes a first offset storage capacitor C1, a fifth switch SW5, a sixth switch SW6, a ninth switch SW9, a ninth NMOS transistor M9, a second offset storage capacitor C2, a seventh switch SW7, an eighth switch SW8, a tenth switch SW10, and a tenth NMOS transistor M10. The first offset storage capacitor C1 has its first terminal connected to GND, and its second terminal connected to both the gate of the ninth NMOS transistor M9 and the first terminal of the sixth switch SW6. The substrate and source of the ninth NMOS transistor M9 are both connected to GND, and its drain is connected to both the negative output terminal of the preamplifier (200) and the first terminal of the fifth switch SW5. The second terminal of the fifth switch SW5 is connected to both the second terminal of the sixth switch SW6 and the first terminal of the ninth switch SW9. The second terminal of the ninth switch SW9 is connected to VDD. The first terminal of the second offset storage capacitor C2 is connected to GND, and its second terminal is connected to both the gate of the tenth NMOS transistor M10 and the first terminal of the eighth switch SW8. The substrate and source of the tenth NMOS transistor M10 are both connected to GND, and its drain is connected to both the positive output terminal of the preamplifier (200) and the first terminal of the seventh switch SW7. The second terminal of the seventh switch SW7 is connected to both the second terminal of the eighth switch SW8 and the first terminal of the tenth switch SW10. The second terminal of the tenth switch SW10 is connected to VDD.
2. The high-gain, low-power comparator with output offset self-calibration according to claim 1, characterized in that: The sampling switch (100) is a differential structure, including input signal sampling switches SW1 and SW2, common-mode signal sampling switches SW3, SW4 and SW11; respectively referred to as the first switch SW1, the second switch SW2, the third switch SW3, the fourth switch SW4 and the eleventh switch SW11; The first terminal of the first switch SW1 is connected to the positive input signal VINP. The second terminal of the first switch SW1 is simultaneously connected to the positive input terminal of the preamplifier (200), the first terminal of the third switch SW3, and the second terminal of the eleventh switch SW11. The first terminal of the second switch SW2 is connected to the negative input signal VINN. The second terminal of the second switch SW2 is simultaneously connected to the negative input terminal of the preamplifier (200), the first terminal of the fourth switch SW4, and the first terminal of the eleventh switch SW11. The second terminals of the third switch SW3 and the fourth switch SW4 are simultaneously connected to the common-mode signal VCM.
3. A high-gain, low-power comparator with output offset self-calibration according to claim 2, characterized in that: The common-mode signal sampling switches SW3, SW4, and SW11 operate in non-overlapping clock phases with the input signal sampling switches SW1 and SW2.
4. A high-gain, low-power comparator with output offset self-calibration according to claim 3, characterized in that: The fifth switch SW5, the sixth switch SW6, the seventh switch SW7 and the eighth switch SW8 operate in the same phase as the common-mode signal sampling switches SW3, SW4 and SW5, and the comparator offset error is stored during the enable period; Switches 9 and 10 operate in opposite phases that do not overlap with the common-mode signal sampling switches SW3, SW4 and SW5, ensuring rapid storage of output offset errors and improving the comparator signal setup speed.
5. A high-gain, low-power comparator with output offset self-calibration according to claim 3, characterized in that: The output dynamic latch (400) includes a reset switch SW12 and a latch LATCH, and the reset switch SW12 is referred to as the twelfth switch SW12; The first terminal of the twelfth switch SW12 is simultaneously connected to the positive output terminal of the preamplifier (200), the drain of the tenth NMOS transistor M10, the first terminal of the seventh switch SW7, and the VN terminal of the latch LATCH; the second terminal of the twelfth switch SW12 is simultaneously connected to the negative output terminal of the preamplifier (200), the drain of the ninth NMOS transistor M9, the first terminal of the fifth switch SW5, and the VP terminal of the latch LATCH; the output terminal of the latch LATCH is connected to DOUT.
6. A high-gain, low-power comparator with output offset self-calibration according to claim 5, characterized in that: The twelfth switch SW12 is reset to zero during the initial pulse phase of the sampled common-mode signal.
7. A high-gain, low-power comparator with output offset self-calibration according to claim 5, characterized in that: The preamplifier can be designed as a comparator structure with multiple preamplifiers cascaded, and a matching output offset self-calibration unit (300) can be designed at the output of each preamplifier stage.
8. A high-gain, low-power comparator with output offset self-calibration according to claim 5, characterized in that: The comparator includes a sampled common-mode signal phase and a sampled input signal operation phase, and the clocks of the two phases are non-overlapping clocks; When the comparator operates in sampling the phase of the common-mode signal, the third switch SW3, the fourth switch SW4, and the eleventh switch SW11 are closed first, and the positive and negative input terminals of the preamplifier (200) are shorted and connected to the common-mode signal VCM. The twelfth switch SW12 is reset during the initial pulse phase of the common-mode signal sampling, resetting the positive and negative output terminals of the preamplifier (200) and simultaneously resetting the latch LATCH. The sixth switch SW6 and the eighth switch SW8 close earlier than the fifth switch SW5 and the seventh switch SW7 after the twelfth switch SW12 is reset. The offset storage capacitors C1 and C2 realize offset error charging calculation during the closing of the fifth switch SW5, the sixth switch SW6, the seventh switch SW7 and the eighth switch SW8. Subsequently, the sixth switch SW6 and the eighth switch SW8 are disconnected before the fifth switch SW5 and the seventh switch SW7, thus completing the accurate storage of the comparator offset error.
9. A high-gain, low-power comparator with output offset self-calibration according to claim 8, characterized in that: When the comparator operates in the sampling input signal operation phase, the first switch SW1 and the second switch SW2 are closed. The positive input signal VINP is connected to the positive input terminal of the preamplifier (200) through the first switch SW1, and the negative input signal VINN is connected to the negative input terminal of the preamplifier (200) through the second switch SW2. At this time, the preamplifier (200) amplifies the difference between the positive input signal VINP and the negative input signal VINN. The offset error of the negative output terminal of the preamplifier (200) is discharged through the path formed by the offset storage capacitor C1 and the NMOS transistor M9 connected to it. The offset error of the positive output terminal of the preamplifier (200) is discharged through the path formed by the offset storage capacitor C2 and the NMOS transistor M10 connected to it, realizing output offset self-calibration. At this time, the differential output signal of the preamplifier (200) is then processed by the latch LATCH to obtain the comparison result DOUT corresponding to the differential input signal VINP-VINN of the comparator.
10. A high-gain, low-power comparator with output offset self-calibration according to claim 9, characterized in that: When the comparator operates in the sampling input signal operation phase, the ninth switch SW9 and the tenth switch SW10 are in the closed state, transmitting the power supply signal VDD to the first terminal of the ninth switch SW9 and the tenth switch SW10, thereby accelerating the establishment speed of the offset voltage of the offset storage capacitors C1 and C2.