Method for time synchronization in cross-device link aggregation for distributed elastic network interconnection

Abstract

The present invention discloses a method for time synchronization in cross-device link aggregation of distributed elastic network interconnection. In the cross-device link aggregation of distributed elastic network interconnection, a corresponding interconnection bus is set in the link aggregation group IRC LAG scenario of interconnection between relay devices, so that adjacent relay devices can achieve time synchronization through the interconnection bus. The present invention provides a method for time synchronization in cross-device link aggregation of distributed elastic network interconnection, which can reduce the number of hops and improve data transmission efficiency without violating the role allocation principle compared with the prior art.

Description

Technical Field

[0001] The present invention relates to the field of communications, and more specifically, to a method for time synchronization in cross-device link aggregation of distributed elastic network interconnection. Background Art

[0002] Distributed Resilient Network Interconnects (DRNI) is a cross-device link aggregation technology based on the IEEE 802.1AX protocol. DRNI virtualizes two physical devices into one device at the aggregation level to achieve cross-device link aggregation, thereby providing device-level redundancy protection and traffic load sharing.

[0003] Figure 1-3 Three connection modes of the cross-device link aggregation scenario are shown, among which IRC LAG (Intra-Relay Connection Link Aggregation Group) represents the link aggregation group of interconnection between relays, and DRNI LAG (Distributed Resilient Network Interconnects Link Aggregation Group) represents the link aggregation group of cross-device link aggregation.

[0004] After the device runs the time synchronization (Precision Time Protocol, PTP) function, the device's physical port roles are divided into three types: MasterPort, SlavePort, and PassivePort. The ports of the master clock device (Grandmaster PTP Instance) in the network are all MasterPort. In addition to the master clock, all other clock devices (PTP Instances) in the network have only one SlavePort, where the SlavePort is the port of the clock device (PTPInstances) closest to the master clock. In terms of clock, except for the SlavePort port, when other ports find a loop in the clock source or a suboptimal clock source, the port will be set to a passive port (PassivePort).

[0005] Figure 4 Shows the various roles of network device ports in the time synchronization function.

[0006] When using the time synchronization function in the cross-device link aggregation scenario of DRNI, there are two cases depending on whether the PTP service is carried out on the IRC LAG. The corresponding device port roles are described as follows:

[0007] Case 1: Do not use the PTP function on the IRC LAG, with the following Figure 5-7 Three port roles:

[0008] Case 2: Using PTP on IRC LAG with Figure 8-10 Three port roles:

[0009] As can be seen from the above, in the prior art, each relay device uses its own local clock. Since the time synchronization function has an upper limit on the number of hops under the condition of ensuring accuracy, the data transmission efficiency between devices is restricted. Summary of the invention

[0010] An object of the present invention is to solve at least the above problems and / or disadvantages and to provide at least the advantages which will be described hereinafter.

[0011] In order to achieve these objectives and other advantages of the present invention, a method for time synchronization in cross-device link aggregation of distributed elastic network interconnection is provided. In the cross-device link aggregation of distributed elastic network interconnection, a corresponding interconnection bus is set in the link aggregation group IRC LAG scenario where relay devices are interconnected, so that adjacent relay devices can achieve time synchronization through the interconnection bus.

[0012] Preferably, the interconnection bus includes: a clock bus and / or a data bus I.

[0013] Preferably, in the cross-device link aggregation of the distributed elastic network interconnection, the following three data transmission schemes are obtained through the interconnection bus and the existing data bus II in the network:

[0014] Solution 1: Use the clock bus and data bus II to coordinate, use the clock bus to achieve time synchronization and sharing between adjacent relay devices, and use data bus II for data transmission;

[0015] Solution 2: directly use the interconnection bus to achieve data transmission, time synchronization and sharing between adjacent relay devices;

[0016] Solution three uses data bus II to achieve data transmission between adjacent relay devices, while time synchronization is achieved through the local clock in each relay device.

[0017] Preferably, the adjacent relay devices are interconnected by two links.

[0018] Preferably, the type of the accessed bus is detected by bus detection between two adjacent relay devices connected by an interconnected bus;

[0019] Among them, between two interconnected adjacent relay devices, if the detection result is that the clock bus and data bus I are connected at the same time or the data bus II is connected, this type of situation is defined as event A;

[0020] If the detection result shows that the clock bus and the data bus I are not connected at the same time, this type of situation is defined as event B.

[0021] Preferably, in event A, when the time synchronization function is running, there is only one slave port SlavePort in the two interconnected relay devices;

[0022] And when the master clock is outside the two interconnected relay devices, the local clock of the relay device where the SlavePort is located works, and the local clock of the other device does not work;

[0023] If the master clock is one of the two interconnected relay devices, all ports of the interconnected relay devices are master ports.

[0024] Preferably, in event B, the local clock of each relay device is in working state, and at least one port of the two interconnected relay devices is a SlavePort;

[0025] If the master clock is one of the two interconnected relay devices, all ports of the device are MasterPort.

[0026] Preferably, in cross-device link aggregation of distributed elastic network interconnection using an interconnect bus, there are three ways to obtain the port role in the DRNI scenario, which are listed as follows:

[0027] Method 1: Do not connect to the interconnection bus, use data bus II, run time synchronization function, and obtain the port role of each device;

[0028] Method 2: Connect the clock bus, use data bus II, run the time synchronization function, and obtain the port role of each device;

[0029] Method three is to directly use the interconnection bus and the operation time synchronization function to obtain the port role of each device.

[0030] The present invention includes at least the following beneficial effects: Compared with the prior art, the present invention can regard two same-level, adjacent relay devices as one device without violating the role allocation principle, and enable the two devices to share the local clock of one of the devices through the clock bus, thereby reducing the number of device hops and improving data transmission efficiency.

[0031] Other advantages, objectives and features of the present invention will be embodied in part through the following description, and in part will be understood by those skilled in the art through study and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1It is one of the connection modes for cross-device link aggregation scenarios in the prior art;

[0033] Figure 2 It is another connection method for cross-device link aggregation scenarios in the prior art;

[0034] Figure 3 It is another connection method for cross-device link aggregation scenarios in the prior art;

[0035] Figure 4 It is the port role of each network device under the time synchronization function in the prior art;

[0036] Figure 5 In the first case of the prior art, the device port role when the aggregation system acts as the master clock;

[0037] Figure 6 In the case 1 of the prior art, the device port role when the DRNI system 1 is used as the master clock;

[0038] Figure 7 In the first case of the prior art, the device port role when the DRNI system 1A is used as the master clock;

[0039] Figure 8 In the second case of the prior art, the device port role when the aggregation system acts as the master clock;

[0040] Fig. 9 In the second case of the prior art, the device port role when the DRNI system 1A is used as the master clock;

[0041] Fig.10 In the second case of the prior art, the device port role when the DRNI system 1A is used as the master clock;

[0042] Fig.11 It is a connection diagram of two relay devices connected by an interconnection bus;

[0043] Fig.12 It is a schematic diagram of the interconnection bus core line layout including the clock bus and the data bus I of the present invention;

[0044] Fig.13 The device port role when the aggregation system is used as the master clock after adopting the interconnection bus of the present invention;

[0045] Fig.14 The device port roles when the DRNI system 1A1B is used as the master clock after the interconnection bus of the present invention is adopted;

[0046] Fig.15 After adopting the interconnection bus of the present invention, the DRNI system 1A1B acts as the device port role of the master clock. DETAILED DESCRIPTION

[0047] The present invention is further described in detail below in conjunction with the accompanying drawings so that those skilled in the art can implement the invention with reference to the description.

[0048] Since the time synchronization function is limited to 7 hops to ensure accuracy, and since the time synchronization function only runs on the physical ports in DRNI and not on the aggregated ports in DRNI, this patent further designs a new time synchronization mechanism, method and device that does not require an increase in hops for the IRC LAG area between distributed devices. The specific design contents are as follows:

[0049] 1. For the cross-device link aggregation scenario of DRNI, a new interconnection bus is designed in the IRC LAG area between two devices that are close to each other. The interconnection bus includes data bus I and clock bus. The designed interconnection bus is different from the traditional IRC LAG bus (or traditional IRC LAG data bus) that only contains data bus II (Ethernet data bus). On the basis of the original traditional IRC LAG bus, after adding the interconnection bus newly designed by this patent, three usage methods are realized:

[0050] 1.1. Use the clock bus in the newly designed interconnect bus, but do not use the data bus I in the interconnect bus. In this case, data can be transmitted using the original traditional IRC LAG bus.

[0051] 1.2. Use the clock bus and data bus I in the newly designed interconnect bus, and no longer use the original traditional IRCLAG bus;

[0052] 1.3. Do not use the newly designed interconnect bus. Instead, use the original traditional IRC LAG bus.

[0053] 2. The introduction of the clock bus inside the newly designed interconnect bus realizes the unification and sharing of the clocks of the two devices, thereby eliminating the traditional mechanism of transferring time between the two devices through port role allocation. At this time, IRC LAG is no longer needed to allocate time synchronization port roles between the two devices. In particular, the premise for the previous allocation is that the clocks of the two devices are not shared (each uses its own), and it is necessary to further synchronize the time between the two devices through role allocation.

[0054] 3. The designed interconnection bus also connects two devices, which is consistent with the traditional connection of two IRC LAG buses in the number of connections, and has the same link reliability. The time bus or data bus I of each interconnection bus is set to one, so it is equivalent to the two interconnection buses being redundant to each other, making the data transmission link more reliable and matching the existing data bus II connection method. Here, the data bus II or data bus I can be set to an Ethernet cable as needed.

[0055] 4. This patent has newly designed a bus detection function for the interconnection bus between two devices. The bus detection function runs on each device and detects the type of bus connected between the two devices (the clock bus of the interconnection bus, and / or the data bus I of the interconnection bus, and / or the traditional IRC LAG bus).

[0056] 4.1. When the clock bus and data bus I (or traditional IRC LAG bus) of the interconnect bus are connected at the same time, the bus detection function of the two devices detects that the event is A. In the case of event A, when the time synchronization function is running, the logical device composed of the two devices will still only have one SlavePort.

[0057] 4.1.1. When the master clock is outside the two devices, it is calculated that the local clock of the device where the SlavePort is located works, while the local clock of the other device in the two does not work (that is, the local clock of the device where the port connected to the master clock is located works, while the local clock of the other device in the two does not work).

[0058] 4.1.2. If the master clock is one of the two stations, all ports of the two stations are MasterPort.

[0059] 4.2. When the clock bus and data bus I are not connected at the same time, the bus detection function of the two devices detects that the event is B. In the case of event B, when the time synchronization function is running, press Figure 5-10 The traditional mechanism works. The logical device composed of two devices still does not have only one SlavePort.

[0060] 4.2.1. When the master clock is outside these two devices, the local clocks of the two devices are both working.

[0061] 4.2.2. If the master clock is one of the two devices, all ports of this device are MasterPort, and the local clocks of the two devices are working.

[0062] 5. After implementing the design of the new interconnect bus device, a new mechanism is added and implemented based on the traditional mechanism and supports flexible selection between 2 different mechanisms:

[0063] 5.1. Traditional mechanisms and methods:

[0064] Without connecting to the interconnect bus, the traditional IRC LAG bus is used to run the time synchronization function and obtain the port role of each device;

[0065] 5.2. New mechanism and its two methods:

[0066] 5.2.1. Connect the clock bus in the interconnect bus, use the traditional IRC LAG bus, run the time synchronization function, and obtain the port role of each device;

[0067] 5.2.2. Connect to the interconnect bus, do not use the traditional IRC LAG bus, run the time synchronization function, and obtain the port role of each device.

[0068] 6. After the design and implementation of the new interconnect bus device, the port role status in several DRNI scenarios is as follows: Figure 13-15 :

[0069] Situation analysis and comparison:

[0070] 1) Improved Fig.13 Compared with the improved Figure 5 , Figure 8 Comparison: After the improvement, DRNI system 1 and DRNI system 2 have only one SlavePort.

[0071] 2) Improved Fig.14 Compared with the improved Fig. 9 Comparison: After the improvement, DRNI system 1A and DRNI system 1B are all MasterPort.

[0072] 3) Improved Fig.15 Compared with the improved Figure 7 , Fig.10 Comparison: After the improvement, DRNI system 2A and DRNI system 2B have only one SlavePort as a whole.

[0073] From the above, it can be seen that compared with the existing technology, this solution can be regarded as treating two same-level and adjacent relay devices as one device without violating the role allocation principle. Through the clock bus, the two devices share the local clock of one of the devices, reducing the number of device hops and improving data transmission efficiency.

[0074] The above solution is only an illustration of a preferred embodiment, but is not limited thereto. When implementing the present invention, appropriate replacement and / or modification can be performed according to user needs.

[0075] The number of devices and processing scales described here are used to simplify the description of the present invention. Applications, modifications and variations of the present invention will be obvious to those skilled in the art.

[0076] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and the embodiments. It can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily realized. Therefore, without departing from the general concept defined by the claims and equivalent scope, the present invention is not limited to the specific details and the illustrations shown and described here.

Claims

1. A method for time synchronization in cross-device link aggregation of distributed elastic network interconnection, characterized in that: In the cross-device link aggregation of the distributed elastic network interconnection, a corresponding interconnection bus is set in the link aggregation group IRC LAG scenario where the relay devices are interconnected, so that the adjacent relay devices can achieve time synchronization through the interconnection bus; The interconnection bus includes: a clock bus and a data bus I; In the cross-device link aggregation of distributed elastic network interconnection, the following three data transmission schemes are obtained through the interconnection bus and the existing data bus II in the network: Solution 1: Use the clock bus and data bus II to coordinate, use the clock bus to achieve time synchronization and sharing between adjacent relay devices, and use data bus II for data transmission; Solution 2: directly use the interconnection bus to achieve data transmission, time synchronization and sharing between adjacent relay devices; Solution three uses data bus II to achieve data transmission between adjacent relay devices, while time synchronization is achieved through the local clock in each relay device.

2. The method for time synchronization in cross-device link aggregation of distributed elastic network interconnection as claimed in claim 1, characterized in that: The interconnection buses of the adjacent relay devices are set to two.

3. The method for time synchronization in cross-device link aggregation of distributed elastic network interconnection as claimed in claim 1, characterized in that: The type of the accessed bus is detected by bus detection between two adjacent relay devices connected by an interconnected bus; Among them, between two interconnected adjacent relay devices, if the detection result is that the clock bus and data bus I are connected at the same time or the data bus II is connected, this type of situation is defined as event A; If the detection result shows that the clock bus and the data bus I are not connected at the same time, this type of situation is defined as event B.

4. The method for time synchronization in cross-device link aggregation of distributed elastic network interconnection as claimed in claim 3, characterized in that: In event A, when the time synchronization function is running, there is only one slave port SlavePort in the two interconnected relay devices; And when the master clock is outside the two interconnected relay devices, the local clock of the relay device where the SlavePort is located works, and the local clock of the other device does not work; If the master clock is one of the two interconnected relay devices, all ports of the interconnected relay devices are master ports.

5. The method for time synchronization in cross-device link aggregation of distributed elastic network interconnection as claimed in claim 3, characterized in that: In event B, the local clock of each relay device is in working state, and at least one port of the two interconnected relay devices is a SlavePort; If the master clock is one of the two interconnected relay devices, all ports of the device are MasterPort.

6. The method for time synchronization in cross-device link aggregation of distributed elastic network interconnection as claimed in claim 1, characterized in that: In cross-device link aggregation of distributed elastic network interconnection using interconnection buses, there are three ways to obtain port roles in DRNI scenarios, as listed below: Method 1: Do not connect to the interconnection bus, use data bus II, run time synchronization function, and obtain the port role of each device; Method 2: Connect the clock bus, use data bus II, run the time synchronization function, and obtain the port role of each device; Method three is to directly use the interconnection bus and the operation time synchronization function to obtain the port role of each device.

Images