Method for selective use of pulse plasma enhanced etching

Abstract

Embodiments of the present disclosure include a method of processing a substrate including etching a first dielectric material formed on a substrate disposed on a substrate support surface of a substrate support assembly disposed within a processing region of a plasma processing chamber. The etching process can include: delivering a process gas to the processing region, wherein the process gas includes a first fluorine-containing carbon gas and a first process gas; delivering a radio frequency signal to a first electrode using a radio frequency generator to form a plasma in the processing region; and establishing a first pulsed voltage waveform at a bias electrode disposed within the substrate support assembly using a first pulsed voltage waveform generator. The first pulsed voltage waveform includes a series of repeating pulsed waveform cycles each including a first portion occurring during a first time interval, a second portion occurring during a second time interval, and a peak-to-peak voltage. The pulsed voltage waveform is substantially constant during at least a portion of the second time interval.

Description

background Technical Field

[0002] The embodiments described herein generally relate to semiconductor device manufacturing hardware and processes, and more specifically to apparatus and methods for processing substrates in a plasma processing chamber. Background Technology

[0004] Reliably generating high aspect ratio features is one of the key technological challenges for next-generation very large-scale integration (VLSI) and ultra-large-scale integration (ULSI) of semiconductor devices. One method for forming high aspect ratio features uses plasma-assisted etching processes, such as reactive ion etching (RIE) plasma processes, to form high aspect ratio openings in material layers (such as dielectric layers) of a substrate. In a typical RIE plasma process, plasma is generated in the RIE processing chamber, and ions from the plasma are accelerated toward the substrate surface to form openings in a material layer disposed beneath a mask layer formed on the substrate surface.

[0005] A typical reactive ion etch (RIE) plasma processing chamber includes a radio frequency (RF) bias generator that supplies an RF voltage to a "power electrode" (e.g., a bias electrode), such as a metal plate adjacent to the "electrostatic chuck" (ESC) assembly, more commonly referred to as a "cathode." The power electrode is capacitively coupled to the plasma of the processing system through a thick layer of dielectric material (e.g., ceramic material) that is part of the ESC assembly. In a capacitively coupled gas discharge, plasma is generated by using the RF generator coupled to the RF electrode via an RF matching network ("RF matching"), which is tuned to an apparent load of 50 Ω to minimize reflected power and maximize power delivery efficiency. Applying an RF voltage to the power electrode results in the formation of an electron-repellent plasma sheath (also known as a "cathode sheath") above the processing surface of the substrate positioned on the substrate support surface of the ESC assembly during processing. The nonlinear, diode-like properties of the plasma sheath cause rectification of the applied RF field, resulting in a direct-current (DC) voltage drop, or "self-bias," between the substrate and the plasma, making the substrate potential negative relative to the plasma potential. This voltage drop determines the average energy of the plasma ions accelerated toward the substrate, and thus the etching anisotropy. More specifically, ion directionality, feature profile, and etch selectivity for the mask and termination layer are controlled by the Ion Energy Distribution Function (IEDF). In a plasma with an RF bias, the IEDF typically has two non-discrete peaks (one at low energy and one at high energy) and an ion swarm extending over an energy range between the two peaks. The ion swarm effect between the two peaks of the IEDF results in the voltage drop between the substrate and the plasma oscillating at the RF bias frequency. When a lower-frequency RF bias generator is used to achieve a higher self-bias voltage, the energy difference between these two peaks can be significant; and because the etching profile at the lower-energy peak is more isotropic, this can potentially lead to bending of the etched feature walls. Compared to high-energy ions, low-energy ions are less efficient at reaching the corners at the bottom of the etched feature (e.g., due to charging effects), but result in less sputtering of mask material. This is important in high aspect ratio etching applications such as hard mask apertures or dielectric mold etching. As feature sizes continue to decrease and aspect ratios increase, while feature profile control requirements become more stringent, a well-controlled IEDF at the substrate surface during processing becomes increasingly desirable.

[0006] Other conventional plasma processes and processing chamber designs have also found that delivering multiple different RF frequencies to one or more electrodes within a plasma processing chamber can be used to control various plasma properties, such as plasma density, ion energy, and / or plasma chemistry. However, it has been found that delivering multiple conventional sinusoidal waveforms from two or more RF sources, each configured to provide different RF frequencies, cannot adequately or desirablely control sheath properties and can lead to undesirable arcing problems. Furthermore, due to direct or capacitive coupling between the RF sources during processing, each RF source can induce RF currents (often referred to as "crosstalk") that supply the output to other connected RF sources, causing power to be diverted away from the intended load (plasma) and potentially damaging each of the RF sources.

[0007] Recently, high-density memory devices, including three-dimensional (3D) stacked memory structures, have been developed. For example, a 3D NAND stacked memory device can be formed from an array of alternating vertically stacked dielectric materials and conductive layers (e.g., tungsten-containing layers). Memory openings are formed and extend vertically through the dielectric material-containing layers in the alternating stack to expose portions of the conductive layers, and thus have varying depths within the alternating stack structure. The memory openings are eventually filled with conductive material to form connections with the exposed portions of each conductive layer in each of the alternating stacks. The conductive layers within the alternating stacks can serve as word lines for the 3D NAND stacked memory device, and bit lines covering the array of memory stack structures can be connected to the drain-side ends of semiconductor channels. However, when memory openings extending to different depths within the alternating stack are formed in a single etching step, it is desirable not to over-etch portions of the alternating stack layers at the shallowest depth relative to the layer formed at the deepest depth. Therefore, the following etching process is required: selectively etching the alternating stacked dielectric portions and terminating on the conductive layer, so that all memory openings can be formed into all layers within the alternating stack during the etching process, without over-etching the exposed portions of the individual conductive features.

[0008] Therefore, there is a need in the art for novel, robust, and reliable plasma processing and biasing methods that achieve the maintenance of a nearly constant sheath voltage and thus generate a desired and repeatable IEDF at the substrate surface to achieve precise control over the shape of the IEDF, and in some cases, precise control over the etching profile of the features formed in the substrate surface. Systems, apparatus, and methods that address the problems described above are also needed. Summary of the Invention

[0009] This disclosure generally includes a method of processing a substrate in a plasma processing chamber, the method comprising etching a first dielectric material formed on a substrate disposed on a substrate support surface of a substrate support assembly disposed within a processing region of the plasma processing chamber. The etching process of the first dielectric material includes: delivering a processing gas to a processing region of the plasma processing chamber, wherein the processing gas comprises a first fluorocarbon gas and a first processing gas; delivering a radio frequency signal to a first electrode disposed within the plasma processing chamber using a radio frequency generator to form plasma in the processing region; and establishing a first pulse voltage waveform at a bias electrode disposed within the substrate support assembly using a first pulse voltage waveform generator, wherein the first pulse voltage waveform comprises a series of repeating pulse waveform cycles. Each pulse waveform cycle includes: a first portion occurring during a first time interval and a second portion occurring during a second time interval, wherein the second time interval is longer than the first time interval; and an inter-peak voltage. The pulse voltage waveform is substantially constant during at least a portion of the second time interval.

[0010] Embodiments of this disclosure may further provide a method for processing a substrate in a plasma processing chamber, the method comprising etching a first dielectric material formed on a substrate disposed on a substrate support surface of a substrate support assembly disposed in a processing region of the plasma processing chamber. The etching process of the first dielectric material includes delivering a processing gas to the processing region of the plasma processing chamber, wherein the processing gas comprises a first fluorocarbon gas and a first processing gas. The first fluorocarbon gas comprises at least one of C4F6 or C3F6, and the first processing gas comprises at least one of N2, Kr, and O2. The etching process of the first dielectric material also includes delivering a radio frequency signal to a first electrode disposed in the plasma processing chamber using a radio frequency generator to form plasma in the processing region; and establishing a first pulse voltage waveform at a bias electrode disposed within the substrate support assembly using a first pulse voltage waveform generator, wherein the first pulse voltage waveform comprises a series of repeating pulse waveform cycles. Each pulse waveform cycle includes: a first portion occurring during a first time interval and a second portion occurring during a second time interval, wherein the second time interval is greater than the first time interval; and an inter-peak voltage. The first time interval may be between approximately 200 ns and approximately 400 ns, and may be less than approximately 20% of one cycle of the series of repetitive cycles. The pulse voltage waveform within each pulse waveform cycle may have an inter-peak voltage between approximately 5 kV and 20 kV. The pulse voltage waveform is substantially constant for at least a portion of the second time interval. Attached Figure Description

[0011] To gain a more detailed understanding of the manner in which the features of this disclosure are described above, a more specific description of the disclosure, which has been briefly summarized above, can be obtained with reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it will be noted that the drawings illustrate exemplary embodiments only and are not intended to limit the scope thereof, and may allow for other equivalent embodiments.

[0012] Figure 1 This is a schematic cross-sectional view of a processing chamber configured to practice the method described herein, according to one embodiment.

[0013] Figure 2 According to one embodiment, it is compatible with Figure 1 The diagram shows a simplified schematic of a bias scheme used in conjunction with the processing chambers.

[0014] Figure 3A According to one embodiment, it is possible Figure 1 The diagram shows the functional equivalent circuit of the negative pulse bias scheme executed in the processing chamber.

[0015] Figure 3B According to one embodiment, it is possible Figure 1 The diagram shows the functional equivalent circuit of the positive pulse bias scheme executed in the processing chamber.

[0016] Figure 4A An example of a negative pulsed voltage (PV) waveform established at the bias electrode according to one embodiment is shown.

[0017] Figure 4B An example of a shaped pulse voltage (PV) waveform established at the bias electrode according to one embodiment is shown.

[0018] Figure 4C An example of a positive pulse voltage (PV) waveform established at the bias electrode according to one embodiment is shown.

[0019] Figure 4D A comparison of negative pulse voltage (PV) waveforms and positive pulse voltage (PV) waveforms established at the substrate during processing is shown according to one embodiment.

[0020] Figure 5 A diagram of a substrate having etched trenches extending to various conductive layers of a substrate, according to one embodiment, is shown.

[0021] Figures 6A to 6C A diagram of a plasma etching process on a substrate according to one embodiment is shown.

[0022] Figure 7 A diagram of a plasma etching process on a substrate according to one embodiment is shown.

[0023] Figure 8 An example sheath thickness during a plasma etching process is shown according to one embodiment.

[0024] Figure 9 An example operation of a plasma etching process according to one embodiment is shown.

[0025] For ease of understanding, the same reference numerals have been used as much as possible to identify common elements in the figures. It is anticipated that elements and features of one embodiment may be advantageously incorporated into other embodiments without further description. Detailed Implementation

[0026] The embodiments of the disclosure provided herein include apparatus and methods for plasma processing of a substrate in a processing chamber. More specifically, embodiments of this disclosure describe processes for enhancing the selectivity of etching dielectric layers using pulsed plasma ion etching processes relative to one or more inorganic materials. Embodiments of this disclosure relate to an apparatus configured to provide an RF waveform generated by a radio frequency (RF) generator from an RF generator to one or more electrodes within a processing chamber, and to provide a pulsed voltage (PV) waveform delivered from one or more pulsed voltage (PV) generators to one or more electrodes within the processing chamber.

[0027] Typically, the generated RF waveform is configured to establish and sustain plasma within the processing chamber, and the delivered PV waveform is configured to control the sheath voltage across the entire substrate surface during a portion of the plasma process, thereby generating a desired ion energy distribution function (IEDF) at the substrate surface during one or more plasma processing steps performed within the processing chamber. The plasma process disclosed herein can be used to control the interaction between the plasma and the substrate surface during processing. In some configurations, the plasma process disclosed herein is used to control the profile of features formed on the substrate surface during processing. In some embodiments, the pulsed voltage waveform is established via a PV generator electrically coupled to a bias electrode disposed within a substrate support assembly disposed within the plasma processing chamber.

[0028] Typically, semiconductor device manufacturing processes can include logic and memory manufacturing processes, such as flash memory manufacturing. As devices shrink, structures used to create multiple effective memory cells are employed to maximize the density of memory cells in memory devices. Three-dimensional (3D) NAND technology addresses the challenges of two-dimensional (2D) NAND technology and the vertical stacking of memory cells in layers.

[0029] Plasma etching processes involved in the fabrication of 3D NAND devices are becoming increasingly challenging. Specifically, stepped contact etching in 3D NAND technology provides access to cells at the bottom of the NAND stack, allowing the deposition of conductive material (e.g., tungsten) to form word lines that allow access to the cell control gates from external peripheral circuitry. Stepped contact etching presents challenges, particularly for high aspect ratio features varying from 20:1 to 40:1. Etching through high aspect ratio conductive layers intensifies the need for etching processes that can create streaks-free, twist-free, and wirelessly bendable, faceted, and feature-blocking openings within the layer. In addition to these requirements, the preference for stepped contact etching applications is a combination of simultaneous multi-quasi-etching with high selectivity across aspect ratios ranging from 20:1 to greater than 40:1 to ensure negligible loss of underlying conductive contact material.

[0030] Therefore, pulsed voltage technology enables precise control of plasma ion density and ion energy during plasma processing. It is believed that precise control of plasma ion density and ion energy, in conjunction with the use of desired dry etching chemicals, can lead to increased etching selectivity and improved etching process results. Furthermore, by using one or more of the methods described herein, etching selectivity and improved etching process results can be further achieved during the etching process through the controlled formation of a fluorocarbon-based polymer layer on the exposed conductive material surface.

[0031] Figure 1 This is a schematic cross-sectional view of a processing chamber configured to practice the methods described herein. During some semiconductor plasma processes, via substrate support assembly 136 ( Figure 1 The voltage drop in the electron repulsion sheath formed above the substrate placed on top of the substrate causes ions to be purposefully accelerated toward the substrate. While not intended to limit the scope of the disclosure provided herein, the substrate support assembly 136 is frequently referred to herein as a “cathode assembly” or “cathode.” In some embodiments, the substrate support assembly 136 includes a substrate support 105 and a support substrate 107. The substrate support 105 may include an electrostatic chuck (ESC) assembly configured to clamp (e.g., hold) the substrate on the substrate receiving surface 105A.

[0032] In some embodiments of the disclosure provided herein, the processing chamber is configured to provide a capacitively coupled gas discharge, such that plasma is generated using an RF generator assembly comprising an RF generator coupled to RF electrodes via an RF matching network (“RF matching”). The RF matching network is configured to tune the apparent load to 50 Ω to minimize reflected power and maximize power delivery efficiency. In some embodiments, the RF electrodes comprise metal plates with plasma-facing surfaces positioned parallel to the substrate.

[0033] Furthermore, during the plasma processing method disclosed herein, the ion-accelerated cathode sheath is typically formed during plasma processing using a pulsed voltage (PV) generator configured to house one or more bias electrodes 104 within the substrate support assembly 136. Figure 1 A pulsed voltage waveform is established at [location missing]. In some embodiments, one or more bias electrodes 104 include clamping electrodes separated from the substrate by a thin layer of dielectric material formed within a substrate support assembly 136 (e.g., an electrostatic clamping (ESC) assembly), and edge control electrodes optionally disposed within or below an edge ring 114 surrounding the substrate 103 when the substrate 103 is positioned on a substrate support surface 105A of the substrate support assembly 136. As will be discussed further below, this PV waveform can be configured to result in a substantially constant sheath voltage (e.g., the difference between the plasma potential and the substrate potential) for a substantial portion of the pulse period of the PV waveform, corresponding to a single (narrow) peak of the ion energy distribution function (IEDF) containing ions arriving at the substrate during this portion of the pulse period, also referred to herein as the “ion current phase.”

[0034] Plasma processing chamber hardware example

[0035] Figure 1 This is one of the complex loads formed during plasma processing ( Figures 3A to 3B A cross-sectional schematic diagram of the processing chamber 100. Figures 3A to 3BThese are examples of simplified circuitry 140 for pulsed voltages and RF bias schemes performed using components found in processing chamber 100. According to one or more embodiments, processing chamber 100 is configured to practice one or more of the bias schemes presented herein. In one embodiment, the processing chamber is a plasma processing chamber, such as a reactive ion etching (RIE) plasma chamber. In some other embodiments, the processing chamber is a plasma-enhanced deposition chamber, such as a plasma-enhanced chemical vapor deposition (PECVD) chamber, a plasma-enhanced physical vapor deposition (PEPVD) chamber, or a plasma-enhanced atomic layer deposition (PEEALD) chamber. In some other embodiments, the processing chamber is a plasma processing chamber or a plasma-based ion implantation chamber, such as a plasma doping (PLAD) chamber. In some embodiments, the plasma source is a capacitively coupled plasma (CCP) source, which includes electrodes (e.g., chamber cover 123) disposed within the processing volume facing the substrate support assembly 136. Figure 1 As shown, a counter electrode (such as chamber cover 123) positioned opposite the substrate support assembly 136 is electrically coupled to ground. However, in other alternative embodiments, the counter electrode is electrically coupled to an RF generator. In still other embodiments, the processing chamber may alternately or additionally include an inductively coupled plasma (ICP) source electrically coupled to a radio frequency (RF) power supply.

[0036] The processing chamber 100 also includes a chamber body 113, which includes a chamber cover 123 defining a processing volume 129, one or more sidewalls 122, and a chamber base 124. The sidewalls 122 and chamber base 124 are typically made of materials whose dimensions and shapes are adjusted to form structural supports for the components of the processing chamber 100 and configured to withstand applied pressures and added energy during the generation of plasma 101 within the vacuum environment maintained in the processing volume 129 of the processing chamber 100 during processing. In one example, the sidewalls 122 and chamber base 124 are formed of a metal, such as aluminum, an aluminum alloy, or stainless steel. A gas inlet 128 disposed through the chamber cover 123 is used to supply one or more processing gases from a processing gas source 119 in fluid communication with the processing volume 129 to the processing volume 129. The substrate 103 is loaded into and removed from the processing volume 129 through an opening (not shown) in one or more sidewalls 122, the opening being sealed with a slit valve (not shown) during plasma processing of the substrate 103. Hereinafter, a lifting pin system (not shown) is used to transfer the substrate 103 to and from the substrate receiving surface 105A of the ESC substrate support 105.

[0037] In some embodiments, the RF generator assembly 160 is configured to deliver RF power to a support substrate 107 disposed near the ESC substrate support 105 and within a substrate support assembly 136. The RF power delivered to the support substrate 107 is configured to ignite and sustain a process plasma 101 formed using a process gas disposed within a process volume 129. In some embodiments, the support substrate 107 is electrically coupled to the RF electrodes of the RF generator 118 via an RF matching circuit 161 and a first filter assembly 162 (both disposed within the RF generator assembly 160). In some embodiments, the plasma generator assembly 160 and the RF generator 118 are used to ignite and sustain the process plasma 101 using the field generated by the process gas disposed in the process volume 129 and the RF power supplied to the support substrate 107 via the RF generator 118. The process volume 129 is fluidly coupled to one or more dedicated vacuum pumps via a vacuum outlet 120, which maintain the process volume 129 under sub-atmospheric pressure conditions and extract process gas and / or other gases therefrom. The substrate support assembly 136, located in the processing volume 129, is mounted on a support shaft 138, which is grounded and extends through the chamber substrate 124. However, in some embodiments, the RF generator assembly 160 is configured to deliver RF power relative to the substrate substrate 107 to a bias electrode 104 located in the substrate support 105.

[0038] The substrate support assembly 136 (as briefly described above) typically includes a substrate support 105 (e.g., an ESC substrate support) and a support substrate 107. In some embodiments, as further discussed below, the substrate support assembly 136 may additionally include an insulating plate 111 and a ground plane 112. The substrate support 105 is thermally coupled to and positioned on the support substrate 107. In some embodiments, the support substrate 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 positioned on the substrate support 105 during substrate processing. In some embodiments, the support substrate 107 includes one or more cooling channels (not shown) disposed therein, which are fluidly coupled to and in communication with a coolant source (not shown), such as a refrigerant source or a water source having relatively high resistance. In some embodiments, the substrate support 105 includes a heater (not shown), such as a resistance heating assembly embedded in its dielectric material. In this paper, the support substrate 107 is formed of a corrosion-resistant and thermally conductive material, such as a corrosion-resistant metal, for example, aluminum, aluminum alloy, or stainless steel, and is coupled to the substrate support using an adhesive or through a mechanical component.

[0039] The support substrate 107 is electrically isolated from the chamber substrate 124 by an insulator plate 111, and a ground plane 112 is inserted between the insulator plate 111 and the chamber substrate 124. In some embodiments, the processing chamber 100 further includes a quartz conduit 110 or a collar that at least partially externalizes a portion of the substrate support assembly 136 to prevent corrosion of the ESC substrate support 105 and / or to prevent the support substrate 107 from contacting corrosive processing gases or plasmas, cleaning gases or plasmas, or their byproducts. Typically, the quartz conduit 110, the insulator plate 111, and the ground plane 112 are externally connected by a gasket 108. Hereinafter, a plasma screen 109, substantially coplanar with the substrate receiving surface of the ESC substrate support 105, prevents plasma from forming in the volume between the gasket 108 and one or more sidewalls 122.

[0040] The substrate support 105 is typically formed of a dielectric material, such as a bulk sintered ceramic material, or a corrosion-resistant metal oxide or metal nitride material, for example, alumina (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof. In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in its dielectric material. In one configuration, the bias electrode 104 is a clamping electrode for securing (clamping) the substrate 103 to the substrate receiving surface 105A of the substrate support 105 (also referred to herein as the ESC substrate support), and biasing the substrate 103 relative to the processing plasma 101 using one or more of the pulsed voltage biasing schemes described herein. Typically, the bias electrode 104 is formed of one or more conductive portions, such as one or more metal meshes, foils, plates, or combinations thereof. In some embodiments, the bias electrode 104 is electrically coupled to a bias compensation module 116, which uses an electrical conductor to provide a clamping voltage to the bias electrode, such as a static DC voltage between approximately -5000 V and approximately 5000 V, the conductor being a coaxial transmission line 106 (e.g., a coaxial cable). As will be discussed further below, the high-voltage module 116 includes a bias compensation circuit assembly 116A (… Figures 3A to 3B The DC power supply 155 and the blocking capacitor 153 are also present. The blocking capacitor (also referred to herein as blocking capacitor 153) of the bias compensation module is positioned between the output of the pulsed voltage waveform generator (PVWG) 150 and the bias electrode 104.

[0041] The bias electrode 104 is spaced apart from the substrate receiving surface 105A of the substrate support 105 via a dielectric material layer, and thus from the substrate 103. Depending on the type of electrostatic clamping method used in the substrate support 105 to hold the substrate 103 during processing, such as Coulomb ESC or Johnsen-Rahbek ESC, the effective circuit elements used to model the electrical coupling from the bias electrode 104 to the plasma 101 will vary. Typically, a parallel plate-like structure is formed by the bias electrode 104 and the dielectric material layer, and the dielectric material can typically have an effective capacitance C between about 5 nF and about 50 nF. ETypically, the dielectric material layer (e.g., aluminum nitride (AlN), aluminum oxide (Al2O3), etc.) has a thickness between about 0.1 mm and about 1 mm, such as between about 0.1 mm and about 0.5 mm, for example, about 0.3 mm. In this document, the bias electrode 104 is electrically coupled to the output of the PVWG 150 using an external conductor (e.g., transmission line 106) disposed within the support shaft 138. In some embodiments, the dielectric material and layer thickness can be selected such that the clamping capacitance C of the dielectric material layer... ESC Between about 5 nF and about 50 nF, for example, between about 7 and about 10 nF.

[0042] In a more complex model of the Johnson-Rabek ESC, the circuit model includes the ESC dielectric clamping capacitor C, as shown in the figure. ESC ESC dielectric material resistance R CER Gap capacitance C abt , substrate capacitor C sub and substrate resistance R sub The combination of gap capacitance C. abt The gas-containing spaces above and below the substrate, typically positioned on the substrate support 105, are considered. The expected gap capacitance C... abt Having in relation to clamping capacitor C ESC Capacitance within the same range.

[0043] In some applications, since the substrate 103 is typically made of a thin layer of semiconductor and / or dielectric material, the substrate 103 can be considered part of an ESC dielectric layer electrically disposed between the bias electrode 104 and the substrate receiving surface 105A. Therefore, in some applications, the clamping capacitor C... ESC A series capacitor (i.e., substrate capacitor C) is connected between the ESC and the substrate. sub Approximately. However, in the case of Coulomb clamping, due to the substrate capacitance C sub Typically, the capacitance is very large (>10 nF), or the substrate can be conductive (infinite capacitance), therefore the series capacitance is mainly through the capacitance C. ESC Decision. In this case, the effective capacitance C E Effectively equal to the clamping capacitance C ESC In the case of the "Johnson-Labek ESC," the ESC dielectric layer is "leaky" because it is not a perfect insulator and has a certain conductivity, attributed to, for example, doped aluminum nitride (AlN) with a permittivity (ε) of about 9. However, the effective capacitance of the Johnson-Labek ESC should be similar to that of a coulomb clamp. In one example, the volume resistivity of the dielectric layer within the Johnson-Labek ESC is less than about 10. 12 ohm-cm (Ω-cm), or less than about 10 10Ω-cm, or even in 10 8 Ω-cm and 10 12 Within the range of Ω-cm.

[0044] The substrate support assembly 136 further includes an edge control electrode 115 positioned below and surrounding the bias electrode 104, such that when biased, the edge control electrode can influence or alter a portion of the generated plasma 101 located at or outside the edge of the substrate 103 due to its position relative to the substrate 103. The edge control electrode 115 can be biased by using a different PVWG 150 than that used for biasing the bias electrode 104. In one configuration, a first PV waveform generator 150 of the first PV source assembly 196 is configured to bias the bias electrode 104, and a second PV waveform generator 150 of the second PV source assembly 197 is configured to bias the edge control electrode 115. In one embodiment, as... Figure 1 As shown, the edge control electrode 115 is positioned within the region of the substrate support 105. Typically, as... Figure 1 As shown, for a processing chamber 100 configured to process a circular substrate, the edge control electrode 115 is annular in shape, made of a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments, such as Figure 1 As shown, the edge control electrode 115 includes a conductive mesh, foil, or plate disposed at a similar distance (i.e., in the Z direction) from the surface 105A of the substrate support 105 as the bias electrode 104. Alternatively, in some other embodiments, the edge control electrode 115 includes a conductive mesh, foil, or plate positioned on or within a region of a quartz tube 110 (not shown) surrounding at least a portion of the bias electrode 104 and / or the substrate support 105. In some other embodiments, the edge control electrode 115 is positioned within or coupled to an edge ring 114 disposed adjacent to the substrate support 105. In this configuration, the edge ring 114 is formed of a semiconductor or dielectric material (e.g., AlN, Al2O3, etc.).

[0045] See Figure 1 The support substrate 107 is spaced apart from the bias electrode 104 by a portion of a dielectric material. In some configurations, the portion of the dielectric material is the same dielectric material used to form the substrate support 105 and extends from the back side of the substrate support 105 to the bias electrode 104. For example... Figure 3A and Figure 3B As schematically shown, a portion of the dielectric material of the substrate support 105 has an ESC capacitor C E Series-connected supporting substrate capacitor C CLIn some embodiments, the thickness of the portion of dielectric material disposed between the support substrate 107 and the bias electrode 104 is greater than the thickness of the dielectric material disposed between the bias electrode 104 and the substrate 103, wherein the dielectric material is the same material and / or forms a portion of the substrate support 105. In one example, the portion of dielectric material of the substrate support 105 (e.g., Al2O3 or AlN) disposed between the support substrate 107 and the bias electrode 104 is greater than 1 mm thick, such as between about 1.5 mm and about 20 mm thick.

[0046] Typically, the low pressure formed in the processing volume 129 of the processing chamber 100 leads to poor thermal conduction between the surfaces of hardware components housed therein, such as between the dielectric material of the substrate support 105 and the substrate 103 mounted on its substrate receiving surface. This reduces the effectiveness of the substrate support in heating or cooling the substrate 103. Therefore, in some processes, a thermally conductive inert heat transfer gas (typically helium) is introduced into a volume (not shown) disposed between the non-device side surface of the substrate 103 and the substrate receiving surface 105A of the substrate support 105 to improve heat transfer therebetween. The heat transfer gas, supplied by a heat transfer gas source (not shown), flows into the back-side volume through a gas communication path (not shown) disposed through the support substrate 107 and further through the substrate support 105.

[0047] Processing chamber 100 further includes a controller 126, also referred to herein as a processing chamber controller. The controller 126 includes a central processing unit (CPU) 133, memory 134, and support circuitry 135. The controller 126 controls a series of processes for processing substrate 103, including the substrate biasing method described herein. The CPU 133 is a general-purpose computer processor in an industrial setup configured to control the processing chamber and its associated subprocessors. The memory 134 described herein (typically non-volatile memory) may include random access memory, read-only memory, floppy disk or hard disk drives, or other suitable forms of digital memory (local or remote). The support circuitry 135 is conventionally coupled to the CPU 133 and includes cache, clock circuitry, input / output subsystems, power supplies, and the like, and combinations thereof. Software instructions (programs) and data may be encoded and stored in memory 124 to instruct the processor within the CPU 133. A software program (or computer instructions) readable by the CPU 133 in the controller 126 determines which tasks the components in the processing chamber 100 perform. Preferably, the program readable by the CPU 133 in the controller 126 includes code that, when executed by the processor (CPU 133), performs tasks related to monitoring and executing the electrode biasing scheme described herein. The program will include instructions for controlling the various hardware and electrical components within the processing chamber 100 to perform various processing tasks and process sequences for implementing the electrode biasing scheme described herein.

[0048] During processing, a PV generator 314 within the PV waveform generator 150 of the first PV source assembly 196 and the second PV source assembly 197 establishes a pulsed voltage waveform on a load (e.g., complex load 130) disposed within the processing chamber 100. While not intended to limit the disclosure provided herein, for the sake of simplicity, components within the second PV source assembly 197 for the bias edge control electrode 115... Figures 3A to 3B Not schematically illustrated. Overall control of the delivery of PV waveforms from each of the PV waveform generators 150 is achieved by using signals provided from the controller 126. In one embodiment, as... Figure 3A As shown, the PV waveform generator 150A is configured to maintain a predetermined, substantially constant positive voltage across its entire output (i.e., to ground) by repeatedly closing and opening its internal switch S1 at a predetermined rate during a periodically repetitive time interval of predetermined length. Alternatively, in one embodiment, as... Figure 3BAs shown, the PV waveform generator 150B maintains a predetermined, substantially constant negative voltage across its entire output (i.e., to ground) by repeatedly closing and opening its internal switch S1 at a predetermined rate during a periodically repetitive time interval of predetermined length. Figures 3A to 3B In this process, the PV waveform generators 150A and 150B are reduced to a minimum combination of components that play a crucial role in understanding how they establish the desired pulse voltage waveform at the bias electrode 104. For example, in Figures 3A to 3B As schematically shown, each PV waveform generator 150 will include a PV generator 314 (e.g., a DC power supply) and one or more electrical components, such as high-repetition-rate switches, capacitors (not shown), inductors (not shown), flyback diodes (not shown), power transistors (not shown), and / or resistors (not shown), configured to provide a PV waveform to an output 350. The actual PV waveform generator 150, configurable as a nanosecond pulse generator, may include any number of internal components and may be based on... Figures 3A to 3B The circuit shown is more complex than the one described above. Figures 3A to 3B The schematic diagrams each provide only a functional equivalent representation of the components and circuitry of the PV waveform generator 150, and are used only to explain the basic principles of its operation, its interaction with the plasma in the processing volume, and its role in establishing pulse voltage waveforms (such as the input pulse voltage waveform at the bias electrode 104). (See also...) Figures 3A to 3B The schematic diagram suggests that when switch S1 moves from the open (closed) position to the closed (on) position, it connects the output of PV waveform generator 150 to its PV generator 314, which produces a substantially constant output voltage. PV waveform generator 150 can primarily function as a charge injector (current source) and not as a constant voltage source; thus, strict requirements are not imposed on the stability of the output voltage, as the output voltage can vary over time even when the switch is held in the closed (on) position. Furthermore, in some configurations, PV generator 314 is essentially a sourcing rather than a sinking supplier, as it conducts current in only one direction (e.g., the output can charge a capacitor without discharging it). Moreover, when switch S1 is held in the open (closed) position, the overall output voltage (V0) of PV waveform generator 150 is not controlled by PV generator 314, but rather determined by the interaction of its internal components with other circuit elements.

[0049] The current return output stage 314A has one end connected to ground and the other end connected to a connection point at the output of the PV waveform generator 150 (i.e., one side of the generator coupling assembly (not shown)). The current return output stage 314A may include components such as resistors, resistors and inductors connected in series, switch S2, and / or more complex combinations of electrical components that allow positive current to flow toward ground, including parallel capacitors.

[0050] Transmission line 131 (forming PV transmission line 157) Figure 1 The output 350 of the PV waveform generator 150 is electrically connected to the second filter assembly 151. Although the following discussion focuses primarily on the PV transmission line 157 for coupling the PV waveform generator 150 to the first PV source assembly 196 of the bias electrode 104, the PV transmission line 158 for coupling the PV waveform generator 150 to the second PV source assembly 197 of the edge control electrode 115 will include the same or similar components. Thus, typically, the output 350 of the PV waveform generator 150 is the end, where the output of the PV pulse generator 314 is connected to the output 350 and the current returns to the output stage 314A via internal electrical conductors. Transmission line 131 connects the generator coupling assembly 181, located at the output 350 of the PV waveform generator 150, to the second filter assembly 151. The electrical conductors within the various portions of PV transmission lines 157 and 158 may include: (a) a coaxial transmission line (e.g., coaxial line 106), which may include a flexible coaxial cable connected in series with a rigid coaxial transmission line; (b) an insulated high-voltage corona-resistant mounting wire; (c) a bare wire; (d) a metal rod; (e) an electrical connector; or (f) any combination of the electrical components in (a)-(e). The outer conductor portion of PV transmission line 157 (e.g., the first electrical conductor), such as the portion of PV transmission line 157 within the support shaft 138 and the bias electrode 104, will have a stray capacitance C of some combination to ground. stray ( Figures 3A to 3B Although not shown in the diagram, the outer conductor portion of the PV transmission line 158 (e.g., the second electrical conductor) and the edge control electrode 115 will also have some combination of stray capacitances C to ground. stray The internal electrical conductors of the PV waveform generator 150 may include the same basic components as the external electrical conductors. In most practical applications, the transmission line 131 will include a line inductance 159, which may include components through the internal parts of the PV waveform generator 150 (i.e., the generator output coupling assembly 181). Figures 3A to 3B The portion generated on the left side of the PV waveform generator 150 and / or the portion generated by connecting the PV waveform generator 150 to the external line / cable of the second filter assembly 151 (i.e., the right side of the generator output coupling assembly 181).

[0051] See back Figure 1 The processing chamber 100 includes a grounded chamber cover 123. In this configuration, which differs from conventional plasma processing chamber designs, RF power is delivered alternatively through a substrate support. Thus, by coupling the RF generator 118 to the support substrate 107, the entire body of the ESC, as a functional part of the cathode assembly, allows the top electrode to be grounded and allows for maximizing the current return area. For plasma processes utilizing both RF power delivery and PV waveform delivery, maximizing the grounded surface area within the plasma processing chamber and thus maximizing the current return area minimizes plasma potential jumps during the ESC recharge / sheath collapse phase of the PV waveform cycle generated by the output of the PV waveform generator 150, as discussed further below. Therefore, the apparatus and methods provided herein minimize power losses to the chamber walls and improve plasma processing efficiency. The RF power and PV pulse waveform delivery methods described herein also provide certain process benefits due to their influence on and allow for improved control over plasma properties and radical generation. However, as mentioned above, there is strong capacitive coupling between the substrate 107 and the bias electrode 104 through the ESC ceramic layer and between the RF transmission line 167 and the PV transmission line 157. Therefore, when the two types of power are delivered through the substrate support assembly 136 (i.e., the cathode assembly), each generator will induce a current through the other, causing the power to deviate from the expected (plasma) load and potentially damage both generators.

[0052] In another alternative configuration of the chamber cover 123 that can be used with one or more of the other embodiments disclosed herein, the chamber cover 123 (i.e., the opposing electrode) is electrically isolated from one or more sidewalls 122 and electrically coupled through the plasma generator assembly 160 to the RF generator 118. In this configuration, the chamber cover 123 can be driven by the RF generator 118 to ignite and sustain the processed plasma 101 within the processed volume 129. In one example, the RF generator 118 is configured to provide an RF signal to the chamber cover 123 at an RF frequency greater than about 300 kHz (such as between about 300 kHz and 60 MHz, or even at frequencies in the range from about 2 MHz to about 40 MHz).

[0053] Plasma treatment bias scheme and process

[0054] Figure 2 Is it possible to... Figure 1 A simplified schematic diagram of a bias scheme used in conjunction with processing chambers is shown. Figure 2As shown, the RF generator 118 and PV waveform generator 150 are configured to deliver an RF waveform and a pulse voltage waveform, respectively, to one or more electrodes disposed within the chamber body 113 of the processing chamber 100. In one embodiment, the RF generator 118 and PV waveform generator 150 are configured to simultaneously deliver an RF waveform and a pulse voltage waveform to one or more electrodes disposed within the substrate support assembly 136. In a non-limiting example, as discussed above, the RF generator 118 and PV waveform generator 150 are configured to deliver an RF waveform and a pulse voltage waveform, respectively, to the support substrate 107 and the bias electrode 104, both of which are disposed within the substrate support assembly 136. In another example, the RF generator 118, the first PV waveform generator 150, and the second PV waveform generator 150 are configured to deliver an RF waveform, a first pulse voltage waveform, and a second pulse voltage waveform, respectively, to the support substrate 107, the bias electrode 104, and the edge control electrode 115, all of which are disposed within the substrate support assembly 136.

[0055] like Figure 2 As shown, the RF generator 118 is configured to deliver a sinusoidal RF waveform 601 through the plasma generator assembly 160. Figures 6A to 6C The plasma generator assembly includes an RF matching circuit 161 and a first filter assembly 162, which provides a sinusoidal RF waveform to one or more electrodes disposed in the chamber body 113. Furthermore, each of the PV waveform generators 150 is configured to generate a PV waveform 401 at the bias electrode 104 by passing through the second filter assembly 151. Figure 4A ), 441 ( Figure 4B ), or 431 ( Figure 4C The PV waveform (typically consisting of a series of voltage pulses, e.g., nanosecond voltage pulses) is supplied to one or more electrodes disposed in the chamber body 113. Components within the bias compensation module 116 may be positioned as needed between each PV waveform generator 150 and the second filter assembly 151.

[0056] As briefly discussed above, Figures 3A to 3B These are examples of the functionally equivalent simplified circuit 149 of the pulse voltage and RF bias scheme proposed in this paper, which also includes a representation of the plasma in the processing volume. Figure 3A A simplified circuit 140 is depicted within a first PV source assembly 196, utilizing a pulse voltage and RF bias scheme from a PV waveform generator 150, which is configured to generate a PV waveform (such as PV waveform 431) at a bias electrode 104. Figure 4C A positive voltage is provided during part of the process. Figure 3BA simplified circuit 140 is depicted within a first PV source assembly 196, utilizing a pulse voltage and RF bias scheme from a PV waveform generator 150, which is configured to generate a PV waveform (such as PV waveform 401) at a bias electrode 104. Figure 4A A negative voltage is provided during part of the process. These circuits show a simplified model of the interaction between the pulse voltage waveform generator 150 of the first PV source component 196 and the RF generator 118 within the processing chamber 100, and generally show the basic components used during operation of the processing chamber 100. For clarity, the following definitions are used throughout this disclosure: (1) all potentials are referenced to ground unless otherwise specified; (2) the voltage at any physical point (such as a substrate or bias electrode) is also defined at the potential at that point relative to ground (zero potential point); (3) the cathode sheath refers to the ion-accelerating sheath that is electron-repelled relative to the plasma corresponding to the negative substrate potential; (4) the sheath voltage (sometimes also referred to as "sheath voltage drop") V sh Defined as the absolute value of the potential difference between the plasma and (e.g., the substrate or chamber wall) an adjacent surface; and (5) the substrate potential is the potential at the substrate surface facing the plasma.

[0057] exist Figures 3A to 3B The complex load 130 shown is illustrated as a standard electroplasma model representing the processed plasma 101 as three elements in series. The first element is an electron-repellent cathode sheath (sometimes referred to as a "plasma sheath" or simply a "sheath") adjacent to the substrate 103. The cathode sheath is in Figures 3A to 3B The circuit is represented by a conventional three-part component, including: (a) diode D SH When disconnected, it indicates sheath collapse; (b) current source l i , representing the ion current flowing to the substrate in the presence of the sheath, and (c) capacitor C SH (e.g., ~100-300 pF), representing the sheath during the main portion of the bias cycle in which ion acceleration and etching occur (i.e., the ion current phase of the PV waveform). The second element is through a single resistor R. plasma (For example, resistor 146 = ~5-10 Ohms) represents the main plasma. The third element is an electron-repellent sheath formed at the chamber wall. The sheath also... Figures 3A to 3B The circuit is represented by three components, including: (a) diode D wall (b) Current source I iwall , representing the ion current to the wall, and (c) capacitor C wall (e.g., ~5-10 nF), primarily representing the wall sheath during the ESC charging phase of the PV waveform (described later in the text). The inner surface of the grounded metal wall can also be considered as being coated with a thin layer of dielectric material, which in Figures 3A to 3BMedium-sized capacitor C coat (For example, ~300-1000 nF) is represented.

[0058] As in Figures 3A to 3B As shown, the RF generator 118 is configured to pass through the first filter assembly 162, the RF matching circuit 161, and the line inductor L. Line Supporting substrate capacitor C CL and effective capacitance C E The generated RF power is delivered to provide RF signals to the support substrate 107 and ultimately to the complex load 130. In one embodiment, the RF matching circuit 161 includes a series inductor element L. SER and an adjustable series capacitor element C that can be controlled by input from controller 126. SER Adjustable parallel capacitor assembly C Shunt In some embodiments, the RF matching circuit 161 may alternatively be formed using other circuit element configurations, such as an L-network, a pi-network, or a transmission impedance circuit, for example. As mentioned above, the RF matching circuit 161 is typically configured to tune the apparent load to 50 Ω to minimize reflected power generated by delivering the RF signal from the RF generator 118 and to maximize its power delivery efficiency. In some embodiments, the RF matching circuit 161 is optional, and in these cases, other RF signal matching techniques (e.g., variable frequency tuning) may be used during the plasma processing of the substrate to avoid inefficiently delivering RF power to the complex load 130.

[0059] The first filter assembly 162 includes one or more electrical components configured to substantially prevent current generated by the output of the PV waveform generator 150 from flowing through the RF transmission line 167 and damaging the RF generator 118. The first filter assembly 162 serves as a high impedance (e.g., high Z) to the PV signal generated by the PV pulse generator 314 within the PV waveform generator 150, and thus suppresses current flow to the RF generator 118. In one embodiment, the first filter assembly 162 includes a blocking capacitor C disposed between the RF matching circuit 161 and the RF generator 118. BC In this configuration, the RF matching element 161 is configured to move in tandem with the blocking capacitor C. BC The capacitance of the blocking capacitor is compensated by tuning the apparent load on the RF generator 118. In one example, to prevent nanosecond PV waveforms (e.g., pulse periods of 10-100 ns) provided from the PV waveform generator 150 from damaging the RF generator 118, the first filter assembly 162 includes a 38-40 pF capacitor. In another example, the first filter assembly 162 includes a blocking capacitor C with a capacitance of less than 38 pF.BC .

[0060] In some embodiments, such as Figures 1 to 3B As shown, each of the PV waveform generators 150 is configured to pass through the blocking capacitor 153 and the second filter assembly 151 of the high voltage module 116, and the high voltage line inductor L. HV and effective capacitance C E The generated pulsed voltage waveform is delivered to the bias electrode 104 and ultimately to the complex load 130. In this case, the system may include a bias compensation module 116 for clamping (e.g., "electrically clamping") the substrate to the substrate receiving surface of the ESC substrate support. Clamping the substrate allows helium (He) gas to be filled in the gap between the substrate receiving surface and the non-device side surface of the substrate. This is done to provide thermal contact between the two and to allow substrate temperature control by regulating the temperature of the ESC substrate support. Combining the DC clamping voltage generated by the bias compensation module 116 with the pulsed voltage generated at the bias electrode 104 by the PV waveform generator 150 will result in an additional voltage offset of the pulsed voltage waveform equal to the DC clamping voltage. The additional voltage offset can be added to or subtracted from the voltage generated at the bias electrode 104. Figures 4A to 4B The offset ΔV is shown in the figure. By selecting appropriately large blocking capacitors 153 and 154, the effect of the bias compensation module 116 on the operation of the PV pulse generator 314 of the PV waveform generator 150 can be ignored. Blocking resistor 154 schematically shows a resistor located within a component at the point where the bias compensation module 116 is connected to the transmission line 131. The value of blocking capacitor 153 is selected such that it does not provide any load to the pulse voltage output of the pulse bias generator when only blocking the DC voltage of the bias compensation circuit. In one example, blocking capacitor C BC The capacitance of the blocking capacitor 153 is approximately 38 pF, and the capacitance of the blocking capacitor 153 is approximately 40 nF. The size of the blocking resistor 154 is typically adjusted to be large enough to effectively minimize the current passing through it. For example, a resistor ≥ 1 MOhm is used to make the 400 kHz current from the PV waveform generator 150 to the bias compensation module 116 negligible. In one example, the blocking resistor has a resistance greater than approximately 500 kOhm. The resulting average induced current, on the order of 0.5–1 mA, is practically far less than the common limitation of the bias compensation module power supply, which is approximately 5 mA of DC current.

[0061] The second filter assembly 151 includes one or more electrical components configured to prevent current generated by the output of the RF generator 118 from flowing through the PV transmission line 157 and damaging the PV pulse generator 314 of the PV waveform generator 150. As discussed above, the PV transmission line 157 is an assembly including the coaxial transmission line 106 and the transmission line 131. In one embodiment, the second filter assembly 151 includes a capacitor C. FC The filter capacitor 151A, and including the inductor L FL A filter inductor 151B is provided, which is connected in parallel and disposed in a transmission line 157 between the PV pulse generator 314 and the bias electrode 104. In some configurations, a second filter assembly 151 is disposed between the blocking capacitor 153 of the bias compensation module 116 and the bias electrode 104. The second filter assembly 151 serves as a high impedance (e.g., high Z) to the RF signal generated by the RF generator 118, and thus suppresses the flow of current to the PV pulse generator 314. Typically, the second filter assembly 151 is configured to block the RF signal, and any associated harmonics, from entering the PV pulse generator 314. In some embodiments, the RF signal generated by the RF generator is configured to deliver an RF frequency greater than 400 kHz, such as ≥1 MHz, ≥2 MHz, ≥13.56 MHz, or ≥40 MHz. In one example, to prevent damage to the PV pulse generator 314 from the RF power supplied from the RF generator 118 at a frequency of 40 MHz, the second filter assembly 151 includes a filter capacitor 151A with a capacitance of about 51 pF and a filter inductor 151B with an inductance of about 311 nH.

[0062] Pulse waveform example

[0063] As mentioned above, embodiments of this disclosure provide novel substrate biasing methods that achieve the maintenance of a nearly constant sheath voltage during processing and thus generate a desired IEDF at the substrate surface, while also providing the ability to individually control aspects of the plasma formed within the processing volume of a plasma processing chamber using one or more RF source components. In some embodiments, a single-peak (single-energy) IEDF can be formed at the substrate surface during processing using the novel substrate biasing apparatus and methods disclosed herein. In other embodiments, a double-peak (dual-energy) IEDF is formed at the substrate surface during processing using one or more of the novel substrate biasing apparatus and methods disclosed herein.

[0064] The following text is about Figures 4A to 4CFurther discussion reveals a novel substrate biasing method for maintaining a nearly constant sheath voltage during plasma processing, comprising delivering a series of pulses and / or short pulses of pulses during a plasma processing sequence performed on the substrate during a plasma process performed in a plasma processing chamber. Embodiments of the disclosure provided herein include delivering pulses having desired PV waveforms, each comprising multiple distinct phases. As further discussed below, each PV waveform includes at least one of multiple phases controlled by delivering a voltage signal or, in some cases, a constant current signal provided from a PV waveform generator 150. Typically, for illustrative purposes, each pulse of the PV waveform may be segmented into two main regions, including a first region 405 and a second region 406, as shown in… Figures 4A to 4C As shown in the diagram. Typically, each PV waveform will include an amplitude (V). out ), offset (e.g., ΔV), pulse period ( T p ), and pulse repetition frequency ( f p =1 / T p ).

[0065] In some embodiments, the PV waveform is established separately at the bias electrode 104 and the edge control electrode 115 using the PV waveform generator 150 of the first PV source component 196 and the PV waveform generator 150 of the second PV source component 197, respectively. Figure 4A The negative pulse bias scheme type of the pulse voltage waveform is indicated, wherein the PV waveform generator 150 is configured to control the generation of a series of 550 multi-stage negative pulse waveforms 401 to establish a PV waveform at the bias electrode 104 or the edge control electrode 115. In some embodiments, the multi-stage negative pulse waveforms 401 include a series of repeating cycles, such that the waveform within each cycle has a first portion appearing during a first time interval and a second portion appearing during a second time interval. The multi-stage negative pulse waveforms 401 will also include a positive voltage present only during at least a portion of the first time interval, and the pulse voltage waveform is substantially constant during at least a portion of the second time interval. The output of the PV waveform generator 150 is connected to a negative voltage supply for at least a portion of the second time interval.

[0066] See Figure 4A and Figure 4DIn one example, the substrate PV waveform 425 is a series of PV waveforms established on the substrate, at the bias electrode 104 or edge control electrode 115, attributable to the PV waveforms formed by the PV waveform generator 150. The substrate PV waveform 425 is established on the substrate surface during processing and includes a sheath collapse and ESC recharge phase 450 (or, for ease of discussion, sheath collapse phase 450) extending between points 420 and 421 of the illustrative substrate PV waveform 425, a sheath formation phase 451 extending between points 421 and 422, and an ion current phase 452 extending between point 422 and point 420, returning to the pulse voltage waveform established in the next sequence. Plasma potential profiles illustrate the local plasma potential during the delivery of negative pulse waveforms 401, which are established at the bias electrode 104 and / or edge control electrode 115 using one or more PV waveform generators 150.

[0067] In this example, during processing in the processing chamber 100, the multi-stage negative pulse waveform 401 is formed when the PV waveform generator 150 supplies and controls the delivery of negative voltage during two phases of the established multi-stage negative pulse waveform 401 (such as a PV waveform that tends toward the negative direction and / or remains at a negative voltage level (e.g., the ion current phase)). Figure 4A For example, these negative voltage-containing portions of the negative pulse waveform 401 will be analogized to the sheath formation phase 451 and ion current phase 452 of the substrate PV waveform 425. In this case, for the multi-stage negative pulse waveform 401, the delivery of a negative voltage from the PV waveform generator 150 occurs during the second phase 406, extending from point 411 or between point 411 (i.e., the peak of the multi-stage negative pulse waveform 401) and the start of the sheath collapse phase 450 of the substrate PV waveform coinciding with the same point 413. In some embodiments, during the ion current phase 452, which partially coincides with the multi-stage negative pulse waveform 401 established between points 412 and 413, the PV waveform generator 150 is configured to provide a constant negative voltage (e.g., V). OUT For example, the ion current (I0) is attributed to the deposition of positive charges on the substrate surface during ion current phase 452. i The voltage at the substrate surface will increase over time, as can be seen from the positive slope of the line between points 422 and 420. This increase in voltage at the substrate surface over time will decrease the sheath voltage and lead to the diffusion of ion energy. Therefore, it is desirable to control and set at least the PV waveform frequency (1 / T). PD T PD It is the PV waveform period ( Figure 4A This minimizes the effects of sheath voltage reduction and ion energy diffusion.

[0068] By delivering and controlling the PV waveform supplied to the bias electrode 104 during plasma processing, a desired ion capability distribution function (IEDF), such as a nearly monoenergetic IEDF, can be formed. The characteristics of generating and controlling the PV waveform (e.g., interpeak voltage, duty cycle, frequency, etc.) allow for precise control of the plasma ion density and the energy of the generated ions, and also lead to more controllable fluorinated carbon (C)-based ion distribution on the conductive material (e.g., W) surface found at the bottom of the etched features. x F y Polymer deposition on conductive material surfaces improves the etch selectivity of dry etching chemicals relative to intermediate etching of dielectric materials on conductive materials.

[0069] Figure 4B A PV waveform shaping pulse bias scheme type is illustrated, wherein a PV waveform generator 150 is configured to control the generation of a series 551 of multi-stage shaped pulse waveforms 441 established at bias electrode 104 and / or edge control electrode 115. In some embodiments, the multi-stage shaped pulse waveforms 441 are formed by the PV waveform generator 150, which is configured to supply a positive voltage during one or more phases of the voltage pulse (e.g., first region 405) and a negative voltage during one or more phases of the voltage pulse (e.g., second region 406) using one or more internal switches and a DC power supply.

[0070] In some embodiments, such as Figure 4C As shown, a PV waveform generator 150 is configured to provide a series of 552 multi-stage positive pulse waveforms 431 to a bias electrode 104 and an edge control electrode 115. Each positive pulse in the positive pulse waveforms 431 may include multiple stages, such as a sheath collapse stage, an ESC recharge stage, a sheath formation stage, and an ion current stage. In this example, a first region 405 typically includes the sheath collapse stage and the ESC recharge stage. A second region 406 typically includes the sheath formation stage and the ion current stage. In some embodiments, the multi-stage positive pulse waveforms 431 include a series of repeating cycles, such that the waveform within each cycle has a first portion occurring during a first time interval and a second portion occurring during a second time interval. The multi-stage positive pulse waveforms 431 will also include a positive voltage occurring only during at least a portion of the first time interval, and the multi-stage positive pulse waveforms 431 are substantially constant during at least a portion of the second time interval. The output of the PV waveform generator 150 is connected to a positive voltage supply for at least a portion of the first time interval.

[0071] In respectively Figure 4A , Figure 4B and Figure 4CThe various pulse voltage waveforms 401, 441, and 431 shown represent the pulse voltage waveforms provided to the input of the bias compensation module 116, and therefore may differ from the pulse voltage waveforms established at the bias electrode 104 and the edge control electrode 115. The DC offset ΔV found in each PV waveform depends on various properties of the configuration of the PV waveform generator 150 used to establish the PV waveform.

[0072] In some embodiments, a series of short pulses of at least one or more types of pulse voltage waveforms 401, 441, and / or 431 are established at the bias electrode 104 and / or the edge control electrode 115 and at the substrate surface. In one example, the plurality of pulses within each short pulse includes a series of negative pulse waveforms 401 established at the bias electrode 104 and / or the edge control electrode 115. In one example, each of the short pulses of the pulse voltage waveforms includes a pulse having a waveform with a consistent pulse voltage shape (e.g., a constant voltage magnitude value provided during a portion of each PV waveform 401) and a short pulse delivery length T that can vary with time between short pulses. ON And the short pulse resting length T, which can also vary with time. OFF Short pulse resting length T OFF By pausing delivery during the short pulse delivery length T ON The PV waveform provided during the time period is formed over a certain period of time. The short pulse work cycle (i.e., the short pulse delivery length T) is... ON The duration of delivering multiple pulses during the period divided by the duration of the short pulse period (i.e., T) BD =T ON +T OFF The ratio of the pulses may be constant or vary over time. It will be understood that in other processing methods, the multiple pulses may include a negative pulse waveform 401, a shaped pulse waveform 441, or a positive pulse waveform 431, or a combination thereof.

[0073] Example of selective etching of silicon dioxide

[0074] As previously mentioned, the plasma etching process involved in manufacturing 3D NAND devices is becoming increasingly challenging. Specifically, stepped contact etching in 3D NAND technology provides access to cells at the bottom of the NAND stack, thereby allowing a layer of conductive material (e.g., a tungsten-containing layer) to be embedded in the NAND stack to form portions of word lines that allow access to cell control gates from external peripheral circuitry.

[0075] Figure 5The results of a stepped contact etching process performed on a substrate according to certain embodiments described herein are shown. According to one embodiment, substrate 500 includes a mask layer 505 and a multilayer stack 501 comprising a plurality of conductive layers 520 and a plurality of intermediate dielectric material layers disposed therebetween. The plurality of intermediate dielectric material layers and the dielectric material disposed adjacent to portions of the conductive layers 520 are collectively described and referred to herein as dielectric material 510. Mask layer 505 includes a pre-etched pattern formed based on customer specifications using photolithography and mask etching processes. The patterned mask layer 505 is guided in a plasma etching process (such as...) Figure 6A The formation of features (such as trenches 515) during the process is illustrated in the diagram. The multilayer stack 501 includes a plurality of conductive layers 520, and forms staggered conductive layers 520 such that each of the trenches 515 formed during the plasma etching process described herein reaches each of the conductive layers 520 positioned at different depths (Z direction) within the multilayer stack 501. Figure 5 As shown, due to the pattern formed in the mask layer 505, each of the trenches 515 formed during the plasma etching process has a different depth and contacts a different conductive layer 520. None of the trenches 515 formed during the plasma etching process extends through the corresponding conductive layer 520.

[0076] In some embodiments, the conductive layer 520 disposed in the dielectric material 510 of the multilayer stack 501 may be composed of tungsten, platinum, titanium, ruthenium, silicon, molybdenum, cobalt and hafnium.

[0077] Figures 6A to 6C Each of the following illustrates a portion of a multilayer stack 501 during different stages of a plasma etching process for forming trench 515 in a stepped contact structure within a portion of a substrate, according to certain embodiments described herein. Figure 6A A substrate with a patterned mask layer 505 formed prior to the plasma etching process for forming trench 515 is shown, referred to herein as time T0 for illustrative purposes. The pre-etching of the mask layer 505 distinguishes the locations where etching is intended to occur within the dielectric layer 510 during subsequent plasma etching processes.

[0078] Figure 6B The illustration shows the substrate 500 during a plasma etching process when the conductive layer 520 of the substrate 500 is contacted by a plasma process. In this example, as... Figure 6B As shown, due to the pattern formed in mask layer 505, the plasma etching process creates two trenches in dielectric layer 510. During the plasma etching process, plasma (e.g., plasma formed in the plasma processing chamber) Figure 7The plasma (530) interacts with the dielectric material 510 through the patterned mask layer 505 and forms trenches 515 within the dielectric material 510 after a period of time. Because the composition of the mask layer 505 used during the etching process and the composition of the plasma chemicals are etched such that minimal etching occurs during the process, the plasma does not etch the mask layer 505 and only etches the dielectric material 510 exposed through the patterned mask layer 505. Each of the trenches 515 has the same depth at this point in time during the plasma etching process; for descriptive purposes, this point in time is referred to herein as time T1. In some embodiments, the plasma etching process operates in the manner described above.

[0079] Figure 6C The substrate 500 is shown at the completion of the plasma etching process, referred to herein as time T2 for illustrative purposes. The plasma etching process continues etching into the dielectric material 510 within trenches 515 distinguished by patterned mask layers 505. Due to the composition of the conductive layer 520 and the requirements for certain components of the plasma chemicals used to perform the etching process, the conductive layer 520 will undergo some undesirable etching, while the plasma etching process continues after the conductive layer 520 is first exposed at time T1 (e.g., ...). Figure 6C (As shown in the diagram). The etching rate into the conductive layer 520 is much lower than the etching rate into the dielectric material 510. Therefore, the plasma etching process etches into the dielectric material 510 to form trenches in the dielectric material 510 until the plasma 530 reaches one or more conductive layers 520 within the multilayer stack 501, or the base layer 525 of the substrate 500. As the plasma 530 reaches one or more conductive layers 520 or the base layer 525 of the substrate 500, the etching rate decreases, while the etching rate through the dielectric material 510 remains the same until it reaches another conductive layer or the base layer 525 of the substrate 500.

[0080] As mentioned above, the plasma etching process etches into the dielectric material 510 to form trenches within it until the plasma 530 reaches one or more conductive layers 520. As the plasma 530 etches through the dielectric material 510 and reaches the conductive layer 520, the etching rate is reduced or suppressed due to the use of desired dry etching chemicals during the plasma etching process, and due to the selectivity of the etching chemical composition relative to the materials in the conductive layer 520 of the dielectric material 510. As further discussed below, the dry etching chemicals, or process gases, may include fluorocarbon gases (e.g., C). x F yThe interface formed at the surface of the conductive layer 520 may consist of a polymer material formed by exposing dry etching chemicals to the conductive layer material found at the bottom of the etched features. For example, if one or more conductive layers 520 are made of tungsten (W), the plasma etching process forms a polymer material on the surface of the tungsten material and thus protects the otherwise exposed surface. In some examples, the interface formed is a fluorocarbon-based polymer deposited on the surface of one or more conductive layers 520 to better prevent plasma radical etching. As the dry etching plasma process proceeds, the interface may be formed on each of the one or more conductive layers 520 disposed at different depths within the substrate. Forming one or more interfaces on one or more conductive layers contributes to etching selectivity. That is, the plasma etching process involves selectively etching the dielectric material 510 and avoiding etching into one or more conductive layers 520 by forming interfaces on the etched surfaces of one or more conductive layers 520. In some examples, forming interfaces on one or more conductive layers 520 promotes etching selectivity of the substrate, such that the plasma 530 (e.g., Figure 7 (As shown in the figure) selectively etched into the dielectric material 510 of the substrate 500 and not etched into one or more conductive layers 520 or other underlying material layers.

[0081] Figure 7 Enhanced etch selectivity is shown according to an example plasma etching process. In PV waveforms (e.g., in PV pulses) Figure 4D During the ESC recharge phase (part of the positive jump within the plasma), the sheath thickness of plasma 530 decreases and substrate 500 undergoes plasma radical etching, or etching primarily by radicals relative to more isotropic ions. During plasma radical etching, fluorocarbon radicals are deposited into trenches 515 of substrate 500, and thus plasma radicals are advantageously used to form polymer deposits on the surfaces of one or more conductive layers 520. Once the ESC recharge phase ends, the sheath of plasma 530 forms and during the ion current phase ( Figure 4D During this period, the substrate 500 undergoes plasma ion etching, or etching primarily by ions relative to more anisotropic free radicals.

[0082] Figure 8 Includes curve 801 according to one embodiment, which illustrates the sheath thickness during a plasma etching process. The sheath thickness varies with PV waveform 401, which... Figure 4DThe diagram shows the changes over time. Specifically, during the ESC recharge phase 450, the sheath thickness decreases and the substrate may undergo plasma radical etching, or etching primarily by radicals relative to more isotropic ions. Once the ESC recharge phase 450 ends, the sheath is formed during the sheath formation phase 451, and during the ion current phase 452, the substrate undergoes plasma ion etching, or etching primarily by ions relative to more anisotropic radicals. During the ion current phase 452, the sheath thickness may decrease linearly with increasing wafer voltage during the ion current phase 452.

[0083] Figure 9 This is a flowchart illustrating an example operation 900 for processing a substrate in a plasma processing chamber according to certain embodiments of this disclosure. Operation 900 may be performed, for example, in a plasma processing chamber (e.g., such as...) Figure 1 It is performed in the plasma processing chamber 100.

[0084] In operation 905, operation 900 may be initiated by positioning a substrate on the substrate support surface of a substrate support assembly disposed within the processing region of the plasma processing chamber, the substrate including a patterned mask layer and a first dielectric material formed thereon. Operation 905 typically includes operations performed in operations 910-920, which may be performed in any order, but will typically be performed simultaneously for most of the time during which operation 905 is performed.

[0085] In operation 910, the plasma etching process involves delivering dry etching chemicals into the processing area of ​​a plasma processing chamber. The dry etching chemicals may include a first fluorocarbon gas (e.g., C). x F yThe process involves delivering dry etching chemicals (such as C4F6, C3F6, etc.) and a first processing gas to the processing area of ​​the plasma processing chamber. This delivery of the dry etching chemicals involves delivering two or more gases selected from, but not limited to, the following: N2 gas at a first flow rate, krypton (Kr) gas at a second flow rate, C4F6 gas at a third flow rate, C3F6 gas at a fourth flow rate, and O2 gas at a fifth flow rate. The plasma etching process will also include controlling the chamber pressure, substrate support temperature, top temperature, and support helium (He) pressure. The first flow rate of N2 can vary between 5 sccm and 1000 sccm. The second flow rate of Kr can vary between 5 sccm and 1000 sccm. The third flow rate of C4F6 can vary between 5 sccm and 1000 sccm. The fourth flow rate of C3F6 can vary between 5 sccm and 1000 sccm. The fifth flow rate of O2 can vary between 5 sccm and 1000 sccm. The plasma etching process will also include controlling the chamber pressure within a range of 1 mTorr to 500 mTorr. The plasma etching process will also include controlling the substrate support temperature within a range of -80 to 500°C. The plasma etching process will also include controlling the top temperature within a range of 10°C to 500°C. The plasma etching process may also include controlling the He pressure within a range of 0-100 Torr. In one example, the plasma etching process includes delivering a process gas having a composition formed by: generating a C4F6 gas flow rate to C3F6 gas flow rate ratio of approximately 4, a C4F6 gas flow rate to O2 gas flow rate ratio of approximately 2, a C4F6 gas flow rate to N2 gas flow rate ratio of approximately 1.1, and a C4F6 gas flow rate to Kr gas flow rate ratio of approximately 0.7 at a chamber pressure between approximately 1 mTorr and approximately 40 mTorr.

[0086] In operation 915, the plasma etching process involves delivering a radio frequency (RF) signal to a first electrode disposed within a plasma processing chamber using an RF generator to form plasma in the processing area. Delivering the RF signal to the first electrode disposed within the plasma processing chamber to form plasma involves parameters including, but not limited to, the following: power supply and frequency. The RF power supply may vary between 500 W and 5000 W at frequencies >400 kHz (e.g., 2 MHz, 13.56 MHz, 40 MHz, or 60 MHz).

[0087] In operation 920, the plasma etching process involves establishing a first pulse voltage waveform at a bias electrode within a substrate support assembly using a first pulse voltage waveform generator. The first pulse voltage waveform may involve a series of repetitive pulse waveform cycles. Each pulse waveform cycle includes a first time interval (…). Figure 8 The first part that appears during the period of 810) and the second time interval ( Figure 8 The second portion occurs during (811) of the second time interval, and the second time interval is greater than the first time interval. Each pulse waveform cycle also includes an inter-peak voltage. The pulse voltage waveform output from the first pulse voltage waveform generator is substantially constant for at least a portion of the second time interval. The first time interval of each pulse waveform cycle may include a sheath collapse phase, an ESC recharge phase, and a sheath formation phase. The second time interval of each pulse waveform cycle may include an ion current phase. In some examples, the plasma etching process involves plasma radical etching during the first time interval and plasma ion etching during the second time interval. During the second time interval of each pulse waveform, the plasma etches through the dielectric material via plasma ion etching, and during the first time interval of each pulse waveform, the plasma etches one or more conductive layers via plasma radical etching.

[0088] Delivering a pulsed voltage waveform to a bias electrode 104 disposed within a plasma processing chamber involves delivering a pulsed voltage waveform having parameters including, but not limited to, the following: PVT bias power, duty cycle, pulse frequency, peak-to-peak voltage, and flow ratio control (FRC). The bias power can vary between 500 W and 500,000 W. For a PV waveform generator 150 configured to provide a positive output voltage during the generation of a positive pulse waveform 431, the duty cycle can vary between 0 and 100%, such as between 1 and 99%, or even between 5% and 20%; or for a PV waveform generator 150 configured to provide a negative output voltage during the generation of a negative pulse waveform 401, the duty cycle is between 50% and 98%. The pulse frequency can vary between 1 and 1000 kHz, such as between approximately 10 kHz and approximately 500 kHz, or between approximately 50 kHz and 400 kHz, or even between approximately 50 kHz and 200 kHz. For all FRC channels, the FRC can vary between 0 and 100%. The peak-to-peak voltage of each of the PV waveforms generated by the PV waveform generator 150 within a series of PV waveforms is between 0.5 kV and 20 kV, such as between approximately 2 kV and 20 kV, or between approximately 5 kV and 9 kV, or between approximately 5 kV and 8 kV. It has been found that higher peak-to-peak voltages increase the characteristic etching rate and also surprisingly improve the selectivity for etching tungsten using dry etching chemicals as described in operation 910, and other processing parameters disclosed herein, such as those in operations 915 and 920.

[0089] Operation 900 can complete the desired time period, or until the desired endpoint is sensed within the plasma processing chamber, allowing the etching process to be performed across one or more layers of a multilayer stack, as described above. Figures 5 to 6C The process described. In some embodiments, one or more software algorithms within controller 126 are used to monitor, control, and / or implement the process executed within operation 900.

[0090] While the foregoing relates to embodiments of this disclosure, other and further embodiments of this disclosure may be designed without departing from its essential scope, the scope of which is defined by the appended claims.

Claims

1. A method for processing a substrate in a plasma processing chamber, comprising the following steps: Etching a first dielectric material formed on a substrate disposed on a substrate support surface of a substrate support assembly disposed within the processing area of ​​the plasma processing chamber, the substrate comprising one or more conductive layers, wherein the step of etching the first dielectric material comprises: etching one or more trenches through the first dielectric material, wherein each of the one or more trenches has a different depth and each of the one or more trenches contacts a different conductive layer of the one or more conductive layers, wherein the step of etching the first dielectric material comprises: A processing gas is delivered to the processing area of ​​the plasma processing chamber, wherein the processing gas comprises a first fluorocarbon gas and a first processing gas; A radio frequency signal is delivered to a first electrode placed inside the plasma processing chamber using a radio frequency generator to form plasma in the processing area. and A first pulse voltage waveform is generated at a bias electrode disposed within the substrate support assembly using a first pulse voltage waveform generator. The first pulse voltage waveform comprises a series of repetitive pulse waveform cycles. Each pulse waveform cycle contains: The first portion occurring during a first time interval and the second portion occurring during a second time interval, wherein the second time interval is greater than the first time interval; and Interpeak voltage; as well as The pulse voltage waveform is constant during at least a portion of the second time interval.

2. The method of claim 1, wherein the first time interval is between 200 ns and 400 ns.

3. The method of claim 1, wherein the first time interval is less than 20% of the cycle in the series of repetitive pulse waveform cycles.

4. The method of claim 3, wherein the pulse voltage waveform within each pulse waveform cycle has an inter-peak voltage between 5 kV and 20 kV.

5. The method of claim 1, wherein the processing gas comprises a second fluorocarbon gas and a second processing gas.

6. The method of claim 1, wherein the first fluorocarbon gas comprises at least one of C4F6 or C3F6, and the first processing gas comprises at least one of N2, Kr, and O2.

7. The method of claim 1, further comprising the following steps: A mask is placed on the substrate; The substrate having the mask is provided within the plasma processing chamber; and The first dielectric material is etched based on multiple parameters.

8. The method of claim 1, wherein the one or more conductive layers comprise at least one of tungsten, platinum, titanium, ruthenium, and silicon.

9. The method of claim 1, wherein the one or more conductive layers comprise at least one of molybdenum, cobalt, and hafnium.

10. The method of claim 1, wherein each of the one or more trenches does not penetrate any of the one or more conductive layers.

11. The method of claim 1, wherein the ends of each of the one or more conductive layers are displaced from one another to form a stepped pattern.

12. The method of claim 1, wherein The step of delivering the processing gas to the processing region of the plasma processing chamber is set at a chamber pressure between 1 mTorr and 500 mTorr, wherein the step of delivering the processing gas includes: flowing the first fluorocarbon-containing gas at a first flow rate and flowing the first processing gas at a second flow rate; and The pulse voltage waveform established at the bias electrode contains a duty cycle between 1 and 99%.

13. The method of claim 12, wherein the first fluorocarbon gas comprises at least one of C4F6 or C3F6, and the first processing gas comprises at least one of N2, Kr, and O2.

14. The method of claim 13, wherein The series of repetitive pulse waveforms are provided at a pulse frequency between 300 and 500 kHz, and The step of etching the first dielectric material further includes maintaining the temperature of the substrate support surface in the range between -80°C and 500°C.

15. A method for processing a substrate in a plasma processing chamber, comprising the following steps: A mask is disposed on the substrate, the substrate comprising one or more conductive layers; The substrate having the mask is provided on the substrate support surface of the substrate support assembly disposed within the processing area of ​​the plasma processing chamber. Etch a first trench through the first dielectric material formed on the substrate until the first trench reaches the first conductive layer in one or more conductive layers; as well as Etching a second trench through the first dielectric material beyond the depth of the first trench until the second trench reaches the second conductive layer in the one or more conductive layers, wherein the step of etching the first trench and the second trench includes: A processing gas is delivered to the processing area of ​​the plasma processing chamber, wherein the processing gas comprises a first fluorocarbon gas and a first processing gas; A radio frequency signal is delivered to a first electrode placed inside the plasma processing chamber using a radio frequency generator to form plasma in the processing area. and A first pulse voltage waveform is generated at a bias electrode disposed within the substrate support assembly using a first pulse voltage waveform generator. The first pulse voltage waveform comprises a series of repetitive pulse waveform cycles, each of which includes: The first portion occurring during a first time interval and the second portion occurring during a second time interval, wherein the second time interval is greater than the first time interval; and Interpeak voltage, of which The first pulse voltage waveform is constant during at least a portion of the second time interval.

16. The method of claim 15, further comprising the following steps: The third trench is etched through the first dielectric material to a depth greater than that of the second trench, until the third trench reaches the base layer of the substrate.

17. The method of claim 15, wherein the step of etching the second trench comprises: etching to a depth matching the depth of the first trench.

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