Storage system and methods for controlling storage system

Abstract

A high-read-performance storage system and a method for controlling the storage system to improve read performance are provided. A first circuit, upon receiving a read request from the host specifying a logical address range greater than a predetermined size, issues multiple first sub-commands, each representing a first data unit, in logical address order. A second circuit assigns a sequential number to each of the multiple first sub-commands. Multiple third circuits, for each of the multiple first sub-commands, share the processing of determining the location of the first data unit based on management information. A fifth circuit, after processing by the multiple third circuits, arranges the multiple first sub-commands in logical address order based on their sequential numbers. A sixth circuit performs a read operation on the first memory based on the logically address-ordered multiple first sub-commands.

Description

[0001] Related applications

[0002] This application enjoys priority over Japanese Patent Application No. 2021-203709 (filed on December 15, 2021). This application is incorporated herein by reference to the entire contents of that earlier application. Technical Field

[0003] Embodiments of the present invention relate to a storage system and a method for controlling the storage system. Background Technology

[0004] Previously, memory systems with non-volatile memory were known. In one example, non-volatile memory is NAND flash memory. Summary of the Invention

[0005] One objective of this implementation is to provide a storage system with high read performance and a method for controlling the storage system that can improve read performance.

[0006] One embodiment of the storage system is capable of being connected to a host. The storage system includes: a first memory, a second memory, and a storage controller. The first memory is a non-volatile memory configured to store data received from the host. The second memory is configured to store management information that associates logical addresses used by the host with the locations where the data is stored in the first memory, per first data unit. The storage controller includes: a first circuit, a second circuit, a plurality of third circuits, a fourth circuit, a fifth circuit, and a sixth circuit. The storage controller receives from the host a read request specifying a consecutive logical address range of the size of the plurality of first data units. The first circuit is configured to, in response to receiving the read request, issue the plurality of first sub-commands requesting the reading of all first data units contained within the logical address range in order of the logical addresses. Each of the plurality of first sub-commands requests the reading of one first data unit. The second circuit is configured to attach a first consecutive number corresponding to the issuance order to each of the plurality of first sub-commands, and then allocate the plurality of first sub-commands, each with the attached first consecutive number, to the plurality of third circuits. Each of the plurality of third circuits is configured to determine, by referring to the management information, the storage location of the first data unit related to the first sub-command allocated to itself within the plurality of first sub-commands, and attach location information indicating the determined storage location to the first sub-command. The fourth circuit is configured to obtain the plurality of first sub-commands, each with the attached location information, from the plurality of third circuits. The fifth circuit is configured to arrange the plurality of first sub-commands obtained by the fourth circuit in order based on the first consecutive number. The sixth circuit is configured to perform a read operation on the first memory based on the arranged plurality of first sub-commands. Attached Figure Description

[0007] Figure 1 This is a schematic diagram illustrating an example of the hardware configuration of a storage system in an implementation method.

[0008] Figure 2 This is a schematic diagram illustrating an example of the configuration of a memory chip in an implementation method.

[0009] Figure 3 This is a schematic diagram illustrating the information stored in the memory of the storage system provided in the embodiment.

[0010] Figure 4 This is a schematic diagram illustrating the details of the LUT used to explain the implementation method.

[0011] Figure 5 This is a schematic diagram illustrating an example of the multiple circuits included in the storage controller of an embodiment.

[0012] Figure 6 This is a schematic diagram illustrating an example of the construction of a lookup message transmitted within the storage controller of an implementation.

[0013] Figure 7 This is a schematic diagram illustrating an example of the configuration of the arrangement circuit in the implementation method.

[0014] Figure 8 This is a schematic diagram illustrating an example of message lookup control in the case of sequential read, implemented by the storage controller of the embodiment.

[0015] Figure 9 This is a schematic diagram illustrating another example of message lookup control implemented by the storage controller of the embodiment in the case of sequential reading.

[0016] Figure 10 This is a flowchart illustrating an example of an action that generates a lookup message based on a read request from the first processing circuit of the implementation method.

[0017] Figure 11 This is a flowchart illustrating an example of the operation of the second processing circuit in the implementation method.

[0018] Figure 12 This is a flowchart illustrating an example of the actions of the LUT engine in an implementation.

[0019] Figure 13 This is a flowchart illustrating an example of the operation of the third processing circuit in the implementation method.

[0020] Figure 14 This is a flowchart illustrating an example of the operation of the arrangement circuit in the implementation method.

[0021] Figure 15 This is a flowchart illustrating an example of the operation of the CPU in an embodiment of processing a lookup message sent from the third processing circuit.

[0022] Figure 16 This is a flowchart illustrating an example of the CPU's actions in an implementation where it sequentially retrieves and processes messages from a group of message buffers.

[0023] Figure 17 This is a flowchart illustrating an example of the operation of sending cluster data of the read object of the first processing circuit of the embodiment to the host. Detailed Implementation

[0024] Hereinafter, the storage system and method according to embodiments will be described in detail with reference to the accompanying drawings. However, this invention is not limited by these embodiments.

[0025] (Implementation Method)

[0026] Figure 1 This is a schematic diagram illustrating an example of the hardware configuration of a storage system in an implementation method.

[0027] Storage system 1 is configured to connect to host 2. The standard for the connection between storage system 1 and host 2 is not limited to a specific standard. Host 2 may be, for example, a personal computer, a portable information terminal, or a server.

[0028] When host 2 accesses storage system 1, it sends an access request to storage system 1. The access request can be a write request or a read request, etc. The access request is accompanied by logical address and size information. The logical address represents the location within the logical address space provided by storage system 1 to host 2. In other words, when host 2 accesses storage system 1, it uses a logical address to specify the access destination. The logical address can also be called an LBA (Logical Block Address). The size information included in the access request indicates a contiguous range within the logical address space, starting from the location specified by the logical address. That is, in each access request, host 2 specifies the access range within the logical address space through logical address and size information.

[0029] In addition, host 2 sends the data of the write object corresponding to the write request, that is, the data to be written, to storage system 1. This data sent from host 2 to storage system 1 is marked as user data.

[0030] The storage system 1 includes: a storage controller 10, a NAND flash memory (NAND memory) 20, and a DRAM (Dynamic Random Access Memory) 30.

[0031] NAND memory 20 is a non-volatile memory that functions as storage for storing user data. NAND memory 20 is an example of a first memory configured to store user data. As the first memory, any type of non-volatile memory can be used.

[0032] The storage controller 10 performs control of the storage system 1. This control includes control related to data transfer between the host 2 and the NAND memory 20. The storage controller 10 uses the DRAM 30 as a buffer memory for data transfer or as a cache memory for caching management information.

[0033] The LUT (LookUp Table) 50 and LUT segment 51, described later, are examples of management information. DRAM 30 is an example of a second memory configured to store management information.

[0034] Furthermore, DRAM30 is an example of a third memory configured to store user data received from host 2 until that user data is stored in NAND memory 20. The second and third memories can be configured as other memories, or they can be configured as a single memory such as DRAM30 in this embodiment.

[0035] The NAND memory 20 consists of one or more memory chips 21. Each of the memory chips 21 is connected to the memory controller 10 via one or more channels. Figure 1 In the example shown, the NAND memory 20 includes memory chips 21-0, 21-1, 21-2, and 21-3. Memory chips 21-0 and 21-1 are connected to the memory controller 10 via channel ch.0, and memory chips 21-2 and 21-3 are connected to the memory controller 10 via channel ch.1. Furthermore, the number of memory chips 21 constituting the NAND memory 20 and the number of channels connecting the NAND memory 20 and the memory controller 10 are not limited thereto.

[0036] Figure 2 This is a schematic diagram illustrating an example of the configuration of the memory chip 21 in the embodiment. The memory chip 21 includes a memory cell array 211 and a page register 212. The page register 212 is an example of a first buffer.

[0037] The storage cell array 211 comprises multiple blocks. All data stored in a block can be erased simultaneously. Each block contains multiple storage regions called pages. Each page is allocated a contiguous physical address. Writes and reads to the storage cell array 211 are performed on a page-by-page basis. Sometimes, data stored in pages is labeled as page data.

[0038] Page register 212 has a capacity of at least the page size. Page register 212 holds page data received from memory controller 10 as write targets until the program on memory cell array 211 is completed. In addition, page register 212 holds page data read from memory cell array 211 until the transfer of page data to memory controller 10 is completed. Furthermore, the action of reading page data from memory cell array 211 and storing the read page data in page register 212, that is, the action of transferring page data from memory cell array 211 to page register 212, is marked as a sense action.

[0039] Data transfer from page register 212 to memory controller 10 is performed in units of clusters. A cluster is a region in the logical address space that is assigned a logical address of the smallest size. The size of a cluster is smaller than the size of a page. Thus, page data read from memory cell array 211 and stored in page register 212 contains multiple cluster data 40. A cluster is an example of a first data unit. Each cluster data 40 is an example of data in a first data unit. By specifying the physical address within the page to memory chip 21, memory controller 10 can cause the desired cluster data 40 in the page data read from memory cell array 211 and stored in page register 212 to be output from page register 212.

[0040] Figure 3 This is a schematic diagram illustrating the information stored in the multiple memory units of the storage system 1 provided in the embodiment.

[0041] The NAND memory 20 non-volatilely stores user data DAT.

[0042] Additionally, the NAND memory 20 non-volatilely stores a LUT 50. The LUT 50 is a group of address translation information that associates the logical address of each cluster with the physical address representing a location within the NAND memory 20. The LUT 201 has a data structure that arranges the physical addresses corresponding to the logical addresses of each cluster in logical address order.

[0043] Figure 4 This is a schematic diagram illustrating the details of the LUT50 used to explain the implementation method.

[0044] In recent years, storage systems with very large user capacity have been developed. The larger the user capacity, the larger the maximum logical address, and the more entries the LUT can have. In other words, the larger the user capacity, the larger the size of the LUT.

[0045] In this implementation, to improve the speed of using LUT50, LUT50 is cached in DRAM30. However, when the tag capacity of storage system 1 is large, caching LUT50 in DRAM30 requires a large-capacity DRAM30, which is costly. Therefore, DRAM30 is configured in storage system 1 to cache a portion of LUT50. Alternatively, storage system 1 can be configured to cache the entire LUT50 in DRAM30.

[0046] LUT 50 is divided into multiple LUT segments 51, and cached in DRAM 30 in units of LUT segments 51. That is, LUT 50 is refilled into DRAM 30 in units of LUT segments 51, and evicted into NAND memory 20 in units of LUT segments 51. The size of LUT segments 51 is, for example, common to all LUT segments 51. The size of LUT segments 51 can be determined, for example, based on the unit of access to DRAM 30.

[0047] Each LUT segment 51 is assigned a segment index. In one example, the segment index is a consecutive number assigned in ascending logical address order, starting from the LUT segment 51 corresponding to the beginning of the logical address space. Figure 4 In the example shown, LUT50 is divided into m+1 LUT segments 51, and each LUT segment 51 is assigned a number from 0 to m as a segment index. For example, the value obtained by deleting the number of low-order bits corresponding to the number of entries contained in the LUT segment 51 from the logical address is used as the segment index.

[0048] Furthermore, the segment index is an example of the third consecutive number.

[0049] return Figure 3 Explanation.

[0050] DRAM 30 is allocated with LUT cache 31, write buffer 32, and read buffer 33. LUT cache 31 is a cache area obtained by caching multiple LUT segments 51. Write buffer 32 stores user data DAT received from host 2 until it is saved to NAND memory 20. Read buffer 33 stores user data DAT read from NAND memory 20 until its transmission to host 2 is completed.

[0051] The storage controller 10 internally includes an SRAM 11. The SRAM 11 is allocated a work area 70 and a queue area 71.

[0052] When the storage controller 10 (specifically, the multiple LUT engines 14 described later) uses a certain LUT segment 51, it transfers the LUT segment 51 from the LUT cache 31 to the SRAM 11, and uses the LUT segment 51 transferred to the SRAM 11. Using the LUT segment 51 includes referencing the LUT segment 51 and updating the LUT segment 51. When the storage controller 10 updates the LUT segment 51 in the SRAM 11, it writes the updated LUT segment 51 back to the LUT cache 31 in a timely manner.

[0053] Queue area 71 is allocated multiple queues. Each queue has a data structure for sending and receiving information between the circuits provided by the storage controller 10. The circuits provided by the storage controller 10 will be described later.

[0054] Furthermore, the SRAM 11 can be configured in one place within the memory controller 10 or distributed in multiple locations. Some or all of the SRAM 11 can also be integrated into any circuitry of the memory controller 10.

[0055] Figure 5 This is a schematic diagram illustrating an example of the multiple circuits included in the storage controller 10 of the embodiment.

[0056] The storage controller 10 comprises multiple circuits, including a first processing circuit 12, a second processing circuit 13, multiple LUT engines 14, a third processing circuit 15, a reordering circuitry 16, and a CPU (Central Processing Unit) 17. Each of the first processing circuit 12, the second processing circuit 13, the multiple LUT engines 14, and the third processing circuit 15 is constructed from hardware circuits such as an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). However, some or all of the first processing circuit 12, the second processing circuit 13, the multiple LUT engines 14, and the third processing circuit 15 may be constructed using a processor that operates based on a computer program, such as a CPU, or a processor that operates based on a computer program in conjunction with hardware circuits. The CPU 17 executes various processes based on firmware. However, some or all of the processes executed by the CPU 17 may also be executed by hardware circuits.

[0057] Processing circuit 12 is an example of circuit 1. Processing circuit 13 is an example of circuit 2. Multiple LUT engines 14 are each an example of circuit 3. Processing circuit 15 is an example of circuit 4. Arrangement circuit 16 is an example of circuit 5. CPU 17 is an example of circuit 6.

[0058] The first processing circuit 12 generates one or more messages that request processing in clusters based on the access request received from the host 2.

[0059] For example, when the first processing circuit 12 receives an access request for accessing a logical address range of N clusters, it generates a message for each of the N clusters contained in that logical range. The message generated when the received access request is a read request is marked as a lookup message.

[0060] A lookup message is a subcommand requesting the reading of one cluster of data 40. Lookup messages are sequentially transmitted to several circuits configured after the first processing circuit 12. Each circuit receiving a lookup message during transmission executes part of a series of processes to store one cluster of data 40 from the requested user data DAT in DRAM 30.

[0061] Figure 6 This is a schematic diagram illustrating an example of the construction of a lookup message transmitted within the storage controller 10 of the embodiment. From now on, using... Figure 5 as well as Figure 6 This section explains the functions of each circuit in the storage controller 10 and the structure of the lookup messages transmitted by each circuit.

[0062] like Figure 6 As shown, the lookup message Ma sent by the first processing circuit 12 contains a logical address. The logical address contained in the lookup message Ma represents the location of one of the more than one clusters within the logical address range specified by the read request in the logical address space.

[0063] Furthermore, from now on, all lookup messages that contain lookup message Ma and are transmitted within the storage controller 10 will be referred to as lookup message M.

[0064] The lookup message Ma may contain a sequential read flag. Specifically, upon receiving a read request, the first processing circuit 12 determines whether the access pattern associated with the read request is a sequential read. If the access pattern is determined to be a sequential read, the first processing circuit 12 appends the sequential read flag to the lookup message Ma. If the access pattern is determined not to be a sequential read, the first processing circuit 12 does not append the sequential read flag to the lookup message Ma.

[0065] Sequential read refers to an access mode in which cluster data 40 is read in logical address order from a contiguous logical address range of a certain number (but more) of cluster sizes. That is, when the first processing circuit 12 receives a read request from the host 2 specifying a contiguous logical address range corresponding to the size of multiple cluster data 40, it generates multiple lookup messages Ma requesting the reading of all cluster data 40 within that logical address range. Furthermore, the first processing circuit 12 adds a sequential read flag to each of the generated multiple lookup messages Ma.

[0066] In addition to sequential read, the access modes for storage system 1 also include sequential write, random read, and random write. Sequential write refers to the access mode where cluster data 40 is written in logical address order within a contiguous range of logical addresses equal to a certain number (or multiple) of cluster sizes. Random read refers to the access mode where a small number (or multiple) of cluster data 40 is read from various locations in multiple non-contiguous logical addresses. Random write refers to the access mode where a small number (or multiple) of cluster data 40 is written to various locations in multiple non-contiguous logical addresses.

[0067] The multiple clusters of data 40 read sequentially are mostly written from the host 2 in a sequential write access mode. Furthermore, when user data DAT is received from the host 2 in a sequential write access mode, the storage controller 10 essentially writes the received user data DAT to a contiguous range of physical addresses in the NAND memory 20. Thus, when user data DAT written to the NAND memory 20 is requested to be read in a sequential read access mode, the storage controller 10 is generally able to retrieve two or more clusters of data 40 constituting the user data DAT from a single page.

[0068] As previously described, during a read operation on memory chip 21, multiple cluster data 40 are transferred from memory cell array 211 to page register 212 in page units via a sensing operation. Then, the desired cluster data 40 is transferred from page register 212 to memory controller 10. In the case of sequential reads, since a single page of data typically contains multiple cluster data 40 that are the target of the read, the number of cluster data 40 that can be acquired with each sensing operation increases, thus improving read efficiency.

[0069] The first processing circuit 12 detects sequential read access patterns to enable efficient reading when a read request is received in a sequential read access pattern. Upon detecting a sequential read access pattern, the first processing circuit 12 appends a flag indicating sequential read, i.e., a sequential read flag, to each generated lookup message Ma.

[0070] The first processing circuit 12 sends the generated messages to the second processing circuit 13 via queue 101.

[0071] Furthermore, sequential reading is performed from multiple clusters of logically consecutive addresses. Therefore, in the case of sequential reading, the first processing circuit 12 generates multiple lookup messages Ma with an appended sequential read flag, and sends the generated multiple lookup messages Ma to the second processing circuit 13 in logical address order.

[0072] The first processing circuit 12 then saves the user data DAT received from the host 2 in the write buffer 32, or prepares an area in the read buffer 33 that can save the user data DAT read from the NAND memory 20.

[0073] Before the second processing circuit 13, the multiple LUT engines 14 will be described. Each LUT engine 14 references or updates the LUT segment 51 based on a message. When referencing or updating the LUT segment 51, the LUT engine 14 transfers the LUT segment 51 as the target from the LUT cache 31 to the SRAM 11 and performs reference or update on the LUT segment 51 in the SRAM 11.

[0074] Referencing and updating LUT segment 51 requires significant computational resources. Therefore, to improve the read performance of storage system 1, it is desirable to process the referencing and updating of LUT segment 51 as quickly as possible. Thus, in this embodiment, multiple LUT engines 14 for referencing or updating LUT segment 51 are provided in the storage controller 10. Each of the multiple LUT engines 14 independently performs the referencing or updating of LUT segment 51. Figure 5 and Figure 6 As an example of multiple LUT engines 14, the storage controller 10 is equipped with LUT engine 14e, which uses LUT segments 51 assigned even-numbered segment indices, and LUT engine 14o, which uses LUT segments 51 assigned odd-numbered segment indices. Furthermore, the storage controller 10 may also be equipped with three or more LUT engines 14.

[0075] Upon receiving a lookup message M (hereinafter referred to as lookup message Mb), the LUT engine 14 determines the location of the target cluster data 40 corresponding to the lookup message M within the storage system 1 by referring to the corresponding LUT segment 51 stored in the LUT cache 31. The cluster data 40 corresponding to the lookup message M is the cluster data 40 located at the logical address contained in the lookup message M, and is one cluster data 40 contained in the user data DAT that is requested to be read. The cluster data 40 corresponding to the lookup message M is marked as the cluster data 40 specified by the lookup message M as the target of reading, or simply marked as the cluster data 40 of the target of reading.

[0076] When the cluster data 40 of the read object is stored in the write buffer 32, the LUT engine 14 refers to the result of the LUT segment 51 to obtain the address (marked as the write buffer address) indicating the location where the cluster data 40 of the read object is stored in the write buffer 32. When the cluster data 40 of the read object is not stored in the write buffer 32, the LUT engine 14 refers to the result of the LUT segment 51 to obtain the address, that is, the physical address, indicating the location within the NAND memory 20.

[0077] That is, each entry in each LUT segment 51 within the LUT cache 31 can associate a write buffer address with a logical address in addition to the physical address. When a value (marked as the first value) is assigned as a logical address and cluster data 40 received from the host 2 (marked as the first cluster data 40) is stored in the NAND memory 20, if another cluster data 40 (marked as the second cluster data 40) is newly received from the host 2 with the first value assigned as a logical address, the second cluster data 40 is first stored in the write buffer 32. At almost the same time as the storage of the second cluster data 40 in the write buffer 32, in the corresponding LUT segment 51 within the LUT cache 31, the LUT engine 14 associates the write buffer address indicating the location where the second cluster data 40 is stored with the first value. When the second cluster of data 40 stored in write buffer 32 is written to NAND memory 20, LUT engine 14 associates the physical address of the destination of the second cluster of data 40 in NAND memory 20 with the first value. Subsequently, when the second cluster of data 40 in write buffer 32 is invalidated, LUT engine 14 eliminates the correspondence between the first value and the write buffer address indicating the location where the second cluster of data 40 was stored.

[0078] This section returns a description of the processing of lookup message M. LUT engine 14 uses the logical address contained in lookup message M as the search keyword to search LUT segment 51. If the search performed by LUT engine 14 yields a write buffer address as the location of the cluster data 40 to be read, LUT engine 14 appends the write buffer address as a reference result to lookup message M. If the search performed by LUT engine 14 yields a physical address that is not a write buffer address as the location of the cluster data 40 to be read, LUT engine 14 appends the physical address as a reference result to lookup message M.

[0079] In addition, sometimes the case where the write buffer address is obtained through retrieval implemented by LUT engine 14 and used as the location of cluster data 40 of the write object is marked as a hit write buffer 32.

[0080] When the second processing circuit 13 receives a lookup message M (i.e., lookup message Ma) via queue 101, it searches the LUT segment 51 of the reference destination, i.e., the LUT segment 51 containing the entry related to the logical address contained in the lookup message M, based on the logical address contained in the received lookup message M. If the LUT segment 51 of the reference destination is not cached in the LUT cache 31, the second processing circuit 13 performs a refill of the LUT segment 51 of the reference destination.

[0081] If the LUT segment 51 at the reference destination is cached in the LUT cache 31, or if the LUT segment 51 at the reference destination is refilled, the second processing circuit 13 distributes the lookup message M to the LUT engines 14e and 14o. More specifically, the second processing circuit 13 distributes the lookup message M based on the segment index of the LUT segment 51 at the reference destination. If the segment index of the LUT segment 51 at the reference destination is even, the second processing circuit 13 sends the lookup message M to the LUT engine 14e. If the segment index of the LUT segment 51 at the reference destination is odd, the second processing circuit 13 sends the lookup message M to the LUT engine 14o.

[0082] Furthermore, when the received lookup message M is given a sequential read flag, the second processing circuit 13 appends a buffer index to the lookup message M. The buffer index appended to the lookup message M is used in the arrangement circuit 16. Details will be described later, but the arrangement circuit 16 includes a message buffer group 161, which consists of multiple message buffers 163, each assigned a consecutively numbered buffer index. Each message buffer 163 is capable of storing one lookup message M. After being processed by the second processing circuit 13 and the third processing circuit 15, the lookup message M, given the sequential read flag, is stored in any one of the multiple message buffers 163 in the arrangement circuit 16. The value of the buffer index appended by the second processing circuit 13 to the lookup message M indicates the message buffer 163 that is the destination for storing the lookup message M. In other words, the second processing circuit 13 uses the buffer index appended to the lookup message M to specify the message buffer 163 that is the destination for storing the lookup message M.

[0083] When the second processing circuit 13 receives multiple lookup messages M with sequential read flags attached, it determines the buffer index value to be attached to each lookup message M, based on the state in which the multiple lookup messages M are stored in the multiple message buffers 163 in logical address order. Since the first processing circuit 12 sends the multiple lookup messages M with sequential read flags attached to the second processing circuit 13 in logical address order, the second processing circuit 13 attaches the value corresponding to the order received from the first processing circuit 12 to the multiple lookup messages M as the buffer index.

[0084] Furthermore, each of the additional buffer indices to the multiple lookup messages M for which a sequential read flag has been attached is an example of the first consecutive number.

[0085] The second processing circuit 13 stores the write pointer 131 and the read pointer 132, used to determine the value of the buffer index, in internal registers, etc. Details of the write pointer 131 and the read pointer 132 will be explained later.

[0086] The number of queues used by the second processing circuit 13 to send lookup messages M to each LUT engine 14 is not limited to a specific number. As an example, the second processing circuit 13 and LUT engine 14e are connected via two queues 102 and 103, and the second processing circuit 13 and LUT engine 14o are connected via two queues 104 and 105.

[0087] For example, when the second processing circuit 13 sends a lookup message M indicating that the segment index of the LUT segment 51 of the object is even to the LUT engine 14e, it selects either queue 102 or 103 based on the segment index of the LUT segment 51 of the object. If the value of the second least significant bit of the segment index of the LUT segment 51 of the object is even, the second processing circuit 13 selects queue 102; if the value of the second least significant bit of the segment index of the LUT segment 51 of the object is odd, the second processing circuit 13 selects queue 103.

[0088] Additionally, for example, when the second processing circuit 13 sends a lookup message to the LUT engine 140 indicating that the segment index of the LUT segment 51 of the object is odd, it selects either of two queues 104 or 105 based on the segment index of the LUT segment 51 of the object. If the value of the second bit from the least significant bit of the segment index of the LUT segment 51 of the object is even, the second processing circuit 13 selects queue 104; if the value of the second bit from the least significant bit of the segment index of the LUT segment 51 of the object is odd, the second processing circuit 13 selects queue 105.

[0089] When the second processing circuit 13 is refilling the LUT segment 51 of the reference destination related to a certain lookup message M, it cannot send the lookup message M to the LUT engine 14 until the refilling is completed. In the embodiment, since the sending path (i.e., the queue) to each LUT engine 14 is doubled, the second processing circuit 13 can process the next lookup message M without waiting for the refilling to be completed.

[0090] Furthermore, for example, if the storage system 1 is configured such that all LUT50s are cached in DRAM30, refilling is unnecessary. In this case, there will be no interruption in the processing of lookup messages due to waiting for refilling to complete. Thus, it is also unnecessary to double the sending path (i.e., queue) to each LUT engine 14.

[0091] The lookup message M transmitted from the second processing circuit 13 to each LUT engine 14 is marked as lookup message Mb. For example... Figure 6 As shown, in the case of sequential reading, the lookup message Mb has a construction that appends a buffer index to the lookup message Ma.

[0092] As mentioned earlier, each LUT engine 14 appends the reference result of LUT segment 51 to the lookup message Mb. The lookup message M, after this processing, is then labeled as lookup message Mc. Figure 6 As shown, the lookup message Mc contains the write buffer address if write buffer 32 is hit, and contains the physical address if write buffer 32 is not hit.

[0093] The third processing circuit 15 receives the lookup message Mc from the LUT engine 14e via queue 106. Additionally, the third processing circuit 15 receives the lookup message Mc from the LUT engine 14o via queue 107.

[0094] The third processing circuit 15 performs different actions based on whether the reference result used as LUT segment 51 in the received lookup message Mc contains a write buffer address and whether it contains a sequential read flag.

[0095] If the lookup message Mc contains a write buffer address but does not contain a sequential read flag, the third processing circuit 15 sends the lookup message Mc to the first processing circuit 12 via queue 108. The lookup message M transmitted from the third processing circuit 15 to the first processing circuit 12 is marked as lookup message Md. Lookup message Md is as follows: Figure 6 The address shown includes the write buffer address. Upon receiving the lookup message Md, the first processing circuit 12 retrieves the cluster data 40 from the write buffer 32 at the position indicated by the write buffer address contained in the lookup message Md, and sends the retrieved cluster data 40 to the host 2.

[0096] If the lookup message Mc does not contain a write buffer address and does not contain a sequential read flag, the third processing circuit 15 sends the lookup message Mc to the CPU 17 via queue 109. The lookup message Mc transmitted from the third processing circuit 15 to the CPU 17 is marked as lookup message Me. Lookup message Me is as follows: Figure 6 As shown, only logical and physical addresses are included. That is, when a read request is made in a random access mode and the cluster data 40 of the read object is not stored in the write buffer 32, the lookup message Me is sent from the third processing circuit 15 to the CPU 17.

[0097] If the lookup message Mc does not contain a write buffer address but contains a sequential read flag, the third processing circuit 15 sends the lookup message Mc to the arrangement circuit 16 via queue 110. The lookup message M transmitted from the third processing circuit 15 to the first processing circuit 12 is marked as lookup message Mf.

[0098] If the lookup message Mc contains a write buffer address and a sequential read flag, the third processing circuit 15 copies the lookup message Mc and sends one of the two copied lookup messages Mc as lookup message Md to the first processing circuit 12 via queue 108. Additionally, the third processing circuit 15 assigns a dummy flag to the other of the two lookup messages Mc and sends it as lookup message Mf to the sorting circuit 16 via queue 110.

[0099] Therefore, the lookup message Md includes a sequential read flag and a buffer index in the case of sequential reading. The lookup message Md does not include either the sequential read flag or the buffer index in the case of random reading. Furthermore, the first processing circuit 12 does not use the sequential read flag and the buffer index. The third processing circuit 15 may also send the lookup message M, after deleting the sequential read flag and the buffer index, as the lookup message Md to the first processing circuit 12.

[0100] The lookup message Mf contains the physical address if the write buffer 32 is not hit. The lookup message Mf contains the write buffer address and a pseudo-flag if the write buffer 32 is hit. Furthermore, the arrangement circuit 16 and CPU 17 do not use the write buffer address. Therefore, even if the write buffer 32 is hit, a lookup message Mf that does not contain the write buffer address can still be sent to the arrangement circuit 16.

[0101] Arrangement circuit 16 receives multiple lookup messages containing sequential read flags via queue 110. Arrangement circuit 16 has the function of arranging the received multiple lookup messages in logical address order. The multiple lookup messages Mf arranged in logical address order by arrangement circuit 16 are retrieved by CPU 17 via queue 111 in the arranged order.

[0102] Figure 7 This is a schematic diagram illustrating an example of the configuration of the arrangement circuit 16 in the embodiment. The arrangement circuit 16 includes a message buffer group 161 and an SRAM 162.

[0103] Message buffer group 161 has multiple message buffers 163, each capable of storing one lookup message M (more precisely, lookup message Mf). Each message buffer 163 is assigned a buffer index as a consecutive number. Figure 7 In the example shown, message buffer group 161 has n+1 message buffers 163, and each message buffer 163 is assigned any one of the numbers from 0 to n as a buffer index.

[0104] Each message buffer 163 is an example of the second buffer. The buffer index assigned to each message buffer 163 is an example of the second consecutive number.

[0105] SRAM 162 stores a buffer management bit map 60. Each buffer management bit map 60 has a number of information bits, each associated one-to-one with a message buffer 163, equal to the number of message buffers 163. Each information bit indicates whether a lookup message Mf that has not yet been retrieved by the CPU 17 is stored in the corresponding message buffer 163. The information bit indicating that a lookup message Mf that has not yet been retrieved is stored in the corresponding message buffer 163 is marked as "enable," and the information bit indicating that a lookup message Mf that has not yet been retrieved is not stored in the corresponding message buffer 163 is marked as "disable."

[0106] Arrangement circuit 16 saves each lookup message Mf received from third processing circuit 15 into message buffer 163, which is represented by the buffer index attached to each lookup message Mf. In response to saving each lookup message Mf, arrangement circuit 16 changes the information bit corresponding to the message buffer 163 where the saving destination is located from "disable" to "enable".

[0107] As described above, in the case of sequential reading, the first processing circuit 12 sends multiple lookup messages M(Ma) with attached sequential read flags to the second processing circuit 13 in logical address order. The second processing circuit 13 appends the value corresponding to the order received from the first processing circuit 12 to the multiple lookup messages M(Ma) as a buffer index. The arrangement circuit 16 stores each lookup message Mf in a message buffer 163 represented by the buffer index attached to each lookup message Mf. Thus, the message buffer group 161 stores the multiple lookup messages Mf in a state arranged in logical address order. That is, when the CPU 17 retrieves the lookup messages Mf from the message buffer group 161 in buffer index order, it can obtain the lookup messages Mf in logical address order. In addition, sometimes the case of retrieving the lookup message Mf from the message buffer group 161 (or message buffer 163) is marked as retrieving the lookup message Mf from the arrangement circuit 16.

[0108] Each lookup message Mf stored in message buffer group 161 is retrieved by CPU 17 in buffer index order. Arrangement circuit 16 notifies the second processing circuit 13 of the buffer index of the last lookup message Mf retrieved.

[0109] More specifically, the buffer index of the message buffer 163 where the search message Mf was last retrieved is stored as a read pointer 132 in the second processing circuit 13. The arrangement circuit 16 increments the read pointer 132 each time the search message Mf is retrieved by the CPU 17. This operation of the read pointer 132 notifies the second processing circuit 13 of the buffer index of the message buffer 163 where the search message Mf was last retrieved.

[0110] Furthermore, message buffer group 161 is treated as a ring buffer. For example, if the value of read pointer 132 is further incremented when the value of read pointer 132 has reached the maximum value of the buffer index, the value of read pointer 132 will return to the minimum value of the buffer index.

[0111] The second processing circuit 13 uses a write pointer 131 to manage the value of the buffer index appended to the next lookup message M. Based on the write pointer 131 and the read pointer 132, the second processing circuit 13 adjusts the timing of sending the lookup message Mb so that the message buffer 163, which holds the lookup message Mf that has not yet been retrieved, will not save the new lookup message Mf in an overwrite manner.

[0112] CPU 17 receives lookup message Me via queue 109. Upon receiving lookup message Me, CPU 17 generates a read command to read one cluster of data 40 starting from the location represented by the physical address contained in the lookup message Me.

[0113] Additionally, CPU 17 retrieves a lookup message Mf from message buffer 163 of message buffer group 161, corresponding to the information bit in buffer management bit mapping 60 that has a value indicating "enable". CPU 17 retrieves the lookup messages Mf in the order of their buffer indices. CPU 17 generates a read command based on the sequentially retrieved lookup messages Mf. When two or more clusters of data 40 within a single page are designated as read targets based on their respective sequentially retrieved lookup messages Mf, CPU 17 generates a read command so that each sensing action can acquire these two or more clusters of data 40.

[0114] Furthermore, after retrieving the lookup message Mf containing the pseudo-flag from the lookup message Mf stored in the message buffer group 161, the CPU 17 discards it without using it. In other words, the CPU 17 generates a read command based on the lookup message Mf without the pseudo-flag retrieved from the lookup message Mf in the message buffer group 161.

[0115] CPU 17 sends the generated read command to NAND memory 20 (more precisely, memory chip 21). Under the control of CPU 17, memory controller 10 saves the cluster data 40 received from memory chip 21 into read buffer 33 according to the read command. CPU 17 notifies the first processing circuit 12 of the intention to save cluster data 40 into read buffer 33. The first processing circuit 12 then sends the cluster data 40 saved in read buffer 33 to host 2. Sometimes, the action of CPU 17 sending a read command to NAND memory 20, thereby retrieving more than one cluster of data 40 from NAND memory 20, is marked as a read action.

[0116] Figure 8 This is a schematic diagram illustrating an example of the control of the lookup message M in the case of sequential reading implemented by the storage controller 10 of the embodiment. This diagram shows the control in the case where the write buffer 32 is not hit.

[0117] exist Figure 8 In this context, the numerical information from 0 to 8 attached to the lookup message M indicates the sending order of the lookup messages M from the first processing circuit 12. That is, the numerical information attached to each lookup message M corresponds to the logical address order. Sometimes, a lookup message M with a tagged value of "x" is marked as lookup message M#x. In this context... Figure 8 In the example shown, "x" is an integer from 0 to 8.

[0118] The second processing circuit 13 will sequentially receive search messages M#0 to M#8 as search messages Ma, and allocate them to LUT engine 14e and LUT engine 14o according to the path corresponding to the segment index.

[0119] As an example, the second processing circuit 13 sends lookup messages M#0 to M#2 to the LUT engine 14e via queue 102. The second processing circuit 13 sends lookup messages M#3 to M#5 to the LUT engine 14o via queue 104. The second processing circuit 13 sends lookup messages M#6 to M#8 to the LUT engine 14e via queue 103.

[0120] LUT engine 14e sequentially retrieves lookup messages Mb from queues 102 and 103, and performs the previously described processing on each retrieved lookup message Mb. Furthermore, LUT engine 14e sends each processed lookup message Mb as a lookup message Mc to the third processing circuit 15.

[0121] As an example, LUT engine 14e retrieves lookup message Mb from queues 102 and 103 using a round-robin scheduling method. Therefore, LUT engine 14e sends lookup messages M#0, M#6, M#1, M#7, M#2, and M#8 as lookup messages Mc in the aforementioned order.

[0122] Furthermore, the LUT engine 14e is not limited to round-robin scheduling in obtaining the lookup message Mb.

[0123] LUT engine 140 retrieves lookup messages Mb sequentially from queues 104 and 105 in the same manner as LUT engine 14e, and performs the previously described processing on each retrieved lookup message Mb. Furthermore, LUT engine 140 sends each processed lookup message Mb as a lookup message Mc to the third processing circuit 15.

[0124] As an example, LUT engine 140 retrieves lookup message Mb from queues 104 and 105 using a round-robin scheduling method. In this example, LUT engine 140 retrieves lookup messages M#3, M#4, and M#5 as lookup messages Mb in the aforementioned order via queue 104. Therefore, LUT engine 140 sends lookup messages M#3, M#4, and M#5 as lookup messages Mc in the aforementioned order.

[0125] The third processing circuit 15 sequentially retrieves search messages Mc from queues 106 and 107, and performs the previously described processing on each retrieved search message Mc. Furthermore, the third processing circuit 15 sends each processed search message Mc as a search message Mf to the arrangement circuit 16.

[0126] As an example, the third processing circuit 15 retrieves the search message Mc from queues 106 and 107 using a round-robin scheduling method. Consequently, the third processing circuit 15 sends search messages M#0, M#3, M#6, M#4, M#1, M#5, M#7, M#2, and M#8 as search messages Mf in that order.

[0127] Furthermore, the method by which the third processing circuit 15 obtains the lookup message Mc is not limited to round-robin scheduling.

[0128] The search messages M#0, M#3, M#6, M#4, M#1, M#5, M#7, M#2, and M#8, which are input to the arrangement circuit 16 as search messages Mf, are arranged in logical address order by the arrangement circuit 16. Furthermore, these search messages Mf are retrieved by the CPU 17 in logical address order.

[0129] In this implementation, since the multiple LUT engines 14 share the reference to the LUT segment 51 corresponding to each of the multiple lookup messages M, the processing order of the multiple lookup messages M is disrupted (shuffled) by the multiple LUT engines 14. Moreover, the back-end circuitry of the multiple LUT engines 14, especially the third processing circuit 15, obtains the multiple lookup messages Mc in an order different from the logical address order.

[0130] If the CPU17 retrieves multiple lookup messages Mf in an order different from the logical address order, the CPU17 will have difficulty generating a read command in a way that allows it to retrieve multiple cluster data 40 from a single page with a single sensing action, resulting in low reading efficiency.

[0131] Therefore, in this embodiment, an arrangement circuit 16 is provided between the third processing circuit 15 and the CPU 17. Multiple lookup messages Mf, which have been shuffled (disorganized) in a manner different from the logical address order, are arranged in logical address order by the arrangement circuit 16, and then retrieved by the CPU 17 in logical address order.

[0132] With the above configuration, CPU17 can generate read commands so that multiple clusters of data 40 can be obtained from a page with a single sensing action, thus suppressing the low read efficiency.

[0133] In other words, according to the implementation method, the determination of the location of cluster data 40 of multiple read objects related to multiple lookup messages M can be performed at high speed by multiple LUT engines 14, and in the case of sequential reading, cluster data 40 of more than two read objects can be obtained from the memory chip 21 for each sensing operation on the memory chip 21. As a result, the read performance of the storage system 1 is improved.

[0134] Figure 9 This is a schematic diagram illustrating yet another example of the control of the lookup message M in a sequential read scenario, implemented by the storage controller 10 of the embodiment. This diagram shows the control in the case where the write buffer 32 is hit. Regarding... Figure 9 The example shown is for... Figure 8 The examples shown illustrate different aspects, and are related to... Figure 8The same items shown in the examples are omitted from the description.

[0135] exist Figure 9 In the example shown, the cluster data 40 corresponding to each of lookup messages M#0, M#5, and M#6 is stored in the write buffer 32.

[0136] In the processing of lookup messages M#0 and M#6, LUT engine 14e obtains the write buffer address as a reference result. Therefore, LUT engine 14e appends the write buffer address, rather than the physical address, to each of lookup messages M#0 and M#6 as the reference result.

[0137] In processing lookup message M#5, LUT engine 140 obtains the write buffer address as a reference result. Therefore, LUT engine 140 appends the write buffer address, rather than the physical address, to lookup message M#5 as a reference result.

[0138] In addition, Figure 9 In the middle, dot hatching is applied to the lookup message M that hits write buffer 32.

[0139] The third processing circuit 15 sends the lookup messages M#0, M#5, and M#6 that hit the write buffer 32 to the first processing circuit 12 in the order they were obtained, that is, in the order of lookup message M#0, lookup message M#6, and lookup message M#5.

[0140] In addition, the third processing circuit 15 and Figure 8 Similarly, in the example shown, lookup messages M#0 through M#8 are sent to the arrangement circuit 16 as lookup messages Mf, respectively. The third processing circuit 15 adds a pseudo-flag to lookup messages M#0, M#5, and M#6 that hit the write buffer 32 and sends them to the arrangement circuit 16.

[0141] If CPU17 retrieves a lookup message Mf containing a pseudo-flag, it discards the retrieved lookup message Mf without using it. That is, CPU17 retrieves lookup messages M#0, M#1, M#2, M#3, M#4, M#5, M#6, M#7, and M#8 from message buffer group 161 in this order, and uses lookup messages M#1, M#2, M#3, M#4, M#7, and M#8.

[0142] Consider the case where the third processing circuit 15 sends the lookup message M that hits the write buffer 32 only to the first processing circuit 12 and not to the arrangement circuit 16. The technique in which the third processing circuit 15 sends the lookup message M that hits the write buffer 32 only to the first processing circuit 12 and not to the arrangement circuit 16 is designated as the comparative example.

[0143] According to the comparative example technique, in the arrangement circuit 16, only lookup messages Mf that do not hit write buffer 32 are stored in message buffer group 161, while lookup messages Mf that hit write buffer 32 are not stored in message buffer group 161. As a result, the message buffer 163 corresponding to the lookup message M that hit write buffer 32 is kept "disabled" in the buffer management bit mapping 60.

[0144] In the comparative example, the CPU 17 can only retrieve the lookup message Mf from the message buffer 163 corresponding to the information bit set to the value indicating "enable" in the buffer management bit mapping 60, and the CPU 17 can retrieve the lookup message Mf in the order of the buffer index. If a lookup message M that hits write buffer 32 exists, even if a lookup message Mf following the logical address point is stored in message buffer 163, the CPU 17 stops processing until the message buffer 163 corresponding to the lookup message M that hits write buffer 32 becomes "enable". However, the lookup message M that hits write buffer 32 is not stored in message buffer 163. Thus, according to the comparative example, in the case of a write buffer 32 hit, the CPU 17 cannot advance processing, and the memory controller 10 becomes unable to continue operating. For example, even if a time limit is set for stopping processing, time is still required until processing resumes.

[0145] In contrast, in this embodiment, the lookup message M that hits the write buffer 32 is copied. One of the two copied lookup messages M is sent to the first processing circuit 12, and the other is given a pseudo-flag and sent to the arrangement circuit 16. Furthermore, the information bit corresponding to the message buffer 163 where the pseudo-flag-tagged lookup message Mf is stored in the buffer management bit map 60 is set to "enable". Therefore, the CPU 17 can retrieve the lookup message Mf from the message buffer 163 where the pseudo-flag-tagged lookup message Mf is stored and continue processing.

[0146] Next, the operation of the storage system 1 according to the embodiment will be described. Here, only the operation corresponding to the read request will be described.

[0147] Figure 10 This is a flowchart illustrating an example of the action of the first processing circuit 12 in an embodiment to generate a lookup message Ma based on a read request.

[0148] The first processing circuit 12 determines whether it has received a read request (S101). If no read request is received (S101: No), the first processing circuit 12 executes the processing of S101 again.

[0149] When the first processing circuit 12 receives a read request (S101: Yes), the logical address range to be read is divided into clusters, and a lookup message Ma is generated for each cluster (S102).

[0150] Then, the storage controller 10 determines whether the access mode corresponding to the read request conforms to sequential read (S103).

[0151] The method for determining whether the access pattern corresponding to a read request conforms to sequential reading can be arbitrarily designed. In one example, the method determines whether the access pattern corresponding to the read request conforms to sequential reading based on a comparison of the size information contained in the read request with a predetermined threshold. If the size information exceeds the threshold, the first processing circuit 12 determines that the access pattern corresponding to the read request conforms to sequential reading. If the size information does not reach the threshold, the first processing circuit 12 determines that the access pattern corresponding to the read request does not conform to sequential reading.

[0152] In another example, if the storage controller 10 receives more than one read request within a predetermined period, it may determine whether the access pattern corresponding to the read request conforms to sequential reading by comparing the total value of the size information contained in the more than one read request with a threshold.

[0153] If the access mode corresponding to the read request is in the order of read (S103: Yes), the first processing circuit 12 adds an order of read flag to each lookup message Ma (S104) and sends each lookup message Ma to the second processing circuit 13 (S105).

[0154] If the access mode corresponding to the read request does not conform to sequential reading (S103: No), the first processing circuit 12 skips the processing of S104 and executes the processing of S105.

[0155] After processing in S105, the first processing circuit 12 executes the processing in S101 again.

[0156] Figure 11 This is a flowchart illustrating an example of the operation of the second processing circuit 13 in the implementation method.

[0157] The second processing circuit 13 determines whether it has received a lookup message Ma from the first processing circuit 12 (S201). If the second processing circuit 13 has not received the lookup message Ma (S201: No), the second processing circuit 13 executes the processing of S201 again.

[0158] When the second processing circuit 13 receives a lookup message Ma (S201: Yes), the second processing circuit 13 determines whether the LUT segment 51 of the object is stored in the LUT cache 31 (S202). The LUT segment 51 of the object is the LUT segment 51 containing the entry related to the logical address contained in the received lookup message Ma.

[0159] If the LUT segment 51 of the object is not stored in the LUT cache 31 (S202: No), the second processing circuit 13 performs a refill of the LUT segment 51 of the object (S203). That is, the second processing circuit 13 reads the LUT segment 51 of the object from the NAND memory 20 and stores it in the LUT cache 31.

[0160] If the LUT segment 51 of the object is stored in the LUT cache 31 (S202: Yes), the second processing circuit 13 skips the processing of S203.

[0161] Next, the second processing circuit 13 determines the segment index of the LUT segment of the object (S204). Then, the second processing circuit 13 determines whether the lookup message Ma contains a sequential read flag (S205).

[0162] If the search message Ma contains a sequential read flag (S205: Yes), the second processing circuit 13 determines whether the value of the write pointer 131 is equal to the value obtained by advancing the read pointer 132 by 1 (S206).

[0163] If the value of the write pointer 131 is equal to the value obtained by advancing the read pointer 132 by 1 (S206: Yes), the second processing circuit 13 executes the processing of S206 again. That is, the second processing circuit 13 waits for subsequent processing (S207-S209), specifically setting the next message buffer 163 to store the execution of sending the destination lookup message Mb.

[0164] As mentioned earlier, message buffer group 161 is treated as a ring buffer. By waiting for the send of lookup message Mb until the determination condition of S206 is met, it can prevent the position indicated by write pointer 131 from exceeding the position indicated by read pointer 132. In other words, it can prevent the lookup message Mf that has not yet been retrieved by CPU 17 from being overwritten by other lookup messages Mf.

[0165] If the value of the write pointer 131 is not equal to the value obtained by advancing the read pointer 132 by 1 (S206: No), the second processing circuit 13 appends the value of the write pointer 131 as the buffer index of the message buffer representing the destination to the lookup message Ma (S207), and then increments the write pointer 131 (S208).

[0166] The second processing circuit 13 sends the processed lookup message Ma as lookup message Mb to any LUT engine 14 along the path corresponding to the segment index (S209). Then, the second processing circuit 13 executes the processing of S201 again.

[0167] If the lookup message Ma does not contain a sequential read flag (S205: No), the second processing circuit 13 skips the processing from S206 to S208 and executes the processing of S209.

[0168] Figure 12 This is a flowchart illustrating an example of the operation of the LUT engine 14 in the implementation method.

[0169] LUT engine 14 determines whether it has received lookup message Mb from second processing circuit 13 (S301). If LUT engine 14 has not received lookup message Mb (S301: No), LUT engine 14 executes the processing of S301 again.

[0170] When LUT engine 14 receives lookup message Mb (S301: Yes), LUT engine 14 refers to LUT segment 51 of the object (S302). That is, LUT engine 14 obtains the physical address or write buffer address associated with the logical address contained in lookup message Mb based on LUT segment 51 of the object.

[0171] LUT engine 14 appends the reference result, i.e., the physical address or write buffer address, to lookup message Mb (S303). Then, LUT engine 14 sends the lookup message M, which has undergone the above processing, as lookup message Mc to the third processing circuit 15 (S304). Then LUT engine 14 executes the processing of S301 again.

[0172] Figure 13 This is a flowchart illustrating an example of the operation of the third processing circuit 15 in the implementation method.

[0173] The third processing circuit 15 determines whether it has received a lookup message Mc from any LUT engine 14 (S401). If the third processing circuit 15 has not received a lookup message Mc (S401: No), the third processing circuit 15 executes the processing of S401 again.

[0174] When the third processing circuit 15 receives the search message Mc (S401: Yes), the third processing circuit 15 determines whether the search message Mc contains a sequential read flag (S402).

[0175] If the lookup message Mc contains a sequential read flag (S402: Yes), the third processing circuit 15 further determines whether the lookup message Mc contains a write buffer address (S403).

[0176] If the lookup message Mc contains a write buffer address (S403: Yes), the third processing circuit 15 copies the lookup message Mc into two (S404). Then, the third processing circuit 15 sends one of the two lookup messages Mc as a lookup message Md to the first processing circuit 12 (S405).

[0177] The third processing circuit 15 adds another pseudo-flag to the two lookup messages Mc (S406). Then, the third processing circuit 15 sends the lookup message Mc with the pseudo-flag added as the lookup message Mf to the arrangement circuit 16 (S407).

[0178] If the lookup message Mc does not contain the write buffer address (S403: No), the lookup message Mc is sent to the arrangement circuit 16 as the lookup message Mf (S408).

[0179] If the lookup message Mc does not contain a sequential read flag (S402: No), the third processing circuit 15 further determines whether the lookup message Mc contains a write buffer address (S409).

[0180] If the lookup message Mc contains a write buffer address (S409: Yes), the third processing circuit 15 sends the lookup message Mc as the lookup message Md to the first processing circuit 12 (S410).

[0181] If the lookup message Mc does not contain a write buffer address (S409: No), the third processing circuit 15 sends the lookup message Mc as a lookup message Me to the CPU 11 (S411).

[0182] After processing in S407, S408, S410, or S411, the third processing circuit 15 executes the processing in S401 again.

[0183] Figure 14 This is a flowchart illustrating an example of the operation of the arrangement circuit 16 in the implementation method.

[0184] Arrangement circuit 16 determines whether it has received a lookup message Mf from the third processing circuit 15 (S501).

[0185] When the arrangement circuit 16 receives the lookup message Mf (S501: Yes), the arrangement circuit 16 saves the lookup message Mf to the message buffer 163, which represents the buffer index contained in the lookup message Mf (S502). Then, the arrangement circuit 16 sets the information bit corresponding to the message buffer 163, the destination of the lookup message Mf, in the buffer management bit mapping 60 to "enable" (S503). Then, the arrangement circuit 16 executes the process of S501 again.

[0186] If the arrangement circuit 16 does not receive a lookup message Mf (S501: No), the arrangement circuit 16 determines whether a lookup message Mf has been retrieved from the message buffer group 161 by the CPU 17 (S504). In addition, the CPU 17 can retrieve the lookup message Mf from the message buffer 163 with the buffer index following the last buffer index from which the lookup message Mf was retrieved.

[0187] When a lookup message Mf is retrieved from message buffer group 161 (S504: Yes), the arrangement circuit 16 sets the information bit corresponding to message buffer 163 where the lookup message Mf was retrieved, as mapped by buffer management bit 60, to "disable" (S505). Additionally, the arrangement circuit 16 increments the read pointer 132 (S506). Then, the arrangement circuit 16 executes the process of S501 again.

[0188] If no lookup message Mf is retrieved from message buffer group 161 (S504: No), the arrangement circuit 16 skips the processing of S505 and S506 and executes the processing of S501 again.

[0189] Figure 15 This is a flowchart illustrating an example of the operation of the CPU 17 in the embodiment of processing the lookup message Me sent from the third processing circuit 15.

[0190] CPU17 determines whether it has received a lookup message Me from the third processing circuit 15 (S601). If CPU17 has not received the lookup message Me (S601: No), CPU17 executes the processing of S601 again.

[0191] Upon receiving a lookup message Me (S601: Yes), CPU 17 generates a read command based on the lookup message Me (S602). That is, CPU 17 generates a read command to retrieve the cluster data 40 of the read object specified by the lookup message Me. According to this read command, page data containing the cluster data 40 of the read object specified by the lookup message Me is transferred from the memory cell array 211 to the page register 212 via a sensing action. Then, the cluster data 40 is output from the page register 212 to the memory controller 10.

[0192] CPU 17 sends the generated read command to memory chip 21, which stores the cluster data 40 of the read object (S603). Then, CPU 17 stores the cluster data 40 of the read object, which is output from memory chip 21 in response to the read command, in read buffer 33 (S604).

[0193] CPU 17 notifies the first processing circuit 12 (S605) that the cluster data 40 of the read object is stored in the read buffer 33. Then, CPU 17 executes the processing of S601 again.

[0194] Figure 16 This is a flowchart illustrating an example of the operation of the CPU 17 in the implementation of the system, in which it sequentially retrieves and processes the lookup message Mf from the message buffer group 161.

[0195] CPU17 determines whether a search message Mf that has not yet been retrieved is stored in message buffer 163 following the last retrieved message Mf (S701). The message buffer 163 following the last retrieved message Mf, as mentioned in the explanation of the S701 process, is marked as the first message buffer 163. Furthermore, if a search message Mf that has not yet been retrieved is stored in the first message buffer 163, that search message Mf is marked as the first search message Mf.

[0196] If the lookup message Mf that has not yet been retrieved is not stored in the first message buffer 163 (S701: No), the CPU 17 executes the processing of S701 again.

[0197] If a lookup message Mf that has not yet been retrieved is stored in the first message buffer 163 (S701: Yes), the CPU 17 retrieves the first lookup message Mf from the first message buffer 163 (S702). Then, the CPU 17 determines whether a lookup message Mf that has not yet been retrieved is stored in the subsequent message buffer 163 (S703).

[0198] If S703 is executed following S702, the subsequent message buffer 163 mentioned in the description of S703 means the message buffer 163 whose buffer index follows the buffer index of the first message buffer 163. If S703 is executed following S705 or S707, the subsequent message buffer 163 mentioned in the description of S703 means the message buffer 163 whose buffer index follows the buffer index of the message buffer 163 that retrieved the lookup message Mf through the processing of S705 or S707. The subsequent message buffer 163 mentioned in the description of S703 is marked as the second message buffer 163. Furthermore, the second message buffer 163 means the message buffer 163 mentioned in the latest (current) S703 processing, and does not mean the message buffer 163 mentioned in the previously executed S703 processing.

[0199] If a lookup message Mf that has not yet been retrieved is stored in the second message buffer 163 (S703: Yes), the CPU 17 determines whether the lookup message Mf stored in the second message buffer 163 contains a false flag (S704).

[0200] If the lookup message Mf stored in the second message buffer 163 contains a false flag (S704: Yes), the CPU 17 retrieves the lookup message Mf from the second message buffer 163 and discards it (S705). Then, the CPU 17 executes the process of S703 again.

[0201] If the lookup message Mf stored in the second message buffer 163 does not contain a pseudo-flag (S704: No), the CPU 17 determines whether the cluster data 40 of the read object specified by the lookup message Mf stored in the second message buffer 163 is stored on the same page as the cluster data 40 of the read object specified by the first lookup message Mf (S706).

[0202] If the cluster data 40 of the read object specified by the lookup message Mf stored in the second message buffer 163 is stored on the same page as the cluster data 40 of the read object specified by the first lookup message Mf (S706: Yes), the CPU 17 retrieves the lookup message Mf from the second message buffer 163 (S707), and then executes the processing of S703 again.

[0203] If no lookup message Mf that has not yet been retrieved is stored in the second message buffer 163 (S703: No), or if the cluster data 40 of the read object specified by the lookup message Mf stored in the second message buffer 163 is not stored on the same page as the cluster data 40 of the read object specified by the first lookup message Mf (S706: No), the CPU 17 generates a read command based on all lookup messages Mf retrieved after the latest S701 processing (S708). That is, the CPU 17 generates a read command that transfers one page of data containing the cluster data 40 of the read object specified by the first lookup message Mf from the memory cell array 211 to the page register 212 through one sensing action, and outputs the cluster data 40 of each lookup message Mf specified by the read object retrieved after the latest S701 processing from the one page of data stored in the page register 212.

[0204] CPU 17 sends the generated read command to memory chip 21 (S709). Then, CPU 17 saves the cluster data 40 of each read object output by memory chip 21 in response to the read command into read buffer 33 (S710).

[0205] The CPU 17 notifies the first processing circuit 12 (S711) that the cluster data 40 of each read object is stored in the read buffer 33. Then, the CPU 17 executes the processing of S701 again.

[0206] Figure 17 This is a flowchart illustrating an example of the operation of sending cluster data 40 of the read object of the first processing circuit 12 of the embodiment to the host 2.

[0207] like Figure 17 As shown, the first processing circuit 12 transmits the cluster data 40 stored in the write buffer 32, represented by the write buffer address contained in the lookup message Mc, or stored in the read buffer 33, to the host 2 (S801). The first processing circuit 12 repeatedly executes the processing of S801.

[0208] As described above, according to the embodiment, when the first processing circuit 12 receives at least one read request from the host 2 specifying a contiguous logical address range of multiple cluster sizes, it issues multiple lookup messages M requesting the reading of all cluster data 40 located within the logical address range in logical address order. The second processing circuit 13 appends a buffer index, representing the destination of a message buffer 163 and corresponding to a first consecutive number corresponding to the issuance order, to each of the multiple lookup messages M, and allocates the multiple lookup messages M with the appended buffer index to multiple LUT engines 14. Each of the multiple LUT engines 14 determines the location of the cluster data 40 of the read object corresponding to the lookup message M allocated to itself by referring to any of the LUT segments 51 within the LUT cache 31, and appends location information indicating the determined location to the lookup message M allocated to itself. The third processing circuit 15 obtains the multiple lookup messages M with the appended buffer index from the multiple LUT engines 14. Arrangement circuit 16 arranges the multiple lookup messages M obtained by third processing circuit 15 according to the buffer index attached to each lookup message M. CPU 17 performs a read operation on NAND memory 20 based on the arranged multiple lookup messages M.

[0209] Therefore, by using multiple LUT engines 14, the storage controller 10 can efficiently perform the referencing and updating processes required for the computationally expensive LUT 50. Furthermore, even if the processing order of multiple lookup messages M issued in logical address order is disrupted (shuffled) by the multiple LUT engines 14, the storage controller 10 can efficiently retrieve the cluster data 40 of the read target from the NAND memory 20 because the arrangement circuit 16 restores the processing order of the multiple lookup messages M to the logical address order. Through these improvements, the read performance of the storage system 1 can be enhanced.

[0210] Furthermore, according to the embodiment, each memory chip 21 constituting the NAND memory 20 includes a page register 212 and a memory cell array 211 configured to store user data DAT. During a read operation, the memory chip 21 is configured to perform a sensing operation, outputting at least one cluster of data 40 from the page data stored in the page register 212 to the memory controller 10. The sensing operation is the transfer of page data larger than the cluster of data 40 from the user data DAT stored in the memory cell array 211 from the memory cell array 211 to the page register 212. The CPU 17 performs the read operation such that each time the memory chip 21 performs a sensing operation, two or more clusters of data 40 are output from the page register 212.

[0211] Thus, the storage controller 10 is able to efficiently obtain the cluster data 40 of the read target from the NAND memory 20.

[0212] Furthermore, according to the embodiment, the storage system 1 also includes a write buffer 32, which is configured to store user data DAT received from the host 2 until the user data DAT is stored in the NAND memory 20. Each LUT segment 51 stored in the LUT cache 31 associates its logical address with the location where the user data DAT is stored in the NAND memory 20 or the write buffer 32, in units of cluster data 40. The third processing circuit 15 causes the lookup message M with an appended physical address from the multiple lookup messages M obtained from the multiple LUT engines 14, each with a sequential read flag, to be sent to the arrangement circuit 16 instead of the first processing circuit 12. Additionally, the third processing circuit 15 sends the lookup message M with an appended write buffer address from the multiple lookup messages M obtained from the multiple LUT engines 14, each with a sequential read flag, to the first processing circuit 12 and the arrangement circuit 16. The CPU 17 performs a read operation only based on the lookup messages M that are arranged in logical address order by the arrangement circuit 16 and have an appended physical address instead of a write buffer address. The first processing circuit 12 sends the data read from the NAND memory 20 by the read operation and the data stored at the location indicated by the write buffer address of the lookup message M received from the third processing circuit 15 to the host 2.

[0213] Therefore, in the case of sequential reading, CPU17 can obtain all lookup messages M related to sequential reading from the arrangement circuit 16 in logical address order, regardless of whether the write buffer 32 is hit.

[0214] Furthermore, according to the implementation, the third processing circuit 15 does not add a pseudo-flag to the lookup message M with an appended physical address among the multiple lookup messages M obtained from the multiple LUT engines 14, but adds a pseudo-flag to the lookup message M with an appended write buffer address among the multiple lookup messages M obtained from the multiple LUT engines 14. The CPU 17 determines whether it is a lookup message M with an appended physical address among the multiple lookup messages M obtained from the arrangement circuit 16 based on the presence or absence of the pseudo-flag.

[0215] Thus, CPU17 can easily determine which lookup messages M should be discarded, i.e., lookup messages M that are not used for read operations, from all lookup messages M obtained from the arrangement circuit 16 in logical address order.

[0216] Furthermore, according to the embodiment, the arrangement circuit 16 includes a plurality of message buffers 163, each of which is assigned a buffer index. The arrangement circuit 16 stores a plurality of lookup messages M in the plurality of message buffers 163, each represented by a buffer index assigned to each of the plurality of lookup messages M. The CPU 17 retrieves the plurality of lookup messages M from the plurality of message buffers 163 in the order of the buffer indices assigned to each message buffer 163.

[0217] Therefore, CPU17 can obtain multiple lookup messages M from the array circuit 16 in logical address order.

[0218] Furthermore, each of the multiple LUT engines 14 is connected to the second processing circuit via multiple queues. The LUT 50 is divided into multiple LUT segments 51, each assigned a segment index. The LUT cache 31 is configured to cache the LUT 50 in units of LUT segments 51. The second processing circuit 13 receives multiple lookup messages M in the order of their issuance. If the LUT segment 51 required for determining the location of the cluster data 40 of the read object corresponding to the received lookup message M is cached in the LUT cache 31, the second processing circuit 13 sends the lookup message M to one of the multiple LUT engines 14 via the queue corresponding to the segment index assigned to that LUT segment 51. If the LUT segment 51 required for determining the location of the cluster data 40 of the read object corresponding to the received lookup message M is not cached in the LUT cache 31, the second processing circuit 13 performs a refill of the LUT cache 31, and then sends the lookup message M to one of the multiple LUT engines 14 via the queue corresponding to the segment index assigned to that LUT segment 51.

[0219] Therefore, even if a lookup message M has been refilled, the second processing circuit 13 can perform processing related to any subsequent lookup message M without waiting for the refilling to complete.

[0220] Several embodiments of the present invention have been described. These embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention as set forth in the claims and its equivalents.

[0221] Label Explanation

[0222] 1. Storage system

[0223] 2. Host

[0224] 10. Storage controller

[0225] 11 SRAM

[0226] 12 First processing circuit

[0227] 13. Second processing circuit

[0228] 14, 14e, 14o LUT engine,

[0229] 15. Third processing circuit

[0230] 16. Arrangement circuits

[0231] 17 CPUs

[0232] 20 NAND memory,

[0233] 21, 21-0, 21-1, 21-2, 21-3 memory chips

[0234] 31 LUT cache,

[0235] 32. Write buffer

[0236] 33 Read buffer

[0237] 40 clusters of data

[0238] 50 LUTs

[0239] 51 LUT segment,

[0240] 60. Buffer management bit mapping

[0241] 70 work areas

[0242] 71 Queue Area

[0243] Queues 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111

[0244] 131 Writing pointers

[0245] 132 Read pointer,

[0246] 161 Message Buffer Group

[0247] 163 Message Buffer

[0248] 211 storage cell array,

[0249] 212 page registers,

[0250] DAT user data

[0251] M, Ma, Mb, Mc, Md, Me, Mf retrieve messages.

Claims

1. A storage system capable of connecting to a host, comprising: The first memory is a non-volatile memory configured to store data received from the host. The second memory is configured to store management information that associates the logical address used by the host with the location where the data is stored in the first memory on a per-first-data-unit basis; and The storage controller includes: a first circuit, a second circuit, multiple third circuits, a fourth circuit, a fifth circuit, and a sixth circuit. The storage controller receives from the host a read request specifying a plurality of consecutive logical address ranges of the size of the first data unit. The first circuit is configured to, in response to receiving the read request, issue a plurality of first sub-commands in the order of the logical addresses, requesting the reading of all first data units of data contained within the logical address range, each of the plurality of first sub-commands requesting the reading of one first data unit of data. The second circuit is configured to append a first consecutive number corresponding to the issuance order to each of the plurality of first sub-commands, and then allocate the plurality of first sub-commands, each appended with the first consecutive number, to the plurality of third circuits. Each of the plurality of third circuits is configured to determine, by referring to the management information, the storage location of the first data unit related to the first sub-command assigned to that third circuit itself among the plurality of first sub-commands, and to append location information representing the determined storage location to the first sub-command. The fourth circuit is configured to obtain multiple first sub-commands, each with the location information appended, from the plurality of third circuits. The fifth circuit is configured such that the plurality of first sub-commands obtained through the fourth circuit are arranged in order based on the first consecutive numbering. The sixth circuit is configured to perform a read operation on the first memory based on the arranged plurality of first sub-commands.

2. The storage system according to claim 1, The first memory is configured to include: a first buffer and a memory cell array configured to store the data. During the read operation, a sensing operation is performed to transfer a second data unit larger than the first data unit from the data stored in the memory cell array to the first buffer. At least one first data unit of the data from the second data unit stored in the first buffer through the sensing operation is then output to the memory controller. The sixth circuit is configured to perform the read operation on the first memory such that for each sensing operation, data of two or more of the first data units are output from the first buffer.

3. The storage system according to claim 1, It also includes a third memory configured to store the data received from the host until the data is stored in the first memory. The management information associates the logical address and the location where the data is stored in the first memory or the third memory with each first data unit. The fourth circuit, The second sub-command from the plurality of first sub-commands obtained from the third circuit is sent to the fifth circuit instead of to the first circuit. The second sub-command is a first sub-command with an appended first location information indicating the location within the first memory. The third sub-command from the plurality of first sub-commands obtained from the third circuit is sent to the first circuit and the fifth circuit. The third sub-command is a first sub-command with an appended second location information indicating the location within the third memory. The sixth circuit performs the read operation based solely on the second sub-command among the arranged plurality of first sub-commands. The first circuit is configured to send the first data read from the first memory by the read action and the second data stored in the third memory at the position indicated by the second position information attached to the third sub-command to the host.

4. The storage system according to claim 3, The fourth circuit is configured to not attach the first flag to the first sub-command that conforms to the second sub-command among the plurality of first sub-commands obtained from the plurality of third circuits, but to attach the first flag to the first sub-command that conforms to the third sub-command among the plurality of first sub-commands obtained from the plurality of third circuits. The sixth circuit determines the first sub-command that matches the second sub-command among the arranged plurality of first sub-commands based on the presence or absence of the first flag.

5. The storage system according to claim 3, The fifth circuit includes a plurality of second buffers, each assigned a second consecutive number, and stores the plurality of first sub-commands obtained by the fourth circuit in the plurality of second buffers, each assigned a second consecutive number that is the same as the first consecutive number attached to each of the plurality of first sub-commands. The sixth circuit retrieves the plurality of first sub-commands from the plurality of second buffers in the order of the second consecutive numbering.

6. The storage system according to any one of claims 1 to 5, Each of the plurality of third circuits is connected to the second circuit via a plurality of queues. The management information is divided into multiple management information segments, each assigned a third consecutive number. The second memory is a cache memory configured to cache the management information in units of management information segments. The second circuit, The plurality of first sub-commands are received in the order of issuance. If the management information segment required to determine the location of the first data unit related to one of the received first sub-commands (i.e., the first management information segment) is cached in the cache memory, then the one first sub-command is sent to one of the multiple third circuits via the queue corresponding to the third consecutive number assigned to the first management information segment in the multiple queues. If the first management information segment is not cached in the cache memory, the first management information segment is refilled, and then the first sub-command is sent to the third circuit among the plurality of third circuits via the queue corresponding to the third consecutive number assigned to the first management information segment in the plurality of queues.

7. A method for controlling a storage system, The storage system includes: a first memory, which is a non-volatile memory configured to store data received from the host; and a second memory configured to store management information that associates the logical address used by the host with the location where the data is stored in the first memory on a per-first-data-unit basis. The method includes: Receive a read request from the host specifying a plurality of consecutive logical address ranges of first data unit size; In response to the receipt of the read request, a plurality of first sub-commands are issued in the order of the logical addresses, each requesting the reading of one first data unit of data contained in the logical address range. Each of the plurality of first sub-commands is appended with a first consecutive number corresponding to the issuance order; The storage location of the data of each relevant first data unit in the plurality of first sub-commands is determined by referring to the management information, and the action of attaching the location information representing the determined storage location to the first sub-command is shared by multiple engines. Arrange the multiple first sub-commands, each with the location information attached, in order based on the first consecutive number; The read operation on the first memory is performed based on the arranged plurality of first sub-commands.

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